CN1409417A - 有机薄膜晶体管及制备方法 - Google Patents

有机薄膜晶体管及制备方法 Download PDF

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CN1409417A
CN1409417A CN02130962A CN02130962A CN1409417A CN 1409417 A CN1409417 A CN 1409417A CN 02130962 A CN02130962 A CN 02130962A CN 02130962 A CN02130962 A CN 02130962A CN 1409417 A CN1409417 A CN 1409417A
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阎东航
袁剑峰
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Changchun Flexible Display Technology Co ltd
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Changchun Institute of Applied Chemistry of CAS
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Abstract

一种有机薄膜晶体管,包括衬底(1)、在衬底(1)上形成的栅极(2),在栅极上面形成栅绝缘层,在绝缘层上形成源电极(5)和漏电极(6),在源电极(5)及漏电极(6)上形成半导体有源层(7),绝缘层为不同介电常数的第一绝缘层(3)和第二绝缘层(4)。本发明在不增加光刻等常规复杂工艺仅增加旋涂或蒸镀第二层绝缘膜和自对准干法刻蚀两步简单工序的情况下,就可以改善载流子的注入特性从而提高OTFT器件的性能,而且还可以阻断栅绝缘膜的漏电流、降低器件的寄生电容。这样,既可以采用高介电材料作为栅绝缘层,增大沟道电容,降低器件的开启电压,同时,降低栅源和栅漏漏电流对器件的不利影响。

Description

有机薄膜晶体管及制备方法
技术领域
本发明涉及有机薄膜晶体管(以下简称OTFT)。本发明还涉及这种结构有机薄膜晶体管的制备方法。
背景技术
近年来,OTFT的性能在不断地提高,其中一些有机材料(如Pentacene、Oligothiophene、Tetracene等)的晶体管器件的室温载流子场效应迁移率已经超过1(平方厘米每伏每秒),在柔性有源矩阵显示和柔性集成电路等方面显现出应用潜力。由于有机半导体对传统光刻工艺中的溶剂比较敏感,器件的微加工一般比较困难。因此,目前人们通常采用有机半导体层置于源漏电极之上(一般称为底电极构型OTFT,附图1)的办法来避免图形微加工的问题,但是这种器件与有机半导体层置于源漏电极之下(顶电极构型OTFT,附图2)的器件相比沟道开态电流小。总之,从器件结构方面讲,目前顶电极器件比底电极器件性能好(比较附图3和附图4)。另外,目前OTFT的开启电压偏高。影响开启电压的因素很多,如有机层与绝缘层的界面特性,源漏电极与有机半导体的接触特性等。有效降低开启电压的现有方法是减小栅绝缘膜的厚度或使用具有高介电常数绝缘材料作为绝缘层(如钛酸钡,BZT)(C.D.Dimitrakopoulos et al Science 283,822,1999)。遗憾的是,这两种方法都增大了器件的栅源、栅漏电极间的漏电流,主要原因是高介电材料绝缘性能差。虽然近年来,中国专利CN1293825A公开了一种直立型结构晶体管(包括无机和有机晶体管),宾西伐尼亚州立大学的Jackson研究组也公开了一种简化OTFT器件结构和制作工序的方法(Appl.Phys.Lett.2000,76:1692-1694),但它们都并不能解决上面提到的问题。
发明内容
本发明的目的是提供一种能有效降低器件中栅源、栅漏电极间的漏电流的高性能OTFT器件。
本发明的另一个目的是提供一种高性能OTFT的制备方法。
为实现上述目的,有机薄膜晶体管包括衬底1、在衬底1上形成的栅极2,在栅极上面形成栅绝缘层,在绝缘层上形成源电极5和漏电极6,在源电极5及漏电极6上形成半导体有源层7,所述的绝缘层为不同介电常数的第一绝缘层3和第二绝缘层4。
按照本发明的另一方面,有机薄膜晶体管的制备方法包括:
第一步,在衬底上溅射或蒸发一层金属(Ta、Ti、W、MO等)并光刻成栅电极。见附图6.(a)
第二步,溅射或蒸发一层栅绝缘膜(Ta2O5、Al2O3、TiO2、BZT等)和旋涂一层高分子聚合物(聚甲基丙烯酸甲脂、聚酰亚胺、聚乙烯醇、聚偏氟乙烯等)或溅射或蒸发一层低介电无机膜(SiO2、SiNx等)作为双栅绝缘膜。见附图6.(b)
第三步,真空热蒸发一层金属(Au、Ag、Mo、Al等)并光刻成源、漏电极。见附图6.(c)
第四步,以源、漏电极为掩模用反应性离子刻蚀(RIE)方式干法刻蚀掉沟道区的第二绝缘膜。见附图6.(d)
第五步,真空热蒸发有机半导体材料作为有源层并光刻和刻蚀(RIE方式)成型。
本发明在不增加光刻等常规复杂工艺仅增加旋涂或蒸镀第二层绝缘膜和自对准干法刻蚀两步简单工序的情况下,就可以改善载流子的注入特性从而提高OTFT器件的性能,而且还可以阻断栅绝缘膜的漏电流、降低器件的寄生电容。这样,既可以采用高介电材料作为栅绝缘层,增大沟道电容,降低器件的开启电压,同时,降低栅源和栅漏漏电流对器件的不利影响。
附图说明
图1是常规底电极结构OTFT器件剖面示意图;
图2是常规顶电极结构OTFT器件剖面示意图;
图3是底电极结构OTFT的输出特性曲线;
图4是顶电极结构OTFT的输出特性曲线;
图5是本发明电极结构OTFT器件剖面示意图;
图6是根据本发明的电极结构的OTFT器件工艺流程图;
图7是根据本发明制备的OTFT器件的输出特性曲线。
具体实施方式
如图5所示,在衬底1上溅射或蒸发一层金属膜并光刻成栅极形状2。在栅极上面溅射一层有机材料、无机材料或铁电材料作为第一栅绝缘层3,在第一绝缘层3上溅射一层有机高分子材料或无机材料作为第二绝缘层4。第一绝缘层3和第二绝缘层4的介电常数不同,一般情况下,第一绝缘层3的介电常数比第二绝缘层4的介电常数高3倍以上。接着在第二绝缘层4上形成源电极5和漏电极6,沟道宽度为1000微米,沟道长度为100微米。然后,在第一绝缘层3上和源电极5及漏电极6上形成半导体有源层。本发明采用具有高介电常数的绝缘材料作为栅绝缘膜和采用具有低介电常数的绝缘材料来垫高源漏电极的位置的结构,有利于增大晶体管的开态电流和降低晶体管的开启电压,同时减小栅源、栅漏交叠处的漏电流和降低栅源、栅漏交叠处的寄生电容。这样的结构使得靠近源极的沟道区与源极距离增大从而使得源极相对于沟道区的电位增大,有利于载流子从源、漏电极注入有机半导体沟道区,提高OTFT的性能。
实施例1
如图6所示,在7059玻璃衬底1上用射频磁控溅射方法镀上一层Ta金属膜(溅射的条件为:本底真空2×10-3Pa;Ar气气压1Pa;射频功率500W;衬底温度100度)并光刻成栅极形状2。在栅极上面用直流磁控溅射方法连续溅射一层400纳米的Ta2O5和一层300纳米的SiO2(反应溅射:本底真空2×10-3Pa;O2气压0.9Pa;直流功率500W;衬底温度100度)分别作为栅绝缘层3和第二绝缘层4。接着涂光刻胶、曝光、显影,然后以光刻胶为漏板在10-5Pa的高真空下热蒸发一层100纳米的金(Au),把样品放入丙酮溶剂中剥离掉非图形区的金形成源电极5和漏电极6。沟道宽度为1000微米,沟道长度为100微米。然后以源漏电极为掩模干法刻蚀(干法刻蚀条件:六氟化硫气体流量50SCCM,射频功率100W)以去除未被源漏电极覆盖的SiO2层。最后在10-5Pa的高真空下加热盛有CuPc粉末的石英舟,使之升华到衬底上形成半导体有源层(厚度300纳米)并经光刻和干法刻蚀成岛状7(干法刻蚀条件:氧气流量100SCCM,射频功率100W)。该晶体管在栅极偏压为-50V时,开态电流为6微安。开关电流比大于104。见附图7。
实施例2
如图6所示,在柔性塑料衬底1上用射频磁控溅射方法镀上一层MoW合金膜(溅射方式为Mo靶和W靶共溅射,溅射的条件为:本底真空2×10-3Pa;Ar气气压1Pa;射频功率500W;衬底温度100度)并光刻成栅极形状2。在栅极上面用直流磁控溅射方法溅射一层500纳米的Ta2O5(反应溅射:本底真空2×10-3Pa;O2气压0.9Pa;直流功率500W;衬底温度100度)作为栅绝缘层3,随后旋涂一层300纳米的聚甲基丙烯酸甲脂(PMMA)作为第二绝缘层4。接下来涂光刻胶、曝光、显影,然后以光刻胶为漏板在10-5Pa的高真空下热蒸发一层100纳米的银(Ag),把样品放入丙酮溶剂中剥离掉非图形区的银形成源电极5和漏电极6。沟道宽度为1000微米,沟道长度为100微米。然后以源漏电极为掩模干法刻蚀(干法刻蚀条件:氧气流量50SCCM,射频功率100W)以去除未被源漏电极覆盖的PMMA层。最后在10-5Pa的高真空下加热盛有NiPc粉末的石英舟,使之升华到衬底上形成半导体有源层(厚度400纳米)并经光刻和干法刻蚀成岛状7(干法刻蚀条件:氧气流量100SCCM,射频功率100W)。该晶体管在栅极偏压为-50V时,开态电流为2微安。开关电流比大于104
实施例3
如图6所示,在柔性塑料衬底1上用射频磁控溅射方法镀上一层铬金属膜(溅射方式为铬靶溅射,溅射的条件为:本底真空2×10-3Pa;Ar气气压1Pa;射频功率500W;衬底温度100度)并光刻成栅极形状2。在栅极上面用直流磁控溅射方法溅射一层500纳米的TiO2(反应溅射:本底真空2×10-3Pa;O2气压0.9Pa;直流功率500W;衬底温度150度)作为栅绝缘层3,随后旋涂一层300纳米的聚酰亚胺作为第二绝缘层4。接下来在10-5Pa的高真空下热蒸发一层100纳米的铝(AL),再涂光刻胶、曝光、显影,然后再光刻成源电极5和漏电极6。沟道宽度为1000微米,沟道长度为100微米。然后以源漏电极为掩模干法刻蚀(干法刻蚀条件:氧气流量50SCCM,射频功率100W)以去除未被源漏电极覆盖的聚酰亚胺层。最后在10-5Pa的高真空下加热盛有氟代酞箐铜粉末的石英舟,使之升华到衬底上形成半导体有源层(厚度400纳米)并经光刻和干法刻蚀成岛状7(干法刻蚀条件:氧气流量100SCCM,射频功率100W)。该晶体管在栅极偏压为50V时,开态电流为8微安。开关电流比大于105
本发明不限于上述实施例。一般来说,本专利所公开的有机晶体管可以加工形成二维和三维的集成器件中的元件。这些集成器件可能应用在柔性集成电路、有源矩阵显示和传感器等方面。使用基于本发明的薄膜晶体管元件可以低温加工。加工本发明的薄膜晶体管不限于传统的光刻工艺,也可以采用打印、印刷等加工方法。

Claims (16)

1.一种有机薄膜晶体管,包括衬底(1)、在衬底(1)上形成的栅极(2),在栅极上面形成栅绝缘层,在绝缘层上形成源电极(5)和漏电极(6),在源电极(5)及漏电极(6)上形成半导体有源层(7),其特征在于所述的绝缘层为不同介电常数的第一绝缘层(3)和第二绝缘层(4)。
2.根据权利要求1所述的有机薄膜晶体管,其特征在于所述第一绝缘层(3)的介电常数高于第二绝缘层(4)。
3.根据权利要求2所述的有机薄膜晶体管,其特征在于所述第一绝缘层(3)的介电常数比第二绝缘层(4)的介电常数高3倍以上。
4.根据权利要求1所述的有机薄膜晶体管,其特征在于所述第一绝缘层(3)的材料为有机材料、无机材料或铁电材料。
5.根据权利要求4所述的有机薄膜晶体管,其特征在于所述的有机材料是聚偏氟乙烯。
6.根据权利要求4所述的有机薄膜晶体管,其特征在于所述的无机材料是金属氧化物:Ta2O5、AL2O3、TiO2
7.根据权利要求4所述的有机薄膜晶体管,其特征在于所述的铁电材料是钛酸钡。
8.根据权利要求1所述的有机薄膜晶体管,其特征在于所述第二绝缘层(4)的材料为有机高分子材料或无机材料。
9.根据权利要求8所述的有机薄膜晶体管,其特征在于所述的有机高分子材料是PMMA或聚酰氩胺或环氧树脂。
10.根据权利要求8所述的有机薄膜晶体管,其特征在于所述的无机材料是SiO2或SiNx
11.根据权利要求1所述的有机薄膜晶体管,其特征在于所述的有机半导体层(7)是N型半导体材料或P型半导体材料。
12.根据权利要求11所述的有机薄膜晶体管,其特征在于所述的N型半导体材料是氟代酞箐铜、氟代酞箐铬、氟代酞箐锌、自由氟代酞箐中的一种,也可以是两种以上混合或共晶。
13.根据权利要求11所述的有机薄膜晶体管,其特征在于所述的P型半导体材料是酞箐铜、酞箐镍、酞箐锌和自由酞箐中的一种,也可以是两种以上混合或共晶。
14.根据权利要求1所述的有机薄膜晶体管,其特征在于所述有机半导体材料(7)是高分子聚合物。
15.根据权利要求14所述的有机薄膜晶体管,其特征在于所述高分子聚合物是聚噻吩。
16.一种有机薄膜晶体管的制备方法,主要包括以下步骤:
(1)在衬底上溅射或蒸发一层金属(Ta、Ti、W、MO等)并光刻成栅电极。
(2)溅射或蒸发一层栅绝缘膜(Ta2O5、Al2O3、TiO2、BZT等)和旋涂一层高分子聚合物(聚甲基丙烯酸甲脂、聚酰亚胺、聚乙烯醇、聚偏氟乙烯等)或溅射或蒸发一层低介电无机膜(SiO2、SiNx等)作为双栅绝缘膜。
(3)真空热蒸发一层金属(Au、Ag、Mo、Al等)并光刻成源、漏电极。
(4)以源、漏电极为掩模用反应性离子刻蚀(RIE)方式干法刻蚀掉沟道区的第二绝缘膜。
(5)真空热蒸发或旋涂有机半导体材料作为有源层并光刻和刻蚀(RIE方式)成型。
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Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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