WO2020232964A1 - 一种薄膜晶体管基板的制备方法 - Google Patents

一种薄膜晶体管基板的制备方法 Download PDF

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WO2020232964A1
WO2020232964A1 PCT/CN2019/112470 CN2019112470W WO2020232964A1 WO 2020232964 A1 WO2020232964 A1 WO 2020232964A1 CN 2019112470 W CN2019112470 W CN 2019112470W WO 2020232964 A1 WO2020232964 A1 WO 2020232964A1
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layer
gate
pattern
layer pattern
etching
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PCT/CN2019/112470
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English (en)
French (fr)
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李子然
章仟益
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/618,676 priority Critical patent/US11862711B2/en
Publication of WO2020232964A1 publication Critical patent/WO2020232964A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the invention relates to the technical field of display panels, in particular to a method for preparing a thin film transistor substrate.
  • TFT with top gate structure Thin Film Transistor (thin film transistor) has lower parasitic capacitance and better electrical characteristics, so it is widely used in display devices.
  • the gate is usually made by a wet etching process, and the gate insulating pattern is made by dry etching.
  • the etching process when the gate is etched by the wet etching process, the etching solution will etch a small distance under the photoresist, which causes the gate to be shorter than the gate insulating pattern by a small distance. That is, the orthographic projections of the gate and gate insulation patterns on the base substrate cannot completely overlap.
  • the active layer pattern under the gate insulating pattern lacking the gate cover is not controlled by the gate, which in turn leads to insufficient turn-on current of the TFT of the top gate structure, which affects the top
  • the electrical characteristics of the gate TFT also affect the display effect of the display device.
  • An object of the present invention is to provide a method for preparing a thin film transistor substrate, which can solve the problem of insufficient turn-on current of the thin film transistor caused by the absence of a gate for a short distance above the edge of the gate insulating layer pattern in the prior art.
  • the present invention provides a method for preparing a thin film transistor substrate, including the following steps:
  • Step S1 providing a substrate, depositing a light shielding layer on the substrate, and forming a light shielding layer pattern after etching;
  • Step S2 deposit a buffer layer and an active layer, and form an active layer pattern after etching
  • Step S3 sequentially deposit a gate insulating layer and a gate layer on the active layer pattern, and form a gate layer pattern after wet etching the gate layer;
  • Step S4 After peeling off the photoresist, dry etching the surface of the gate layer pattern and forming a protective layer on the surface; then dry etching the gate insulating layer to form a gate insulating layer pattern, and Conducting the non-channel region of the active layer pattern;
  • Step S5 deposit an interlayer dielectric layer, and set a first via hole on the interlayer dielectric layer;
  • Step S6 deposit a source and drain layer, and form a source and drain layer pattern after etching
  • Step S7 deposit an organic layer, and set a second via hole on the organic layer;
  • Step S8 deposit a pixel electrode layer, and form the pixel electrode by etching.
  • the dry etching of the gate insulating layer to form a gate insulating layer pattern, and conducting the non-channel region of the active layer pattern includes: using the gate
  • the layer pattern is a mask dry etching the gate insulating layer to form a gate insulating layer pattern, and conducts a non-channel area of the active layer pattern into a conductor.
  • the adjustment of the metal layer compensates for the defect of no gate at a short distance above the edge of the gate insulating layer pattern in the prior art, improves the turn-on current of the thin film transistor, enhances the electrical characteristics of the thin film transistor, and improves the display of the display device effect.
  • the active layer is an oxide semiconductor.
  • the oxide semiconductor is indium gallium zinc oxide.
  • the thickness of the active layer is 400 ⁇ to 600 ⁇ .
  • the material used for the gate insulating layer includes silicon oxide or silicon nitride.
  • a fluorine-based etching gas is used for the dry etching treatment on the surface of the gate layer pattern.
  • the fluorine-based etching gas is nitrogen trifluoride and oxygen.
  • the non-channel region of the active layer is formed by argon or helium ion bombardment to conduct the conductorization.
  • the non-channel region of the active layer pattern is conductively formed by an aluminum or calcium ion implantation method.
  • the thickness of the protective layer ranges from 40 ⁇ to 60 ⁇ .
  • the beneficial effect of the present invention is that the present invention provides a method for preparing a thin film transistor substrate. After sequentially depositing an active layer, a gate insulating layer, and a gate layer, the gate layer is wet-etched to form a gate. Layer pattern, and then generate a protective layer on the surface of the gate layer pattern, and then use the gate layer as a mask to conduct conductive treatment on the gate insulating layer and the exposed active layer.
  • This preparation method can ensure the gate
  • the orthographic projection of the pattern of the gate insulating layer and the gate insulating layer on the base substrate completely overlaps, that is, the entire active layer pattern is under the gate insulating layer, so that the active layer pattern area can be controlled by the gate layer, which makes up for the existing In the technology, there is no gate defect for a short distance above the edge of the gate insulating layer pattern, which increases the turn-on current of the thin film transistor, enhances the electrical characteristics of the thin film transistor, and improves the display effect of the display device.
  • FIG. 1 is a flow chart of a method for preparing a thin film transistor substrate provided by Embodiment 1 of the present invention
  • FIG. 2 is a schematic diagram of the structure of the thin film transistor substrate in step S1 in the manufacturing method provided by the embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of the structure of the thin film transistor substrate in step S2 in the manufacturing method provided by the embodiment 1 of the present invention
  • FIG. 4 is a schematic diagram of the structure of the thin film transistor substrate in step S3 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of the structure of the thin film transistor substrate in step S4 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor substrate in step S5 of the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the thin film transistor substrate in step S6 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the thin film transistor substrate at step S7 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the thin film transistor substrate in step S8 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 1 shows a flow chart of the method for preparing a thin film transistor substrate provided in this embodiment, including the following steps:
  • Step S1 providing a substrate 100, depositing a light shielding layer 11 on the substrate 100, and forming a light shielding layer pattern after etching;
  • FIG. 2 is a schematic diagram of the structure of the thin film transistor substrate in step S1 of the manufacturing method provided by this embodiment.
  • Step S2 deposit the buffer layer 12 and the active layer 13, and form the active layer pattern after etching;
  • FIG. 3 shows a schematic diagram of the structure of the thin film transistor substrate in step S2 of the manufacturing method provided by this embodiment.
  • the active layer 13 may specifically be indium tin oxide (ITO, Indium Tin Oxides) or indium zinc oxide (IZO, Idium Zinc Oxides) or indium gallium zinc oxide (IGZO, Indium Zinc Oxides). Gallium Zinc Oxides), etc., are not limited here.
  • the thickness of the active layer 13 is 400 ⁇ to 600 ⁇ .
  • Step S3 sequentially deposit a gate insulating layer 14 and a gate layer 15 on the pattern of the active layer 13, and wet-etch the gate layer 15 to form a gate layer pattern;
  • FIG. 4 shows a schematic diagram of the structure of the thin film transistor substrate in step S3 of the manufacturing method provided in this embodiment.
  • the material used for the gate insulating layer 14 can be silicon oxide or silicon nitride, which is not limited here.
  • Step S4 After stripping off the photoresist, dry etching the surface of the gate layer 15 pattern and forming a protective layer 151 on the surface; then dry etching the gate insulating layer 14 with the gate layer 15 pattern as a mask The gate insulating layer 14 is patterned, and the non-channel region 131 of the active layer 13 pattern is conductive;
  • FIG. 5 shows a schematic diagram of the structure of the thin film transistor substrate in step S4 of the manufacturing method provided in this embodiment.
  • the protective layer 151 is used to protect the pattern of the gate layer 15 to prevent the pattern of the gate layer 15 from being etched during subsequent etching of the gate insulating layer 14 and conducting the active layer 13.
  • the thickness of the protective layer 151 ranges from 40 ⁇ to 60 ⁇ .
  • a fluorine-based etching gas specifically nitrogen trifluoride and oxygen, is used for the dry etching process on the pattern surface of the gate layer 15.
  • Conducting the patterned non-channel region 131 of the active layer 13 can be formed by argon or helium ion bombardment, or can be formed by aluminum or calcium ion implantation, which is not limited here.
  • the gate insulating layer 14 is dry-etched using the gate layer 15 pattern as a mask to form the gate insulating layer 14 pattern, and the non-channel region 131 of the active layer 13 pattern is conductive.
  • This preparation step can ensure the gate insulation
  • the widths of the layer 14 and the gate layer are equal, and the orthographic projections of the gate layer 15 and the gate insulating layer 14 on the substrate layer 100 completely coincide, that is, the entire active layer 13 is under the gate insulating layer 14, so that the active layer 13 All regions can be controlled by the gate layer, which compensates for the defect that there is no gate for a short distance above the edge of the gate insulating layer pattern in the prior art, improves the turn-on current of the thin film transistor, and enhances the electrical characteristics of the thin film transistor.
  • the display effect of the display device is dry-etched using the gate layer 15 pattern as a mask to form the gate insulating layer 14 pattern, and the non-channel region 131 of the active layer 13 pattern is conductive.
  • Step S5 deposit the interlayer dielectric layer 16, and set the first via 161 on the interlayer dielectric layer 16;
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor substrate in step S5 of the manufacturing method provided by this embodiment.
  • Step S6 deposit the source and drain layer 17, and form the pattern of the source and drain layer 17 after etching
  • FIG. 7 is a schematic diagram of the structure of the thin film transistor substrate in step S6 of the manufacturing method provided by this embodiment.
  • Step S7 deposit an organic layer 18, and provide a second via 181 on the organic layer;
  • FIG. 8 is a schematic diagram of the structure of the thin film transistor substrate in step S7 of the manufacturing method provided by this embodiment.
  • Step S8 deposit a pixel electrode layer, and form the pixel electrode 19 by etching
  • FIG. 9 is a schematic diagram of the structure of the thin film transistor substrate in step S8 of the manufacturing method provided by this embodiment.
  • the beneficial effect of the present invention is that the present invention provides a method for preparing a thin film transistor substrate. After sequentially depositing an active layer, a gate insulating layer and a gate layer, the gate layer is wet-etched to form a gate layer pattern, and then the gate layer is patterned. A protective layer is formed on the surface of the electrode pattern, and then the gate insulating layer is etched and the exposed active layer is conductive using the gate layer as a mask.
  • This preparation method can ensure the gate layer and the gate insulating layer
  • the orthographic projection of the pattern on the base substrate completely overlaps, that is, the entire active layer pattern is under the gate insulating layer, so that the active layer pattern area can be controlled by the gate layer, which makes up for the gate insulating layer in the prior art. There is no gate defect for a short distance above the edge of the pattern, which increases the turn-on current of the thin film transistor, enhances the electrical characteristics of the thin film transistor, and improves the display effect of the display device.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种薄膜晶体管基板的制备方法，包括以下步骤：提供一基板（100），在基板上沉积遮光层（11），刻蚀后形成遮光层图案；沉积缓冲层（12）和有源层（13），刻蚀后形成有源层图案；在有源层图案上依次沉积栅极绝缘层（14）和栅极层（15），对栅极层湿法刻蚀后形成栅极层图案；剥离掉光阻后，对栅极层图案表面干法刻蚀处理并在其表面生成保护层（151）；然后以栅极层为掩模版干法刻蚀栅极绝缘层形成栅极绝缘层图案，并且对有源层图案非沟道区域进行导体化。此制备方法可以保证栅极层与栅极绝缘层图案在衬底基板上的正投影完全重合，使得有源层图案区域均可以被栅极层调控，提升了薄膜晶体管的开启电流，增强了薄膜晶体管的电学特性。

Description

一种薄膜晶体管基板的制备方法 技术领域
本发明涉及显示面板技术领域，特别涉及一种薄膜晶体管基板的制备方法。
 背景技术
顶栅结构的TFT（Thin Film Transistor，薄膜晶体管)具有较低的寄生电容，较优良的电学特性，因此被广泛应用于显示装置中。
现有技术中在制作顶栅结构的TFT时，由于要采用到栅极与栅极绝缘图案的自对准工艺，而栅极通常采用湿法刻蚀工艺制作，栅极绝缘图案通过干法刻蚀工艺制作，在利用湿法刻蚀工艺刻蚀栅极时，由于刻蚀液会在光刻胶下面多刻蚀一小段距离，这样导致栅极相比栅极绝缘图案短出一小段距离，即栅极与栅极绝缘图案在衬底基板上的正投影不能完全重合。由于两侧均有一小段距离没有栅极在上方，导致缺少栅极覆盖的栅极绝缘图案下方的有源层图案没有被栅极调控，进而导致顶栅结构的TFT的开启电流不足，从而影响顶栅TFT的电学特性，使得显示装置的显示效果也受到影响。
因此，确有必要来开发一种新型的薄膜晶体管基板的制备方法，以克服现有技术的缺陷。
 技术问题
本发明的一个目的是提供一种薄膜晶体管基板的制备方法，其能够解决现有技术中栅极绝缘层图案边缘处的上方一小段距离无栅极导致的薄膜晶体管的开启电流不足的问题。
 技术解决方案
为实现上述目的，本发明提供一种薄膜晶体管基板的制备方法，包括以下步骤：
步骤S1：提供一基板，在所述基板上沉积遮光层，刻蚀后形成遮光层图案；
步骤S2：沉积缓冲层和有源层，刻蚀后形成有源层图案；
步骤S3：在所述有源层图案上依次沉积栅极绝缘层和栅极层，对所述栅极层湿法刻蚀后形成栅极层图案；
步骤S4：剥离掉光阻后，对所述栅极层图案表面干法刻蚀处理并在其表面生成保护层；然后干法刻蚀所述栅极绝缘层形成栅极绝缘层图案，并且对所述有源层图案非沟道区域进行导体化；
步骤S5：沉积层间介质层，在所述层间介质层上设置第一过孔；
步骤S6：沉积源漏极层，刻蚀后形成源漏极层图案；
步骤S7：沉积有机层，在所述有机层上设置第二过孔；
步骤S8：沉积像素电极层，通过刻蚀形成像素电极。
其中，在所述步骤S4中，所述干法刻蚀所述栅极绝缘层形成栅极绝缘层图案，并且对所述有源层图案非沟道区域进行导体化包括：以所述栅极层图案为掩模版干法刻蚀所述栅极绝缘层形成栅极绝缘层图案，并且对所述有源层图案非沟道区域进行导体化。此制备方法可以保证栅极层与栅极绝缘层图案在衬底基板上的正投影完全重合，即整个有源层图案均在栅极绝缘层下方，使得有源层图案区域均可以被栅极金属层调控，弥补了现有技术中栅极绝缘层图案边缘处的上方一小段距离无栅极的缺陷，提升了薄膜晶体管的开启电流，增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
进一步的，在其他实施方式中，其中所述有源层为氧化物半导体。
进一步的，在其他实施方式中，其中所述氧化物半导体为铟镓锌氧化物。
进一步的，在其他实施方式中，其中所述有源层的厚度为400Å～600Å。
进一步的，在其他实施方式中，其中所述栅极绝缘层采用的材料包括氧化硅或氮化硅。
进一步的，在其他实施方式中，其中在所述步骤S4中，对所述栅极层图案表面干法刻蚀处理采用氟系刻蚀气体。
进一步的，在其他实施方式中，其中所述氟系刻蚀气体为三氟化氮和氧气。
进一步的，在其他实施方式中，其中在所述步骤S4中，对有源层非沟道区域进行导体化采用氩或氦离子轰击的方法形成。
进一步的，在其他实施方式中，其中在所述步骤S4中，对所述有源层图案非沟道区域进行导体化采用铝或钙离子注入的方法形成。
进一步的，在其他实施方式中，其中所述保护层的厚度范围为40Å～60Å。
 有益效果
相对于现有技术，本发明的有益效果在于：本发明提供一种薄膜晶体管基板的制备方法，依次沉积有源层、栅极绝缘层和栅极层后，湿法蚀刻栅极层形成栅极层图案，然后对栅极层图案进行表面生成一层保护层，之后以栅极层为掩模版对栅极绝缘层蚀刻及裸漏的有源层进行导体化处理，此制备方法可以保证栅极层与栅极绝缘层图案在衬底基板上的正投影完全重合，即整个有源层图案均在栅极绝缘层下方，使得有源层图案区域均可以被栅极层调控，弥补了现有技术中栅极绝缘层图案边缘处的上方一小段距离无栅极的缺陷，提升了薄膜晶体管的开启电流，增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1提供的薄膜晶体管基板的制备方法的流程图；
图2为本发明实施例1提供的制备方法中步骤S1时薄膜晶体管基板的结构示意图；
图3为本发明实施例1提供的制备方法中步骤S2时薄膜晶体管基板的结构示意图；
图4为本发明实施例1提供的制备方法中步骤S3时薄膜晶体管基板的结构示意图；
图5为本发明实施例1提供的制备方法中步骤S4时薄膜晶体管基板的结构示意图；
图6为本发明实施例1提供的制备方法中步骤S5时薄膜晶体管基板的结构示意图；
图7为本发明实施例1提供的制备方法中步骤S6时薄膜晶体管基板的结构示意图；
图8为本发明实施例1提供的制备方法中步骤S7时薄膜晶体管基板的结构示意图；
图9为本发明实施例1提供的制备方法中步骤S8时薄膜晶体管基板的结构示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
实施例1
本实施例提供一种薄膜晶体管基板的制备方法，请参阅图1，图1所示为本实施例提供的薄膜晶体管基板的制备方法的流程图，包括以下步骤：
步骤S1：提供一基板100，在基板100上沉积遮光层11，刻蚀后形成遮光层图案；
请参阅图2，图2所示为本实施例提供的制备方法中步骤S1时薄膜晶体管基板的结构示意图。
步骤S2：沉积缓冲层12和有源层13，刻蚀后形成有源层图案；
请参阅图3，图3所示为本实施例提供的制备方法中步骤S2时薄膜晶体管基板的结构示意图。
在本实施例中，有源层13具体可以采用氧化铟锡 (ITO,Indium Tin  Oxides)或氧化铟锌(IZO,Idium Zinc Oxides)或氧化铟镓锌(IGZO,Indium Gallium Zinc Oxides) 等制作，在此不做限定。
在本实施例中，有源层13的厚度为400Å～600Å。
步骤S3：在有源层13图案上依次沉积栅极绝缘层14和栅极层15，对栅极层15湿法刻蚀后形成栅极层图案；
请参阅图4，图4所示为本实施例提供的制备方法中步骤S3时薄膜晶体管基板的结构示意图。
在本实施例中，栅极绝缘层14采用的材料可以氧化硅或氮化硅，在此不做限定。
步骤S4：剥离掉光阻后，对栅极层15图案表面干法刻蚀处理并在其表面生成保护层151；然后以栅极层15图案为掩模版干法刻蚀栅极绝缘层14形成栅极绝缘层14图案，并且对有源层13图案非沟道区域131进行导体化；
请参阅图5，图5所示为本实施例提供的制备方法中步骤S4时薄膜晶体管基板的结构示意图。
其中保护层151是为了保护栅极层15图案的，防止栅极层15图案在后续刻蚀栅极绝缘层14和对有源层13进行导体化时会被刻蚀到。
在本实施例中，保护层151的厚度范围为40Å～60Å。
对栅极层15图案表面干法刻蚀处理采用氟系刻蚀气体，具体为三氟化氮和氧气。
对有源层13图案非沟道区域131进行导体化可以采用氩或氦离子轰击的方法形成，也可以采用铝或钙离子注入的方法形成，在此不做限定。
以栅极层15图案为掩模版干法刻蚀栅极绝缘层14形成栅极绝缘层14图案，并且对有源层13图案非沟道区域131进行导体化，此制备步骤可以保证栅极绝缘层14和栅极层宽度相等，栅极层15与栅极绝缘层14在基板层100上的正投影完全重合，即整个有源层13均在栅极绝缘层14下方，使得有源层13区域均可以被栅极层调控，弥补了现有技术中栅极绝缘层图案边缘处的上方一小段距离无栅极的缺陷，提升了薄膜晶体管的开启电流，增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
步骤S5：沉积层间介质层16，在层间介质层16上设置第一过孔161；
请参阅图6，图6所示为本实施例提供的制备方法中步骤S5时薄膜晶体管基板的结构示意图。
步骤S6：沉积源漏极层17，刻蚀后形成源漏极层17图案；
请参阅图7，图7所示为本实施例提供的制备方法中步骤S6时薄膜晶体管基板的结构示意图。
步骤S7：沉积有机层18，在所述有机层上设置第二过孔181；
请参阅图8，图8所示为本实施例提供的制备方法中步骤S7时薄膜晶体管基板的结构示意图。
步骤S8：沉积像素电极层，通过刻蚀形成像素电极19；
请参阅图9，图9所示为本实施例提供的制备方法中步骤S8时薄膜晶体管基板的结构示意图。
本发明的有益效果在于：本发明提供一种薄膜晶体管基板的制备方法，依次沉积有源层、栅极绝缘层和栅极层后，湿法蚀刻栅极层形成栅极层图案，然后对栅极层图案进行表面生成一层保护层，之后以栅极层为掩模版对栅极绝缘层蚀刻及裸漏的有源层进行导体化处理，此制备方法可以保证栅极层与栅极绝缘层图案在衬底基板上的正投影完全重合，即整个有源层图案均在栅极绝缘层下方，使得有源层图案区域均可以被栅极层调控，弥补了现有技术中栅极绝缘层图案边缘处的上方一小段距离无栅极的缺陷，提升了薄膜晶体管的开启电流，增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种薄膜晶体管基板的制备方法，其中，包括以下步骤：
    步骤S1：提供一基板，在所述基板上沉积遮光层，刻蚀后形成遮光层图案；
    步骤S2：沉积缓冲层和有源层，刻蚀后形成有源层图案；
    步骤S3：在所述有源层图案上依次沉积栅极绝缘层和栅极层，对所述栅极层湿法刻蚀后形成栅极层图案；
    步骤S4：剥离掉光阻后，对所述栅极层图案表面干法刻蚀处理并在其表面生成保护层；然后干法刻蚀所述栅极绝缘层形成栅极绝缘层图案，并且对所述有源层图案非沟道区域进行导体化；
    步骤S5：沉积层间介质层，在所述层间介质层上设置第一过孔；
    步骤S6：沉积源漏极层，刻蚀后形成源漏极层图案；
    步骤S7：沉积有机层，在所述有机层上设置第二过孔；
    步骤S8：沉积像素电极层，通过刻蚀形成像素电极。
  2. 根据权利要求1所述的制备方法，其中，在所述步骤S4中，对所述栅极层图案表面干法刻蚀处理采用氟系刻蚀气体。
  3. 根据权利要求2所述的制备方法，其中，所述氟系刻蚀气体为三氟化氮和氧气。
  4. 根据权利要求1所述的制备方法，其中，在所述步骤S4中，对有源层非沟道区域进行导体化采用氩或氦离子轰击的方法形成。
  5. 根据权利要求1所述的制备方法，其中，对所述有源层图案非沟道区域进行导体化采用铝或钙离子注入的方法形成。
  6. 根据权利要求1所述的制备方法，其中，所述有源层为氧化物半导体。
  7. 根据权利要求6所述的制备方法，其中，所述氧化物半导体为铟镓锌氧化物。
  8. 根据权利要求1所述的制备方法，其中，所述有源层的厚度为400Å～600Å。
  9. 根据权利要求1所述的制备方法，其中，所述保护层的厚度范围为40Å～60Å。
  10. 根据权利要求1所述的制备方法，其中，所述栅极绝缘层采用的材料包括氧化硅或氮化硅。
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Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
CN110190031B (zh) 2019-05-17 2021-07-23 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管基板的制备方法
CN110600517B (zh) * 2019-09-16 2021-06-01 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN110797349B (zh) * 2019-10-15 2022-04-05 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管基板及其制备方法
CN111463267A (zh) * 2020-04-08 2020-07-28 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840865A (zh) * 2010-05-12 2010-09-22 深圳丹邦投资集团有限公司 一种薄膜晶体管的制造方法及用该方法制造的晶体管
CN103531641A (zh) * 2013-06-27 2014-01-22 友达光电股份有限公司 薄膜晶体管及其制造方法
CN105529366A (zh) * 2016-02-05 2016-04-27 深圳市华星光电技术有限公司 金属氧化物薄膜晶体管及其制造方法
CN109742029A (zh) * 2019-01-08 2019-05-10 合肥鑫晟光电科技有限公司 薄膜晶体管及制备方法、阵列基板的制备方法及显示装置
CN110190031A (zh) * 2019-05-17 2019-08-30 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管基板的制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4036917B2 (ja) * 1997-05-30 2008-01-23 シャープ株式会社 薄膜トランジスタの製造方法
US9331206B2 (en) * 2011-04-22 2016-05-03 Semiconductor Energy Laboratory Co., Ltd. Oxide material and semiconductor device
US9533332B2 (en) * 2011-10-06 2017-01-03 Applied Materials, Inc. Methods for in-situ chamber clean utilized in an etching processing chamber
CN103730346B (zh) * 2013-12-24 2016-08-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
US10468434B2 (en) * 2016-04-08 2019-11-05 Innolux Corporation Hybrid thin film transistor structure, display device, and method of making the same
CN106158978B (zh) * 2016-07-08 2019-05-21 武汉华星光电技术有限公司 薄膜晶体管、阵列基板及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840865A (zh) * 2010-05-12 2010-09-22 深圳丹邦投资集团有限公司 一种薄膜晶体管的制造方法及用该方法制造的晶体管
CN103531641A (zh) * 2013-06-27 2014-01-22 友达光电股份有限公司 薄膜晶体管及其制造方法
CN105529366A (zh) * 2016-02-05 2016-04-27 深圳市华星光电技术有限公司 金属氧化物薄膜晶体管及其制造方法
CN109742029A (zh) * 2019-01-08 2019-05-10 合肥鑫晟光电科技有限公司 薄膜晶体管及制备方法、阵列基板的制备方法及显示装置
CN110190031A (zh) * 2019-05-17 2019-08-30 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管基板的制备方法

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