WO2017008347A1 - 阵列基板、阵列基板的制造方法及显示装置 - Google Patents

阵列基板、阵列基板的制造方法及显示装置 Download PDF

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WO2017008347A1
WO2017008347A1 PCT/CN2015/085780 CN2015085780W WO2017008347A1 WO 2017008347 A1 WO2017008347 A1 WO 2017008347A1 CN 2015085780 W CN2015085780 W CN 2015085780W WO 2017008347 A1 WO2017008347 A1 WO 2017008347A1
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layer
oxide semiconductor
semiconductor layer
oxide
array substrate
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PCT/CN2015/085780
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English (en)
French (fr)
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李文辉
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深圳市华星光电技术有限公司
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Priority to US14/904,847 priority Critical patent/US20170170213A1/en
Publication of WO2017008347A1 publication Critical patent/WO2017008347A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of manufacturing array substrates, and in particular to an array substrate, a method for fabricating an array substrate, and a display device.
  • the array substrate includes a gate line and a gate, a semiconductor layer, a source and a drain, an etch barrier layer, an insulating layer, and a pixel electrode.
  • the two metal layers In the manufacturing process, due to process accuracy and deviation (such as an exposure stage), The two metal layers must have a certain overlap width with the etch barrier layer when forming the source and drain electrodes, so as to ensure that the second metal layer can completely cover the semiconductor layer when the process is biased, so that the channel length formed by the semiconductor layer is large.
  • the conductivity is deteriorated, resulting in a decrease in pixel aperture ratio.
  • the invention provides a method for manufacturing an array substrate, which avoids a large channel length formed by a semiconductor layer, deteriorates electrical conductivity, and ensures an aperture ratio of the array substrate.
  • the invention provides a method for manufacturing an array substrate, and the method for manufacturing the array substrate comprises:
  • a photoresist layer is disposed on the oxide semiconductor layer, a width of the photoresist layer is smaller than a width of the oxide semiconductor layer, and a portion of the oxide semiconductor layer projected by the photoresist layer is opposite a channel region, and a channel region on the oxide semiconductor layer is a first oxide semiconductor layer and a second oxide semiconductor layer;
  • etch barrier layer Forming an etch barrier layer on the substrate forming the gate insulating layer, the channel region, the first oxide conductor layer, and the second oxide conductor layer; wherein the first oxide conductor layer and the second oxide conductor layer are partially exposed Etching barrier layer;
  • the plasma treatment implants the first oxide semiconductor layer and the second oxide semiconductor layer with nitrogen gas or ammonia gas.
  • the material of the oxide conductor layer is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide (ZnSnO).
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • InZnO indium zinc oxide
  • ZnSnO zinc tin oxide
  • the material of the etching barrier layer is silicon oxide.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum and a combination thereof
  • the material of the second metal layer is selected from the group consisting of copper, tungsten, chromium, aluminum and combinations thereof.
  • the method for manufacturing an array substrate further includes the step of patterning the insulating protective layer by an insulating protective layer formed on the substrate and the patterned second metal layer.
  • the gate insulating layer and the insulating protective layer are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • the gate insulating layer and the etch barrier layer are formed by a patterning process.
  • the invention provides an array substrate, the array substrate comprising:
  • first oxide semiconductor layer and a second oxide semiconductor layer wherein the first oxide semiconductor layer and the second oxide semiconductor layer are respectively connected to both sides of the channel region, and are disposed in the same plane as the channel region
  • the channel region, the first oxide semiconductor layer and the second oxide semiconductor layer collectively cover the gate
  • An etch barrier layer is disposed on the substrate to cover the gate insulating layer and the channel region;
  • a source and a drain disposed on the etch stop layer, the source and the drain being located at two sides of the channel region, the source covering and contacting the first oxide semiconductor layer, the drain Covering and contacting the second oxide semiconductor layer.
  • the present invention provides a display device including the array substrate.
  • an oxide semiconductor layer is formed on a gate insulating layer, and a portion of the oxide semiconductor layer is shielded by a photoresist layer as a channel region, and two oxide semiconductors of the channel region are plasma-treated.
  • the pole and drain contacts simultaneously reduce the overall length of the channel region, thereby reducing the size of the array substrate to increase the aperture ratio and energization performance of the array substrate.
  • FIG. 1 is a flow chart of a method of fabricating an array substrate in accordance with a preferred embodiment of the present invention.
  • FIG. 2 to FIG. 9 are schematic cross-sectional views of an array substrate in various manufacturing processes of the array substrate method according to a preferred embodiment of the present invention.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the array substrate belongs to an oxide semiconductor structure transistor.
  • the patterning refers to a patterning process, which may include a mask process, or a mask process and an etching step, and may also include printing, Other processes for forming a predetermined pattern such as inkjet;
  • the reticle process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the manufacturing method of the manufacturing method of the array substrate includes the following steps.
  • a substrate 10 is provided.
  • the substrate 10 is a glass substrate. It can be understood that in other embodiments, the substrate 10 is not limited to a glass substrate.
  • a first metal layer (not shown) is formed on the substrate 10, and the first metal 12 layer is patterned by a patterning process to include a pattern including the gate electrode 12.
  • the first metal layer is formed on one surface of the substrate 10 to serve as the gate electrode 12 of the array substrate 10.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the gate electrode 12 is patterned by patterning the first metal layer by a prior art patterning process such as photoresisting, exposure, and development.
  • a gate insulating layer 13 is formed on the substrate 10 and the patterned first metal layer.
  • the gate insulating layer 13 covers the surface of the substrate 10 and the gate 12 .
  • the gate insulating layer 130 is formed on a surface of the substrate 10 not covering the first metal layer and on the gate electrode 12.
  • the material of the gate insulating layer 13 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • step S4 an oxide semiconductor layer 14 orthographically projected on the gate electrode 12 is formed on the gate insulating layer 13; wherein the width L1 of the oxide semiconductor layer 14 is The gate 12 has the same width L2.
  • the material of the oxide conductor layer 14 is indium gallium zinc oxide (IGZO), oxygen Zinc (ZnO), indium zinc oxide (InZnO) or zinc tin oxide (ZnSnO).
  • the oxide conductor layer 14 is made of indium gallium zinc oxide (IGZO) having an oxygen content of 0-%10.
  • a photoresist layer 15 is disposed on the oxide semiconductor layer 14.
  • the photoresist layer 15 is projected onto the oxide semiconductor layer 14, and the oxide semiconductor layer is A portion of the 15th portion opposite to the projection of the photoresist layer is a channel region 16, and the channel region 16 on the oxide semiconductor layer 14 is a first oxide semiconductor layer 141 and a second oxide semiconductor. Layer 142.
  • the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142 provided with the photoresist layer 15 are plasma-treated to expose the projection of the photoresist layer 15.
  • the oxide semiconductor layer 141 and the second oxide semiconductor layer 142 are converted into the first oxide conductor layer 17 and the second oxide conductor layer 18.
  • the plasma treatment implants the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142 with nitrogen or ammonia gas to cause oxygen in the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142. Reduce the amount and reduce the resistance.
  • step S7 the photoresist layer 15 is removed.
  • the purpose is to expose the channel region.
  • step S8 an etch stop layer 21 is formed on the substrate on which the gate insulating layer, the channel region, the first oxide conductor layer 19, and the second oxide conductor layer 20 are formed.
  • the material of the etch barrier layer 21 is silicon oxide.
  • the etch stop layer 21 covers the channel region 16 and exposes most of the first oxide conductor layer 17 and the second oxide conductor layer 18.
  • a second metal layer (not shown) is formed on the substrate 10 , and the second metal layer is patterned to form a source 19 and a drain 20 of the array substrate.
  • the source 19 is in contact with the first oxide conductor layer 17, and the drain 20 is in contact with the second oxide conductor layer 18.
  • the channel region 16 is located between the source 19 and the drain 20.
  • the second metal layer and the first oxide conductor layer 17, the second oxide conductor layer 18, and the gate insulating layer 13 are sequentially stacked.
  • the second metal layer is patterned by a prior art patterning process to form source 19 and drain 20 as shown.
  • the material of the second metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the source 19 is in contact with the first oxide conductor layer 17, and the drain 20 is in contact with the second oxide conductor layer 18 to form a conduction between the source 19 and the drain 20 of the array substrate.
  • a broken channel which is equivalent to the action of the ohmic contact layer, and the source 19 and the drain 20 can respectively form a good layer through the conductor layer and the channel region 16 underneath. Good ohmic contact, with low resistance, achieves good energization of source 19 to drain 20.
  • the material of the second metal layer is generally a metal material.
  • the present invention is not limited thereto.
  • the material of the second metal layer may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or A stacked layer of metallic material and other conductive materials.
  • step S10 the insulating protective layer is patterned on the substrate 10 and the patterned second metal layer (source 19 and drain 20).
  • the gate insulating layer 13 and the insulating protective layer are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy). Up to this step, the array substrate manufacturing method in this embodiment is completed.
  • the gate insulating layer 13 and the insulating protective layer are made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • the gate insulating layer and the etch barrier layer are formed by a patterning process.
  • the method for fabricating the array substrate of the present invention forms the oxide semiconductor layer 14 on the gate insulating layer 13, and blocks the partial oxide semiconductor layer 15 as the channel region 16 by providing the photoresist layer 15, and the channel region 16 is plasma-treated.
  • the two oxide semiconductor layers 15 form a first oxide conductor layer 17 having a small oxygen content, and the second oxide conductor layer 18 is used for contacting the contact layer with the source electrode 19 and the drain electrode 20 to ensure that the process is generated.
  • the second metal layer is in contact with the source 19 and the drain 20, the overall length of the channel region 16 is reduced, and the size of the array substrate is reduced to increase the aperture ratio and the electrification performance of the array substrate.
  • the present invention also relates to an array substrate manufacturing method, comprising: a substrate, a gate, a gate insulating layer covering the gate; a channel region directly above the gate; the first oxide semiconductor a layer and a second oxide semiconductor layer, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are respectively connected to both sides of the channel region, and are disposed in the same plane as the channel region, the channel region, a first oxide semiconductor layer and a second oxide semiconductor layer collectively covering the gate; an etch barrier layer disposed on the substrate to cover the gate insulating layer and the channel region; a source and a drain on the barrier layer, the source and the drain are located at two sides of the channel region, the source covers and contacts the first oxide semiconductor layer, and the drain covers and contacts the first A dioxide semiconductor layer.
  • the present invention also includes the display device of the array substrate of the above aspect, and the display device formed by the method for manufacturing the array substrate according to the embodiment of the present invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital Photo frames, mobile phones, etc.

Abstract

一种阵列基板的制造方法，其特征在于，所述阵列基板的制造方法包括：在所述基板(10)上形成第一金属层(12)，通过构图工艺使第一金属层(12)形成包括栅极(12)的图案；在上述基板(10)及第一金属层(12)上形成栅极绝缘层(13)，在所述栅极绝缘层(13)上形成正投影于所述栅极(12)的氧化物半导体层(14)；在所述氧化物半导体层(14)上设置光阻层(15)，而位于所述氧化物半导体层(14)上沟道区域(16)两侧为第一氧化物半导体层(141)及第二氧化物半导体层(142)；对设置有光阻层(15)的所述第一氧化物半导体层(141)及第二氧化物半导体层(142)进行等离子处理，移除所述光阻层(15)；在基板(10)上形成蚀刻阻挡层(21)；在所述基板(10)上形成源极(19及漏极(20)，其中，所述源极(19)与第一氧化物导体层(17)接触，所述漏极(20)与第二氧化物导体层(18)接触。

Description

阵列基板、阵列基板的制造方法及显示装置
本发明要求2015年7月16日递交的发明名称为“阵列基板、阵列基板的制造方法及显示装置”的申请号201510419425.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及阵列基板的制造领域，尤其涉及一种阵列基板、阵列基板的制造方法及显示装置。
背景技术
目前广泛应用的Oxide阵列基板采用氧化物半导体作为有源层，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。现有技术中阵列基板包括栅线及栅极，半导体层，源漏极，蚀刻阻挡层、绝缘层及像素电极等，在制造过程中，由于制程精度及偏差的问题(如曝光阶段)，第二金属层在形成源漏极时与蚀刻阻挡层必须有一定的重叠宽度，以保证在制程产生偏差时，第二金属层能完全覆盖住半导体层，使得半导体层构成的沟道长度较大，导电能力变差，造成像素开口率下降。
发明内容
本发明提供一种阵列基板的制造方法，避免半导体层构成的沟道长度较大，导电能力变差，保证阵列基板开口率。
本发明提供一种阵列基板的制造方法，所述阵列基板的制造方法包括：
提供一基板；
在所述基板上形成第一金属层，通过构图工艺使第一金属层形成包括栅极的图案；
在上述基板及第一金属层上形成栅极绝缘层，栅极绝缘层覆盖所述基板的表面及所述栅极；
在所述栅极绝缘层上形成正投影于所述栅极的氧化物半导体层；其中，所述氧化物半导体层的宽度与所述栅极宽度相同；
在所述氧化物半导体层上设置光阻层，所述光阻层的宽度小于所述氧化物半导体层的宽度，且所述氧化物半导体层上由所述光阻层投影正对的部分为沟道区域，而位于所述氧化物半导体层上沟道区域两侧为第一氧化物半导体层及第二氧化物半导体层；
对设置有光阻层的所述第一氧化物半导体层及第二氧化物半导体层进行等离子处理，使露出所述光阻层投影的第一氧化物半导体层及第二氧化物半导体层转换为第一氧化物导体层及第二氧化物导体层；
移除所述光阻层；
在形成栅极绝缘层、沟道区域、第一氧化物导体层及第二氧化物导体层的基板上形成蚀刻阻挡层；其中，第一氧化物导体层及第二氧化物导体层部分露出所述蚀刻阻挡层；
在所述基板上形成第二金属层，图案化所述第二金属层形成所述阵列基板的源极及漏极，其中，所述源极与第一氧化物导体层接触，所述漏极与第二氧化物导体层接触。
其中，所述等离子处理采用氮气或者氨气注入所述第一氧化物半导体层及第二氧化物半导体层。
其中，所述氧化物导体层的材料为氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
其中，所述蚀刻阻挡层的材料为氧化硅。
其中，所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一，所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
其中，所述的阵列基板的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化的步骤。
其中，所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
其中，所述栅极绝缘层及蚀刻阻挡层通过构图工艺形成。
本发明提供一种阵列基板，所述阵列基板包括：
基板、形成于基板上的栅极；
栅绝缘层，覆盖所述栅极；
沟道区域，位于所述栅极正上方；
第一氧化物半导体层及第二氧化物半导体层，所述第一氧化物半导体层及第二氧化物半导体层分别连接所述沟道区域两侧，且与沟道区域同一平面设置的，所述沟道区域、第一氧化物半导体层及第二氧化物半导体层共同覆盖于所述栅极；
蚀刻阻挡层，设于所述基板上，覆盖所述栅极绝缘层及所述沟道区域；
设于蚀刻阻阻挡层上的源极与漏极，所述源极与所述漏位于所述沟道区域两侧位置，所述源极覆盖并接触第一氧化物半导体层，所述漏极覆盖并接触第二氧化物半导体层。
本发明提供一种显示装置，其包括所述的阵列基板。
本发明的阵列基板的制造方法在栅极绝缘层上形成氧化物半导体层，通过设置光阻层遮挡部分氧化物半导体层作为沟道区域，通过等离子处理方式将沟道区域两个的氧化物半导体层形成含氧量较少的第一氧化物导体层、第二氧化物导体层用于接触层与所述源极和漏极接触，保证在制程产生偏差时第二金属层能与所述源极和漏极接触同时减少了沟道区域的整体长度，进而减少阵列基板的尺寸提升了阵列基板的开口率及通电性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的制造方法的流程图。
图2至图9为本发明较佳实施方式的阵列基板方法的各个制造流程中阵列基板的截面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，其为本发明一较佳实施方式的阵列基板的制造方法的流程图。所述阵列基板属于氧化物半导体结构晶体管。在阐述具体制备方法之前，应所述理解，在本发明中，所述图案化即是指构图工艺，可包括光罩工艺，或，包括光罩工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光罩工艺，是指包括成膜、曝光、显影，等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
所述阵列基板的制造方法制造方法包括如下步骤。
步骤S1，提供一基板10。请一并参阅图2，在本实施方式中，所述基板10为一玻璃基板。可以理解地，在其他实施方式中，所述基板10并不仅限于为玻璃基板。
请一并参阅图3，步骤S2，在所述基板10上形成第一金属层(图未示)，通过构图工艺使第一金属12层形成包括栅极12的图案；具体的，在所述基板10的一表面上形成所述第一金属层，以作为所述阵列基板10的栅极12。所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。本实施方式中通过现有技术的涂光阻、曝光、显影等构图工艺对所述第一金属层图案化形成栅极12。
请一并参阅图4，步骤S3，在上述基板10及图案化的第一金属层上形成栅极绝缘层13，所述栅极绝缘层13覆盖所述基板10的表面及所述栅极12。具体的在所述基板10未覆盖所述第一金属层的表面及所述栅极12上形成所述栅极绝缘层130。所述栅极绝缘层13的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
请一并参阅图5，步骤S4，在所述栅极绝缘层13上形成正投影于所述栅极12的氧化物半导体层14；其中，所述氧化物半导体层14的宽度L1与所述栅极12宽度L2相同。所述氧化物导体层14的材料为氧化铟镓锌(IGZO)、氧 化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。优选的，所述所述氧化物导体层14采用含氧量0-％10的氧化铟镓锌(IGZO)。
请一并参阅图6，步骤S5，在所述氧化物半导体层14上设置光阻层15，所述光阻层15正投影于所述氧化物半导体层14上，且所述氧化物半导体层15上由所述光阻层投影影正对的部分为沟道区域16，而位于所述氧化物半导体层14上沟道区域16两侧为第一氧化物半导体层141及第二氧化物半导体层142。
请一并参阅图7，步骤S6，对设置有光阻层15的所述第一氧化物半导体层141及第二氧化物半导体层142进行等离子处理，使露出所述光阻层15投影的第一氧化物半导体层141及第二氧化物半导体层142转换为第一氧化物导体层17及第二氧化物导体层18。所述等离子处理采用氮气或者氨气注入所述第一氧化物半导体层141及第二氧化物半导体层142，使所述第一氧化物半导体层141及第二氧化物半导体层142内的含氧量减少，降低阻值。
步骤S7，移除所述光阻层15。目的是露出所述沟道区域。
请一并参阅图8，步骤S8，在形成栅极绝缘层、沟道区域、第一氧化物导体层19及第二氧化物导体层20的基板上形成蚀刻阻挡层21。所述蚀刻阻挡层21的材料为氧化硅。所述蚀刻阻挡层21覆盖所述沟道区域16并露出大部分第一氧化物导体层17及第二氧化物导体层18。
请一并参阅图9，步骤S9，在基板10上形成第二金属层(图未示)，图案化所述第二金属层，形成所述阵列基板的源极19及漏极20，其中，所述源极19与第一氧化物导体层17接触，所述漏极20与第二氧化物导体层18接触。所述沟道区域16位于所述源极19与漏极20之间。
具体的，所述第二金属层与所述第一氧化物导体层17、第二氧化物导体层18及所述栅极绝缘层13依次层叠设置。通过现有技术的构图工艺对所述第二金属层进行图案化形成如图所示的源极19和漏极20。所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。其中，所述源极19与第一氧化物导体层17接触，所述漏极20与第二氧化物导体层18接触用于形成所述阵列基板的源极19和漏极20之间导通或者断开的通道，相当于欧姆接触层的作用，源极19和漏极20可分别通过位于其下的导体层与沟道区域16形成一良 好的欧姆接触(ohmic contact)，具有低阻值，实现源极19到漏极20良好的通电性能。
本实施例中，第二金属层的材料一般是金属材料。但，本发明不限于此，在其他实施例中，第二金属层的材料也可以使用其他导电材料，如合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或是金属材料与其它导材料的堆叠层。
步骤S10，在所述基板10及所述图案化的第二金属层(源极19和漏极20)上形成的绝缘保护层，对所述绝缘保护层进行图案化。所述栅极绝缘层13与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。到此步骤，本实施例中的阵列基板制造方法完成。
进一步的，所述栅极绝缘层13与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。本实施例中，所述栅极绝缘层及蚀刻阻挡层通过构图工艺形成。
本发明的阵列基板的制造方法在栅极绝缘层13上形成氧化物半导体层14，通过设置光阻层15遮挡部分氧化物半导体层15作为沟道区域16，通过等离子处理方式将沟道区域16两个的氧化物半导体层15形成含氧量较少的第一氧化物导体层17、第二氧化物导体层18用于接触层与所述源极19和漏极20接触，保证在制程产生偏差时第二金属层能与所述源极19和漏极20接触同时减少了沟道区域16的整体长度，进而减少阵列基板的尺寸提升了阵列基板的开口率及通电性能。
针对上述阵列基板制造方法，本发明还涉及一种阵列基板，其包括基板、栅极，栅绝缘层，覆盖所述栅极；沟道区域，位于所述栅极正上方；第一氧化物半导体层及第二氧化物半导体层，所述第一氧化物半导体层及第二氧化物半导体层分别连接所述沟道区域两侧，且与沟道区域同一平面设置的，所述沟道区域、第一氧化物半导体层及第二氧化物半导体层共同覆盖于所述栅极；蚀刻阻挡层，设于所述基板上，覆盖所述栅极绝缘层及所述沟道区域；设于蚀刻阻阻挡层上的源极与漏极，所述源极与所述漏位于所述沟道区域两侧位置，所述源极覆盖并接触第一氧化物半导体层，所述漏极覆盖并接触第二氧化物半导体层。
本发明还包括以上方式的阵列基板的显示装置，通过本发明实施例阵列基板的制造方法形成的显示装置，可以为：液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、手机等。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板的制造方法，其中，所述阵列基板的制造方法包括：
    提供一基板；
    在所述基板上形成第一金属层，通过构图工艺使第一金属层形成包括栅极的图案；
    在上述基板及第一金属层上形成栅极绝缘层，栅极绝缘层覆盖所述基板的表面及所述栅极；
    在所述栅极绝缘层上形成正投影于所述栅极的氧化物半导体层；其中，所述氧化物半导体层的宽度与所述栅极宽度相同；
    在所述氧化物半导体层上设置光阻层，所述光阻层的宽度小于所述氧化物半导体层的宽度，且所述氧化物半导体层上由所述光阻层投影正对的部分为沟道区域，而位于所述氧化物半导体层上沟道区域两侧为第一氧化物半导体层及第二氧化物半导体层；
    对设置有光阻层的所述第一氧化物半导体层及第二氧化物半导体层进行等离子处理，使露出所述光阻层投影的第一氧化物半导体层及第二氧化物半导体层转换为第一氧化物导体层及第二氧化物导体层；
    移除所述光阻层；
    在形成栅极绝缘层、沟道区域、第一氧化物导体层及第二氧化物导体层的基板上形成蚀刻阻挡层；其中，第一氧化物导体层及第二氧化物导体层部分露出所述蚀刻阻挡层；
    在所述基板上形成第二金属层，图案化所述第二金属层形成所述阵列基板的源极及漏极，其中，所述源极与第一氧化物导体层接触，所述漏极与第二氧化物导体层接触。
  2. 如权利要求1所述的阵列基板的制造方法，其中，所述等离子处理采用氮气或者氨气注入所述第一氧化物半导体层及第二氧化物半导体层。
  3. 如权利要求2所述的阵列基板的制造方法，其中，所述氧化物导体层的材料为氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)。
  4. 如权利要求1所述的阵列基板的制造方法，其中，所述蚀刻阻挡层的材料为氧化硅。
  5. 如权利要求1所述的阵列基板的制造方法，其中，所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一，所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
  6. 如权利要求1所述的阵列基板的制造方法，其中，所述的阵列基板的制造方法还包括在所述基板及所述图案化的第二金属层上形成的绝缘保护层，对所述绝缘保护层进行图案化的步骤。
  7. 如权利要求6所述的阵列基板的制造方法，其中，所述栅极绝缘层与所述绝缘保护层采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
  8. 如权利要求1所述的阵列基板的制造方法，其中，所述栅极绝缘层及蚀刻阻挡层通过构图工艺形成。
  9. 一种阵列基板，其中，所述阵列基板包括：
    基板、形成于基板上的栅极；
    栅绝缘层，覆盖所述栅极；
    沟道区域，位于所述栅极正上方；
    第一氧化物半导体层及第二氧化物半导体层，所述第一氧化物半导体层及第二氧化物半导体层分别连接所述沟道区域两侧，且与沟道区域同一平面设置的，所述沟道区域、第一氧化物半导体层及第二氧化物半导体层共同覆盖于所述栅极；
    蚀刻阻挡层，设于所述基板上，覆盖所述栅极绝缘层及所述沟道区域；
    设于蚀刻阻阻挡层上的源极与漏极，所述源极与所述漏位于所述沟道区域两侧位置，所述源极覆盖并接触第一氧化物半导体层，所述漏极覆盖并接触第二氧化物半导体层。
  10. 一种显示装置，其包括权利要求9所述的阵列基板。
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