TWI569456B - 薄膜電晶體及其製造方法 - Google Patents

薄膜電晶體及其製造方法 Download PDF

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TWI569456B
TWI569456B TW104133811A TW104133811A TWI569456B TW I569456 B TWI569456 B TW I569456B TW 104133811 A TW104133811 A TW 104133811A TW 104133811 A TW104133811 A TW 104133811A TW I569456 B TWI569456 B TW I569456B
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thin film
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侯智元
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友達光電股份有限公司
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Description

薄膜電晶體及其製造方法
本發明是有關於一種薄膜電晶體及其製造方法，且特別是有關於一種閘極具有貫穿孔的薄膜電晶體及其製造方法。
無輻射、高畫質等優越特性的平面顯示面板（flat display panels）已成為市場主流。常見的平面顯示器包括液晶顯示器（liquid crystal displays）、電漿顯示器（plasma displays）、有機電激發光顯示器（electroluminescent displays）等。以目前最普及的液晶顯示器為例，液晶顯示器主要是由畫素陣列基板、彩色濾光基板以及夾設於二者之間的液晶層所構成。在習知的畫素陣列基板上，多採用薄膜電晶體作為各個畫素結構的切換元件，故液晶顯示器的性能會取決於薄膜電晶體的品質好壞。換言之，薄膜電晶體中通道層的導電性對於薄膜電晶體的品質以及液晶顯示器的性能來說具有較大的影響。
另一方面，在目前薄膜電晶體的製造過程中，需要用到四個光罩，以分別圖案化閘極、氧化半導體層、蝕刻終止層以及源極/汲極。然而，由於光罩價格不斐，故使用較多的光罩來製作薄膜電晶體將會增加整體的製造成本。因此，如何減少光罩數目並同時兼顧薄膜電晶體的品質成為目前液晶顯示器亟待克服的課題。
本發明提供一種薄膜電晶體及其製造方法，其閘極具有貫穿孔，能夠有效地減少製程所需要使用的光罩數目並且提升通道層的導電性。
本發明提供一種薄膜電晶體，包括一基板、一閘極、一通道層、一閘絕緣層、一蝕刻終止層、一源極以及一汲極。閘極配置於基板上且具有多個貫穿孔。通道層位於閘極上。閘絕緣層配置於閘極以及通道層之間。蝕刻終止層配置於通道層上且具有多個接觸孔以暴露出部分的通道層。源極以及汲極配置於蝕刻終止層上分別藉由接觸孔與通道層電性連接。
本發明提供一種薄膜電晶體的製造方法，其包括提供一基板，並形成一閘極於基板上，其中閘極具有多個貫穿孔。接著，形成閘絕緣層於閘極上，並形成通道層於閘絕緣層上。形成蝕刻終止層於通道層上並圖案化蝕刻終止層，以在蝕刻終止層中形成多個接觸孔以暴露出部分的通道層。形成一源極以及一汲極於蝕刻終止層上，其中源極以及汲極分別藉由接觸孔與通道層電性連接。
基於上述，本發明的薄膜電晶體中的閘極具有貫穿孔，使得在蝕刻終止層中形成接觸孔的製程能夠藉由背曝（Backside Exposure）來實現。因此，相較於傳統的薄膜電晶體能夠省下一道光罩，降低製造成本並減少對位誤差。另一方面，由於在背曝的過程中部份的通道層會受到光線的照射，故這些區域的導電性能夠受到提升，進而改善薄膜電晶體以及液晶顯示器的品質。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖6A是根據本發明一實施例之薄膜電晶體的製造方法的上視流程示意圖。圖1B至6B是根據圖1A至圖6A的剖線A-A’的剖面流程示意圖。以下將針對本發明一實施例的薄膜電晶體的製造流程作詳細的說明。
請同時參照圖1A以及圖1B，提供基板100，並在基板上形成第一導電材料層200。基板100之材質可為玻璃、石英、有機聚合物、或是其它可適用的材料。具體來說，由於在後續的製程中會進行背曝的製程，故基板100的材質較佳為高透光度的材質。另一方面，基於導電性的考量，第一導電材料層200一般是使用金屬材料，但本發明不限於此。第一導電材料層200亦可以使用其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物或是金屬材料與其它導電材料的堆疊層。
緊接著，對第一導電材料層200進行一圖案化程序，以在基板100上形成閘極G，如圖2A以及圖2B所示。閘極G具有多個貫穿孔TH，且貫穿孔TH具有直徑Y。在本實施例中，是以兩個貫穿孔TH為例示，但本發明不限於此。在其他實施例中，視後續製程所需，閘極G亦可以具有多於兩個的貫穿孔TH。另一方面，在本實施例中，貫穿孔TH的直徑Y為3μm至7μm之間。
請同時參照圖3A以及圖3B，在形成閘極G之後，依序形成閘絕緣層GI以及通道層CH。閘絕緣層GI的材質例如為無機介電材料。具體來說，閘絕緣層GI的材質可以包括如氧化矽（SiOx）、氮化矽（SiNx）或其堆疊結構。另一方面，通道層CH的材質可選擇為非晶矽材料、多晶矽材料或是金屬氧化物半導體材料，包括非晶矽（amorphous Silicon, a-Si）、氧化銦鎵鋅（Indium-Gallium-Zinc Oxide, IGZO）、氧化鋅（ZnO）、氧化錫（SnO）、氧化銦鋅（Indium-Zinc Oxide, IZO）、氧化鎵鋅（Gallium-Zinc Oxide, GZO）、氧化鋅錫（Zinc-Tin Oxide, ZTO）或氧化銦錫（Indium-Tin Oxide, ITO），但本發明不限於此。值得注意的是，通道層CH與閘極G中的兩個貫穿孔TH重疊。
如圖4A以及圖4B所示，在閘絕緣層GI以及通道層CH上形成蝕刻終止層ES以及光阻層PR。蝕刻終止層ES的材料例如是氧化矽（SiOx）或是氧化鋁（AlOx），但本發明不限於此。在其他的實施例中，亦可使用其他適合的材料作為蝕刻終止層ES。蝕刻終止層ES的作用在於阻擋後續製程所使用的蝕刻液，以避免蝕刻液破壞到通道層CH等其他元件。另一方面，光阻層PR的材料例如是感光性樹脂或其他感光性材料。
緊接著，利用紫外線光UV對薄膜電晶體半成品進行背曝以及蝕刻程序，以圖案化蝕刻終止層ES，進而得到如圖5A以及圖5B所繪示之結構。具體來說，在此道製程中，能夠利用具有貫穿孔TH的閘極G作為罩幕，而對光阻層PR進行圖案化製程以使得光阻層PR暴露出部分的蝕刻終止層ES。接著，移除蝕刻終止層ES被光阻層PR暴露出的部份，以圖案化蝕刻終止層ES，使得蝕刻終止層ES具有暴露出部分通道層CH的接觸孔C。由於是利用閘極G作為罩幕，在理想的狀況下，蝕刻終止層ES的接觸孔C會與閘極G的貫穿孔TH完全重疊。換言之，蝕刻終止層ES的接觸孔C的邊緣實質上會與閘極G的貫穿孔TH的邊緣對齊。在這樣的狀況下，接觸孔C的直徑X會等於貫穿孔TH的直徑Y。然而，基於使用不同蝕刻方式與光阻的搭配，蝕刻終止層ES的接觸孔C的邊緣亦可以不會與閘極G的貫穿孔TH的邊緣對齊。具體來說，接觸孔C可以小於貫穿孔TH。舉例來說，接觸孔C的直徑X為3μm至5μm之間，且每一貫穿孔TH的直徑Y為X至X+2μm之間。值得注意的是，在本實施例中，照射的光線是以紫外線光UV為例示，但本發明不限於此。在其他實施例中，其他類型的光線亦可以與特定的光阻搭配而達到相同的圖案化效果。
承上述，由於蝕刻終止層ES的圖案化是採取背曝的方式，故紫外線光UV會照射到通道層CH對應閘極G的貫穿孔TH的部份，形成第一通道區300a。另一方面，通道層CH被閘極G遮蔽而並未受到紫外線光UV照射的區域則形成第二通道區300b。由於第一通道區300a受到紫外線光UV的照射，故相較於第二通道區300b具有較大的導電性。換言之，被接觸孔C暴露的第一通道區300a的導電性大於被蝕刻終止層ES所遮蔽的第二通道區300b的導電性。
請同時參照圖6A以及圖6B，在完成蝕刻終止層ES的圖案化之後，先移除光阻層PR，並形成源極S以及汲極D於蝕刻終止層ES上。詳細來說，在蝕刻終止層ES上形成一第二導電材料層（未繪示），並經由黃光製程圖案化第二導電材料層以形成源極S以及汲極D。第二導電材料層的材料可以與第一導電材料層200相同或不同。換言之，源極S以及汲極D包括金屬材料、合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物或是金屬材料與其它導電材料的堆疊層。源極S以及汲極D分別藉由接觸孔C與通道層CH電性連接。由於被接觸孔C暴露的區域為第一通道區300a，故源極S以及汲極D實質上是與具有較大導電性的第一通道區300a電性連接。因此，本發明之薄膜電晶體能夠具有較佳的導電性。
圖7是習知的薄膜電晶體以及本發明一實施例的薄膜電晶體之線性汲源極電流(I DS)-閘源極電壓(V GS)曲線圖。請參照圖7，其中A代表本發明一實施例的薄膜電晶體的曲線，而B則代表習知的薄膜電晶體的曲線。具體來說，曲線A的薄膜電晶體的閘極包括貫穿孔而曲線B的薄膜電晶體的閘極不包括貫穿孔，故曲線B的薄膜電晶體中的通道層並不會受到背光光源的照射。從圖7可以得知，在相同的閘源極電壓下，曲線A具有較高的線性汲源極電流量，且這種情況在電壓越高時越為明顯。換言之，曲線A所代表的薄膜電晶體相較於曲線B所代表的薄膜電晶體具有較佳的導電性。圖7所繪示的曲線驗證了在本發明的薄膜電晶體中，由於源極S以及汲極D實質上是與具有較大導電性的第一通道區300a電性連接，故相較於傳統的薄膜電晶體具有較佳的導電性。
綜上所述，本發明的薄膜電晶體中的閘極具有貫穿孔，使得在蝕刻終止層中形成接觸孔的製程能夠藉由背曝（Backside Exposure）來實現。因此，相較於傳統的薄膜電晶體能夠省下一道光罩，降低製造成本並減少對位誤差。另一方面，由於在背曝的過程中部份的通道層會受到光線的照射，故這些區域的導電性能夠受到提升，進而改善薄膜電晶體以及液晶顯示器的品質。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧基板
G‧‧‧閘極
TH‧‧‧貫穿孔
GI‧‧‧閘絕緣層
ES‧‧‧蝕刻終止層
CH‧‧‧通道層
C‧‧‧接觸孔
S‧‧‧源極
D‧‧‧汲極
300a‧‧‧第一通道區
300b‧‧‧第二通道區
X、Y‧‧‧直徑
UV‧‧‧紫外線光
200‧‧‧第一導電材料層
PR‧‧‧光阻層
A‧‧‧本發明一實施例的薄膜電晶體的線性汲源極電流(IDS)-閘源極電壓(VGS)曲線
B‧‧‧習知的薄膜電晶體的線性汲源極電流(IDS)-閘源極電壓(VGS)曲線
圖1A至圖6A是根據本發明一實施例之薄膜電晶體的製造方法的上視流程示意圖。 圖1B至6B是根據圖1A至圖6A的剖線A-A’的剖面流程示意圖。 圖7是習知的薄膜電晶體以及本發明一實施例的薄膜電晶體之線性汲源極電流(I DS)-閘源極電壓(V GS)曲線圖。
100‧‧‧基板
G‧‧‧閘極
TH‧‧‧貫穿孔
GI‧‧‧閘絕緣層
ES‧‧‧蝕刻終止層
CH‧‧‧通道層
C‧‧‧接觸孔
S‧‧‧源極
D‧‧‧汲極
300a‧‧‧第一通道區
300b‧‧‧第二通道區
X、Y‧‧‧直徑

Claims (11)

  1. 一種薄膜電晶體，包括：一基板；一閘極，配置於該基板上，且該閘極具有多個貫穿孔；一通道層，位於該閘極上；一閘絕緣層，配置於該閘極以及該通道層之間；一蝕刻終止層，配置於該通道層上，且該蝕刻終止層具有多個接觸孔以暴露出部分的該通道層；以及一源極以及一汲極，其中該源極以及該汲極配置於該蝕刻終止層上且分別藉由該些接觸孔與該通道層電性連接。
  2. 如申請專利範圍第1項所述的薄膜電晶體，其中該些貫穿孔與該些接觸孔重疊。
  3. 如申請專利範圍第2項所述的薄膜電晶體，其中該些貫穿孔的邊緣與該些接觸孔的邊緣實質上對齊。
  4. 如申請專利範圍第3項所述的薄膜電晶體，其中該通道層被該接觸孔暴露出的區域的導電性大於該通道層被該蝕刻終止層所遮蔽的區域的導電性。
  5. 如申請專利範圍第2項所述的薄膜電晶體，其中每一接觸孔的直徑為Xμm，且每一貫穿孔的直徑為Xμm至(X+2)μm之間。
  6. 如申請專利範圍第5項所述的薄膜電晶體，其中X為3μm至5μm之間。
  7. 如申請專利範圍第4項所述的薄膜電晶體，其中該閘絕緣層包括氧化矽(SiOx)、氮化矽(SiNx)或其堆疊結構。
  8. 如申請專利範圍第4項所述的薄膜電晶體，其中該通道層的材料包括非晶矽材料、多晶矽材料或金屬氧化物半導體材料。
  9. 如申請專利範圍第4項所述的薄膜電晶體，其中該蝕刻終止層的材料包括氧化矽(SiOx)或是氧化鋁(AlOx)。
  10. 一種薄膜電晶體的製造方法，包括：提供一基板；形成一閘極於該基板上，其中該閘極具有多個貫穿孔；形成一閘絕緣層於該閘極上；形成一通道層於該閘絕緣層上；形成一蝕刻終止層於該通道層上，圖案化該蝕刻終止層，以在該蝕刻終止層中形成多個接觸孔以暴露出部分的該通道層；以及形成一源極以及一汲極於該蝕刻終止層上，其中該源極以及該汲極分別藉由該些接觸孔與該通道層電性連接。
  11. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，其中該圖案化該蝕刻終止層的步驟包括：形成一光阻層於該蝕刻終止層上；利用該閘極作為曝光罩幕圖案化該光阻層，以暴露出部分的該蝕刻終止層；以及移除該蝕刻終止層被該光阻層暴露出的部份，以形成該些接觸孔。
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