TWI578546B - 薄膜電晶體的製造方法 - Google Patents
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- 239000010409 thin film Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 62
- 229920002120 photoresistant polymer Polymers 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- SKRWFPLZQAAQSU-UHFFFAOYSA-N stibanylidynetin;hydrate Chemical compound O.[Sn].[Sb] SKRWFPLZQAAQSU-UHFFFAOYSA-N 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 239000002042 Silver nanowire Substances 0.000 claims description 2
- 239000002041 carbon nanotube Substances 0.000 claims description 2
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000012780 transparent material Substances 0.000 claims description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- -1 etc.) Chemical compound 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Description
本發明涉及一種薄膜電晶體的製造方法。
薄膜電晶體(Thin Film Transistor，TFT)作為開關元件已被廣泛應用於顯示、觸控領域。例如，顯示裝置(如液晶電視、筆記型電腦及顯示器)中的陣列基板通常採用薄膜電晶體作為開關元件。常見的TFT通常包括位於基板上的閘極、覆蓋閘極的閘極絕緣層、位於閘極絕緣層上的半導體溝道層及分別覆蓋於溝道層兩側的源/汲極。
然，隨著著電子產品朝大尺寸、高解析度發展，陣列基板上的TFT的數量越來越多，因而對TFT的回應速度要求越來越高，而此類TFT存在電子遷移率低，而回應速度不夠的問題。為解決上述問題，現有的一種對TFT的結構改良是通過在TFT的半導體溝道層與閘極絕緣層之間增設一導體溝道層，以增大TFT的電子遷移率，從而提高薄膜電晶體的回應速度。然而，上述半導體溝道層及導體溝道層結構在製程過程中需要借助不同圖案的光罩進行曝光蝕刻製程，導致製造成本的增高且製造工序較複雜。
鑒於此，有必要提供一種製造成本較低的薄膜電晶體的製造方法。
一種薄膜電晶體的製造方法，該製造方法包括：提供一基板，並於該基板上形成閘極及閘極絕緣層；於該閘極絕緣層上覆蓋一導電層；於該導電層上形成一第一光阻層，並以一光罩為正面曝光掩膜及以該閘極作為背面曝光掩膜對該第一光阻層進行正背面同時曝光以形成第一圖案化光阻層；蝕刻去除未被該第一圖案化光阻層覆蓋的所述導電層以形成導電溝道層；於該導電溝道層上形成半導體層及於該半導體層上形成第二光阻層，並以所述光罩為正面曝光掩膜及以該閘極作為背面曝光掩膜對該第二光阻層進行正背面同時曝光以形成第二圖案化光阻層；蝕刻去除未被該第二圖案化光阻層覆蓋的所述半導體層以形成覆蓋該導電溝道層的半導體溝道層；於該半導體溝道層兩相對側分別形成源極及汲極。
與習知技術相對比，本發明在分別形成半導體溝道層及導電溝道層時均以閘極為背面曝光膜及以同一光罩作為正面曝光掩膜進行正背面同時曝光，由於兩次曝光製程均採用同一光罩，而無需針對不同的曝光製程製造不同的光罩，因而可以降低製造成本。
100‧‧‧薄膜電晶體
101‧‧‧基板
102‧‧‧閘極
103‧‧‧閘極絕緣層
104a‧‧‧導電層
104‧‧‧導電溝道層
105a‧‧‧半導體層
105‧‧‧半導體溝道層
1051‧‧‧源接觸區
1052‧‧‧汲接觸區
106‧‧‧蝕刻阻擋層
1061‧‧‧開孔
107‧‧‧源極
108‧‧‧汲極
200‧‧‧第一圖案化光阻層
300‧‧‧第二圖案化光阻層
M‧‧‧光罩
M1‧‧‧不透光區
M2‧‧‧透光區
L1，L3‧‧‧長度
L2，L4‧‧‧寬度
圖1為本發明第一實施方式所提供的薄膜電晶體的截面示意圖。
圖2為本發明一變更實施方式所提供的薄膜電晶體的截面示意圖。
圖3圖為本發明另一變更實施方式所提供的薄膜電晶體的截面示意圖。
圖4為圖1所示薄膜電晶體的製造流程圖。
圖5至圖10為圖4中各步驟流程的剖視圖。
圖11為圖7中光罩及閘極在基板上的結構投影圖。
圖12為圖10中半導體溝道層及導電溝道層在基板上的結構投影圖。
下面結合附圖將對本發明實施方式作進一步的詳細說明，其中，本發明以底閘極型薄膜電晶體為例進行說明。
請參閱圖1，圖1為本發明第一實施方式所提供的薄膜電晶體100的截面示意圖。該薄膜電晶體100可應用於一陣列基板101(例如液晶顯示陣列基板101)中作為一開關元件。該薄膜電晶體100包括基板101、閘極102、閘極絕緣層103、導電溝道層104、半導體溝道層105、源極107及汲極108。該閘極102形成於該基板101表面，該閘極絕緣層103覆蓋於該閘極102遠離該基板101的一側。該導電溝道層104位於該閘極絕緣層103上且與該閘極102對應設置，該閘極絕緣層103將該導電溝道層104和該閘極102及該半導體溝道層105和該閘極102彼此隔開而相互絕緣。所述半導體溝道層105覆蓋於所述導電溝道層104上。所述源極107與所述汲極108分別覆蓋於所述半導體溝道層105相對兩側，該半導體溝道層105將該源極107與該導電溝道層104及該汲極108與該導電溝道層104隔開。
進一步地，所述半導體溝道層105包括源接觸區1051與汲接觸區1052。所述源接觸區1051位於所述源極107與所述導電溝道層104之間。所述源極107上的電流會依次經由所述源接觸區1051、所述導電溝道層104、所述汲接觸區1052傳導至所述汲極108。所述汲接觸區1052位於所述汲極108與所述導電溝道層104之間。本實施方式中，該源極107及該汲極108選擇與該導電溝道層104相同的材質，且均為透明材質。當然，在其他實施方式中，也可以為不同的導電材質。該導電溝道層104的材料包括氧化銦錫(ITO)、氧化銻錫(ATO)、銀奈米線、銦鋅氧化物(IZO)或碳納米管等透明導電材料。該半導體溝道層105的材質包括非晶矽(例如本徵非晶矽、n型非晶矽等)、晶矽、氧化物半導體及有機材料之一或其組合。其中，該氧化物半導體包括但不限於銦鎵鋅氧化物(Indium Gallium Zinc Oxide，IGZO)。
在一變更實施方式中，如圖2所示，當所述半導體溝道層105選用氧化物半導體材料時，所述薄膜電晶體100還包括一蝕刻阻擋層106。該蝕刻阻擋層106設置於該半導體溝道層105上的中間位置，該源極107及該汲極108分別覆蓋該蝕刻阻擋層106的相對兩側，且分別與該半導體溝道層105的相對兩側接觸。在另一變更實施方式中，如圖3所示，該蝕刻阻擋層106覆蓋於該半導體溝道層105上，該蝕刻阻擋層106的相對兩側分別形成連通該半導體溝道層105的開孔1061，該二開孔1061分別對應位於該源接觸區1051及該汲接觸區1052，所述源極107及所述汲極108分別對應形成於該二開孔1061上，並通過該二開孔1061分別與該半導體溝道層105連通。
請一併參閱圖4-10，圖4為圖1所示薄膜電晶體100的製造流程圖。圖5至圖10為圖4中各步驟流程的剖視圖。
步驟S101，請首先參閱圖5，提供一基板101，在基板101上依次形成閘極102及覆蓋該閘極102的閘極絕緣層103。其中，該閘極102的長度為L1，寬度為L2，如圖12所示。
步驟S102，請進一步參閱圖6，於該閘極絕緣層103上覆蓋一導電層104a。
步驟S103，請進一步參閱圖7及圖11，於該導電層104a上形成一第一光阻層，並以一光罩M為正面曝光掩膜及以該閘極102作為背面曝光掩膜對該第一光阻層進行正背面同時曝光以形成第一圖案化光阻層200。
具體地，如圖所示11，該光罩M包括一不透光區M1及包圍該不透光區的一透光區M2，該不透光區M1的長度為L3，寬度為L4，如圖12。該不透光區M1在所述基板101上的正投影及所述閘極102在所述基板101上的正投影至少部分重疊，使得通過該光罩M及該閘極102對該第一光阻層進行曝光後，該第一圖案化光阻層200在該基板101上的正投影與該重疊處正好重合。本實施方式中，該不透光區M1的長度L3小於該閘極102的長度L1，該不透光區M1的寬度L4大於該閘極102的寬度L2。該第一圖案化光阻層200鄰近該導電層104a的接觸面的寬度由該閘極102界定，長度由該光罩M的不透光區M1界定。其中，該第一光阻層為正型光阻。
由於以該光罩M及該閘極102分別作為正背面曝光掩膜，二光罩M的正投影交疊圖案為該第一圖案化光阻層200的正投影圖案，因
而可實現自動對位的效果，而省去了曝光製程中的對位元校準程式，有利於提高工作效率。此外，由於借助所述閘極102作為背面曝光掩膜，有利於提高對位的準確度。
步驟S104，請進一步參閱圖8，蝕刻去除未被該第一圖案化光阻層200覆蓋的所述導電層104a以形成導電溝道層104。
步驟S105，請進一步參閱圖9及圖11，於該導電溝道層104上形成半導體層105a及於該半導體層105a上形成第二光阻層，並以所述光罩M為正面曝光掩膜及以該閘極102作為背面曝光掩膜對該第二光阻層進行正背面同時曝光以形成第二圖案化光阻層300。
本實施方式中，所述第一光阻層及所述第二光阻層為相同的材質。具體地，如圖所示11，該光罩M在所述基板101上的正投影及所述閘極102在所述基板101上的正投影的重疊部分面積與該第二圖案化光阻層300的正投影面積相等，通過該光罩M及該閘極102對該第二光阻層進行曝光後，該第二圖案化光阻層300鄰近該半導體層105a的接觸面的寬度由該閘極102界定，長度由該不透光區M1界定，所述第二圖案化光阻層300與所述第一圖案化光阻層200在該基板101上正投影正好重疊。借助所述閘極102作為背面曝光掩膜，形成該第一、二圖案化光阻層200、300均可採用同一光罩M，提高了光罩M利用率，有利於節省製造成本。
步驟S106，請進一步參閱圖10及圖12，蝕刻去除未被該第二圖案化光阻層300覆蓋的所述半導體層105a以形成覆蓋該導電溝道層104的半導體溝道層105。
需要說明的是，在分別對該導電層104a及該半導體層105a進行蝕
刻時，可通過調節蝕刻液濃度、蝕刻速度及蝕刻時間或選擇不同蝕刻液等方式調節蝕刻率，使該導電溝道層104在該基板101上的投影面積小於該半導體溝道層105在該基板101上的正投影面積，如圖12所示，從而使該導電溝道層104被該半導體溝道層105所包覆而不與所述源、汲極107、108接觸。本實施方式中，在上述其他參數固定的情況下，通過調節對該導電層104a及該半導體層105a進行蝕刻的蝕刻時間，使該導電溝道層104在該基板101上的投影面積小於該半導體溝道層105在該基板101上的正投影面積。實際實施時，可根據所述導電層104a及所述半導體層105a的具體材質及所選擇的蝕刻液確認需要的蝕刻時間。
步驟S107，請再次參閱圖1，於該半導體溝道層105兩相對側分別形成源極107及汲極108。得到圖1所示薄膜電晶體100。
在其他變更實施方式中，還可先在該半導體溝道層105上形成蝕刻蝕擋層後再形成分別覆蓋所述蝕刻蝕擋層相對兩側的所述源極107及所述汲極108，得到圖2所示薄膜電晶體100。
在另一變更實施方式中，還可在形成該半導體溝道層105上後，在該半導體溝道層105上形成蝕刻阻擋層106，並在該蝕刻阻擋層106的相對兩側分別形成連通該半導體溝道層105的開孔1061，然後在該蝕刻阻擋層106上分別對應該二開孔1061處形成所述源極107及所述汲極108，得到圖3所示薄膜電晶體100。需要說明的是，製造如圖3所示的薄膜電晶體100的過程中，在進行上述步驟S104與步驟S106，分別對該導電層104a及該半導體層105a進行蝕刻時，由於該結構的薄膜電晶體100對該半導體溝道層105是否將該導電溝道層104的頂面及側面完全覆蓋並無嚴格要求，因而，
在其他蝕刻參數不變的情況下，分別對該導電層104a及該半導體層105a的蝕刻時間長短無嚴格控製。但若該半導體溝道層105未将該導電層104a包覆，則在進行步驟S107時，該薄膜電晶體100的蝕刻阻擋層106需將該半導體溝道層105及該導電溝道層104的頂面及側面包覆。
在後續製程中，在薄膜電晶體100上還可形成平坦層、鈍化層等習知技術，在此不再贅述。
綜上所述，本創作符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本創作之較佳實施例，本創作之範圍並不以上述實施例為限，舉凡熟習本案技藝之人士爰依本創作之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。
S101-S107‧‧‧步驟
Claims (10)
- 一種薄膜電晶體的製造方法，其中，該製造方法包括：提供一基板，並於該基板上形成閘極及閘極絕緣層；於該閘極絕緣層上覆蓋一導電層；於該導電層上形成一第一光阻層，並以一光罩為正面曝光掩膜及以該閘極作為背面曝光掩膜對該第一光阻層進行正背面同時曝光以形成第一圖案化光阻層；蝕刻去除未被該第一圖案化光阻層覆蓋的所述導電層以形成導電溝道層；於該導電溝道層上形成半導體層及於該半導體層上形成第二光阻層，並以所述光罩為正面曝光掩膜及以該閘極作為背面曝光掩膜對該第二光阻層進行正背面同時曝光以形成第二圖案化光阻層；蝕刻去除未被該第二圖案化光阻層覆蓋的所述半導體層以形成覆蓋該導電溝道層的半導體溝道層；於該半導體溝道層兩相對側分別形成源極及汲極。
- 如請求項1所述的薄膜電晶體的製造方法，其中，蝕刻該導電層的時長不同於蝕刻該半導體層的時長，以使該導電溝道層的面積小於該半導體溝道層的面積。
- 如請求項1所述的薄膜電晶體的製造方法，其中，該第一、二圖案化光阻層及該閘極在該基板上的正投影重合。
- 如請求項1所述的薄膜電晶體的製造方法，其中，該第一、二光阻層均為正型光阻。
- 如請求項1所述的薄膜電晶體的製造方法，其中，該導電層為透明材料。
- 如請求項1所述的薄膜電晶體的製造方法，其中，該導電溝道層的材料包括氧化銦錫、氧化銻錫、銀納米線、銦鋅氧化物或碳納米管之一。
- 如請求項1所述的薄膜電晶體的製造方法，其中，形成該半導體溝道層後還包括：在該半導體溝道層上形成蝕刻阻擋層，再形成該源極及該汲極，該源極及該汲極分別覆蓋於該蝕刻阻擋層的兩相對側。
- 如請求項1所述的薄膜電晶體的製造方法，其中，形成該半導體溝道層後還包括：在該半導體溝道層上形成蝕刻阻擋層，並在該蝕刻阻擋層的相對兩側分別形成連通該半導體溝道層的開孔；於該蝕刻阻擋層上分別對應該二開孔處形成所述源極及所述汲極。
- 如請求項1所述的薄膜電晶體的製造方法，其中：該光罩包括一透光區與一不透光區，該第一圖案化光阻層鄰近該導電層的接觸面的寬度由該閘極界定，長度由該光罩的不透光區界定，該第二圖案化光阻層鄰近該半導體層的接觸面的寬度亦由該閘極界定，長度亦由該光罩的不透光區界定。
- 如請求項9所述的薄膜電晶體的製造方法，其中：該光罩的不透光區的長度小於該閘極的長度，該光罩的不透光區的寬度大於該閘極的寬度。
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