WO2021031374A1 - 阵列基板的制备方法及阵列基板 - Google Patents

阵列基板的制备方法及阵列基板 Download PDF

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Publication number
WO2021031374A1
WO2021031374A1 PCT/CN2019/116102 CN2019116102W WO2021031374A1 WO 2021031374 A1 WO2021031374 A1 WO 2021031374A1 CN 2019116102 W CN2019116102 W CN 2019116102W WO 2021031374 A1 WO2021031374 A1 WO 2021031374A1
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WO
WIPO (PCT)
Prior art keywords
layer
patterned
transmitting portion
pixel electrode
photoresist
Prior art date
Application number
PCT/CN2019/116102
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English (en)
French (fr)
Inventor
颜源
艾飞
何鹏
陆鹏
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/641,663 priority Critical patent/US11018165B2/en
Publication of WO2021031374A1 publication Critical patent/WO2021031374A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • This application relates to a display technology, in particular to a method for preparing an array substrate and an array substrate.
  • the embodiments of the present application provide a method for manufacturing an array substrate and an array substrate, so as to solve the technical problems of complicated steps in the method for manufacturing an array substrate of an existing touch integrated type array substrate, resulting in higher production costs and longer cycles.
  • the embodiment of the application provides a method for preparing an array substrate, which includes the following steps:
  • the patterned pixel electrode layer includes a pixel electrode
  • the patterned second metal layer includes a drain electrode and a touch signal line, and the drain electrode is electrically connected to the pixel electrode;
  • the patterned common electrode layer includes touch electrodes, and the touch electrodes are electrically connected to the touch signal lines;
  • the forming a patterned interlayer dielectric layer and a pixel electrode layer on the first metal layer by using the same photomask includes the following steps:
  • first photoresist layer Expose the first photoresist layer by using a first halftone photomask, and then develop the first photoresist layer so that the first photoresist layer corresponds to the source/drain of the active layer A portion of the region forms a first through hole, and a portion corresponding to the touch signal line to be formed in the second metal layer forms a first recess, wherein the first photoresist layer corresponds to the source of the active layer
  • the first through hole of the pole region communicates with the first recessed portion;
  • the first photoresist layer is removed.
  • the first halftone mask includes a first light transmitting portion and a second light transmitting portion, and the light transmittance of the first light transmitting portion is greater than the second light transmitting portion.
  • the light transmittance of the first light transmitting portion is 100%, the first light transmitting portion corresponds to the source/drain region of the active layer, and the second light transmitting portion corresponds to The portion of the second metal layer where the touch signal line is to be formed.
  • the forming a patterned protective layer and a common electrode layer on the second metal layer using the same photomask includes the following steps:
  • the second through hole forms a second recessed portion corresponding to the portion of the common electrode layer where the common electrode and the touch electrode are to be formed, wherein the second photoresist layer corresponds to the first portion of the source region of the active layer
  • Two through holes communicate with the second recessed portion;
  • a common electrode layer on the second photoresist layer Forming a common electrode layer on the second photoresist layer, a part of the common electrode layer is formed on the second photoresist layer, and the other part is formed on the protection layer;
  • the second photoresist layer is removed.
  • the first halftone mask includes a third light transmitting portion and a fourth light transmitting portion, and the light transmittance of the third light transmitting portion is greater than that of the fourth light transmitting portion
  • the light transmittance of the third light transmitting portion is 100%, the third light transmitting portion corresponds to the touch signal trace, and the fourth light transmitting portion corresponds to the common electrode Common electrodes and touch electrodes to be formed in the layer.
  • a self-aligned doping process is used to form the patterned first metal layer.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, which includes the following steps:
  • the patterned pixel electrode layer includes a pixel electrode
  • the patterned second metal layer includes a drain electrode and a touch signal line, and the drain electrode is electrically connected to the pixel electrode;
  • a patterned protective layer and a common electrode layer are formed on the second metal layer.
  • the patterned common electrode layer includes touch electrodes, and the touch electrodes are electrically connected to the touch signal lines.
  • the forming the patterned interlayer dielectric layer and the pixel electrode layer on the first metal layer by using the same photomask includes the following steps:
  • first photoresist layer Expose the first photoresist layer by using a first halftone photomask, and then develop the first photoresist layer so that the first photoresist layer corresponds to the source/drain of the active layer A portion of the region forms a first through hole, and a portion corresponding to the touch signal line to be formed in the second metal layer forms a first recess, wherein the first photoresist layer corresponds to the source of the active layer
  • the first through hole of the pole region communicates with the first recessed portion;
  • the first photoresist layer is removed.
  • the first halftone mask includes a first light transmitting portion and a second light transmitting portion, and the light transmittance of the first light transmitting portion is greater than the second light transmitting portion.
  • the light transmittance of the first light transmitting portion is 100%, the first light transmitting portion corresponds to the source/drain region of the active layer, and the second light transmitting portion corresponds to The portion of the second metal layer where the touch signal line is to be formed.
  • the same photomask is used to form a patterned protective layer and a common electrode layer on the second metal layer.
  • the forming a patterned protective layer and a common electrode layer on the second metal layer using the same photomask includes the following steps:
  • the second through hole forms a second recessed portion corresponding to the portion of the common electrode layer where the common electrode and the touch electrode are to be formed, wherein the second photoresist layer corresponds to the first portion of the source region of the active layer
  • Two through holes communicate with the second recessed portion;
  • a common electrode layer on the second photoresist layer Forming a common electrode layer on the second photoresist layer, a part of the common electrode layer is formed on the second photoresist layer, and the other part is formed on the protection layer;
  • the second photoresist layer is removed.
  • the first halftone mask includes a third light transmitting portion and a fourth light transmitting portion, and the light transmittance of the third light transmitting portion is greater than that of the fourth light transmitting portion
  • the light transmittance of the third light transmitting portion is 100%, the third light transmitting portion corresponds to the touch signal trace, and the fourth light transmitting portion corresponds to the common electrode Common electrodes and touch electrodes to be formed in the layer.
  • a self-aligned doping process is used to form the patterned first metal layer.
  • the common electrode layer and the pixel electrode layer are both transparent conductive layers.
  • the material of the transparent conductive layer is indium tin oxide.
  • the present application also relates to an array substrate, which includes a substrate and an active layer, an insulating layer, a first metal layer, an interlayer dielectric layer, a pixel electrode layer, a second metal layer, a protective layer, and Common electrode layer
  • the second metal layer includes a drain electrode and a touch signal line
  • the pixel electrode layer includes a pixel electrode
  • the common electrode layer includes a touch electrode
  • the drain electrode is electrically connected to the pixel electrode
  • the The touch signal line is electrically connected to the touch electrode.
  • the touch signal line and the pixel electrode layer are provided in the same layer.
  • the drain electrode is stacked on the pixel electrode layer.
  • the manufacturing method of the array substrate of the present application and the array substrate use the same photomask to form the patterned interlayer dielectric layer and the pixel electrode layer, which not only saves a photomask, but also omits
  • the organic flat layer solves the technical problems of complicated steps in the preparation method of the existing touch integrated array substrate, resulting in higher production costs and longer cycles.
  • FIG. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the application
  • FIG. 2 is a schematic diagram of another process of the manufacturing method of the array substrate according to the embodiment of the application;
  • FIG. 3 is a schematic flowchart of step S5 of the method for manufacturing an array substrate according to an embodiment of the application;
  • FIG. 4 is a schematic flowchart of step S7 of the method for manufacturing an array substrate according to an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of an array substrate according to an embodiment of the application.
  • FIG. 1 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the application
  • FIG. 2 is another schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the application.
  • a preparation method of an array substrate includes the following steps:
  • Step S1 Provide a substrate 11;
  • Step S2 forming a patterned active layer 12 on the substrate 11;
  • Step S3 forming an insulating layer 13 on the active layer 12;
  • Step S4 forming a patterned first metal layer 14 on the insulating layer 13, and the patterned first metal layer 14 includes a gate;
  • Step S5 using the same photomask to form a patterned interlayer dielectric layer 15 and a pixel electrode layer 16 on the first metal layer 14;
  • Step S6 forming a patterned second metal layer 17 on the interlayer dielectric layer 15, and the patterned second metal layer 17 includes a source electrode, a drain electrode and a touch signal line 171;
  • Step S7 forming a patterned protective layer 18 and a common electrode layer 19 on the second metal layer 17.
  • the patterned interlayer dielectric layer 15 and the pixel electrode layer 16 are formed by using the same photomask, which saves a photomask process, and saves an organic flat layer, which improves the implementation The preparation efficiency of the case saves the cost.
  • the preparation method of the array substrate of the embodiment of the present application will be described in detail below.
  • a substrate 11 is provided.
  • the substrate 11 is a rigid substrate, optionally a glass substrate, but not limited to this. Then go to step S2.
  • a patterned active layer 12 is formed on the substrate 11.
  • an amorphous silicon layer is formed on the substrate 11; then the amorphous silicon layer is laser-annealed to form a polysilicon layer; finally, a photomask is used to pattern the polysilicon layer to form a patterned low-temperature polysilicon layer , That is, the patterned active layer 12 is formed.
  • a light shielding layer for shielding the active layer 12 is saved. Since the light shielding layer is saved, it is necessary to adjust the ion doping ratio of the source/drain region of the active layer 12 to compensate for the weak electric property generated after the active layer is illuminated. Then go to step S3.
  • step S3 an insulating layer 13 is formed on the active layer 12. Then go to step S4.
  • a patterned first metal layer 14 is formed on the insulating layer 13.
  • a self-aligned doping process is used to form the patterned first metal layer 14.
  • the self-aligned doping process can realize the patterning of the gate electrode, the ohmic contact area and the lightly doped area with only one photomask, which reduces the number of photomasks.
  • the patterned first metal layer 14 includes a gate.
  • the gate is the gate of the thin film transistor of the array substrate of this embodiment. Then go to step S5.
  • step S5 a patterned interlayer dielectric layer 15 and a pixel electrode layer 16 are formed on the first metal layer 14 by using the same photomask.
  • FIG. 3 is a schematic flowchart of step S5 of the method for manufacturing an array substrate according to an embodiment of the application.
  • Step S5 using the same photomask to form a patterned interlayer dielectric layer 15 and a pixel electrode layer 16 on the first metal layer 14, including the following steps:
  • Step S511 sequentially forming an interlayer dielectric layer 15, a pixel electrode layer 16, and a first photoresist layer 21 on the first metal layer 14;
  • Step S512 Expose the first photoresist layer 21 by using a first halftone mask, and then develop the first photoresist layer 21 so that the first photoresist layer 21 corresponds to the active
  • the portion of the source/drain region of the layer 12 forms the first through hole 211, and the portion corresponding to the touch signal line 171 to be formed in the second metal layer forms the first recess 212, wherein the first photoresist
  • the first through hole 211 of the layer 21 corresponding to the source region of the active layer 12 communicates with the first recess 212;
  • Step S513 etching the pixel electrode layer 16 and the interlayer dielectric layer 15 so that the first through hole 211 exposes the source/drain regions of the active layer 12;
  • Step S514 Ashing the first photoresist layer 21 to remove the part of the first photoresist layer 21 corresponding to the first recess 212;
  • Step S515 etching the pixel electrode layer 16 to remove the portion of the pixel electrode layer 16 corresponding to the first recess 212;
  • Step S516 Remove the first photoresist layer 21.
  • step S511 the interlayer dielectric layer 15 and the pixel electrode layer 16 are sequentially formed on the first metal layer 14.
  • an organic flat layer is saved, the process steps are simplified, and the manufacturing cost is reduced.
  • the organic flat layer is located between the interlayer dielectric layer and the pixel electrode layer.
  • the pixel electrode layer 16 is a transparent conductive layer.
  • the material of the transparent conductive layer is indium tin oxide.
  • the first halftone mask includes a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion,
  • the light transmittance of the first light transmission portion is 100%
  • the first light transmission portion corresponds to the source/drain region of the active layer
  • the second light transmission portion corresponds to the second metal layer
  • the part where the touch signal line 171 is to be formed wherein, after the first photoresist layer 21 in the area of the touch signal line 171 is removed, it is convenient to form the touch signal line 171 on the interlayer dielectric layer 15 corresponding to this area.
  • step S513 in addition to etching the pixel electrode layer 16 and the interlayer dielectric layer 15, the insulating layer 13 also needs to be etched to expose the source/drain regions of the active layer 12. Then proceed to steps S514-516.
  • step 515 the pixel electrode layer 16 is patterned by etching the exposed pixel electrode layer 16. The patterned pixel electrode layer 16 includes pixel electrodes.
  • step S5 a photomask is used to form the patterned interlayer dielectric layer 14 and the pixel electrode layer 16, which saves a photomask process and simplifies the steps of the manufacturing method of the array substrate of this embodiment. Then go to step S6.
  • a patterned second metal layer 17 is formed on the interlayer dielectric layer 15, and the patterned second metal layer 17 includes a source electrode, a drain electrode and a touch signal line 171. Specifically, the second metal layer 17 is formed by the yellow light process.
  • the source and drain serve as the source and drain of the thin film transistor of this embodiment.
  • the drain of the thin film transistor is electrically connected to the pixel electrode. Then go to step S7.
  • step S7 a patterned protective layer 18 and a common electrode layer 19 are formed on the second metal layer 17.
  • the same photomask is used to form a patterned protective layer 18 and a common electrode layer 19 on the second metal layer 17.
  • FIG. 4 is a schematic flowchart of step S7 of the method for manufacturing an array substrate according to an embodiment of the application.
  • step S7: using the same photomask to form a patterned protective layer 18 and a common electrode layer 19 on the second metal layer 17 includes the following steps:
  • Step S711 sequentially forming a protective layer 18 and a second photoresist layer 22 on the second metal layer 17;
  • Step S712 Expose the second photoresist layer 22 by using a second halftone mask, and then develop the second photoresist layer 22 so that the second photoresist layer 22 corresponds to the touch
  • the portion of the signal wiring forms the second through hole 221, and the portion corresponding to the common electrode and the touch electrode to be formed forms the second recess 222, wherein the second photoresist layer 22 corresponds to the active layer 12
  • the second through hole 221 in the source region communicates with the second recess 222;
  • Step S713 etching the protection layer so that the second through hole 221 exposes the touch signal trace;
  • Step S714 Ashing the second photoresist layer 22 to remove the part of the second photoresist layer 22 corresponding to the second recess 222, so that the remaining second photoresist layer 22 is defined A plurality of third recesses 223 exposing the protection layer 18;
  • Step S715 Ashing the second photoresist layer 22 and the protective layer 18, so that the third recess 223 extends into the protective layer 18;
  • Step S716 forming a common electrode layer 19 on the second photoresist layer 22, a part of the common electrode layer 19 is formed on the second photoresist layer 22, and the other part is formed on the protection layer 18;
  • Step S717 Remove the second photoresist layer 22.
  • the first halftone mask includes a third light-transmitting portion and a fourth light-transmitting portion, the light transmittance of the third light-transmitting portion is greater than the light transmittance of the fourth light-transmitting portion, and the first The light transmittance of the three light-transmitting portions is 100%, the third light-transmitting portion corresponds to the touch signal wiring, and the fourth light-transmitting portion corresponds to the common electrode and the common electrode to be formed in the common electrode layer 19 Touch electrodes.
  • step S715 the materials of the second photoresist layer 22 and the protective layer 18 are different, so in the ashing process, a specific gas ion is used to etch the second photoresist layer 22 and the protective layer 18
  • the ashing rate of the second photoresist layer 22 by the gas ion is less than the ashing rate of the protective layer 18 by the gas ion.
  • the third recessed portion 223 can extend into the protective layer 18 and deepen the depth of the third recessed portion 223.
  • the common electrode layer 19 formed on the photoresist layer 22 and the common electrode layer 19 formed on the protective layer 18 are disconnected from each other, and as long as the second photoresist layer 22 is removed, The patterned common electrode layer 19 is formed.
  • the portion of the third recess 223 located in the protective layer 18 extends in the direction of the second photoresist layer 22 and exposes the bottom surface of the second photoresist layer 22, that is, the protruding part of the second photoresist layer 22 and the protective layer 18 overlap A protrusion with a chamfer is formed, and the chamfer is located at the protruding part of the protective layer 18.
  • the setting of the chamfer on the one hand, makes the common electrode layer 19 on the second photoresist layer 22 and the common electrode layer 19 on the protection layer 18 easier to disconnect; on the other hand, it makes the stripping liquid of the second photoresist layer 22 easier to disconnect.
  • the sufficient contact with the second photoresist layer 22 improves the stability and efficiency of peeling of the second photoresist layer 22.
  • the patterned common electrode layer 19 includes touch electrodes and common electrodes, wherein the touch electrodes and the common electrodes share the same patterned common electrode layer, that is, the touch electrodes are also common electrodes.
  • the touch electrodes are electrically connected to the touch signal lines 171 through via holes.
  • step S7 a photomask is used to form the patterned protective layer 18 and the common electrode layer 19, which saves a photomask process and simplifies the steps of the manufacturing method of the array substrate of this embodiment. Then go to step S6.
  • the common electrode layer 19 is a transparent conductive layer.
  • the material of the transparent conductive layer is indium tin oxide.
  • FIG. 5 is a schematic structural diagram of an array substrate according to an embodiment of the application.
  • the present application also relates to an array substrate, which includes a substrate 11 and an active layer 12, an insulating layer 13, a first metal layer 14, an interlayer dielectric layer 15, a pixel electrode layer 16, and a second layer which are sequentially arranged on the substrate 11.
  • the first metal layer 14 includes a gate
  • the second metal layer 17 includes a source electrode, a drain electrode, and a touch signal line 171
  • the common electrode layer 19 includes a common electrode and a touch electrode, wherein the touch electrode It shares the same patterned common electrode layer with the common electrode, that is, the touch electrode is also a common electrode.
  • the pixel electrode layer 16 includes pixel electrodes. The touch electrodes are electrically connected to the touch signal lines 171 through vias. The drain is electrically connected to the pixel electrode.
  • the touch signal line 171 and the pixel electrode layer 16 are provided in the same layer.
  • the drain is stacked on the pixel electrode layer 16.
  • a through hole is formed in the pixel electrode layer 16 corresponding to the drain position of the active layer 12.
  • the through hole penetrates the pixel electrode layer 16 and the interlayer dielectric layer 15 and exposes the active layer 12.
  • the drain extends into the through hole and is connected to the drain position of the active layer 12.
  • the array substrate in this embodiment saves a light shielding layer and an organic flat layer for shielding the active layer, which simplifies the process and reduces the cost.
  • the array substrate of this embodiment is manufactured by the manufacturing method of the array substrate of the foregoing embodiment.
  • the manufacturing method of the array substrate of the present application and the array substrate use the same photomask to form the patterned interlayer dielectric layer and the pixel electrode layer, which not only saves a photomask, but also omits
  • the organic flat layer solves the technical problems of complicated steps in the preparation method of the existing touch integrated array substrate, resulting in higher production costs and longer cycles.

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Abstract

一种阵列基板的制备方法及阵列基板，该方法包括：在基板上形成有源层；在有源层上形成绝缘层；在绝缘层上形成第一金属层；采用同一光罩在第一金属层上形成层间介质层和像素电极层；在层间介质层上形成第二金属层，第二金属层包括源极、漏极和触控信号线；在第二金属层上形成图案化的保护层和公共电极层。

Description

阵列基板的制备方法及阵列基板 技术领域
本申请涉及一种显示技术，特别涉及一种阵列基板的制备方法及阵列基板。
 背景技术
随着集成式触控显示面板的发展，人们对高分辨率的要求越来越高。因此需要精细的有源驱动矩阵（阵列基板）配合各像素区液晶进行偏转。
但是现有技术中的触控集成式的阵列基板的制备方法步骤较为繁琐，导致生产成本较高和周期较长。
 技术问题
本申请实施例提供一种阵列基板的制备方法及阵列基板，以解决现有的触控集成式的阵列基板的制备方法步骤较为繁琐，导致生产成本较高和周期较长的技术问题。
 技术解决方案
本申请实施例提供一种阵列基板的制备方法，其包括以下步骤：
提供一基板；
在所述基板上形成图案化的有源层；
在所述有源层上形成绝缘层；
在所述绝缘层上形成图案化的第一金属层；
采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，图案化的像素电极层包括像素电极；
在所述层间介质层上形成图案化的第二金属层，图案化的第二金属层包括漏极和触控信号线，所述漏极电性连接于所述像素电极；
采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，图案化的公共电极层包括触控电极，所述触控电极电性连接于所述触控信号线；
所述采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，包括以下步骤：
依次在所述第一金属层上形成层间介质层、像素电极层和第一光阻层；
采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，使所述第一光阻层对应于所述有源层的源/漏极区域的部分形成第一通孔、和对应于所述第二金属层中待形成触控信号线的部分形成第一凹陷部，其中所述第一光阻层对应于所述有源层的源极区域的第一通孔连通所述第一凹陷部；
刻蚀所述像素电极层和所述层间介质层，使所述第一通孔暴露出所述有源层的源/漏极区域；
灰化所述第一光阻层，以去除所述第一光阻层对应于所述第一凹陷部的部分；
刻蚀所述像素电极层，以去除所述像素电极层对应于所述第一凹陷部的部分；
去除所述第一光阻层。
在本申请的阵列基板的制备方法中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应所述有源层的源/漏极区域，所述第二透光部对应于所述第二金属层中待形成触控信号线的部分。
在本申请的阵列基板的制备方法中，所述采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，包括以下步骤：
依次在所述第二金属层上形成保护层和第二光阻层；
采用第二半色调光罩对所述第二光阻层进行曝光，随后对所述第二光阻层进行显影，使所述第二光阻层对应于所述触控信号走线的部分形成第二通孔、对应于所述公共电极层中待形成公共电极和触控电极的部分形成第二凹陷部，其中所述第二光阻层对应于所述有源层的源极区域的第二通孔连通所述第二凹陷部；
刻蚀所述保护层，使所述第二通孔暴露出所述触控信号走线；
灰化所述第二光阻层，以去除所述第二光阻层对应于所述第二凹陷部的部分，使保留下来的第二光阻层之间界定形成多个暴露所述保护层的第三凹陷部；
灰化所述第二光阻层和保护层，以使所述第三凹陷部伸入所述保护层；
在所述第二光阻层上形成公共电极层，所述公共电极层的一部分形成在第二光阻层上，另一部分形成在所述保护层上；
去除所述第二光阻层。
在本申请的阵列基板的制备方法中，所述第一半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应所述触控信号走线，所述第四透光部对应于所述公共电极层中待形成的公共电极和触控电极。
在本申请的阵列基板的制备方法中，采用自对准掺杂工艺形成图案化的第一金属层。
本申请实施例还提供一种阵列基板的制备方法，其包括以下步骤：
提供一基板；
在所述基板上形成图案化的有源层；
在所述有源层上形成绝缘层；
在所述绝缘层上形成图案化的第一金属层；
采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，图案化的像素电极层包括像素电极；
在所述层间介质层上形成图案化的第二金属层，图案化的第二金属层包括漏极和触控信号线，所述漏极电性连接于所述像素电极；
在所述第二金属层上形成图案化的保护层和公共电极层，图案化的公共电极层包括触控电极，所述触控电极电性连接于所述触控信号线。
在本申请的阵列基板的制备方法中，所述采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，包括以下步骤：
依次在所述第一金属层上形成层间介质层、像素电极层和第一光阻层；
采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，使所述第一光阻层对应于所述有源层的源/漏极区域的部分形成第一通孔、和对应于所述第二金属层中待形成触控信号线的部分形成第一凹陷部，其中所述第一光阻层对应于所述有源层的源极区域的第一通孔连通所述第一凹陷部；
刻蚀所述像素电极层和所述层间介质层，使所述第一通孔暴露出所述有源层的源/漏极区域；
灰化所述第一光阻层，以去除所述第一光阻层对应于所述第一凹陷部的部分；
刻蚀所述像素电极层，以去除所述像素电极层对应于所述第一凹陷部的部分；
去除所述第一光阻层。
在本申请的阵列基板的制备方法中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应所述有源层的源/漏极区域，所述第二透光部对应于所述第二金属层中待形成触控信号线的部分。
在本申请的阵列基板的制备方法中，采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层。
在本申请的阵列基板的制备方法中，所述采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，包括以下步骤：
依次在所述第二金属层上形成保护层和第二光阻层；
采用第二半色调光罩对所述第二光阻层进行曝光，随后对所述第二光阻层进行显影，使所述第二光阻层对应于所述触控信号走线的部分形成第二通孔、对应于所述公共电极层中待形成公共电极和触控电极的部分形成第二凹陷部，其中所述第二光阻层对应于所述有源层的源极区域的第二通孔连通所述第二凹陷部；
刻蚀所述保护层，使所述第二通孔暴露出所述触控信号走线；
灰化所述第二光阻层，以去除所述第二光阻层对应于所述第二凹陷部的部分，使保留下来的第二光阻层之间界定形成多个暴露所述保护层的第三凹陷部；
灰化所述第二光阻层和保护层，以使所述第三凹陷部伸入所述保护层；
在所述第二光阻层上形成公共电极层，所述公共电极层的一部分形成在第二光阻层上，另一部分形成在所述保护层上；
去除所述第二光阻层。
在本申请的阵列基板的制备方法中，所述第一半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应所述触控信号走线，所述第四透光部对应于所述公共电极层中待形成的公共电极和触控电极。
在本申请的阵列基板的制备方法中，采用自对准掺杂工艺形成图案化的第一金属层。
在本申请的阵列基板的制备方法中，所述公共电极层和所述像素电极层均为透明导电层。
在本申请的阵列基板的制备方法中，所述透明导电层的材质为氧化铟锡。
本申请还涉及一种阵列基板，其包括基板和依次设置在所述基板上的有源层、绝缘层、第一金属层、层间介质层、像素电极层、第二金属层、保护层和公共电极层；
其中所述第二金属层包括漏极和触控信号线，所述像素电极层包括像素电极，所述公共电极层包括触控电极，所述漏极电性连接于所述像素电极，所述触控信号线电性连接于所述触控电极。
在本申请的阵列基板中，所述触控信号线与所述像素电极层同层设置。
在本申请的阵列基板中，所述漏极叠设在所述像素电极层上。
 有益效果
相较于现有技术的阵列基板的制备方法，本申请的阵列基板的制备方法和阵列基板使用同一光罩形成图案化的层间介质层和像素电极层，不但节省一个光罩，而且省略了有机平坦层；解决了现有的触控集成式的阵列基板的制备方法步骤较为繁琐，导致生产成本较高和周期较长的技术问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为本申请实施例的阵列基板的制备方法的流程示意图；
图2为本申请实施例的阵列基板的制备方法的另一流程示意图；
图3为本申请实施例的阵列基板的制备方法的步骤S5的流程示意图；
图4为本申请实施例的阵列基板的制备方法的步骤S7的流程示意图；
图5为本申请实施例的阵列基板的结构示意图。
 本发明的实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
图1为本申请实施例的阵列基板的制备方法的流程示意图；图2为本申请实施例的阵列基板的制备方法的另一流程示意图。
一种阵列基板的制备方法，其包括以下步骤：
步骤S1：提供一基板11；
步骤S2：在所述基板11上形成图案化的有源层12；
步骤S3：在所述有源层12上形成绝缘层13；
步骤S4：在所述绝缘层13上形成图案化的第一金属层14，图案化的第一金属层14包括栅极；
步骤S5：采用同一光罩在所述第一金属层14上形成图案化的层间介质层15和像素电极层16；
步骤S6：在所述层间介质层15上形成图案化的第二金属层17，图案化的第二金属层17包括源极、漏极和触控信号线171；
步骤S7：在所述第二金属层17上形成图案化的保护层18和公共电极层19。
本申请实施例的阵列基板的制备方法，通过采用同一光罩形成图案化的层间介质层15和像素电极层16，节省了一道光罩工序，而且节省了一有机平坦层，提高了本实施例的制备效率，节省了成本。下面对本申请实施例的阵列基板的制备方法进行详细的阐述。
在步骤S1中，提供一基板11。基板11为一硬性基板，可选的，玻璃基板，但并不限于此。随后转入步骤S2。
在步骤S2中，在所述基板11上形成图案化的有源层12。先在基板11上形成一非晶硅层；然后对非晶硅层进行激光镭射退火处理，形成多晶硅层；最后，采用一光罩对多晶硅层进行图案化处理，以形成图案化的低温多晶硅层，即形成图案化的有源层12。
在本实施例中，节省了一遮挡有源层12的遮光层。由于节省了遮光层，则需要对有源层12的源/漏区域的部分进行离子掺杂比例的调整，以弥补有源层被光照后产生的弱电性。随后转入步骤S3。
在步骤S3中，在所述有源层12上形成绝缘层13。随后转入步骤S4。
在步骤S4中，在所述绝缘层13上形成图案化的第一金属层14。其中，采用自对准掺杂工艺形成图案化的第一金属层14。采用自对准掺杂工艺可以只用一道光罩实现栅极、欧姆接触区和轻掺杂区制程的图案化，减少了光罩的数量。
图案化的第一金属层14包括栅极。该栅极为本实施例的阵列基板的薄膜晶体管的栅极。随后转入步骤S5。
在步骤S5中，采用同一光罩在所述第一金属层14上形成图案化的层间介质层15和像素电极层16。
具体的，请参照图3，图3为本申请实施例的阵列基板的制备方法的步骤S5的流程示意图。
步骤S5：所述采用同一光罩在所述第一金属层14上形成图案化的层间介质层15和像素电极层16，包括以下步骤：
步骤S511：依次在所述第一金属层14上形成层间介质层15、像素电极层16和第一光阻层21；
步骤S512：采用第一半色调光罩对所述第一光阻层21进行曝光，随后对所述第一光阻层21进行显影，使所述第一光阻层21对应于所述有源层12的源/漏极区域的部分形成第一通孔211、和对应于所述第二金属层中待形成触控信号线171的部分形成第一凹陷部212，其中所述第一光阻层21对应于所述有源层12的源极区域的第一通孔211连通所述第一凹陷部212；
步骤S513：刻蚀所述像素电极层16和所述层间介质层15，使所述第一通孔211暴露出所述有源层12的源/漏极区域；
步骤S514：灰化所述第一光阻层21，以去除所述第一光阻层21对应于所述第一凹陷部212的部分；
步骤S515：刻蚀所述像素电极层16，以去除所述像素电极层16对应于所述第一凹陷部212的部分；
步骤S516：去除所述第一光阻层21。
在步骤S511中，依次在第一金属层14上形成层间介质层15和像素电极层16，相较于现有技术节省了一有机平坦层，简化的工艺步骤，降低了制备成本。在现有技术中，有机平坦层位于层间介质层和像素电极层之间。像素电极层16为透明导电层。可选的，所述透明导电层的材质为氧化铟锡。
在步骤S512中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应所述有源层的源/漏极区域，所述第二透光部对应于所述第二金属层中待形成触控信号线171的部分。其中，当触控信号线171区域的第一光阻层21去除后，便于在该区域对应的层间介质层15上形成触控信号线171。
在步骤S513中，除了刻蚀像素电极层16和层间介质层15，还需要刻蚀绝缘层13，以露出有源层12的源/漏极区域。接着进行步骤S514-516。在步骤515中，通过刻蚀裸露的像素电极层16，以图案化像素电极层16。图案化的像素电极层16包括像素电极。
步骤S5采用一道光罩形成图案化的层间介质层14和像素电极层16，节省了一道光罩的工序，简化了本实施例的阵列基板的制备方法的步骤。随后转入步骤S6。
在步骤S6中，在所述层间介质层15上形成图案化的第二金属层17，图案化的第二金属层17包括源极、漏极和触控信号线171。具体的，采用黄光工艺形成第二金属层17。其中源极和漏极作为本实施例的薄膜晶体管的源极和漏极。薄膜晶体管的漏极电性连接像素电极。随后转入步骤S7。
在步骤S7中，在所述第二金属层17上形成图案化的保护层18和公共电极层19。
采用同一光罩在所述第二金属层17上形成图案化的保护层18和公共电极层19。
请参照图4，图4为本申请实施例的阵列基板的制备方法的步骤S7的流程示意图。
具体的，步骤S7：所述采用同一光罩在所述第二金属层17上形成图案化的保护层18和公共电极层19，包括以下步骤：
步骤S711：依次在所述第二金属层17上形成保护层18和第二光阻层22；
步骤S712：采用第二半色调光罩对所述第二光阻层22进行曝光，随后对所述第二光阻层22进行显影，使所述第二光阻层22对应于所述触控信号走线的部分形成第二通孔221、对应于待形成的公共电极和触控电极的部分形成第二凹陷部222，其中所述第二光阻层22对应于所述有源层12的源极区域的第二通孔221连通所述第二凹陷部222；
步骤S713：刻蚀所述保护层，使所述第二通孔221暴露出所述触控信号走线；
步骤S714：灰化所述第二光阻层22，以去除所述第二光阻层22对应于所述第二凹陷部222的部分，使保留下来的第二光阻层22之间界定形成多个暴露所述保护层18的第三凹陷部223；
步骤S715：灰化所述第二光阻层22和保护层18，以使所述第三凹陷部223伸入所述保护层18；
步骤S716：在所述第二光阻层22上形成公共电极层19，所述公共电极层19的一部分形成在第二光阻层22上，另一部分形成在所述保护层18上；
步骤S717：去除所述第二光阻层22。
其中，所述第一半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应所述触控信号走线，所述第四透光部对应于所述公共电极层19中待形成的公共电极和触控电极。
在步骤S715中，第二光阻层22和保护层18的材料不同，那么在进行灰化的过程中，采用一特定的气体离子对所述第二光阻层22和保护层18进行刻蚀，其中该气体离子对第二光阻层22的灰化速率小于该气体离子对保护层18的灰化速率。这样的设置，使得第三凹陷部223可以延伸入保护层18，且加深第三凹陷部223的深度。由于第三凹陷部223的深度地加深，使得形成在光阻层22上的公共电极层19和形成在保护层18上的公共电极层19彼此断开，进而只要去除第二光阻层22，便构成了图案化的公共电极层19。
另外，第三凹陷部223位于保护层18的部分向第二光阻层22的方向延伸并暴露出第二光阻层22的底面，即第二光阻层22和保护层18突出的部分叠加形成一具有倒角的凸起部，该倒角位于保护层18突出的部分。倒角的设置，一方面使得第二光阻层22上的公共电极层19和保护层18上的公共电极层19更容易断开；另一方面，使得第二光阻层22的剥离液更充分与第二光阻层22接触，提高了第二光阻层22剥离的稳定性和效率。
其中图案化的公共电极层19包括触控电极和公共电极，其中触控电极和公共电极共用同一图案化的公共电极层，即触控电极也为公共电极。触控电极通过过孔电性连接于触控信号线171。
接着进行步骤S716-717。
步骤S7采用一道光罩形成图案化的保护层18和公共电极层19，节省了一道光罩的工序，简化了本实施例的阵列基板的制备方法的步骤。随后转入步骤S6。
公共电极层19为透明导电层。可选的，所述透明导电层的材质为氧化铟锡。
这样便完成了本实施例的阵列基板的制备方法。
请参照图5，图5为本申请实施例的阵列基板的结构示意图。本申请还涉及一种阵列基板，其包括基板11和依次设置在所述基板11上的有源层12、绝缘层13、第一金属层14、层间介质层15、像素电极层16、第二金属层17、保护层18和公共电极层19。
其中所述第一金属层14包括栅极，所述第二金属层17包括源极、漏极、触控信号线171，所述公共电极层19包括公共电极和触控电极，其中触控电极和公共电极共用同一图案化的公共电极层，即触控电极也为公共电极。像素电极层16包括像素电极。触控电极通过过孔电性连接触控信号线171。漏极电性连接于像素电极。
在本实施例的阵列基板中，触控信号线171与像素电极层16同层设置。漏极叠设在像素电极层16上。
且像素电极层16对应于有源层12的漏极位置的部分开设一通孔，该通孔贯通像素电极层16和层间介质层15并裸露出有源层12。漏极延伸入该通孔与有源层12的漏极位置相连。
其中本实施例中的阵列基板相较于现有的阵列基板节省了一用于遮挡有源层的遮光层和一有机平坦层，简化的工序，降低了成本。
本实施例的阵列基板由上述实施例的阵列基板的制备方法制作而成。
相较于现有技术的阵列基板的制备方法，本申请的阵列基板的制备方法和阵列基板使用同一光罩形成图案化的层间介质层和像素电极层，不但节省一个光罩，而且省略了有机平坦层；解决了现有的触控集成式的阵列基板的制备方法步骤较为繁琐，导致生产成本较高和周期较长的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本申请的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本申请后附的权利要求的保护范围。

Claims (15)

  1. 一种阵列基板的制备方法，其包括以下步骤：
    提供一基板；
    在所述基板上形成图案化的有源层；
    在所述有源层上形成绝缘层；
    在所述绝缘层上形成图案化的第一金属层；
    采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，图案化的像素电极层包括像素电极；
    在所述层间介质层上形成图案化的第二金属层，图案化的第二金属层包括漏极和触控信号线，所述漏极电性连接于所述像素电极；
    采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，图案化的公共电极层包括触控电极，所述触控电极电性连接于所述触控信号线；
    所述采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，包括以下步骤：
    依次在所述第一金属层上形成层间介质层、像素电极层和第一光阻层；
    采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，使所述第一光阻层对应于所述有源层的源/漏极区域的部分形成第一通孔、和对应于所述第二金属层中待形成触控信号线的部分形成第一凹陷部，其中所述第一光阻层对应于所述有源层的源极区域的第一通孔连通所述第一凹陷部；
    刻蚀所述像素电极层和所述层间介质层，使所述第一通孔暴露出所述有源层的源/漏极区域；
    灰化所述第一光阻层，以去除所述第一光阻层对应于所述第一凹陷部的部分；
    刻蚀所述像素电极层，以去除所述像素电极层对应于所述第一凹陷部的部分；
    去除所述第一光阻层。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应所述有源层的源/漏极区域，所述第二透光部对应于所述第二金属层中待形成触控信号线的部分。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，所述采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，包括以下步骤：
    依次在所述第二金属层上形成保护层和第二光阻层；
    采用第二半色调光罩对所述第二光阻层进行曝光，随后对所述第二光阻层进行显影，使所述第二光阻层对应于所述触控信号走线的部分形成第二通孔、对应于所述公共电极层中待形成公共电极和触控电极的部分形成第二凹陷部，其中所述第二光阻层对应于所述有源层的源极区域的第二通孔连通所述第二凹陷部；
    刻蚀所述保护层，使所述第二通孔暴露出所述触控信号走线；
    灰化所述第二光阻层，以去除所述第二光阻层对应于所述第二凹陷部的部分，使保留下来的第二光阻层之间界定形成多个暴露所述保护层的第三凹陷部；
    灰化所述第二光阻层和保护层，以使所述第三凹陷部伸入所述保护层；
    在所述第二光阻层上形成公共电极层，所述公共电极层的一部分形成在第二光阻层上，另一部分形成在所述保护层上；
    去除所述第二光阻层。
  4. 根据权利要求3所述的阵列基板的制备方法，其中，所述第一半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应所述触控信号走线，所述第四透光部对应于所述公共电极层中待形成的公共电极和触控电极。
  5. 根据权利要求1所述的阵列基板的制备方法，其中，采用自对准掺杂工艺形成图案化的第一金属层。
  6. 一种阵列基板的制备方法，其包括以下步骤：
    提供一基板；
    在所述基板上形成图案化的有源层；
    在所述有源层上形成绝缘层；
    在所述绝缘层上形成图案化的第一金属层；
    采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，图案化的像素电极层包括像素电极；
    在所述层间介质层上形成图案化的第二金属层，图案化的第二金属层包括漏极和触控信号线，所述漏极电性连接于所述像素电极；
    在所述第二金属层上形成图案化的保护层和公共电极层，图案化的公共电极层包括触控电极，所述触控电极电性连接于所述触控信号线。
  7. 根据权利要求6所述的阵列基板的制备方法，其中，所述采用同一光罩在所述第一金属层上形成图案化的层间介质层和像素电极层，包括以下步骤：
    依次在所述第一金属层上形成层间介质层、像素电极层和第一光阻层；
    采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，使所述第一光阻层对应于所述有源层的源/漏极区域的部分形成第一通孔、和对应于所述第二金属层中待形成触控信号线的部分形成第一凹陷部，其中所述第一光阻层对应于所述有源层的源极区域的第一通孔连通所述第一凹陷部；
    刻蚀所述像素电极层和所述层间介质层，使所述第一通孔暴露出所述有源层的源/漏极区域；
    灰化所述第一光阻层，以去除所述第一光阻层对应于所述第一凹陷部的部分；
    刻蚀所述像素电极层，以去除所述像素电极层对应于所述第一凹陷部的部分；
    去除所述第一光阻层。
  8. 根据权利要求7所述的阵列基板的制备方法，其中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应所述有源层的源/漏极区域，所述第二透光部对应于所述第二金属层中待形成触控信号线的部分。
  9. 根据权利要求6所述的阵列基板的制备方法，其中，采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，所述采用同一光罩在所述第二金属层上形成图案化的保护层和公共电极层，包括以下步骤：
    依次在所述第二金属层上形成保护层和第二光阻层；
    采用第二半色调光罩对所述第二光阻层进行曝光，随后对所述第二光阻层进行显影，使所述第二光阻层对应于所述触控信号走线的部分形成第二通孔、对应于所述公共电极层中待形成公共电极和触控电极的部分形成第二凹陷部，其中所述第二光阻层对应于所述有源层的源极区域的第二通孔连通所述第二凹陷部；
    刻蚀所述保护层，使所述第二通孔暴露出所述触控信号走线；
    灰化所述第二光阻层，以去除所述第二光阻层对应于所述第二凹陷部的部分，使保留下来的第二光阻层之间界定形成多个暴露所述保护层的第三凹陷部；
    灰化所述第二光阻层和保护层，以使所述第三凹陷部伸入所述保护层；
    在所述第二光阻层上形成公共电极层，所述公共电极层的一部分形成在第二光阻层上，另一部分形成在所述保护层上；
    去除所述第二光阻层。
  11. 根据权利要求10所述的阵列基板的制备方法，其中，所述第一半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应所述触控信号走线，所述第四透光部对应于所述公共电极层中待形成的公共电极和触控电极。
  12. 根据权利要求6所述的阵列基板的制备方法，其中，采用自对准掺杂工艺形成图案化的第一金属层。
  13. 一种阵列基板，其包括基板和依次设置在所述基板上的有源层、绝缘层、第一金属层、层间介质层、像素电极层、第二金属层、保护层和公共电极层；
    其中所述第二金属层包括漏极和触控信号线，所述像素电极层包括像素电极，所述公共电极层包括触控电极，所述漏极电性连接于所述像素电极，所述触控信号线电性连接于所述触控电极。
  14. 根据权利要求13所述的阵列基板，其中，所述触控信号线与所述像素电极层同层设置。
  15. 根据权利要求13所述的阵列基板，其中，所述漏极叠设在所述像素电极层上。
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