WO2021027059A1 - 一种阵列基板及其制备方法、触控显示面板 - Google Patents

一种阵列基板及其制备方法、触控显示面板 Download PDF

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Publication number
WO2021027059A1
WO2021027059A1 PCT/CN2019/111997 CN2019111997W WO2021027059A1 WO 2021027059 A1 WO2021027059 A1 WO 2021027059A1 CN 2019111997 W CN2019111997 W CN 2019111997W WO 2021027059 A1 WO2021027059 A1 WO 2021027059A1
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Prior art keywords
layer
electrode
touch
drain
signal line
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PCT/CN2019/111997
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English (en)
French (fr)
Inventor
艾飞
宋德伟
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武汉华星光电技术有限公司
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Priority to US16/613,419 priority Critical patent/US20210041733A1/en
Publication of WO2021027059A1 publication Critical patent/WO2021027059A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present application relates to the technical field of touch display panel manufacturing, in particular to an array substrate and a preparation method thereof, and a touch display panel.
  • Liquid Crystal Display has now become the mainstream of display devices.
  • LTPS low-temperature polysilicon display technology
  • the transistor can obtain a higher switching current ratio.
  • each pixel transistor can be smaller in size. Increase the light transmission area of each pixel, increase the aperture ratio of the panel, improve the brightness and high resolution of the panel, and reduce the power consumption of the panel, thereby obtaining a better visual experience.
  • a liquid crystal display is a passive display device that relies on an electric field to adjust the arrangement of liquid crystal molecules to achieve light flux modulation
  • a fine active drive matrix is required to match the deflection of the liquid crystal in each pixel area.
  • the present application provides an array substrate, a preparation method thereof, and a touch display panel, which can solve the problems of increased equipment cost and complicated manufacturing process when the low-temperature polysilicon active matrix develops in the direction of reducing the feature size.
  • the present application provides a method for manufacturing an array substrate.
  • the method includes the following steps:
  • Step S10 providing a substrate on which an inorganic film layer, a thin film transistor and a touch signal line are formed, wherein the touch signal line is prepared on the surface of the inorganic film layer and is connected to the source of the thin film transistor. Drain in the same layer;
  • Step S20 preparing an inorganic insulating layer on the surface of the source/drain electrode and the touch signal line, and forming a patterned common electrode on the surface of the inorganic insulating layer;
  • step S30 a passivation layer is prepared on the surface of the common electrode, and the passivation layer and the inorganic insulating layer are patterned through the same photomask process to form a first electrode exposing the drain electrode and the touch signal line.
  • Step S40 forming a patterned pixel electrode and a touch electrode on the surface of the passivation layer, the pixel electrode is electrically connected to the drain through the first via hole, and the touch electrode passes through the second A via hole and the second via hole are electrically connected to the touch signal line and the common electrode, so that the touch signal line and the common electrode are bridged by the touch electrode.
  • the step S10 includes the following steps:
  • Step S101 preparing a light shielding layer on the substrate, and patterning the light shielding layer to form a light shielding block;
  • step S102 a buffer layer and an amorphous silicon layer are sequentially prepared on the shading block, the amorphous silicon layer is patterned, and the patterned amorphous silicon layer is subjected to laser laser and annealing processes to form Polysilicon layer;
  • Step S103 sequentially preparing a gate insulating layer and a gate metal layer on the polysilicon layer, patterning the gate metal layer to form a gate, and ion doping the polysilicon layer to form an active Floor;
  • step S104 an interlayer insulating layer is prepared on the gate, and the interlayer insulating layer and the gate insulating layer are patterned through the same photomask process to form source-drain heavy doping exposing the active layer. Source/drain vias in miscellaneous regions;
  • step S105 a source/drain metal layer is prepared on the interlayer insulating layer, and the source/drain metal layer is patterned to form the source/drain corresponding to the source/drain via hole, and form and The source/drain isolation of the touch signal line.
  • the step S103 includes the following steps:
  • the gate metal layer is patterned for the first time to form a gate middle block, and the polysilicon layer located on both sides of the gate middle block is ionized using the gate middle block as a mask. Doping to form the source and drain heavily doped regions;
  • the gate metal layer is patterned a second time to form the gate, and the polysilicon layer located on both sides of the gate is ion-doped using the gate as a mask, and the polysilicon layer is Lightly doped regions are formed on both sides of the gate portion.
  • the pixel electrode and the touch electrode are formed using the same material and simultaneously formed through the same photomask process.
  • the material of the pixel electrode and the touch electrode includes indium tin oxide, One or more of indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and zinc aluminum oxide.
  • the material of the inorganic insulating layer includes one or more of silicon nitride and silicon oxide.
  • an array substrate including:
  • a thin film transistor layer disposed on the substrate, and the thin film transistor layer includes source/drain electrodes
  • a touch signal line, the touch signal line and the source/drain electrode are in the same layer and insulated from each other;
  • An inorganic insulating layer disposed on the touch signal line and the source/drain;
  • Common electrodes are arranged on the inorganic insulating layer at intervals;
  • the passivation layer is arranged on the common electrode
  • a pixel electrode arranged on the passivation layer, and electrically connected to the source/drain of the thin film transistor through a first via hole;
  • the touch electrode is arranged in the same layer as the pixel electrode, and the touch electrode is electrically connected to the touch signal line and the common electrode, respectively.
  • the first via hole is arranged corresponding to the touch signal line and the source/drain, and the first via hole penetrates the passivation layer and the inorganic insulating layer and is connected to The touch signal line is in contact with the source/drain, and the touch signal line is electrically connected to the touch electrode through the corresponding first via hole.
  • a second via hole is formed on the passivation layer at a position corresponding to the common electrode, and the touch electrode is electrically connected to the common electrode through the second via hole.
  • the touch electrodes are located in the gap between two adjacent pixel electrodes and are insulated from the pixel electrodes, and the touch electrodes are distributed in a grid or in blocks. Shaped interval distribution.
  • the present application also provides a touch display panel, which includes the above-mentioned array substrate, and a color filter substrate disposed opposite to the array substrate, and a touch display panel located between the array substrate and the color filter.
  • the liquid crystal layer between the substrates.
  • the beneficial effects of the present application are: the array substrate, the preparation method thereof, and the touch display panel provided by the present application replace the organic planarization layer in the traditional process with an inorganic insulating layer, eliminating the need for the organic planarization layer in the traditional process
  • the photomask process is to perform photolithography on the inorganic insulating layer at the same time during the passivation layer photolithography process, which saves a photomask process, makes the process simple and reduces the cost, which is beneficial to the low-temperature polysilicon active matrix toward the shrinking feature
  • the direction of size development the use of inorganic materials to replace the organic materials of the planarization layer in the traditional structure can also prevent the contamination of the sputtering chamber when the common electrode is formed by the subsequent sputtering process.
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the application
  • FIG. 2 is a method flowchart of step S10 in the method for manufacturing an array substrate provided by an embodiment of the application;
  • 3 to 14 are schematic diagrams of the manufacturing process of the array substrate provided by the embodiments of the application.
  • FIG. 15 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • the present application addresses the technical problems of increasing equipment cost and complicated manufacturing process when the existing low-temperature polysilicon active matrix is developing in the direction of reducing the feature size.
  • This embodiment can solve the defects.
  • FIG. 1 it is a flow chart of the manufacturing method of the array substrate provided by the embodiment of this application.
  • the method includes the following steps:
  • Step S10 providing a substrate on which an inorganic film layer, a thin film transistor and a touch signal line are formed, wherein the touch signal line is prepared on the surface of the inorganic film layer and is connected to the source of the thin film transistor.
  • the drain is the same layer.
  • the step S10 includes the following steps:
  • Step S101 as shown in FIG. 3, a light-shielding layer (not shown) is prepared on the substrate 10, and the light-shielding layer is patterned to form a light-shielding pattern 11 after the first mask process.
  • Step S102 as shown in FIG. 4, a buffer layer 12 and an amorphous silicon layer are sequentially prepared on the light-shielding pattern 11, and laser laser and annealing processes are performed on the amorphous silicon layer to make the amorphous silicon form polysilicon, and A second photomask process is performed to form a polysilicon layer 130 after patterning.
  • Step S103 as shown in FIGS. 5 to 8, a gate insulating layer 14 and a gate metal layer (not shown) are sequentially prepared on the polysilicon layer 130, and a third photomask process is performed on the gate metal layer Specifically, the gate metal layer is first patterned to form a gate middle block 131', and the gate middle block 131' is used as a mask to align the gate middle block
  • the polysilicon layer 130 on both sides of 131' is doped with N+ ions, and source and drain heavily doped regions 130a are formed at both ends of the polysilicon layer 130.
  • the gate metal layer is patterned a second time to form a gate 131, and the polysilicon layer 130 located on both sides of the gate 131 is doped with N-ion using the gate 131 as a mask.
  • lightly doped regions 130b are formed on both sides of the part of the polysilicon layer 130 corresponding to the gate 131 to form an active layer.
  • the part of the polysilicon layer 130 corresponding to the gate 131 serves as the active layer.
  • step S104 as shown in FIG. 9, an interlayer insulating layer 15 is prepared on the gate 131, and the interlayer insulating layer 15 and the gate insulating layer 14 are patterned through a fourth photomask process to form The source/drain vias 150 of the source and drain heavily doped regions 130a of the active layer are exposed.
  • Step S105 as shown in FIG. 10, a source/drain metal layer is prepared on the interlayer insulating layer 15, and a fifth photomask process is performed on the source/drain metal layer to form a pattern corresponding to the source/drain.
  • the source/drain 132 of the via 150 and the touch signal line 16 insulated from the source/drain 132 are formed.
  • Step S20 as shown in FIG. 11, an inorganic insulating layer 17 is prepared on the surface of the source/drain electrode 132 and the touch signal line 16, and a first electrode layer is prepared on the surface of the inorganic insulating layer 17, and The first electrode layer is subjected to a sixth photomask process, and the common electrode 18 is formed after patterning.
  • the material of the inorganic insulating layer 17 includes, but is not limited to, one or more of silicon nitride and silicon oxide.
  • Step S30 as shown in FIGS. 12 to 13, a passivation layer 19 is prepared on the surface of the common electrode 18, and the passivation layer 19 and the inorganic insulating layer 17 are patterned through a seventh photomask process. After patterning, a first via 20 exposing the drain electrode 132 and the touch signal line 16 is formed, and a second via 20 ′ exposing the common electrode 18 is formed.
  • the material of the inorganic insulating layer 17 is the same as the material of the passivation layer 19, or the material of the inorganic insulating layer 17 and the material of the passivation layer 19 are silicon nitride. , Silicon oxide one of the two.
  • the seventh photomask process includes two etchings.
  • the passivation layer 19 is made of silicon nitride and the inorganic insulating layer 17 is made of silicon oxide as an example. 19 is etched to form the second via hole 20 ′, and the inorganic insulating layer 17 is etched a second time to form the first via hole 20.
  • Step S40 as shown in FIG. 14, a second electrode layer is prepared on the surface of the passivation layer 19, and an eighth photomask process is performed on the second electrode layer to form pixel electrodes 21 and touch electrodes after patterning.
  • the pixel electrode 21 is electrically connected to the drain 132 through the first via hole 20, and the touch electrode 21' passes through the first via hole 20 and the second via hole 20' respectively It is electrically connected to the touch signal line 16 and the common electrode 18 so that the touch signal line 16 and the common electrode 18 are bridged by the touch electrode 21 ′.
  • the material of the pixel electrode 21, the touch electrode 21' and the common electrode 18 includes, but is not limited to, indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and zinc aluminum oxide. One or more than one.
  • the photomask process for the organic planarization layer in the traditional process is omitted, and the inorganic insulating layer 17 does not need to be exposed. Instead, the inorganic insulating layer 17 is photoetched at the same time during the photolithography process of the passivation layer 19, which saves a photomask process, makes the process simple and reduces the cost. This process is beneficial to low-temperature polysilicon active matrix. Towards the direction of reducing the feature size.
  • the use of inorganic materials to replace the organic materials of the planarization layer in the traditional structure can prevent the subsequent formation of the common electrode 18 by a sputtering process from causing the decomposition of the planarization layer, thereby preventing subsequent formation of the common electrode 18 by the sputtering process It sometimes causes contamination of the sputtering chamber.
  • the present application also provides an array substrate prepared by the above-mentioned preparation method.
  • the array substrate includes: a substrate 10; a thin film transistor layer disposed on the substrate 10, and the thin film transistor layer includes an inorganic film. Layer and thin film transistor 13.
  • the inorganic film layer includes but is not limited to the buffer layer 12, the gate insulating layer 14, the interlayer insulating layer 15, etc.; the touch signal line 16 is arranged on the thin film transistor layer and is connected to the The source/drain electrodes 132 of the thin film transistor 13 are arranged in the same layer and are insulated; the inorganic insulating layer 17 is arranged on the touch signal line 16; the common electrode 18 is arranged on the inorganic insulating layer 17 at intervals; the passivation layer 19.
  • the pixel electrode 21 is arranged on the common electrode 18; the pixel electrode 21 is arranged on the passivation layer 19 and passes through the passivation layer 19 and the inorganic insulating layer 17 through the first via hole 20 and the The source/drain 132 of the thin film transistor 13 are electrically connected; the touch electrode 21' is arranged in the same layer as the pixel electrode 21, and the touch electrode 21' is connected to the touch signal line 16 and the common electrode 18 respectively Electric connection.
  • the first via 20 is provided corresponding to the touch signal line 16 and the source/drain 132, and the first via 20 is connected to the touch signal line 16 and the source/drain 132 Contact, the touch signal line 16 is electrically connected to the touch electrode 21' through the corresponding first via 20.
  • a second via 20' is formed on the passivation layer 19 at a position corresponding to the common electrode 18, and the touch electrode 21' is electrically connected to the common electrode 18 through the second via 20'.
  • the touch electrode 21' is located in the gap between two adjacent pixel electrodes 21, and is insulated from the pixel electrode 21.
  • the touch electrodes 21' are distributed in a grid shape, or distributed in a block shape at intervals.
  • the touch signal line 16 and the common electrode 18 are bridged by the touch electrode 21', and the touch electrode 21' is used to generate a touch voltage signal when subjected to a pressing operation, and send it to the corresponding
  • the common electrode 18 transmits the touch voltage signal, and the voltage of the common electrode 18 changes to realize touch control.
  • the array substrate may also include other conventional film layers, which are not limited here.
  • the present application also provides a touch display panel, including the array substrate described in the above-mentioned embodiment, and a color filter substrate disposed opposite to the array substrate, and a color filter substrate located between the array substrate and the color filter substrate. Please refer to the description in the above-mentioned embodiment for the specific structure of the array substrate, which will not be repeated here.
  • the thin film transistor 13 is turned on and provides pixel voltage signals for the pixel electrodes 21, and the touch signal line 16 passes the common voltage signal through
  • the touch electrode 21' is provided to the common electrode 18, and a voltage difference is formed between the pixel electrode 21 and the common electrode 18 to drive the deflection of liquid crystal molecules, so that the touch display panel performs display.
  • the touch electrode 21' In the touch phase of the touch display panel, the touch electrode 21' generates a touch voltage signal when subjected to a pressing operation, and transmits the touch voltage signal to the corresponding common electrode 18, and the common The voltage of the electrode 18 changes to achieve touch control.
  • the manufacturing process of the touch display panel of the present application is simple, and the cost is reduced, and the thin film transistor 13 can achieve a small size and meet the requirements of the manufacturing process.

Abstract

一种阵列基板及其制备方法、触控显示面板，在形成有薄膜晶体管（13）及触控信号线（16）的基板（10）上依次制备无机绝缘层（17）、公共电极（18）、钝化层（19），对钝化层（19）及无机绝缘层（17）图案化，以形成露出薄膜晶体管（13）的漏极（132）以及触控信号线（16）的第一过孔（20），以及形成露出公共电极（18）的第二过孔（20'），使得触控信号线（16）与公共电极（18）通过形成于钝化层（19）表面的触控电极（21'）桥接。

Description

一种阵列基板及其制备方法、触控显示面板 技术领域
本申请涉及触控显示面板制造技术领域，尤其涉及一种阵列基板及其制备方法、触控显示面板。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）现在成为显示装置中的主流。特别是低温多晶硅显示技术（LTPS），由于其较高的载流子迁移率可以使晶体管获得更高的开关电流比，在满足要求的充电电流条件下，每个像素晶体管可以更加小尺寸化，增加每个像素透光区，提高面板开口率，改善面板亮点和高分辨率，降低面板功耗，从而获得更好的视觉体验。
由于液晶显示器是一种靠电场来调节液晶分子的排列状态，从而实现光通量调制的被动型显示器件，需要精细的有源驱动矩阵（Array）配合各像素区液晶的偏转状况。鉴于低温多晶硅有源矩阵朝着不断缩小特征尺寸方向发展，随之而来的光刻技术进步导致了设备成本以指数增长，如何降低成本、简化工艺制程已成为当下研究热点。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请提供一种阵列基板及其制备方法、触控显示面板，能够解决低温多晶硅有源矩阵朝着缩小特征尺寸的方向发展时，造成设备成本增长，且制程工艺复杂的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S10，提供一基板，在所述基板上形成无机膜层和薄膜晶体管以及触控信号线，其中，所述触控信号线制备于所述无机膜层表面且与所述薄膜晶体管的源/漏极同层；
步骤S20，在所述源/漏极以及所述触控信号线表面制备无机绝缘层，并在所述无机绝缘层表面形成图案化的公共电极；
步骤S30，在所述公共电极表面制备钝化层，并通过同一道光罩制程图案化所述钝化层以及所述无机绝缘层，形成露出所述漏极以及所述触控信号线的第一过孔，以及形成露出所述公共电极的第二过孔；
步骤S40，在所述钝化层表面形成图案化的像素电极以及触控电极，所述像素电极通过所述第一过孔与所述漏极电连接，所述触控电极分别通过所述第一过孔以及所述第二过孔与所述触控信号线以及所述公共电极电连接，以使所述触控信号线与所述公共电极通过所述触控电极桥接。
在本申请的制备方法中，所述步骤S10包括以下步骤：
步骤S101，在所述基板上制备遮光层，并对所述遮光层进行图案化形成遮光图块；
步骤S102，在所述遮光图块上依次制备缓冲层和非晶硅层，对所述非晶硅层进行图案化，并对图案化的所述非晶硅层进行激光镭射及退火工艺，形成多晶硅层；
步骤S103，在所述多晶硅层上依次制备栅极绝缘层以及栅极金属层，对所述栅极金属层进行图案化以形成栅极，以及对所述多晶硅层进行离子掺杂以形成有源层；
步骤S104，在所述栅极上制备层间绝缘层，通过同一道光罩制程对所述层间绝缘层以及所述栅极绝缘层进行图案化以形成露出所述有源层的源漏重掺杂区的源/漏极过孔；
步骤S105，在所述层间绝缘层上制备源漏金属层，并对所述源漏金属层进行图案化以形成对应所述源/漏极过孔的所述源/漏极，以及形成与所述源/漏极绝缘的所述触控信号线。
在本申请的制备方法中，所述步骤S103包括以下步骤：
对所述栅极金属层进行第一次图案化以形成栅极中间图块，以所述栅极中间图块为掩膜对位于所述栅极中间图块两侧的所述多晶硅层进行离子掺杂，形成所述源漏重掺杂区；
对所述栅极金属层进行第二次图案化以形成所述栅极，以所述栅极为掩膜对位于所述栅极两侧的所述多晶硅层进行离子掺杂，在所述多晶硅层对应所述栅极部分的两侧形成轻掺杂区。
在本申请的制备方法中，所述像素电极以及所述触控电极是采用同种材料并经由同一道光罩制程同时形成的，所述像素电极以及所述触控电极的材料包括氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化锌铝中的一种或一种以上。
在本申请的制备方法中，所述无机绝缘层的材料包括氮化硅、氧化硅中的一种或一种以上。
为解决上述技术问题，本申请还提供一种阵列基板，包括：
基板；
薄膜晶体管层，设置于所述基板上，所述薄膜晶体管层包括源/漏极；
触控信号线，所述触控信号线与所述源/漏极同层且绝缘设置；
无机绝缘层，设置于所述触控信号线和所述源/漏极上；
公共电极，间隔的设置于所述无机绝缘层上；
钝化层，设置于所述公共电极上；
像素电极，设置于所述钝化层上，并通过第一过孔与所述薄膜晶体管的所述源/漏极电连接；
触控电极，与所述像素电极同层设置，所述触控电极分别与所述触控信号线以及所述公共电极电连接。
在本申请的阵列基板中，所述第一过孔对应所述触控信号线以及所述源/漏极设置，所述第一过孔贯穿所述钝化层以及所述无机绝缘层并与所述触控信号线以及所述源/漏极接触，所述触控信号线通过与之对应的所述第一过孔与所述触控电极电连接。
在本申请的阵列基板中，在所述钝化层上对应所述公共电极的位置形成有第二过孔，所述触控电极通过所述第二过孔与所述公共电极电连接。
在本申请的阵列基板中，所述触控电极位于相邻两所述像素电极之间的间隙处，且与所述像素电极绝缘设置，所述触控电极呈网格状分布，或者呈块状间隔分布。
为解决上述技术问题，本申请还提供一种触控显示面板，包括如上所述的阵列基板，以及与所述阵列基板对向设置的彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层。
 有益效果
本申请的有益效果为：本申请提供的阵列基板及其制备方法、触控显示面板，将传统工艺中的有机平坦化层替换为无机绝缘层，省去了传统工艺中对有机平坦化层的光罩工艺，而是在钝化层光刻制程中同时对无机绝缘层进行光刻，节省了一道光罩工艺，使得工艺制程简单，降低成本，从而有利于低温多晶硅有源矩阵朝着缩小特征尺寸的方向发展。另外，采用无机材料代替传统结构中平坦化层的有机材料，还可以防止后续采用溅射工艺形成公共电极时引起溅射腔室的污染。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的制备方法流程图；
图2为本申请实施例提供的阵列基板的制备方法中步骤S10的方法流程图；
图3~图14为本申请实施例提供的阵列基板的制备过程示意图；
图15为本申请实施例提供的阵列基板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的低温多晶硅有源矩阵朝着缩小特征尺寸的方向发展时，造成设备成本增长，且制程工艺复杂的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例提供的阵列基板的制备方法流程图。所述方法包括以下步骤：
步骤S10，提供一基板，在所述基板上形成无机膜层和薄膜晶体管以及触控信号线，其中，所述触控信号线制备于所述无机膜层表面且与所述薄膜晶体管的源/漏极同层。
具体地，结合图2~图10所示，所述步骤S10包括以下步骤：
步骤S101，如图3所示，在所述基板10上制备遮光层（未图示），并对所述遮光层进行图案化，在第一道光罩工艺之后形成遮光图块11。
步骤S102，如图4所示，在所述遮光图块11上依次制备缓冲层12和非晶硅层，对所述非晶硅层进行激光镭射及退火工艺，使非晶硅形成多晶硅，并进行第二道光罩工艺，图案化后形成多晶硅层130。
步骤S103，如图5~图8所示，在所述多晶硅层130上依次制备栅极绝缘层14以及栅极金属层（未图示），对所述栅极金属层进行第三道光罩工艺，具体地，首先对所述栅极金属层进行第一次图案化以形成栅极中间图块131’，以所述栅极中间图块131’为掩膜对位于所述栅极中间图块131’两侧的所述多晶硅层130进行N+离子掺杂，在所述多晶硅层130两端形成源漏重掺杂区130a。然后再对所述栅极金属层进行第二次图案化以形成栅极131，以所述栅极131为掩膜对位于所述栅极131两侧的所述多晶硅层130进行N-离子掺杂，在所述多晶硅层130对应所述栅极131部分的两侧形成轻掺杂区130b，以此形成有源层，所述多晶硅层130对应所述栅极131的部分作为所述有源层的沟道区。
步骤S104，如图9所示，在所述栅极131上制备层间绝缘层15，通过第四道光罩工艺对所述层间绝缘层15以及所述栅极绝缘层14进行图案化，形成露出所述有源层的源漏重掺杂区130a的源/漏极过孔150。
步骤S105，如图10所示，在所述层间绝缘层15上制备源漏金属层，并对所述源漏金属层进行第五道光罩工艺，图案化后形成对应所述源/漏极过孔150的所述源/漏极132，以及形成与所述源/漏极132绝缘的所述触控信号线16。
步骤S20，如图11所示，在所述源/漏极132以及所述触控信号线16表面制备无机绝缘层17，并在所述无机绝缘层17表面制备第一电极层，对所述第一电极层进行第六道光罩工艺，图案化后形成公共电极18。其中，所述无机绝缘层17的材料包括但不限于氮化硅、氧化硅中的一种或一种以上。
步骤S30，如图12~图13所示，在所述公共电极18表面制备钝化层19，并通过第七道光罩工艺对所述钝化层19以及所述无机绝缘层17进行图案化，图案化后形成露出所述漏极132以及所述触控信号线16的第一过孔20，以及形成露出所述公共电极18的第二过孔20’。
在一种实施例中，所述无机绝缘层17的材料与所述钝化层19的材料相同，或者，所述无机绝缘层17的材料与所述钝化层19的材料分别为氮化硅、氧化硅二者中的一者。
其中，所述第七道光罩工艺中包括两次蚀刻，以所述钝化层19为氮化硅以及所述无机绝缘层17为氧化硅为例进行说明，第一次对所述钝化层19进行蚀刻，以形成所述第二过孔20’，第二次对所述无机绝缘层17进行蚀刻，以形成所述第一过孔20。
步骤S40，如图14所示，在所述钝化层19表面制备第二电极层，并对所述第二电极层进行第八道光罩工艺，图案化后形成像素电极21以及触控电极21’，所述像素电极21通过所述第一过孔20与所述漏极132电连接，所述触控电极21’分别通过所述第一过孔20以及所述第二过孔20’与所述触控信号线16以及所述公共电极18电连接，以使所述触控信号线16与所述公共电极18通过所述触控电极21’桥接。
其中，所述像素电极21、所述触控电极21’以及所述公共电极18的材料包括但不限于氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化锌铝中的一种或一种以上。
在本实施例中，通过将传统工艺中的有机平坦化层替换为所述无机绝缘层17，省去了传统工艺中对有机平坦化层的光罩工艺，所述无机绝缘层17无需曝光，而是在所述钝化层19光刻制程中同时对所述无机绝缘层17进行光刻，节省了一道光罩工艺，使得工艺制程简单，降低成本，该工艺制程有利于低温多晶硅有源矩阵朝着缩小特征尺寸的方向发展。
另外，采用无机材料代替传统结构中平坦化层的有机材料，可以防止后续采用溅射工艺形成所述公共电极18时引起平坦化层的分解，从而防止后续采用溅射工艺形成所述公共电极18时引起溅射腔室的污染。
本申请还提供一种采用上述制备方法制备的阵列基板，如图15所示，所述阵列基板包括：基板10；薄膜晶体管层，设置于所述基板10上，所述薄膜晶体管层包括无机膜层以及薄膜晶体管13，所述无机膜层包括但不限于缓冲层12、栅绝缘层14、层间绝缘层15等；触控信号线16，设置于所述薄膜晶体管层上，并与所述薄膜晶体管13的源/漏极132同层且绝缘设置；无机绝缘层17，设置于所述触控信号线16上；公共电极18，间隔的设置于所述无机绝缘层17上；钝化层19，设置于所述公共电极18上；像素电极21，设置于所述钝化层19上，并通过贯穿所述钝化层19以及所述无机绝缘层17的第一过孔20与所述薄膜晶体管13的源/漏极132电连接；触控电极21’，与所述像素电极21同层设置，所述触控电极21’分别与所述触控信号线16以及所述公共电极18电连接。其中，所述第一过孔20对应所述触控信号线16以及所述源/漏极132设置，所述第一过孔20与所述触控信号线16以及所述源/漏极132接触，所述触控信号线16通过与之对应的所述第一过孔20与所述触控电极21’电连接。
在所述钝化层19上对应所述公共电极18的位置形成有第二过孔20’，所述触控电极21’通过所述第二过孔20’与所述公共电极18电连接。
在本实施例中，所述触控电极21’位于相邻两所述像素电极21之间的间隙处，且与所述像素电极21绝缘设置。在一种实施例中，所述触控电极21’呈网格状分布，或者呈块状间隔分布。
其中，所述触控信号线16与所述公共电极18通过所述触控电极21’桥接，所述触控电极21’用于在受到按压操作时产生触控电压信号，并向对应的所述公共电极18传输所述触控电压信号，所述公共电极18的电压发生变化以实现触控。
当然，所述阵列基板还可以包括其他常规膜层，此处不做限制。
本申请还提供一种触控显示面板，包括如上述实施例中所述的阵列基板，以及与所述阵列基板对向设置的彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层，所述阵列基板的具体结构请参照上述实施例中的描述，此处不再赘述。
其中，结合图15所示，在所述触控显示面板的显示阶段，所述薄膜晶体管13导通并为所述像素电极21提供像素电压信号，所述触控信号线16将公共电压信号通过所述触控电极21’提供给所述公共电极18，所述像素电极21与所述公共电极18之间形成电压差，从而驱动液晶分子偏转，使得所述触控显示面板进行显示。
在所述触控显示面板的触控阶段，所述触控电极21’在受到按压操作时产生触控电压信号，并向对应的所述公共电极18传输所述触控电压信号，所述公共电极18的电压发生变化以实现触控。
本申请的触控显示面板制程工艺简单，成本降低，且所述薄膜晶体管13可以实现小尺寸规格，满足制程需求。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S10，提供一基板，在所述基板上形成无机膜层和薄膜晶体管以及触控信号线，其中，所述触控信号线制备于所述无机膜层表面且与所述薄膜晶体管的源/漏极同层；
    步骤S20，在所述源/漏极以及所述触控信号线表面制备无机绝缘层，并在所述无机绝缘层表面形成图案化的公共电极；
    步骤S30，在所述公共电极表面制备钝化层，并通过同一道光罩制程图案化所述钝化层以及所述无机绝缘层，形成露出所述漏极以及所述触控信号线的第一过孔，以及形成露出所述公共电极的第二过孔；
    步骤S40，在所述钝化层表面形成图案化的像素电极以及触控电极，所述像素电极通过所述第一过孔与所述漏极电连接，所述触控电极分别通过所述第一过孔以及所述第二过孔与所述触控信号线以及所述公共电极电连接，以使所述触控信号线与所述公共电极通过所述触控电极桥接。
  2. 根据权利要求1所述的制备方法，其中，所述步骤S10包括以下步骤：
    步骤S101，在所述基板上制备遮光层，并对所述遮光层进行图案化形成遮光图块；
    步骤S102，在所述遮光图块上依次制备缓冲层和非晶硅层，对所述非晶硅层进行图案化，并对图案化的所述非晶硅层进行激光镭射及退火工艺，形成多晶硅层；
    步骤S103，在所述多晶硅层上依次制备栅极绝缘层以及栅极金属层，对所述栅极金属层进行图案化以形成栅极，以及对所述多晶硅层进行离子掺杂以形成有源层；
    步骤S104，在所述栅极上制备层间绝缘层，通过同一道光罩制程对所述层间绝缘层以及所述栅极绝缘层进行图案化以形成露出所述有源层的源漏重掺杂区的源/漏极过孔；
    步骤S105，在所述层间绝缘层上制备源漏金属层，并对所述源漏金属层进行图案化以形成对应所述源/漏极过孔的所述源/漏极，以及形成与所述源/漏极绝缘的所述触控信号线。
  3. 根据权利要求2所述的制备方法，其中，所述步骤S103包括以下步骤：
    对所述栅极金属层进行第一次图案化以形成栅极中间图块，以所述栅极中间图块为掩膜对位于所述栅极中间图块两侧的所述多晶硅层进行离子掺杂，形成所述源漏重掺杂区；
    对所述栅极金属层进行第二次图案化以形成所述栅极，以所述栅极为掩膜对位于所述栅极两侧的所述多晶硅层进行离子掺杂，在所述多晶硅层对应所述栅极部分的两侧形成轻掺杂区。
  4. 根据权利要求1所述的制备方法，其中，所述像素电极以及所述触控电极是采用同种材料并经由同一道光罩制程同时形成的，所述像素电极以及所述触控电极的材料包括氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化锌铝中的一种或一种以上。
  5. 根据权利要求1所述的制备方法，其中，所述无机绝缘层的材料包括氮化硅、氧化硅中的一种或一种以上。
  6. 一种阵列基板，其包括：
    基板；
    薄膜晶体管层，设置于所述基板上，所述薄膜晶体管层包括源/漏极；
    触控信号线，所述触控信号线与所述源/漏极同层且绝缘设置；
    无机绝缘层，设置于所述触控信号线和所述源/漏极上；
    公共电极，间隔的设置于所述无机绝缘层上；
    钝化层，设置于所述公共电极上；
    像素电极，设置于所述钝化层上，并通过第一过孔与所述薄膜晶体管的所述源/漏极电连接；
    触控电极，与所述像素电极同层设置，所述触控电极分别与所述触控信号线以及所述公共电极电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第一过孔对应所述触控信号线以及所述源/漏极设置，所述第一过孔贯穿所述钝化层以及所述无机绝缘层并与所述触控信号线以及所述源/漏极接触，所述触控信号线通过与之对应的所述第一过孔与所述触控电极电连接。
  8. 根据权利要求6所述的阵列基板，其中，在所述钝化层上对应所述公共电极的位置形成有第二过孔，所述触控电极通过所述第二过孔与所述公共电极电连接。
  9. 根据权利要求6所述的阵列基板，其中，所述触控电极位于相邻两所述像素电极之间的间隙处，且与所述像素电极绝缘设置，所述触控电极呈网格状分布，或者呈块状间隔分布。
  10. 一种触控显示面板，其包括如权利要求6所述的阵列基板，以及与所述阵列基板对向设置的彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层。
PCT/CN2019/111997 2019-08-09 2019-10-18 一种阵列基板及其制备方法、触控显示面板 WO2021027059A1 (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111129033B (zh) * 2019-12-19 2024-01-19 武汉华星光电技术有限公司 阵列基板及其制备方法
CN111223818B (zh) * 2020-01-17 2022-07-12 深圳市华星光电半导体显示技术有限公司 像素驱动电路及其制作方法
CN111273492A (zh) * 2020-02-25 2020-06-12 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
CN114115572A (zh) * 2020-08-26 2022-03-01 深圳市柔宇科技股份有限公司 触控显示面板、其制作方法及电子设备
CN111900129B (zh) * 2020-09-14 2022-06-10 武汉华星光电技术有限公司 一种显示面板、阵列基板及其制备方法
CN113571530A (zh) * 2021-07-07 2021-10-29 武汉华星光电技术有限公司 阵列基板及其制备方法
CN114156288A (zh) * 2021-11-30 2022-03-08 武汉华星光电技术有限公司 阵列基板及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104656332A (zh) * 2015-01-28 2015-05-27 上海天马微电子有限公司 阵列基板及其制备方法和显示装置
CN106876417A (zh) * 2017-04-24 2017-06-20 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN109887885A (zh) * 2019-03-01 2019-06-14 武汉华星光电技术有限公司 阵列基板的制作方法及阵列基板
WO2019137062A1 (zh) * 2018-01-11 2019-07-18 京东方科技集团股份有限公司 阵列基板及其制造方法、触控显示面板以及触控显示装置
CN110085601A (zh) * 2018-01-26 2019-08-02 华为技术有限公司 一种阵列基板及其制备方法、显示面板、终端设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104808376B (zh) * 2015-05-11 2018-05-11 厦门天马微电子有限公司 阵列基板及显示装置
CN106971980A (zh) * 2017-03-30 2017-07-21 武汉华星光电技术有限公司 一种阵列基板的制作方法及阵列基板
CN108376687B (zh) * 2018-03-30 2020-05-19 武汉华星光电技术有限公司 阵列基板及其制备方法、内嵌式触摸屏
CN108649036B (zh) * 2018-04-28 2021-02-02 武汉华星光电技术有限公司 一种阵列基板及其制作方法
CN108550581A (zh) * 2018-05-04 2018-09-18 武汉华星光电技术有限公司 一种低温多晶硅阵列基板及其制备方法
CN109101136B (zh) * 2018-08-21 2021-09-03 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104656332A (zh) * 2015-01-28 2015-05-27 上海天马微电子有限公司 阵列基板及其制备方法和显示装置
CN106876417A (zh) * 2017-04-24 2017-06-20 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
WO2019137062A1 (zh) * 2018-01-11 2019-07-18 京东方科技集团股份有限公司 阵列基板及其制造方法、触控显示面板以及触控显示装置
CN110085601A (zh) * 2018-01-26 2019-08-02 华为技术有限公司 一种阵列基板及其制备方法、显示面板、终端设备
CN109887885A (zh) * 2019-03-01 2019-06-14 武汉华星光电技术有限公司 阵列基板的制作方法及阵列基板

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