WO2019137062A1 - 阵列基板及其制造方法、触控显示面板以及触控显示装置 - Google Patents

阵列基板及其制造方法、触控显示面板以及触控显示装置 Download PDF

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Publication number
WO2019137062A1
WO2019137062A1 PCT/CN2018/111586 CN2018111586W WO2019137062A1 WO 2019137062 A1 WO2019137062 A1 WO 2019137062A1 CN 2018111586 W CN2018111586 W CN 2018111586W WO 2019137062 A1 WO2019137062 A1 WO 2019137062A1
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Prior art keywords
substrate
thin film
layer
insulating planarization
touch
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PCT/CN2018/111586
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English (en)
French (fr)
Inventor
马明超
樊君
李付强
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/338,288 priority Critical patent/US11385732B2/en
Publication of WO2019137062A1 publication Critical patent/WO2019137062A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present disclosure relates to the field of touch display technology, and discloses an array substrate and a method of manufacturing the same, a touch display panel, and a touch display device.
  • the touch display device is a device that can realize display and can realize touch.
  • touch display devices generally include a touch display panel, wherein the touch display panel generally includes a display panel and a touch panel.
  • the touch display panel can be divided into a built-in touch display panel and an out-cell touch display panel according to the relative positional relationship between the touch panel and the display panel.
  • the built-in touch display panel can be further divided into a built-in in-cell touch display panel (also referred to as an in-cell touch display panel) and an on-cell touch panel. Display panel.
  • the built-in in-cell touch display panel has been widely researched and applied for its convenience in manufacturing thin and light products.
  • a built-in in-cell touch display panel generally includes an array substrate, wherein the array substrate generally includes: a substrate substrate, and a thin film transistor and a touch electrode sequentially formed on the substrate , common electrode and pixel electrode. Additionally, the touch electrodes are connected to the corresponding common electrodes, and the pixel electrodes are connected to the drains of the corresponding thin film transistors. In addition, an insulating planarization layer is formed between the thin film transistor and the touch electrode.
  • the thin film transistor is turned on and provides a pixel voltage signal for the pixel electrode; meanwhile, the touch electrode provides a common voltage signal for the common electrode, This creates a voltage difference between the pixel electrode and the common electrode to realize the display function of the touch display panel.
  • the touch electrode provides a touch voltage signal to the common electrode, so that the common electrode experiences a voltage change after the touch is sensed, thereby implementing the touch function of the touch display panel.
  • the pixel electrode is located at a side of the common electrode facing away from the thin film transistor. Therefore, during operation of the touch display panel provided with the above array substrate, in particular, during the display phase, a large capacitance is easily formed between the common electrode and an electrode (for example, a source) in the thin film transistor. Therefore, in order to achieve a good display effect of the touch display panel, it is generally required to increase the size of the common voltage signal supplied to the common electrode, which will cause an increase in power consumption when the touch display panel operates. Meanwhile, in the above array substrate, the touch electrodes are formed on the insulating planarization layer. Currently, touch electrodes are generally made of a metal material, and a touch electrode is usually formed by a sputtering process.
  • the insulating planarization layer is typically made of an organic material.
  • the insulating planarization layer will easily be decomposed in the sputtering chamber having a higher temperature, thereby causing contamination of the sputtering chamber.
  • an array substrate includes: a substrate substrate; a plurality of thin film transistors arranged in an array on the substrate; an insulating planarization layer, wherein the insulating planarization layer is located away from the substrate And a plurality of via holes respectively exposing a drain of each of the thin film transistors; a plurality of pixel electrodes arranged in an array on the side of the insulating planarization layer away from the plurality of thin film transistors, each a pixel electrode is connected to a drain of the corresponding thin film transistor through a via hole in the insulating planarization layer; and a plurality of touch arrays arranged on the side of the plurality of pixel electrodes away from the insulating planarization layer And a plurality of common electrodes arranged in an array on the side of the plurality of touch electrodes away from the plurality of pixel electrodes, each common electrode being connected to the corresponding touch electrode.
  • the insulating planarization layer includes a single layer having a thickness greater than or equal to 6 ⁇ m.
  • the insulating planarization layer includes a plurality of sub-layers, and the total thickness of the plurality of sub-layers is greater than or equal to 6 ⁇ m.
  • the insulating planarization layer includes a first sub-layer adjacent to the plurality of thin film transistors and a second sub-layer away from the plurality of thin film transistors,
  • the thickness of the first sub-layer is greater than or equal to 4 ⁇ m, and the thickness of the second sub-layer is between 2 ⁇ m and 4 ⁇ m.
  • the insulating planarization layer is made of an acryl material.
  • the array substrate provided by the embodiment of the present disclosure further includes: a plurality of data lines on the base substrate, wherein a source of each thin film transistor is connected to a corresponding data line; and each touch An orthographic projection of the electrode on the substrate substrate at least partially overlaps with an orthographic projection of the corresponding data line on the substrate substrate.
  • each common electrode includes a first portion and a second portion, and the orthographic projection of the first portion on the substrate substrate and the corresponding touch electrode are The orthographic projections on the substrate substrate at least partially overlap, the orthographic projection of the second portion on the substrate substrate does not overlap with the orthographic projection of the corresponding touch electrode on the substrate substrate, and The common electrode is connected to the corresponding touch electrode through the first portion.
  • the array substrate provided by the embodiment of the present disclosure further includes: a first dielectric layer between the plurality of pixel electrodes and the plurality of touch electrodes, and the plurality of touch electrodes a second dielectric layer between the plurality of common electrodes, wherein an orthographic projection of the second dielectric layer on the substrate substrate and the plurality of pixel electrodes on the substrate The orthographic projections do not overlap.
  • the first dielectric layer is made of an inorganic material
  • the second dielectric layer is made of an organic material or an inorganic material.
  • each of the thin film transistors includes a low temperature polysilicon thin film transistor.
  • a touch display panel is also provided.
  • the touch display panel includes the array substrate described in any of the previous embodiments.
  • a touch display device is also provided.
  • the touch display device includes the touch display panel described in any of the preceding embodiments.
  • a method of fabricating an array substrate includes the steps of: providing a base substrate (S1); forming a plurality of thin film transistors (S2) arranged in an array on the base substrate; and separating the plurality of thin film transistors from the substrate
  • An insulating planarization layer is formed on one side and a plurality of via holes respectively exposing a drain of each thin film transistor are formed in the insulating planarization layer (S3); the insulating planarization layer is away from the plurality of thin films
  • an insulating planarization layer is formed on a side of the plurality of thin film transistors away from the substrate substrate and is flat at the insulation
  • the step of forming a plurality of vias in the layer includes the substep of depositing an insulating planarizing material on the side of the plurality of thin film transistors remote from the substrate (S31); planarizing the insulating layer at the layer Forming the plurality of vias in the material (S32); and repeating the above two sub-steps a plurality of times such that the plurality of vias in each of the insulating planarization materials formed thereafter are insulated from each of the previously formed layers
  • the corresponding via holes in the planarization material are in communication with each other (S33).
  • the manufacturing method for an array substrate further includes the following steps: after forming the plurality of pixel electrodes and before forming the plurality of touch electrodes, in the plurality of Forming a first dielectric layer on a side of the pixel electrode away from the insulating planarization layer; and after forming the plurality of touch electrodes and before forming the plurality of common electrodes, at the plurality of touch electrodes A second dielectric layer is formed on a side away from the plurality of pixel electrodes, and a plurality of via holes are formed in the second dielectric layer such that each via corresponds to one touch electrode.
  • FIG. 1 schematically illustrates a top view of an array substrate in accordance with an embodiment of the present disclosure
  • Figure 2 is a schematic side view taken along line A-A of Figure 1;
  • Figure 3 is a schematic side view taken along line B-B of Figure 1;
  • FIG. 4 schematically illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 5 schematically shows a flow chart of step S2 in Figure 4;
  • Fig. 6 schematically shows a flow chart of step S3 in Fig. 4.
  • the array substrate includes: a substrate substrate; a plurality of thin film transistors 11 arranged in an array on the substrate substrate 10; an insulating planarization layer 12, the insulating planarization layer 12 is located away from the lining of the plurality of thin film transistors 11.
  • a plurality of pixel electrodes 13 which are planarized in insulation
  • the layers 12 are arranged in an array on a side away from the plurality of thin film transistors 11, and each of the pixel electrodes 13 is connected to the drain 116 of the corresponding thin film transistor 11 through one via of the insulating planarization layer 12;
  • the plurality of touch electrodes 15 are arranged in an array on a side of the plurality of pixel electrodes 13 away from the insulating planarization layer 12; a plurality of common electrodes 17 and the plurality of common electrodes 17 are The touch electrodes 15 are arranged in an array on a side away from the pixel electrodes 13, and each of the common electrodes 17 is connected to the corresponding touch electrodes 15.
  • inventions of the present disclosure provide an array substrate.
  • the array substrate can be applied to a touch display panel to implement a display function and a touch function of the touch display panel.
  • the array substrate includes a base substrate 10 and a thin film transistor 11, an insulating planarization layer 12, a pixel electrode 13, a touch electrode 15, and a common electrode 17 which are sequentially formed on the base substrate 10.
  • the number of the thin film transistors 11 is plural, and the plurality of thin film transistors 11 are arranged in an array on the base substrate 10.
  • the insulating planarization layer 12 is on the thin film transistor 11 and covers the thin film transistor 11.
  • the pixel electrode 13 is formed on the insulating planarization layer 12.
  • the pixel electrode 13 is located on the side of the insulating planarization layer 12 away from the thin film transistor 11.
  • the number of the pixel electrodes 13 is also plural, and the plurality of pixel electrodes 13 are arranged in an array.
  • Each of the pixel electrodes 13 is connected to the drain 116 of the corresponding thin film transistor 11 through a corresponding via hole in the insulating planarization layer 12.
  • a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Gallium Zinc Oxide (IGZO) can be used.
  • the touch electrode 15 is located on a side of the pixel electrode 13 away from the insulating planarization layer 12 , that is, the touch electrode 15 is located above the pixel electrode 13 .
  • the common electrode 17 is located on a side of the touch electrode 15 away from the pixel electrode 13 , that is, the common electrode 17 is located above the touch electrode 15 . Further, the common electrode 17 is connected to the corresponding touch electrode 15.
  • a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Gallium Zinc Oxide (IGZO) can be used.
  • the thin film transistor 11 is turned on, and the thin film transistor 11 is provided for the pixel electrode 13 Pixel voltage signal.
  • a common voltage signal is supplied to the corresponding common electrode 17 through the touch electrode 15.
  • the touch electrode 15 provides a touch voltage signal to the corresponding common electrode 17.
  • the voltage signal on the common electrode 17 will change, thereby implementing the touch function of the touch display panel.
  • an insulating planarization layer 12 is disposed between the thin film transistor 11 and the pixel electrode 13, and the common electrode 17 is disposed on a side of the touch electrode 15 away from the pixel electrode 13.
  • the touch electrode 15 is located on a side of the pixel electrode 13 away from the insulating planarization layer 12. That is, the common electrode 17 is disposed on the side of the pixel electrode 13 away from the insulating planarization layer 12, and the touch electrode 15, the pixel electrode 13, and the insulating planarization layer 12 are interposed between the common electrode 17 and the thin film transistor 11.
  • the distance between the common electrode 17 and the thin film transistor 11 is made large, for example, the distance between the common electrode 17 and the source 115 of the thin film transistor 11 is large.
  • the pixel electrode 13 is located between the thin film transistor 11 and the common electrode 17. In this case, when the array substrate provided by the embodiment of the present disclosure is applied to the touch display panel, the pixel electrode 13 can be blocked in each of the common electrode 17 and the thin film transistor 11 during the operation of the touch display panel. The power line generated between the electrodes.
  • the common electrode 17 and the thin film can be reduced.
  • the capacitance between the electrodes (eg, source 115) in transistor 11. In this way, the voltage required to be supplied to the common electrode 17 when the touch display panel is displayed can be reduced, and the power consumption of the touch display panel during operation can be reduced.
  • the pixel electrode 13 is formed on the insulating planarization layer 12, and the touch electrode 15 is prevented from being formed on the insulating planarization layer 12.
  • the decomposition of the insulating planarization layer 12 is not caused by the high temperature. Therefore, contamination caused by the sputtering chamber when the touch electrode 15 is formed by the sputtering process can be avoided.
  • the insulating planarization layer 12 on the thin film transistor 11 is generally made of an organic material.
  • the insulating planarization layer 12 and the insulating planarization layer 12 are formed.
  • a protective layer of inorganic material is formed.
  • via holes corresponding to the drain electrodes 116 are also formed in the inorganic material protective layer, and advantageously, the diameter of the via holes in the inorganic material protective layer is smaller than the diameter of the via holes in the insulating planarization layer 12.
  • the common electrode 17 is disposed at the uppermost layer.
  • a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Gallium Zinc Oxide (IGZO) can be used. Therefore, there is no need to worry about the oxidation of the common electrode 17, and it is not necessary to form a protective layer on the common electrode 17. In this way, the total thickness of the array substrate can be reduced, thereby reducing the total thickness of the touch display panel, and facilitating the slim design of the touch display panel.
  • the thin film transistor 11 When the array substrate provided in the above embodiment is applied to the touch display panel, during operation of the touch display panel, for example, during the display phase, the thin film transistor 11 is turned on, and the thin film transistor 11 supplies the pixel to the pixel electrode 13. Voltage signal. At the same time, a common voltage signal is supplied to the corresponding common electrode 17 through the touch electrode 15. At this time, a voltage difference is generated between the pixel electrode 13 and the common electrode 17, thereby realizing the display function of the touch display panel. Similarly, during the touch phase, the touch voltage is provided to the common electrode 17 through the touch electrode 15 to implement the touch function of the touch display panel.
  • the common electrode 17 and the pixel electrode 13 together realize the display function of the touch display panel; during the touch phase, the common electrode 17 serves as a part of the touch sensing element, thereby helping to implement the touch display panel. Touch function. Therefore, in the embodiment of the present disclosure, the number of the common electrodes 17 is also plural, and the coverage area of each of the common electrodes 17 can be set according to actual needs. For example, it can be determined according to the required touch resolution and the number of touch electrodes 15 that the touch driving chip can support.
  • the number of sub-layers and the total thickness of the insulating planarization layer 12 can be set according to actual needs.
  • the insulating planarization layer 12 may have a single layer structure.
  • the thickness of the insulating planarization layer 12 can be set to be greater than or equal to 6 ⁇ m.
  • the distance between the common electrode 17 and the thin film transistor 11 can be made larger, thereby reducing the electrodes in the common electrode 17 and the thin film transistor 11 during operation of the touch display panel (specifically, during the display phase) ( For example, the capacitance between sources 115). Therefore, the voltage required to be supplied to the common electrode 17 when the touch display panel is displayed can be reduced, thereby reducing the power consumption of the touch display panel during operation.
  • the insulating planarization layer 12 may also include a multilayer structure.
  • the insulating planarization layer 12 may include a plurality of sub-layers, for example, two, three or more sub-layers.
  • the respective sub-layers of the insulating planarization layer 12 are stacked and covered with the thin film transistor 11.
  • the total thickness of the plurality of sub-layers of the insulating planarization layer 12 may be set to be greater than or equal to 6 ⁇ m.
  • the thickness of each of the insulating planarization layers 12 having a multilayer structure is relatively small.
  • the process difficulty for forming the insulating planarization layer 12 can be reduced, and at the same time, it is also convenient to form via holes in the insulating planarization layer 12.
  • a via hole penetrating the sub-layer is disposed at a position corresponding to the drain 116 of the thin film transistor 11 in each sub-layer, and the via hole is exposed.
  • the drain 116 of the thin film transistor 11 and the corresponding vias in the respective sub-layers of the insulating planarization layer 12 are in communication with each other.
  • an insulating planarization layer 12 is further disposed between the thin film transistor 11 and the pixel electrode 13, and the total thickness of the insulating planarization layer 12 is greater than or equal to 6 ⁇ m.
  • the thin film transistor 11 and the pixel electrode 13 can be increased in accordance with an embodiment of the present disclosure. The insulation reliability, while also increasing the distance between the common electrode 17 and the thin film transistor 11.
  • the insulating planarization layer 12 may include at least one sub-layer.
  • the number of sub-layers of the insulating planarization layer 12 can be determined according to the actual needs of the product, the manufacturing process capability, and the like.
  • the distance between the pixel electrode 13 and the thin film transistor 11 in the array substrate can be calculated according to the actual needs of the product, and the distance can also be understood as the total thickness of the insulating planarization layer 12.
  • the total thickness needs to be greater than or equal to 6 ⁇ m.
  • the total thickness calculated, the manufacturing process of the insulating planarization layer 12, and the process capability of the manufacturing process used to fabricate the insulating planarization layer 12 (for example, the maximum thickness of the film layer that can be achieved by the manufacturing process)
  • the number of sublayers of the insulating planarization layer 12 is calculated.
  • the number of sub-layers of the insulating planarization layer 12 may be two.
  • the total thickness of the insulating planarization layer 12 can be increased to some extent as compared with the insulating planarization layer 12 having a single layer structure, so as to increase the distance between the thin film transistor 11 and the pixel electrode 13, and increase the thin film transistor.
  • the distance between the common electrode 17 and the common electrode 17 reduces the capacitance between the common electrode 17 and the electrode (such as the source 115) in the thin film transistor 11 when the touch display panel operates, and finally reduces the operation of the touch display panel. Power consumption.
  • the process steps for fabricating the array substrate can be reduced as required to satisfy the total thickness of the insulating planarization layer 12 as compared with the insulating planarization layer 12 including three or more sub-layers.
  • the thickness of the first sub-layer close to the thin film transistor 11 is greater than or equal to 4 ⁇ m. This means that after the fabrication of the thin film transistor 11 is completed, the thickness of the first sub-layer of the insulating planarization layer 12 formed first is greater than or equal to 4 ⁇ m. In this manner, the planarization effect of the first sub-layer of the insulating planarization layer 12 on other structures that have been formed on the substrate 10 can be enhanced, thereby facilitating the formation of subsequent sub-layers of the insulating planarization layer 12.
  • the drain 116 of the thin film transistor 11 is usually on the base substrate 10
  • the raised state such that the portion of the first sub-layer of the insulating planarization layer 12 corresponding to the drain 116 of the thin film transistor 11 will typically have a smaller thickness (generally less than the actual setting of the first sub-layer of the insulating planarization layer 12) Thickness) and does not cause an increase in the difficulty of forming via holes in the first sub-layer.
  • the thickness of the second sublayer of the insulating planarization layer 12 away from the thin film transistor 11 is 2 ⁇ m to 4 ⁇ m. This means that after the formation of the first sub-layer of the thin film transistor 11 and the insulating planarization layer 12, the thickness of the second sub-layer of the subsequently formed insulating planarization layer 12 may be 2 ⁇ m to 4 ⁇ m.
  • the first sub-layer of the insulating layer planarization layer is substantially planar away from the surface of the substrate substrate 10. That is, as shown in FIG.
  • the upper surface of the first sub-layer of the insulating layer planarization layer is substantially flat.
  • the thickness of each sub-layer of the subsequently formed insulating planarization layer 12 will be substantially the same in each region.
  • the thickness of the second sub-layer of the subsequently formed insulating planarization layer 12 is selected to be 2 ⁇ m to 4 ⁇ m. In such a manner, under the premise that the total thickness of the insulating planarization layer 12 having a plurality of sub-layers is required to be required, it is also possible to prevent the thickness of each sub-layer due to the insulating planarization layer 12 from being too large. The difficulty in forming vias is increased.
  • the insulating planarization layer 12 includes a plurality of sub-layers, in order to form a plurality of sub-layers of the insulating planarization layer 12 and via holes penetrating the respective sub-layers, the following methods may be employed.
  • a plurality of sub-layer structures forming the insulating planarization layer 12 may be sequentially stacked, and then a plurality of through holes penetrating through the respective sub-layers may be formed at one time by a patterning process, wherein each of the through holes is exposed Corresponding to the drain 116 of the thin film transistor 11.
  • each sub-layer of the insulating planarization layer 12 is formed, a patterning process is employed to form a plurality of passes through the sub-layer in the sub-layer of the insulating planarization layer 12. Holes, wherein each of the vias corresponds to the position of the drain 116 of the corresponding thin film transistor 11 and communicates with a corresponding via in the previous sub-layer. For example, assume that the number of sublayers of the insulating planarization layer 12 is two.
  • the first sub-layer of the insulating planarization layer 12 may be formed first, the first sub-layer covering the thin film transistor 11 and the substrate substrate 10; and then, planarizing the insulation
  • a plurality of via holes respectively corresponding to the drains 116 of each of the thin film transistors 11 are formed in the first sub-layer of the layer 12, wherein each of the via holes exposes the drain 116 of the corresponding thin film transistor 11; and then, an insulating flat is formed a second sub-layer of the layer 12, the second sub-layer being on the first sub-layer of the insulating planarization layer 12 and covering the first sub-layer; and finally, forming a difference in the second sub-layer of the insulating planarization layer 12 a plurality of vias corresponding to the drain 116 of each of the thin film transistors 11, the vias in the second sub-layer of the insulating planarization layer 12 are in one-to-one correspondence with the vias in the first sub-layer of the insulating
  • the material for forming the insulating planarization layer 12 can be selected according to actual needs.
  • the insulating layer planarization layer may be made of an organic material such as an acrylic material.
  • the thickness of the insulating planarization layer 12 can be increased by selecting the material of the insulating planarization layer 12 as an organic material as compared with the insulating planarization layer 12 made of an inorganic material.
  • only exposure and development are required, and etching and gel removal are not required. Thus, the process steps for fabricating the array substrate can be reduced.
  • the array substrate provided by the embodiment of the present disclosure further includes a plurality of data lines 2 on the substrate substrate 10 , wherein the source 115 of each thin film transistor 11 and corresponding data Line 2 is connected. Furthermore, the orthographic projection of each touch electrode 15 on the base substrate 10 at least partially overlaps with the orthographic projection of the corresponding data line 2 on the base substrate 10. This means that the orthographic projection of each touch electrode 15 on the base substrate 10 can completely coincide with the orthographic projection of the corresponding data line 2 on the base substrate 10. Alternatively, the orthographic projection of each touch electrode 15 on the base substrate 10 may also fall within the orthographic projection of the corresponding data line 2 on the base substrate 10.
  • each touch electrode 15 on the base substrate 10 may also cover the orthographic projection of the corresponding data line 2 on the base substrate 10, and advantageously, in a direction perpendicular to the data line 2
  • the orthographic projection of each touch electrode 15 on the base substrate 10 may be slightly larger than the orthographic projection of the corresponding data line 2 on the base substrate 10. Therefore, in the embodiment of the present disclosure, each touch electrode 15 will be formed directly above the data line 2, so the touch electrode 15 will not cover the pixel display area and will not open to the touch display panel. The rate has an adverse effect.
  • each common electrode 17 includes a first portion (eg, a portion directly above the touch electrode 15 in the figure) and a second portion (eg, except for the first portion in the figure) Other than the part), the common electrode 17 is connected to the corresponding touch electrode 15 through the first portion. Further, in the array substrate provided by the embodiment of the present disclosure, the orthographic projection of the first portion on the substrate 10 and the orthographic projection of the corresponding touch electrode 15 on the substrate 10 are performed for each common electrode 17. At least partially overlapping, and the orthographic projection of the second portion on the base substrate 10 does not overlap with the orthographic projection of the corresponding touch electrode 15 on the base substrate 10.
  • the orthographic projection of the other portion of the common electrode 17 on the base substrate 10 and the orthographic projection of the touch electrode 15 on the base substrate 10 do not overlap except for the portion where the common electrode 17 is connected to the corresponding touch electrode 15. .
  • the type of the thin film transistor 11 can be set according to actual needs.
  • the type of the thin film transistor 11 can be selected according to the material of the active layer 111.
  • the thin film transistor 11 may be an amorphous silicon thin film transistor, a single crystal silicon thin film transistor, a polysilicon thin film transistor, a metal oxide thin film transistor, or the like.
  • the thin film transistor 11 can be selected according to the structure.
  • the thin film transistor 11 may be a top gate thin film transistor or a bottom gate thin film transistor.
  • the structure when the material of the active layer 111 in the thin film transistor 11 is selected as low temperature polysilicon, the structure may be selected to be a top gate type, that is, the thin film transistor 11 in the embodiment of the present disclosure is a top gate type.
  • Low temperature polysilicon thin film transistor Specifically, referring to FIG. 2, in an embodiment of the present disclosure, the thin film transistor 11 includes an active layer 111, a gate insulating layer 112, a gate electrode 113, an interlayer insulating layer 114, a source 115, and a drain 116.
  • the active layer 111 is formed on the base substrate 10, and the material of the active layer 111 is low temperature polysilicon.
  • the gate insulating layer 112 covers the active layer 111 and the base substrate 10, and the gate electrode 113 is formed at a position on the gate insulating layer 112 corresponding to the active layer 111.
  • a gate line 1 is also provided in the same layer as the gate electrode 113, and the gate electrode 113 is connected to the corresponding gate line 1.
  • the interlayer insulating layer 114 covers the gate electrode 113, the gate line 1 and the gate insulating layer 112, and the source 115 and the drain 116 are formed on the interlayer insulating layer 114, wherein the source 115 is on the base substrate 10
  • the orthographic projections on the upper projections and the drains 116 on the base substrate 10 are respectively located on both sides of the orthographic projection of the gate electrodes 113 on the substrate substrate 10 (in a direction parallel to the gate lines 1).
  • the source 115 and the drain 116 are connected to the active layer 111 through via holes penetrating the interlayer insulating layer 114 and the gate insulating layer 112, respectively.
  • the data line 2 is also disposed in the same layer as the source 115 and the drain 116, and the source 115 is connected to the corresponding data line 2, wherein the data line 2 and the gate line 1 cross each other perpendicularly, thereby dividing the pixel area.
  • a first dielectric layer 14 may be disposed between the pixel electrode 13 and the touch electrode 15 to insulate between the pixel electrode 13 and the touch electrode 15 .
  • an inorganic material such as silicon oxide (SiOx), silicon oxide (SiNx) or silicon oxynitride (SiNO) may be selected.
  • SiOx silicon oxide
  • SiNx silicon oxide
  • SiNO silicon oxynitride
  • a second dielectric layer 16 may be disposed between the touch electrode 15 and the common electrode 17 so that the touch electrode 15 is The common electrode 17 is kept insulated between the electrodes.
  • the second dielectric layer 16 may be made of an organic material or an inorganic material.
  • the orthographic projection of the second dielectric layer 16 on the substrate 10 and the pixel electrode 13 on the substrate 10 are in addition to the portion corresponding to the touch electrode 15 .
  • the orthographic projections on the top do not overlap.
  • only the first dielectric layer 14 is present between the common electrode 17 and the pixel electrode 13, so that the distance between the common electrode 17 and the pixel electrode 13 can be reduced, and the pixel electrode during display of the touch display panel can be increased.
  • the storage retention capacitance between the 13 and the common electrode 17 ultimately improves the display effect of the touch display panel.
  • An embodiment of the present disclosure further provides a touch display panel comprising the array substrate described in any of the above embodiments.
  • the touch display panel has the same or similar advantages as the above array substrate, and details are not described herein again.
  • An embodiment of the present disclosure further provides a touch display device including the touch display panel described in any of the above embodiments.
  • FIG. 4 a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure is schematically illustrated. Such a fabrication method can be used to fabricate an array substrate as described in any of the above embodiments. Specifically, the method of manufacturing the array substrate includes the following steps.
  • Step S1 provides a substrate.
  • Step S2 forming a plurality of thin film transistors arranged in an array on the base substrate.
  • Step S3 forming an insulating planarization layer on a side of the plurality of thin film transistors away from the base substrate and forming a plurality of via holes respectively exposing drains of each of the thin film transistors in the insulating planarization layer.
  • Step S4 forming a plurality of pixel electrodes arranged in an array on a side of the insulating planarization layer away from the plurality of thin film transistors, each pixel electrode passing through a via hole in the insulating planarization layer and a corresponding thin film transistor Drain connection.
  • Step S5 forming a plurality of touch electrodes arranged in an array on a side of the plurality of pixel electrodes away from the insulating planarization layer.
  • step S6 a plurality of common electrodes arranged in an array are formed on a side of the plurality of touch electrodes away from the plurality of pixel electrodes, and each of the common electrodes is connected to a corresponding touch electrode.
  • the manufacturing method of the array substrate has the same or similar advantages as the above array substrate, and will not be described herein.
  • step S2 the step of forming a plurality of thin film transistors arranged in an array on the base substrate may include the following sub-steps.
  • Step S21 forming an active layer on the base substrate.
  • Step S22 forming a gate insulating layer, the gate insulating layer covering the active layer and the substrate.
  • Step S23 forming a gate on the gate insulating layer, wherein the gate corresponds vertically to the active layer.
  • a gate line on the gate insulating layer wherein the gate is connected to the corresponding gate line.
  • Step S24 forming an interlayer insulating layer covering the gate electrode, the gate line, and the gate insulating layer.
  • Step S25 forming via holes penetrating the interlayer insulating layer and the gate insulating layer on both sides of the gate electrode in a direction parallel to the gate line.
  • Step S26 forming a source and a drain, wherein the source and the drain are respectively connected to the active layer through the corresponding via holes penetrating the interlayer insulating layer and the gate insulating layer.
  • formed simultaneously with the source and the drain are data lines on the interlayer insulating layer, wherein the source is connected to the corresponding data line.
  • the step S3 of forming the insulating planarization layer and the plurality of via holes in the insulating planarization layer may include the following sub-steps.
  • Step S31 depositing an insulating planarization material on a side of the plurality of thin film transistors away from the substrate.
  • Step S32 forming a plurality of via holes respectively exposing the drains of the corresponding thin film transistors in the insulating planarization material.
  • Step S33 repeating step S31 and step S32 a plurality of times, so that a plurality of via holes in each of the insulating planarization materials formed later are respectively in communication with corresponding via holes in each of the previously formed insulating planarization materials.
  • the method of fabricating an array substrate may further include: step S4' after step S4 and before step S5, that is, planarizing the plurality of pixel electrodes away from the insulation A first dielectric layer is formed on one side of the layer.
  • the manufacturing method of the array substrate may further include: after step S5 and before step S5, step S5', that is, the plurality of touch electrodes are away from the plurality of A second dielectric layer is formed on one side of the pixel electrode, and a plurality of via holes are formed in the second dielectric layer such that each touch electrode is connected to the corresponding common electrode through a via.

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Abstract

一种阵列基板及其制造方法、触控显示面板、触控显示装置。阵列基板包括：衬底基板（10），以及依次形成在衬底基板上（10）上的薄膜晶体管（11）、绝缘平坦化层（12）、多个像素电极（13）、多个触控电极（15）和多个公共电极（17），其中，绝缘平坦化层（12）具有分别暴露出每一个薄膜晶体管（11）的漏极（116）的多个过孔；每一个像素电极（13）通过绝缘平坦化层（12）中的一个过孔与对应薄膜晶体管（11）的漏极（116）连接；每一个公共电极（17）与对应的触控电极（15）连接。

Description

阵列基板及其制造方法、触控显示面板以及触控显示装置
对相关申请的交叉引用
本申请要求2018年1月11日提交的中国专利申请号201810026777.3的优先权，该中国专利申请以其整体通过引用并入本文。
技术领域
本公开涉及触控显示技术领域，并且公开了阵列基板及其制造方法、触控显示面板以及触控显示装置。
背景技术
触控显示装置是一种即可以实现显示又可以实现触控的装置。目前，触控显示装置通常包括触控显示面板，其中，触控显示面板通常包括显示面板和触控面板。根据触控面板与显示面板的相对位置关系，可以将触控显示面板划分为内置式触控显示面板和外挂式(Out-cell)触控显示面板。具体地，内置式触控显示面板又可以分为内置面内式(In-cell)触控显示面板(也称为内嵌式触控显示面板)和内置面上式(On-cell)触控显示面板。内置面内式(In-cell)触控显示面板由于方便制造轻薄化的产品而得到广泛的研究和应用。
现有的一种内置面内式(In-cell)触控显示面板通常包括阵列基板，其中，该阵列基板通常包括：衬底基板，以及依次形成在衬底基板上的薄膜晶体管、触控电极、公共电极和像素电极。附加地，触控电极与对应的公共电极连接，并且像素电极与对应的薄膜晶体管的漏极连接。此外，在薄膜晶体管与触控电极之间还形成有一层绝缘平坦化层。在提供有上述阵列基板的触控显示面板的工作期间，例如，在显示阶段期间，薄膜晶体管导通，并且为像素电极提供像素电压信号；同时，触控电极为公共电极提供公共电压信号，由此在像素电极与公共电极之间产生电压差，以便实现触控显示面板的显示功能。与此相对，在触控阶段期间，触控电极为公共电极提供触控电压信号，使得公共电极在感受到触控之后发生电压变化，从而实现触控显示面板的触控功能。
在上述阵列基板中，像素电极位于公共电极背向薄膜晶体管的一侧处。因此，在提供有上述阵列基板的触控显示面板的工作期间，特别地，在显示阶段期间，在公共电极与薄膜晶体管中的电极(比如，源极)之间将容易形成较大的电容。因此，为了实现触控显示面板的良好显示效果，通常需要增加提供给公共电极的公共电压信号的大小，这将造成触控显示面板工作时的功耗增加。同时，在上述阵列基板中，触控电极形成在绝缘平坦化层上。目前，触控电极一般由金属材料制成，并且通常采用溅射工艺形成触控电极。此外，绝缘平坦化层一般又由有机材料制成。在这样的情况下，当采用溅射工艺形成金属触控电极时，绝缘平坦化层将容易在温度较高的溅射腔室内发生分解，从而造成溅射腔室的污染。
发明内容
根据本公开的一方面，提供了一种阵列基板。所述阵列基板包括：衬底基板；在所述衬底基板上阵列排布的多个薄膜晶体管；绝缘平坦化层，所述绝缘平坦化层位于所述多个薄膜晶体管远离所述衬底基板的一侧上并且具有分别暴露出每一个薄膜晶体管的漏极的多个过孔；在所述绝缘平坦化层远离所述多个薄膜晶体管的一侧上阵列排布的多个像素电极，每一个像素电极通过所述绝缘平坦化层中的一个过孔与对应薄膜晶体管的漏极连接；在所述多个像素电极远离所述绝缘平坦化层的一侧上阵列排布的多个触控电极；以及在所述多个触控电极远离所述多个像素电极的一侧上阵列排布的多个公共电极，每一个公共电极与对应触控电极连接。
根据具体实现方案，在本公开的实施例提供的阵列基板中，所述绝缘平坦化层包括厚度大于或等于6μm的单层。
根据具体实现方案，在本公开的实施例提供的阵列基板中，所述绝缘平坦化层包括多个子层，所述多个子层的总厚度大于或等于6μm。
根据具体实现方案，在本公开的实施例提供的阵列基板中，所述绝缘平坦化层包括靠近所述多个薄膜晶体管的第一子层和远离所述多个薄膜晶体管的第二子层，所述第一子层的厚度大于或等于4μm，并且所述第二子层的厚度为2μm-4μm。
根据具体实现方案，在本公开的实施例提供的阵列基板中，所述 绝缘平坦化层由亚克力材料制成。
根据具体实现方案，由本公开的实施例提供的阵列基板还包括：位于所述衬底基板上的多个数据线，其中，每一个薄膜晶体管的源极与对应数据线连接；并且每一个触控电极在所述衬底基板上的正投影与对应数据线在所述衬底基板上的正投影至少部分地重叠。
根据具体实现方案，在本公开的实施例提供的阵列基板中，每一个公共电极包括第一部分和第二部分，所述第一部分在所述衬底基板上的正投影与对应触控电极在所述衬底基板上的正投影至少部分地重叠，所述第二部分在所述衬底基板上的正投影与对应触控电极在所述衬底基板上的正投影上不重叠，并且所述公共电极通过所述第一部分与对应触控电极连接。
根据具体实现方案，由本公开的实施例提供的阵列基板还包括：位于所述多个像素电极与所述多个触控电极之间的第一介电层，以及位于所述多个触控电极与所述多个公共电极之间的第二介电层，其中，所述第二介电层在所述衬底基板上的正投影与所述多个像素电极在所述衬底基板上的正投影不重叠。
根据具体实现方案，在本公开的实施例提供的阵列基板中，所述第一介电层由无机材料制成，并且所述第二介电层由有机材料或无机材料制成。
根据具体实现方案，在本公开的实施例提供的阵列基板中，每一个薄膜晶体管包括低温多晶硅薄膜晶体管。
根据本公开的另一方面，还提供了一种触控显示面板。所述触控显示面板包括在前面任一个实施例中描述的阵列基板。
根据本公开的又一方面，还提供了一种触控显示装置。所述触控显示装置包括在前面任一个实施例中描述的触控显示面板。
根据本公开的再一方面，还提供了一种用于阵列基板的制造方法。所述制造方法包括以下步骤：提供衬底基板(S1)；在所述衬底基板上形成阵列排布的多个薄膜晶体管(S2)；在所述多个薄膜晶体管远离所述衬底基板的一侧上形成绝缘平坦化层并且在所述绝缘平坦化层中形成分别暴露出每一个薄膜晶体管的漏极的多个过孔(S3)；在所述绝缘平坦化层远离所述多个薄膜晶体管的一侧上形成阵列排布的多个像素电极(S4)，每一个像素电极通过所述绝缘平坦化层中的一个 过孔与对应薄膜晶体管的漏极连接；在所述多个像素电极远离所述绝缘平坦化层的一侧上形成阵列排布的多个触控电极(S5)；以及在所述多个触控电极远离所述多个像素电极的一侧上形成阵列排布的公共电极(S6)，每一个公共电极与对应触控电极连接。
根据具体实现方案，在本公开的实施例提供的用于阵列基板的制造方法中，在所述多个薄膜晶体管远离所述衬底基板的一侧上形成绝缘平坦化层并且在所述绝缘平坦化层中形成多个过孔的步骤包括以下子步骤：在所述多个薄膜晶体管远离所述衬底基板的一侧上沉积一层绝缘平坦化材料(S31)；在这一层绝缘平坦化材料中形成所述多个过孔(S32)；以及重复以上两个子步骤多次，使得之后形成的每一层绝缘平坦化材料中的所述多个过孔分别与之前形成的每一层绝缘平坦化材料中的对应过孔相互连通(S33)。
根据具体实现方案，由本公开的实施例提供的用于阵列基板的制造方法还包括以下步骤：在形成所述多个像素电极之后并且在形成所述多个触控电极之前，在所述多个像素电极远离所述绝缘平坦化层的一侧上形成第一介电层；以及在形成所述多个触控电极之后并且在形成所述多个公共电极之前，在所述多个触控电极远离所述多个像素电极的一侧上形成第二介电层，并且在所述第二介电层中形成多个过孔，使得每一个过孔对应于一个触控电极。
附图说明
此处所说明的附图仅仅用来提供对本公开的进一步理解，并且构成本公开的一部分。本公开的示意性实施例及其说明用于解释本公开，但是并不构成对本公开的不当限定。在附图中：
图1示意性示出了根据本公开的实施例的阵列基板的俯视图；
图2示意性示出了沿图1中的线A-A的侧视图；
图3示意性示出了沿图1中的线B-B的侧视图；
图4示意性示出了根据本公开的实施例的用于阵列基板的制造方法的流程图；
图5示意性示出了图4中的步骤S2的流程图；以及
图6示意性示出了图4中的步骤S3的流程图。
具体实施方式
为了进一步说明在本公开的实施例中提供的阵列基板及其制造方法、触控显示面板以及触控显示装置，下面将结合说明书附图进行详细的描述。
在接下来的描述中，使用以下附图标记来指代在本公开的实施例中提供的阵列基板中的各个组件：
Figure PCTCN2018111586-appb-000001
参照图1和图2，示意性示出了根据本公开的实施例的阵列基板的俯视图和侧视图。具体地，阵列基板包括：衬底基板；在衬底基板10上阵列排布的多个薄膜晶体管11；绝缘平坦化层12，绝缘平坦化层12位于所述多个薄膜晶体管11远离所述衬底基板的一侧上，并且绝缘平坦化层12中具有分别暴露出每一个薄膜晶体管11的漏极116的多个过孔；多个像素电极13，所述多个像素电极13在绝缘平坦化层12远离所述多个薄膜晶体管11的一侧上阵列排布，并且每一个像素电极13通过绝缘平坦化层12中的一个过孔与对应薄膜晶体管11的漏极116连接；多个触控电极15，所述多个触控电极15在所述多个像素电极13远离绝缘平坦化层12的一侧上阵列排布；多个公共电极17，所述多个公共电极17在所述多个触控电极15远离所述像素电极13的一侧上阵列排布，并且每一个公共电极17与对应的触控电极15连接。
作为示例，继续参照图1和图2，本公开的实施例提供了一种阵列基板。该阵列基板可以应用于触控显示面板，以实现触控显示面板的显示功能和触控功能。该阵列基板包括衬底基板10以及依次形成在衬底基板10上的薄膜晶体管11、绝缘平坦化层12、像素电极13、触控电极15和公共电极17。薄膜晶体管11的数量为多个，并且多个薄膜晶体管11在衬底基板10上呈阵列排布。绝缘平坦化层12位于薄膜晶 体管11上，并且覆盖薄膜晶体管11。像素电极13形成在绝缘平坦化层12上。具体地，像素电极13位于绝缘平坦化层12远离薄膜晶体管11的一侧上。像素电极13的数量也为多个，并且多个像素电极13呈阵列排布。每个像素电极13通过绝缘平坦化层12中对应的过孔与对应的薄膜晶体管11的漏极116连接。关于像素电极13的材料，可以选用铟锡氧化物(Indium Tin Oxide，ITO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)等透明导电材料。触控电极15位于像素电极13远离绝缘平坦化层12的一侧上，即，触控电极15位于像素电极13的上方。公共电极17位于触控电极15远离像素电极13的一侧上，即，公共电极17位于触控电极15的上方。此外，公共电极17与对应的触控电极15连接。关于公共电极17的材料，可以选用铟锡氧化物(Indium Tin Oxide，ITO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)等透明导电材料。
当将本公开的实施例提供的阵列基板应用于触控显示面板中，在触控显示面板的工作期间，例如，在显示阶段期间，薄膜晶体管11导通，并且薄膜晶体管11为像素电极13提供像素电压信号。与此同时，通过触控电极15为对应的公共电极17提供公共电压信号。此时，在像素电极13与公共电极17之间将产生电压差，从而实现触控显示面板的显示功能。对应地，在在触控阶段期间，通过触控电极15为对应的公共电极17提供触控电压信号。例如，当触控发生时，公共电极17上的电压信号将发生变化，从而实现触控显示面板的触控功能。
由上文可知，在本公开的实施例提供的阵列基板中，薄膜晶体管11与像素电极13之间设置有绝缘平坦化层12，公共电极17设置在触控电极15远离像素电极13的一侧，而触控电极15位于像素电极13远离绝缘平坦化层12的一侧。也就是说，公共电极17设置在像素电极13远离绝缘平坦化层12的一侧，并且在公共电极17与薄膜晶体管11之间间隔有触控电极15、像素电极13和绝缘平坦化层12。以这样的方式，使得公共电极17与薄膜晶体管11之间的距离较大，比如，公共电极17与薄膜晶体管11的源极115之间的距离较大。此外，在本公开的实施例提供的阵列基板中，像素电极13位于薄膜晶体管11与公共电极17之间。在这样的情况下，当将本公开的实施例提供的阵列基板应用于触控显示面板中，在触控显示面板的工作期间，像素电 极13可以隔断在公共电极17与薄膜晶体管11中的各个电极之间产生的电力线。因此，当将本公开的实施例提供的阵列基板应用于触控显示面板中，在触控显示面板的工作期间，例如，在触控显示面板的显示阶段期间，可以减小公共电极17与薄膜晶体管11中的电极(比如，源极115)之间的电容。以这样的方式，可以降低触控显示面板在显示时需要给公共电极17提供的电压大小，并且进而降低触控显示面板工作时的功耗。同时，在本公开的实施例提供的阵列基板中，将像素电极13形成在绝缘平坦化层12上，并且避免将触控电极15形成在绝缘平坦化层12上。因此，当采用溅射工艺形成触控电极15时，不会因为温度较高而造成绝缘平坦化层12的分解。由此，可以避免在采用溅射工艺形成触控电极15时对溅射腔室所引起的污染。
另外，在常规方案中，薄膜晶体管11上的绝缘平坦化层12一般由有机材料制成。在这样的情况下，为了防止采用溅射工艺在绝缘平坦化层12上形成触控电极15时所引起的有机材料的分解，通常，在形成该绝缘平坦化层12以及该绝缘平坦化层12中与漏极116对应的过孔之后，要形成一层无机材料保护层。具体地，在该无机材料保护层中同样形成与漏极116对应的过孔，并且有利地，无机材料保护层中的过孔的直径小于绝缘平坦化层12中的过孔的直径。鉴于此，往往需要专门配备一个掩膜版，以形成无机材料保护层中的过孔。这造成制造阵列基板的工艺繁琐，并且成本较高。与此相对，在本公开的实施例中，避免了在有机材料的绝缘平坦化层12上形成触控电极15。因而，无需设置多个掩膜版，从而简化了制造阵列基板的工艺步骤，并且降低了制造阵列基板的成本。
再者，在本公开的实施例中，公共电极17设置在最上层。关于公共电极17的材料，可以选用铟锡氧化物(Indium Tin Oxide，ITO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)等透明导电材料。因此，无需担心公共电极17的氧化问题，也就不用在公共电极17上形成保护层。这样，可以减小阵列基板的总厚度，进而减小触控显示面板的总厚度，并且有利于触控显示面板的轻薄化设计。
当将上述实施例提供的阵列基板应用于触控显示面板中时，在触控显示面板的工作期间，例如，在显示阶段期间，薄膜晶体管11导通，并且薄膜晶体管11为像素电极13提供像素电压信号。与此同时，通 过触控电极15为对应的公共电极17提供公共电压信号。此时，像素电极13与公共电极17之间将产生电压差，从而实现触控显示面板的显示功能。类似地，在触控阶段期间，通过触控电极15为公共电极17提供触控电压信号，从而实现触控显示面板的触控功能。因此，在显示阶段期间，公共电极17与像素电极13共同实现触控显示面板的显示功能；而在触控阶段期间，公共电极17作为触控感应元件的一部分，从而帮助实现触控显示面板的触控功能。因此，在本公开的实施例中，公共电极17的数量同样为多个，并且每一个公共电极17的覆盖面积可以根据实际需要进行设定。例如，它可以根据所需要的触控分辨率以及触控驱动芯片所能支持的触控电极15的数量来确定。
在上述实施例中，绝缘平坦化层12的子层数以及总厚度可以根据实际需要进行设定。例如，绝缘平坦化层12可以为单层结构。此时，绝缘平坦化层12的厚度可以设定为大于或等于6μm。以这样的方式，可以使公共电极17与薄膜晶体管11之间的距离更大，进而减小触控显示面板工作时(具体地，在显示阶段期间)公共电极17与薄膜晶体管11中的电极(诸如，源极115)之间的电容。由此，可以降低触控显示面板在显示时需要向公共电极17提供的电压大小，进而有利于降低触控显示面板工作时的功耗。
可替换地，绝缘平坦化层12也可以包括多层结构。例如，绝缘平坦化层12可以包括多个子层，例如，两个、三个或者三个以上的子层。在这样的多层结构中，绝缘平坦化层12的各个子层层叠设置，并且覆盖薄膜晶体管11。在这样的情况下，绝缘平坦化层12的多个子层的总厚度可以设定为大于或等于6μm。与绝缘平坦化层12为单层结构的情况相比，当总厚度确定时，具有多层结构的绝缘平坦化层12中的每个子层的厚度相对较小。以这样的方式，可以减少用于形成绝缘平坦化层12的工艺难度，并且同时也方便在绝缘平坦化层12中形成过孔。需要说明的是，当绝缘平坦化层12包括多个子层时，在每一个子层与薄膜晶体管11的漏极116对应的地方，都设置有贯穿该子层的过孔，该过孔暴露出薄膜晶体管11的漏极116，并且绝缘平坦化层12的各个子层中的对应过孔相互连通。
在本公开的实施例提供的阵列基板中，在薄膜晶体管11与像素电极13之间还设置有绝缘平坦化层12，并且该绝缘平坦化层12的总厚 度大于或等于6μm。与常规方案中通过一层无机材料的绝缘平坦化层12来实现薄膜晶体管11与像素电极13之间的绝缘相比，依照本公开的实施例，可以增加薄膜晶体管11与像素电极13之间的绝缘可靠性，而同时还增加了公共电极17与薄膜晶体管11之间的距离。
在上述实施例中，绝缘平坦化层12可以包括至少一个子层。在实际应用中，绝缘平坦化层12的子层数可以根据产品实际需要、制造工艺能力等来确定。例如，可以根据产品实际需要来计算阵列基板中的像素电极13与薄膜晶体管11之间的距离，并且该距离也可以理解为绝缘平坦化层12的总厚度。通常，该总厚度需要大于或等于6μm。在此之后，根据计算得到的总厚度、绝缘平坦化层12的制造工艺、以及制造绝缘平坦化层12时所采用的制造工艺的工艺能力(比如，制造工艺所能达到的膜层的最大厚度)等，计算绝缘平坦化层12的子层数。
继续参照图2，在本公开的实施例中，绝缘平坦化层12的子层数可以选用为两个。此时，与具有单层结构的绝缘平坦化层12相比，还可以在一定程度上增加绝缘平坦化层12的总厚度，以便增加薄膜晶体管11与像素电极13之间的距离，增加薄膜晶体管11与公共电极17之间的距离，减小当触控显示面板工作时公共电极17与薄膜晶体管11中的电极(诸如源极115)之间的电容，并且最终降低触控显示面板工作时的功耗。与此同时，与绝缘平坦化层12包括三个或者三个以上的子层相比，在满足绝缘平坦化层12的总厚度的要求下，还可以减少用于制造阵列基板的工艺步骤。
当绝缘平坦化层12的子层数选择为两个时，在本公开的实施例中，靠近薄膜晶体管11的第一子层的厚度大于或等于4μm。这意味着，在完成薄膜晶体管11的制作之后，首先形成的绝缘平坦化层12的第一子层的厚度大于或等于4μm。以这样的方式，可以加强绝缘平坦化层12的第一子层对衬底基板10上已形成的其它结构的平坦化效果，从而便于绝缘平坦化层12的后续子层的形成。同时，由于绝缘平坦化层12的第一子层(即，靠近薄膜晶体管11的子层)所起到的作用主要是平坦化，而薄膜晶体管11的漏极116在衬底基板10上通常为凸起状态，因此绝缘平坦化层12的第一子层与薄膜晶体管11的漏极116对应的部分通常会具有较小的厚度(一般小于绝缘平坦化层12的第一子层的实际设定厚度)，并且不会造成在第一子层中形成过孔的难度的增加。
当绝缘平坦化层12的子层数选择为两个时，在本公开的实施例中，远离薄膜晶体管11的绝缘平坦化层12的第二子层的厚度为2μm-4μm。这意味着，在完成薄膜晶体管11以及绝缘平坦化层12的第一子层的形成之后，后形成的绝缘平坦化层12的第二子层的厚度可以为2μm-4μm。在形成绝缘平坦化层12的第一子层之后，绝缘层平坦化层的第一子层远离衬底基板10的表面基本上为平整的。即，如图2所示，绝缘层平坦化层的第一子层的上表面基本上平整。鉴于此，后续形成的绝缘平坦化层12的各个子层的厚度将在各个区域中基本上相同。作为示例，将后续形成的绝缘平坦化层12的第二子层的厚度选择为2μm-4μm。以这样的方式，在保证具有多个子层的绝缘平坦化层12的总厚度达到要求的前提下，还可以防止由于绝缘平坦化层12的各个子层的厚度太大而造成在该子层中形成过孔的难度的增加。
值得一提的是，当绝缘平坦化层12包括多个子层时，为了形成绝缘平坦化层12的多个子层以及贯穿各个子层的过孔，可以采用以下几种方式。作为第一种实现方式，首先可以依次层叠形成绝缘平坦化层12的多个子层结构，并且然后再采用构图工艺一次性形成贯穿各个子层的多个贯穿孔，其中，每一个贯穿孔暴露出对应薄膜晶体管11的漏极116。可替换地，作为第二种实现方式，在形成绝缘平坦化层12的每一个子层之后，都采用构图工艺在绝缘平坦化层12的这一子层中形成贯穿该子层的多个过孔，其中，每一个过孔与相应薄膜晶体管11的漏极116位置对应，并且与前一子层中的相应过孔相互连通。举例来说，假设绝缘平坦化层12的子层数为两个。在这样的情况下，当采用第二种实现方式时，首先可以形成绝缘平坦化层12的第一子层，该第一子层覆盖薄膜晶体管11和衬底基板10；然后，在绝缘平坦化层12的第一子层中形成分别与每一个薄膜晶体管11的漏极116对应的多个过孔，其中，每一个过孔暴露出相应薄膜晶体管11的漏极116；再然后，形成绝缘平坦化层12的第二子层，该第二子层位于绝缘平坦化层12的第一子层上并且覆盖第一子层；并且最后，在绝缘平坦化层12的第二子层中形成分别与每一个薄膜晶体管11的漏极116对应的多个过孔，绝缘平坦化层12的第二子层中的过孔与绝缘平坦化层12的第一子层中的过孔一一对应并且相互连通，从而暴露出各个薄膜晶体管11的漏极116。
在上述实施例中，用于形成绝缘平坦化层12的材料可以根据实际需要进行选择。例如，绝缘层平坦化层可以由有机材料制成，例如，亚克力材料。与无机材料制成的绝缘平坦化层12相比，通过将绝缘平坦化层12的材料选择为有机材料，可以增加绝缘平坦化层12的厚度。与此同时，在形成过孔的过程中，只需要曝光、显影即可，无需进行刻蚀、去胶。因而，可以减少用于制造阵列基板的工艺步骤。
继续参照图1、图2和图3，本公开的实施例提供的阵列基板还包括位于衬底基板10上的多个数据线2，其中，每一个薄膜晶体管11的源极115与对应的数据线2连接。此外，每一个触控电极15在衬底基板10上的正投影与对应数据线2在衬底基板10上的正投影至少部分地重叠。这意味着，每一个触控电极15在衬底基板10上的正投影可以与对应数据线2在衬底基板10上的正投影完全重合。可替换地，每一个触控电极15在衬底基板10上的正投影也可以落入在对应数据线2在衬底基板10上的正投影内。进一步可替换地，每一个触控电极15在衬底基板10上的正投影还可以覆盖对应数据线2在衬底基板10上的正投影，并且有利地，在垂直于数据线2的方向上，每一个触控电极15在衬底基板10上的正投影可以略微大于对应数据线2在衬底基板10上的正投影。由此可见，在本公开的实施例中，每一个触控电极15将形成在数据线2的正上方，因而触控电极15将不会覆盖像素显示区并且不会对触控显示面板的开口率造成不良影响。
继续参照图1和图3，在本公开的实施例中，每一个公共电极17包括第一部分(例如，图中触控电极15正上方的部分)和第二部分(例如，图中除第一部分以外的其它部分)，其中，该公共电极17通过第一部分与对应触控电极15连接。进一步地，在本公开的实施例提供的阵列基板中，对于每一个公共电极17而言，第一部分在衬底基板10上的正投影与对应触控电极15在衬底基板10上的正投影至少部分地重叠，并且第二部分在衬底基板10上的正投影与对应触控电极15在衬底基板10上的正投影上不重叠。也就是说，除公共电极17与对应触控电极15连接的部位以外，公共电极17的其它部分在衬底基板10上的正投影与触控电极15在衬底基板10上的正投影不重叠。这意味着，在公共电极17中，除与对应触控电极15连接的部位以外，其它部分均不会与对应触控电极15发生衬底基板上的交叠。因而，可以减 少公共电极17与数据线2的彼此对应面积，从而可以减小在触控显示面板的显示期间公共电极17与数据线2之间的电容，并且进而降低触控显示面板工作时的功耗。
在上述实施例中，薄膜晶体管11的类型可以根据实际需要进行设定。例如，薄膜晶体管11的类型可以根据有源层111的材料来选择。比如，薄膜晶体管11可以为非晶硅薄膜晶体管、单晶硅薄膜晶体管、多晶硅薄膜晶体管、金属氧化物薄膜晶体管等。进一步地或者可替换地，薄膜晶体管11可以根据结构来选择。例如，薄膜晶体管11可以为顶栅型薄膜晶体管或底栅型薄膜晶体管。在本公开的实施例中，当薄膜晶体管11中的有源层111的材料选择为低温多晶硅时，结构可以选择为顶栅型，即，本公开的实施例中的薄膜晶体管11为顶栅型低温多晶硅薄膜晶体管。具体地，参照图2，在本公开的实施例中，薄膜晶体管11包括有源层111、栅极绝缘层112、栅极113、层间绝缘层114、源极115和漏极116。具体地，有源层111形成在衬底基板10上，并且有源层111的材料为低温多晶硅。此外，栅极绝缘层112覆盖有源层111和衬底基板10，并且栅极113形成在栅极绝缘层112上与有源层111对应的位置处。与栅极113同层还设置有栅线1，并且栅极113与对应的栅线1连接。进一步地，层间绝缘层114覆盖栅极113、栅线1和栅极绝缘层112，并且源极115和漏极116形成在层间绝缘层114上，其中，源极115在衬底基板10上的正投影和漏极116在衬底基板10上的正投影分别位于栅极113在衬底基板10上的正投影的两侧(沿平行于栅线1的方向)。源极115和漏极116分别通过贯穿层间绝缘层114和栅极绝缘层112的过孔与有源层111连接。与源极115和漏极116同层还设置有数据线2，并且源极115与对应的数据线2连接，其中，数据线2与栅线1相互垂直交叉，从而划分出像素区。
继续参照图2和图3，在本公开的实施例中，在像素电极13与触控电极15之间还可以设置第一介电层14，以使像素电极13与触控电极15之间绝缘。对于第一介电层14的材料，可以选择为无机材料，比如，氧化硅(SiOx)、氧化硅(SiNx)或氮氧化硅(SiNO)。在这样的情况下，可以防止在后续采用溅射工艺形成金属触控电极15时引起的第一介电层14的分解，从而防止在采用溅射工艺形成金属触控电极15时对溅射腔室引起的污染。
继续参照图2和图3，在本公开的实施例中，在触控电极15与公共电极17之间还可以设置第二介电层16，以使得除连接处之外，触控电极15与公共电极17之间均保持绝缘。作为示例，第二介电层16可以由有机材料或无机材料制成。
值得一提的是，在本公开的实施例中，除与触控电极15对应的部分之外，第二介电层16在衬底基板10上的正投影与像素电极13在衬底基板10上的正投影不重叠。以这样的方式，使得公共电极17与像素电极13之间只存在第一介电层14，从而可以减小公共电极17与像素电极13之间的距离，增大触控显示面板显示期间像素电极13与公共电极17之间的存储保持电容，并且最终改善触控显示面板的显示效果。
本公开的实施例还提供了一种触控显示面板，所述触控显示面板包括在以上任一个实施例中描述的阵列基板。
所述触控显示面板与上述阵列基板具有相同或相似的优势，并且在此不再赘述。
本公开的实施例还提供了一种触控显示装置，所述触控显示装置包括在以上任一个实施例中描述的触控显示面板。
参照图4，示意性示出了根据本公开的实施例的用于阵列基板的制造方法的流程图。这样的制作方法可以用于制造如上述任一个实施例所述的阵列基板。具体地，所述阵列基板的制造方法包括以下步骤。
步骤S1、提供衬底基板。
步骤S2、在衬底基板上形成阵列排布的多个薄膜晶体管。
步骤S3、在所述多个薄膜晶体管远离所述衬底基板的一侧上形成绝缘平坦化层并且在绝缘平坦化层中形成分别暴露出每一个薄膜晶体管的漏极的多个过孔。
步骤S4、在所述绝缘平坦化层远离所述多个薄膜晶体管的一侧上形成阵列排布的多个像素电极，每一个像素电极通过绝缘平坦化层中的一个过孔与对应薄膜晶体管的漏极连接。
步骤S5、在所述多个像素电极远离所述绝缘平坦化层的一侧上形成阵列排布的多个触控电极。
步骤S6、在所述多个触控电极远离所述多个像素电极的一侧上形成阵列排布的多个公共电极，每一个公共电极与对应的触控电极连接。
所述阵列基板的制造方法与上述阵列基板具有相同或者相似的优势，并且在此不再赘述。
进一步地，参照图5，在步骤S2中，在衬底基板上形成阵列排布的多个薄膜晶体管的步骤可以包括以下子步骤。
步骤S21、在衬底基板上形成有源层。
步骤S22、形成栅极绝缘层，栅极绝缘层覆盖有源层和衬底基板。
步骤S23、在栅极绝缘层上形成栅极，其中，栅极与有源层竖直对应。此外，与栅极同时形成的还有位于栅极绝缘层上的栅线，其中，栅极与对应的栅线连接。
步骤S24、形成层间绝缘层，层间绝缘层覆盖栅极、栅线和栅极绝缘层。
步骤S25、沿平行于栅线的方向在栅极的两侧分别形成贯穿层间绝缘层和栅极绝缘层的过孔。
步骤S26、形成源极和漏极，其中，源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的对应过孔与有源层连接。此外，与源极、漏极同时形成的还有位于层间绝缘层上的数据线，其中，源极与对应的数据线连接。
参照图6，在上述实施例的具体示例中，当绝缘平坦化层包括多个子层时，形成绝缘平坦化层以及绝缘平坦化层中的多个过孔的步骤S3可以包括以下子步骤。
步骤S31、在所述多个薄膜晶体管远离所述衬底基板的一侧上沉积一层绝缘平坦化材料。
步骤S32、在这一层绝缘平坦化材料中形成分别暴露出对应薄膜晶体管的漏极的多个过孔。
步骤S33、重复步骤S31和步骤S32多次，使得之后形成的每一层绝缘平坦化材料中的多个过孔分别与之前形成的每一层绝缘平坦化材料中的对应过孔相互连通。
继续参照图4，由本公开的实施例提供的阵列基板的制造方法还可以包括：在步骤S4之后并且在步骤S5之前的步骤S4’，即，在所述多个像素电极远离所述绝缘平坦化层的一侧上形成第一介电层。可替换地，在其它实施例中，所述阵列基板的制造方法还可以包括：在步骤S5之后并且在步骤S6之前的步骤S5’，即，在所述多个触控电极远离 所述多个像素电极的一侧上形成第二介电层，并且在第二介电层中形成多个过孔，使得每一个触控电极通过一个过孔与对应公共电极连接。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以任何合适的方式结合。
以上所述，仅为本公开的具体实施方式，但是本公开的保护范围并不局限于此。熟悉本技术领域的技术人员在本公开揭露的技术范围内可容易设想到的任何变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括：
    衬底基板；
    在所述衬底基板上阵列排布的多个薄膜晶体管；
    绝缘平坦化层，所述绝缘平坦化层位于所述多个薄膜晶体管远离所述衬底基板的一侧上并且具有分别暴露出每一个薄膜晶体管的漏极的多个过孔；
    在所述绝缘平坦化层远离所述多个薄膜晶体管的一侧上阵列排布的多个像素电极，每一个像素电极通过所述绝缘平坦化层中的一个过孔与对应薄膜晶体管的漏极连接；
    在所述多个像素电极远离所述绝缘平坦化层的一侧上阵列排布的多个触控电极；以及
    在所述多个触控电极远离所述多个像素电极的一侧上阵列排布的多个公共电极，每一个公共电极与对应触控电极连接。
  2. 根据权利要求1所述的阵列基板，其中，
    所述绝缘平坦化层包括厚度大于或等于6μm的单层。
  3. 根据权利要求1所述的阵列基板，其中，
    所述绝缘平坦化层包括多个子层，所述多个子层的总厚度大于或等于6μm。
  4. 根据权利要求3所述的阵列基板，其中，
    所述绝缘平坦化层包括靠近所述多个薄膜晶体管的第一子层和远离所述多个薄膜晶体管的第二子层，所述第一子层的厚度大于或等于4μm，并且所述第二子层的厚度为2μm-4μm。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述绝缘平坦化层由亚克力材料制成。
  6. 根据权利要求1-4中任一项所述的阵列基板，还包括：位于所述衬底基板上的多个数据线，其中，
    每一个薄膜晶体管的源极与对应数据线连接；并且
    每一个触控电极在所述衬底基板上的正投影与对应数据线在所述衬底基板上的正投影至少部分地重叠。
  7. 根据权利要求1-4中任一项所述的阵列基板，其中，
    每一个公共电极包括第一部分和第二部分，所述第一部分在所述衬底基板上的正投影与对应触控电极在所述衬底基板上的正投影至少部分地重叠，所述第二部分在所述衬底基板上的正投影与对应触控电极在所述衬底基板上的正投影上不重叠，并且所述公共电极通过所述第一部分与对应触控电极连接。
  8. 根据权利要求1-4中任一项所述的阵列基板，还包括：
    位于所述多个像素电极与所述多个触控电极之间的第一介电层，以及
    位于所述多个触控电极与所述多个公共电极之间的第二介电层，其中，
    所述第二介电层在所述衬底基板上的正投影与所述多个像素电极在所述衬底基板上的正投影不重叠。
  9. 根据权利要求8所述的阵列基板，其中，
    所述第一介电层由无机材料制成，并且所述第二介电层由有机材料或无机材料制成。
  10. 根据权利要求1-4中任一项所述的阵列基板，其中，
    每一个薄膜晶体管包括低温多晶硅薄膜晶体管。
  11. 一种触控显示面板，包括根据权利要求1-10中任一所述的阵列基板。
  12. 一种触控显示装置，包括根据权利要求11所述的触控显示面板。
  13. 一种用于阵列基板的制造方法，包括：
    提供衬底基板(S1)；
    在所述衬底基板上形成阵列排布的多个薄膜晶体管(S2)；
    在所述多个薄膜晶体管远离所述衬底基板的一侧上形成绝缘平坦化层并且在所述绝缘平坦化层中形成分别暴露出每一个薄膜晶体管的漏极的多个过孔(S3)；
    在所述绝缘平坦化层远离所述多个薄膜晶体管的一侧上形成阵列排布的多个像素电极(S4)，每一个像素电极通过所述绝缘平坦化层中的一个过孔与对应薄膜晶体管的漏极连接；
    在所述多个像素电极远离所述绝缘平坦化层的一侧上形成阵列排布的多个触控电极(S5)；以及
    在所述多个触控电极远离所述多个像素电极的一侧上形成阵列排布的公共电极(S6)，每一个公共电极与对应触控电极连接。
  14. 根据权利要求13所述的用于阵列基板的制造方法，其中，在所述多个薄膜晶体管远离所述衬底基板的一侧上形成绝缘平坦化层并且在所述绝缘平坦化层中形成多个过孔的步骤包括以下子步骤：
    在所述多个薄膜晶体管远离所述衬底基板的一侧上沉积一层绝缘平坦化材料(S31)；
    在这一层绝缘平坦化材料中形成所述多个过孔(S32)；以及
    重复以上两个子步骤多次，使得之后形成的每一层绝缘平坦化材料中的所述多个过孔分别与之前形成的每一层绝缘平坦化材料中的对应过孔相互连通(S33)。
  15. 根据权利要求13所述的用于阵列基板的制造方法，还包括：
    在形成所述多个像素电极之后并且在形成所述多个触控电极之前，在所述多个像素电极远离所述绝缘平坦化层的一侧上形成第一介电层；以及
    在形成所述多个触控电极之后并且在形成所述多个公共电极之前，在所述多个触控电极远离所述多个像素电极的一侧上形成第二介电层，并且在所述第二介电层中形成多个过孔，使得每一个过孔对应于一个触控电极。
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