WO2019206051A1 - 显示面板及显示装置 - Google Patents
显示面板及显示装置 Download PDFInfo
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- WO2019206051A1 WO2019206051A1 PCT/CN2019/083516 CN2019083516W WO2019206051A1 WO 2019206051 A1 WO2019206051 A1 WO 2019206051A1 CN 2019083516 W CN2019083516 W CN 2019083516W WO 2019206051 A1 WO2019206051 A1 WO 2019206051A1
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- substrate
- display panel
- insulating layer
- driving circuit
- orthographic projection
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Definitions
- the present application relates to the field of display technologies, and in particular, to a display panel and a display device.
- the area of the periphery of the display panel corresponding to the bezel is getting smaller and smaller, so that the wiring density in the display panel is higher and higher, in order to avoid short circuit of the circuit, the manufacturing process of the display panel The requirements are also getting higher and higher.
- a display panel having a display area, the display panel comprising: a substrate; a driving circuit and at least one signal line on the substrate; and the driving circuit At least one insulating layer between the at least one signal line; wherein the driving circuit is located at a periphery of the display area; and an orthographic projection of at least one of the signal lines on the substrate substrate The orthographic projection of the driving circuit on the substrate substrate has overlapping regions.
- the display panel further includes: a plurality of light emitting devices located in the display area; the at least one signal line is at least one electrode power line, and the first of each of the plurality of light emitting devices The electrodes are all coupled to at least one of the electrode power lines; wherein the first electrode is an electrode of the light emitting device remote from the substrate.
- the first electrodes of all of the light emitting devices are connected to each other to form an electrode layer, and all of the electrode power lines are coupled to the electrode layer.
- the number of electrode power lines is one and is located at three sides of the electrode layer; the drive circuit is located at at least one of the three sides.
- the strip power line is provided with At least one opening, wherein at least one of the orthographic projections of the openings on the base substrate overlaps with an orthographic projection of at least one of the metal portions of the drive circuit on the substrate.
- the number of the openings is plural, and an orthographic projection of each of the openings on the substrate and an orthographic projection of at least one of the metal portions on the substrate There are overlapping areas.
- the driving circuit includes: a plurality of transistors, each of the transistors having a gate of one of the metal portions, a source of each transistor being one of the metal portions, and a drain of each transistor being one The metal portion; wherein one of the openings corresponds to at least one of a gate, a source, and a drain of at least one of the transistors.
- the driving circuit includes: at least one metal trace, one of the metal traces being one of the metal portions, wherein one of the openings corresponds to at least a portion of at least one of the metal traces .
- At least one of the metal traces corresponds to a plurality of the openings, wherein a plurality of the openings corresponding to the same metal trace are on the base substrate
- the total area of the area between the orthographic projection and the orthographic projection of the metal trace on the substrate is greater than or equal to 20% of the area of the orthographic projection of the metal trace on the substrate.
- an orthographic projection of a plurality of the openings corresponding to the same metal trace on the substrate and an orthographic projection of the metal trace on the substrate The total area of the overlap region is equal to 80% or 90% of the area of the orthographic projection of the metal trace on the substrate.
- the driving circuit, the at least one insulating layer, and the at least one electrode power line are sequentially stacked on the base substrate.
- the at least one insulating layer comprises: an organic insulating layer and/or an inorganic insulating layer.
- the at least one insulating layer comprises: a layer of the organic insulating layer and a layer of the inorganic insulating layer, wherein the inorganic insulating layer is disposed adjacent to the driving circuit, the organic insulating layer Set near the at least one signal line.
- the thickness of the organic insulating layer is greater than the thickness of the inorganic insulating layer.
- the driving circuit has a first region and a second region outside the first region; a metal portion in the driving circuit is located in the first region; all insulating layers correspond to The first region; or, all of the insulating layers correspond to the first region and the second region, and a thickness of a portion of all insulating layers corresponding to the first region is greater than a corresponding one of all insulating layers The thickness of the portion of the second region.
- the base substrate is a flexible substrate.
- a display device comprising the display panel of any of the above.
- FIG. 1 is a schematic top plan view of a display panel according to some embodiments of the present disclosure.
- FIG. 2 is a cross-sectional structural view of a display panel according to some embodiments of the present disclosure
- 3a is a schematic top plan view of still another display panel according to some embodiments of the present disclosure.
- 3b is a schematic top plan view of another display panel according to some embodiments of the present disclosure.
- FIG. 4 is a cross-sectional structural view of another display panel according to some embodiments of the present disclosure.
- FIG. 5 is a schematic structural diagram of a cathode layer and an electrode power line in a display panel according to some embodiments of the present disclosure
- FIG. 6 is a schematic structural view of the gate driving circuit of FIG. 3a or 3b;
- FIG. 7 is a schematic cross-sectional structural view of a display panel according to some embodiments of the present disclosure.
- FIG. 8 is a schematic structural diagram of an opening of an electrode power line in a display panel according to some embodiments of the present disclosure.
- FIG. 9a is a schematic view showing an arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- FIG. 9b is a schematic view showing still another arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- FIG. 9c is a schematic view showing another arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- Figure 9d is a schematic view of the shape of the opening in Figure 8.
- FIG. 10 is a schematic view showing still another arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- FIG. 11 is a schematic view showing still another arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- FIG. 12 is a schematic view showing still another arrangement manner in which the opening of FIG. 8 corresponds to the position of the TFT;
- Figure 13 is a schematic view showing an arrangement of the opening of the hole in Figure 8 corresponding to the position of the metal trace;
- Figure 14 is a schematic view showing another arrangement of the opening of the hole in Figure 8 corresponding to the position of the metal trace;
- Figure 15 is a schematic view showing an arrangement of at least one insulating layer in Figure 5;
- Figure 16 is a schematic view showing still another arrangement of at least one insulating layer in Figure 5;
- FIG. 17 is a schematic view showing another arrangement of at least one insulating layer in FIG. 5;
- Figure 18 is a schematic view showing still another arrangement of at least one insulating layer in Figure 5;
- Figure 19 is a schematic view showing still another arrangement of at least one insulating layer in Figure 5;
- FIG. 20 is a flowchart of a manufacturing process of a display panel according to some embodiments of the present disclosure.
- 21 is a cross-sectional structural view of a portion of a TFT in a display panel according to some embodiments of the present disclosure.
- FIG. 22 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.
- the display panel 01 having a display area 100 as shown in FIG. As shown in FIG. 2, the display panel 01 includes: a substrate substrate 10; a driving circuit 20 on the substrate substrate 10 and at least one signal line 30; and at least one between the driving circuit 20 and the at least one signal line 30. Layer insulating layer 40.
- the driving circuit 20 is located at the periphery of the display area 100, and the orthogonal projection of the at least one signal line 30 on the substrate 10 and the orthographic projection of the driving circuit 20 on the substrate 10 have an overlapping area A1.
- the display area 100 is an effective display area (Active Area) for the entire display panel, and thus may also be referred to as an AA area.
- AA area an effective display area
- the display area 100 is not connected to each edge of the display panel 01 as an example.
- one display panel 01 may also have A plurality of (ie, two or more) display areas 100 spaced apart from each other, and/or one display area 100 may extend to one or opposite edges of the display panel 01.
- the base substrate 10, the drive circuit 20, the signal line 30, and the insulating layer 40 are illustrated in Fig. 2, and the cross-sectional direction of Fig. 2 corresponds to the A-A' direction in Fig. 1.
- the driving circuit 20, the at least one insulating layer 40, and the at least one signal line 30 are sequentially stacked on the base substrate 10 as an example. Some embodiments of the present disclosure are not limited thereto, and the configurations of the above structures are not limited thereto.
- the method may further include: at least one signal line 30, at least one insulating layer 40, and a driving circuit 20 are sequentially stacked on the base substrate 10.
- the area of the overlapping area A1 is not limited.
- the display panel 01 may further include a buffer layer between the substrate substrate 10 and the driving circuit 20.
- the buffer layer can prevent the impurity ions in the substrate substrate 10 from being migrated into the driving circuit 20 by the high-temperature process, thereby improving the product of the display panel 01. rate.
- the base substrate 10 and at least one signal line 30 are disposed.
- Other layers may be provided according to actual needs, for example, the above-mentioned buffer layer (Buffer), and detailed description thereof will not be repeated.
- Buffer buffer layer
- the orthographic projection of at least one signal line 30 on the base substrate 10 and the orthographic projection of the drive circuit 20 on the base substrate 10 have an overlapping area A1
- the utilization of the peripheral area of the display area 100 is improved, thus, on the one hand, The wiring space around the display area 100 can be further compressed.
- the driving circuit 20 may be fabricated on the base substrate 10, for example, electronic components such as switches and capacitors in the driving circuit 20; and then at least one layer of insulation may be formed on the substrate 10 on which the driving circuit 20 is formed.
- the electronic components in the driving circuit 20 are disposed separately from the signal line 30 and insulated, so that the signal line 30 can be prevented from occupying the wiring space around the driving circuit 20, so that the wiring space around the display area 100 can be further compressed. At the same time, it is not necessary to increase the wiring density of the drive circuit 20 itself.
- the display panel 01 further includes a plurality of light emitting devices 50 located in the display area 100.
- the base substrate 10 in the display panel 01 may be a rigid substrate such as a glass substrate or a hard resin substrate; or the base substrate 10 may be a flexible substrate such as a flexible resin substrate.
- the plurality of light emitting devices 50 in the display region 100 may be packaged by a Thin Film Encapsulation (TFE) process, that is, The thin film encapsulation layer 60 is covered on the plurality of light emitting devices 50.
- TFE Thin Film Encapsulation
- the display panel 01 is a flexible display panel.
- the partial area located at the periphery of the display area 100 may be the bending area B1, and the bending area B1 may include, for example, the overlapping area A1 described above.
- the frame size can be reduced, which is advantageous for realizing the full screen design of the display panel 01.
- the display panel 01 may further include: a plurality of sub-pixels 100a arranged in an array in the display area 100, and each of the sub-pixels 100a includes: a pixel circuit.
- each of the pixel circuits may include at least one Thin Film Transistor (TFT), at least one capacitor, and one of the above-described light emitting devices 50.
- TFT Thin Film Transistor
- each pixel circuit is 2T1C, that is, each pixel circuit includes: two TFTs and one capacitor C, but some embodiments of the present disclosure are not limited thereto, and each pixel circuit
- the number of thin film transistors TFT and capacitor C can be determined according to actual needs.
- the light emitting device 50 may be a Light Emitting Diode (LED) or an Organic Light Emitting Diode (OLED).
- LED Light Emitting Diode
- OLED Organic Light Emitting Diode
- the above-described light emitting device 50 may be an OLED device as an example, and accordingly, the above display panel 01 is an OLED display panel.
- the above-described light emitting device includes a first electrode 51 and a second electrode 52 disposed opposite to each other, and a light emitting layer 53 interposed therebetween.
- the first electrode 51 is an electrode away from the base substrate 10 in the light emitting device, that is, the first electrode 51 is disposed farther away from the base substrate 1010 than the second electrode 52.
- the first electrode is also referred to as an upper electrode
- the second electrode is also referred to as a lower electrode
- the first electrode 51 may be a cathode, and the second electrode 52 may be an anode.
- the first electrode 51 may be an anode, and the second electrode 52 may be a cathode.
- the light-emitting principle of the above-mentioned light-emitting device is that, under the driving of an applied voltage, the positively charged holes excited from the anode and the negatively charged electrons excited from the cathode recombine in the light-emitting layer, thereby releasing energy and causing the light to be emitted.
- the molecules of the luminescent material in the layer are excited by this energy, which in turn produces light emission.
- the first electrode 51 is used as a cathode and the second electrode 52 is an anode.
- each of the sub-pixels 100a includes a light-emitting device 50.
- each of the sub-pixels 100a can be displayed with a corresponding color to realize the display function of the display panel 01.
- the second electrodes 52 of the respective light emitting devices 50 may be block-shaped and insulated from each other.
- the second electrodes 52 of two adjacent light emitting devices 50 may be spaced apart by a Pixel Defined Layer (PDL) 70.
- PDL Pixel Defined Layer
- the first electrodes 51 in the different light emitting devices 50 need only receive one reference voltage, that is, may be in different light emitting devices 50.
- the first electrode 51 applies the same voltage.
- the at least one signal line may be at least one electrode power line (Voltage Series, VSS), and the first electrode 51 of each of the plurality of light emitting devices 50 is coupled to one electrode power line to receive the same voltage.
- VSS Voltage Series, VSS
- the signal line may be another trace.
- only the signal line is the electrode power line VSS as an example.
- the first electrodes 51 of all the light emitting devices 50 may be connected to each other to form an entire electrode layer, and all of the electrode power lines are coupled to the electrode layer.
- the entire electrode layer of the above layer may be a whole layer of the cathode layer 510.
- the number of the electrode power lines 30 coupled to the cathode layer 510 may be one and located at the periphery of the cathode layer 510.
- the perimeter includes three sides of the cathode layer 510.
- the manner in which the electrode power line 30 is coupled to the cathode layer 510 includes, but is not limited to, direct connection by overlapping (ie, a portion of one is overlaid on a portion of the other); or, the electrode power line 30 and the cathode layer 510 may be formed simultaneously in a single process, that is, the two are directly connected together; or the electrode power supply line 30 and the cathode layer 510 may be connected through a via hole, which is not limited in some embodiments of the present disclosure, as long as the electrode is made
- the voltage on the power line 30 can be applied to the cathode layer 510.
- the number of the electrode power lines 30 coupled to the cathode layer 510 may be two, and the opposite two of the cathode layers 510 are respectively located. Side.
- the driving circuit 20 located around the display area 100 includes at least one gate driver circuit (GOA) 21 and at least one source driving circuit 22.
- GOA gate driver circuit
- the gate driving circuit 21 is configured to provide a corresponding scan signal to each of the sub-pixels 100a, which may be located at at least one of the opposite sides of the periphery of the display area 100; the source driving circuit 22 is configured to each sub- Pixel 100a provides a corresponding data signal, typically located at the side of display area 100 near the gate drive circuit 21.
- the orthographic projection of the at least one signal line 30 on the base substrate 10 may be on the substrate substrate 10 with at least one of the at least one gate driver circuit (GOA) 21 and the at least one source driver circuit 22 described above.
- the orthographic projection on the top has overlapping areas.
- the electrode power source line 30 needs to supply a relatively stable voltage to the entire cathode layer 510, the line width thereof is large, and the area of the area where the GOA is located is also large, so that the electrode power source line 30 can be lined.
- the orthographic projection on the base substrate 10 has an overlapping area with the orthographic projection of the GOA on the base substrate 10, that is, the position of the electrode power supply line 30 on one side in the periphery of the display area 100 may correspond to the position of the GOA on the side.
- the GOA may be located at one side of the periphery of the display area 100 as shown in FIG. 3a; or, the GOA may be located at opposite sides of the periphery of the display area 100 as shown in FIG. 3b.
- any of the gate drive circuits 21 includes a plurality of cascaded shift register sub-circuits (RS, labeled as RS1, RS2, ..., RSn, respectively, in FIG. 6 for clarity).
- RS cascaded shift register sub-circuits
- each shift register sub-circuit RS is coupled to a gate line GATE, and a shift register sub-circuit RS is configured to: control the on and off of each TFT in each pixel circuit in the sub-pixels of the same row status.
- the data voltage supplied from the above-described source driving circuit can be output to the second electrode 52 of the light emitting device 50 in each pixel circuit through the data line.
- the electric field between the first electrode 51 and the second electrode 52 can be driven between the first electrode 51 and the second electrode 52.
- the luminescent layer 53 emits light, thereby achieving the purpose of illuminating the light emitting device 50.
- the preparation of the gate driving circuit 21 (one or more) may be completed on the above-mentioned substrate substrate 10, for example, in the gate driving circuit 21 is prepared.
- an electronic component such as a switch (such as a TFT) or a capacitor; then, at least one insulating layer 40 covering the gate driving circuit 21 is formed on the base substrate 10 on which the gate driving circuit 21 is formed; On the base substrate 10 having the gate driving circuit 21 and the at least one insulating layer 40, at least one of the electrode power lines 30 coupled to the cathode layer 510 is formed, and at least one of the electrode power lines 30 is on the base substrate 10.
- the orthographic projection has an overlapping area with the orthographic projection of the gate drive circuit 21 (one or both) on the substrate substrate 10.
- the plurality of metal portions in the gate driving circuit 21 include, for example, a gate, a source, a drain, a metal trace in the same layer as the gate, and a source.
- the metal traces of the same layer of the pole (and/or the drain) are disposed separately from the electrode power supply line 30 and insulated, so that the electrode power supply line 30 can be prevented from occupying the wiring space around the gate drive circuit 21, so that the periphery of the display area 100 is The wiring space can be further compressed, and at the same time, it is not necessary to increase the wiring density of the gate driving circuit 21 itself.
- any of the electrode power lines 30 having overlapping regions on the substrate substrate 10 and the orthographic projection of the driving circuit 20 on the substrate substrate 10 are shown.
- the strip power supply line 30 is provided with at least one opening 301, wherein at least one of the openings 301 is projected on the base substrate 10 and at least one metal portion 201 of the driving circuit 20 is on the base substrate 10.
- the orthographic projection has an overlapping area A2.
- Fig. 7 corresponds to the A-A' direction in Fig. 8.
- the shape, number, and distribution of the openings 301 are not limited; the shape, number, and distribution of the metal portions 201 in the drive circuit 20 are not limited.
- the overlapping area A2 includes, but is not limited to, that shown in FIG. 7, that is, the area of one overlapping area A2 is equal to the area of the area of the orthographic projection of one metal part 201 on the base substrate 10 as long as at least one opening 301 is on the substrate.
- the orthographic projection on the substrate 10 and the orthographic projection of at least one of the metal portions 201 of the drive circuit 20 on the base substrate 10 may have an overlapping area A2.
- the driving circuit can be reduced in the electrode power line 30.
- the facing region of at least one of the metal portions 201 of 20 prevents or weakens the interference of the electrode power source line 30 to the metal portion 201 in the driving circuit 20, that is, the coupling effect.
- the strip power line 30 is disposed for any of the electrode power lines 30 having an overlapping area on the base substrate 10 and an orthographic projection of the drive circuit 20 on the base substrate 10.
- the strip power line 30 is disposed.
- the orthographic projection on the top has overlapping areas.
- the manner in which the openings 301 in the electrode power supply line 30 are provided will be exemplified by the gate driving circuit 21 as an example, according to different metal portions 201 in the gate driving circuit 21.
- the gate (G) of each transistor TFT is a metal portion
- the source (S) of each transistor TFT is a metal portion
- each transistor The drain (D) of the TFT is a metal portion.
- an opening 301 in the electrode power supply line 30 corresponds to at least one of the gate, the source and the drain of the at least one transistor TFT, that is, an opening 301 and A position of at least one of a gate, a source, and a drain of one transistor TFT corresponds.
- the line width of the electrode power supply line 30 is generally large, it can be regarded as a conductive layer by providing at least one opening 301 on the electrode power supply line 30, and such that an opening 301 corresponds to the gate of at least one transistor TFT. At least one of the pole, the source and the drain can prevent the voltage applied to the electrode TFT 30 from being applied to the channel of the lower transistor TFT for a long time when the electrode power source line 30 is in the voltage-increasing (VSS) state for a long time.
- VSS voltage-increasing
- the transistor TFT is a transistor having a relatively large length and a large length, for example, a driving transistor, interference with the channel can be remarkably reduced by providing the opening 301 on the electrode power supply line 30.
- each of the openings 301 may correspond to at least one of a gate, a source, and a drain of one transistor TFT.
- each opening 301 can be made. It corresponds to only one of the gate, source and drain of one transistor TFT.
- each of the openings 301 may correspond to a plurality of transistor TFTs.
- an orthographic projection of one opening 301 on the base substrate 10 covers the orthographic projection of the plurality of transistor TFTs on the base substrate 10.
- each of the openings 301 corresponds to the gate, the source and the drain of one transistor TFT. At least one of the other, the opening 301 of the other portion of the opening 301 corresponds to the plurality of transistor TFTs.
- the opening 301 when one opening 301 corresponds to a plurality of transistor TFTs, as shown in FIG. 9d, the opening 301 may have an elongated shape so that the area of the opening 301 is large, and thus the opening
- the orthographic projection of 301 on the base substrate 10 may cover the orthographic projection of the plurality of transistor TFTs on the substrate substrate 10.
- the source and the drain in the transistor TFT are generally symmetrical in structure and composition, the source and the drain in one transistor are generally indistinguishable.
- one of the poles is referred to as a source and the other pole is referred to as a drain.
- each of the shift register sub-circuits includes a driving transistor (abbreviated as DTFT) and a selection transistor (STFT for short).
- DTFT driving transistor
- STFT selection transistor
- the width and length of the driving transistor are relatively large, and can drive a certain load; the width and length of the selection transistor are relatively small compared to the driving transistor, as long as the signal can be transmitted, for example, a selection transistor is only required after being turned on.
- the signal loaded on the source (or drain) can be transmitted to the drain (or source).
- each of the openings 301 on the electrode power supply line 30 may correspond to one DTFT.
- a part of the opening 301 on the electrode power supply line 30 corresponds to the DTFT, and the other part of the opening 301 corresponds to the STFT.
- the positions of the plurality of openings 301 are not limited. As shown in FIG. 10 or FIG. 11, the plurality of openings 301 are aligned in the lateral or longitudinal direction, or, as shown in FIG. 12, the plurality of openings 301 are in the horizontal or vertical direction. Staggered.
- one metal trace is a metal portion.
- the gate driving circuit 21 generally includes a plurality of metal traces, and the plurality of metal traces include:
- STV start signal line
- CLK1 and CLK2 clock signal line
- VDD power supply voltage signal Line
- Vgatelow VGL
- one opening 301 corresponds to at least a portion of at least one metal trace (eg, CLK), that is, the position of one opening 301 corresponds to at least a portion of at least one metal trace.
- at least one metal trace eg, CLK
- the line width of the electrode power supply line 30 is generally large, it can be regarded as a conductive layer by providing at least one opening 301 on the electrode power supply line 30, and such that one opening 301 corresponds to at least one metal trace. At least a portion can reduce the coupling effect between the electrode power line 30 and the underlying metal trace when the electrode power line 30 is in a voltage-applying (VSS) state for a long time, for example:
- VSS voltage-applying
- the parasitic capacitance generated between the electrode power line 30 and the underlying metal trace is reduced, thereby preventing a delay (ie, signal attenuation) of a signal (eg, an AC signal) transmitted on the metal trace, thereby ensuring the normality of the gate drive circuit 21.
- a delay ie, signal attenuation
- the shape, the number, and the distribution of the openings 301 provided in the electrode power supply line 30 can be as much as possible corresponding to the underlying metal traces on the basis of maintaining the conduction performance of the electrode power supply line 30 to reduce the above coupling effect. .
- At least one metal trace corresponds to a plurality of openings 301, wherein a plurality of openings 301 corresponding to the same metal trace are on the base substrate 10.
- the total area of the area where the orthographic projection overlaps with the orthographic projection of the metal trace on the base substrate 10 is greater than or equal to 20% of the area of the orthographic projection of the metal trace on the base substrate 10.
- the orthographic projection of the plurality of openings 301 corresponding to the same metal trace on the base substrate 10 and the metal trace on the substrate The total area of the area of the orthographic projection on the substrate 10 is equal to 80% or 90% of the area of the orthographic projection of the metal trace on the substrate 10.
- the distribution of the plurality of openings 301 corresponding to the same metal trace is not limited.
- a plurality of openings 301 corresponding to the same metal trace may be continuously distributed, in which case the spacing between adjacent two openings 301 is small; or, corresponding to the same metal trace
- the plurality of openings 301 may also be distributed, in which case the spacing between adjacent two openings 301 is large.
- the gate driving circuit 21 includes the plurality of transistor TFTs and the plurality of metal traces
- the gate of each transistor TFT is a metal portion
- the source of each transistor TFT is a metal
- the drain in each transistor TFT is a metal portion
- each metal trace is also a metal portion.
- an opening 301 in the electrode power supply line 30 may correspond to the position of the transistor TFT or correspond to the position of the metal trace, and an opening 301 may correspond to the position of the transistor TFT and the position of the metal trace.
- each of the above openings 301 is exemplified by a rectangular opening (that is, a rectangular cross section in a direction parallel to the substrate), and some embodiments of the present disclosure have a shape of the opening. Without limitation, it may be a rectangular opening as described above, or a circular opening (ie, a circular cross section of the opening), a triangular opening (ie, a triangular cross section of the opening), and a diamond opening (ie, the opening of the opening is Diamond shape) and irregular shape opening (that is, the cross section of the opening is irregular).
- At least one layer is disposed between the gate driving circuit 21 and the electrode power source line 30. Insulation layer 40.
- the at least one insulating layer 40 may include at least one organic insulating layer and/or at least one inorganic insulating layer.
- the at least one insulating layer 40 may include a layer of an organic insulating layer 41.
- the organic insulating layer 41 may be a planarization layer (PLN) mainly composed of a resin material.
- PPN planarization layer
- the thickness of the organic insulating layer 41 may be 500 nm to 5000 nm. This numerical range enables the organic insulating layer 41 to have superior planarization and insulation effects, and at the same time satisfies the requirements of the ultra-thin design of the display panel 01.
- the organic insulating layer 41 may have a thickness of 800 nm to 2000 nm.
- the at least one insulating layer 40 may include a layer of inorganic insulating layer 42.
- the inorganic insulating layer 42 may be a passivation layer (PVX) mainly composed of a silicon nitride and/or silicon oxynitride material.
- PVX passivation layer
- the inorganic insulating layer 42 may have a thickness of 100 nm to 500 nm, which enables the inorganic insulating layer 42 to have a superior insulating effect and at the same time satisfies the requirements of the ultra-thin design of the display panel 01.
- the inorganic insulating layer 42 may have a thickness of 150 nm to 300 nm.
- the at least one insulating layer 40 may include an organic insulating layer 41 and an inorganic insulating layer 42.
- the inorganic insulating layer 42 is disposed adjacent to the gate driving circuit 21, and the organic insulating layer 41 is adjacent to the electrode power source line 30.
- the gate driving circuit 21 can be better protected by the inorganic insulating layer 42 to block water vapor or oxygen from entering the gate driving circuit 21, thereby avoiding the gate.
- the performance of the pole drive circuit 101 is affected.
- At least one insulating layer 40 includes an organic insulating layer 41 and an inorganic insulating layer 42
- the thickness of the organic insulating layer 41 and the inorganic insulating layer 42 can be set with reference to the above numerical range, and details are not described herein again.
- the preparation method of the organic insulating layer 41 is simpler than the preparation method of the inorganic insulating layer 42, it can be set as follows:
- the thickness of the organic insulating layer 41 is larger than the thickness of the inorganic insulating layer 42, so that the spacing between the respective metal portions in the gate driving circuit 21 and the above-described electrode power supply line 30 can be increased by the organic insulating layer 41, thereby further reducing the electrode power supply line 30.
- the coupling effect with each of the above metal portions further reduces the influence of the coupling effect on the TFTs in the gate driving circuit 21 and the transmission signal.
- the driving circuit (for example, the gate driving circuit 21) has the first region C1 and the second region C2 outside the first region C1, and the gate driving circuit 21 Each of the metal portions is located in the first region C1.
- all the insulating layers 40 correspond to the first region C1; or, as shown in FIG. 16, all the insulating layers 40 correspond to the first region C1 and the second region C2, and all the insulating layers 40
- the thickness of the portion corresponding to the first region C1 is greater than the thickness of the portion of all the insulating layers 40 corresponding to the second region C2.
- the electrode power supply line is in the process of leveling the organic encapsulation layer 61
- the convex portion away from the side of the base substrate 10 blocks the leveling of the organic encapsulating layer 61, thereby functioning as a damper to prevent the organic encapsulating layer 61 from flowing out of the preset area (the preset)
- the area usually includes the display area and slightly exceeds the display area.
- the insulating layers 40 may include an organic insulating layer 41 and/or an inorganic insulating layer 42.
- the thickness of the organic insulating layer 41 and the inorganic insulating layer 42 can be set by referring to the above numerical range, and details are not described herein again.
- the manufacturing process of the display panel 01 will be described by taking the structure shown in FIG. 19 as an example. As shown in FIG. 20, the manufacturing process includes steps 101-104 (S101-S104):
- each of the pixel circuits and the transistor TFTs in the gate driving circuit can be fabricated in the following manner:
- an active layer of a transistor TFT for example, polysilicon, denoted as P-Si in FIG. 21
- a source (S), and the like are formed by a patterning process.
- Drain (D) drain
- an insulating layer is formed between the gate (G) and the active layer, and the insulating layer is, for example, a first gate insulating layer (Gate Insulating layer 1, GL1);
- An insulating layer is formed between the gate (G) and the source (S) and the drain (D), and the insulating layer includes a second gate insulating layer (GL2) and/or an interlayer dielectric layer ( Inter Layer Dielectric, ILD).
- each pixel circuit and gate drive circuit can be made in the following manner:
- each of the gates While fabricating each of the gates, one of each of the capacitors is fabricated; while the respective sources and drains are fabricated, the other of the capacitors is fabricated.
- the second gate insulating layer GL2 and/or the interlayer dielectric layer ILD can isolate the opposite two electrodes in each capacitor, thereby forming respective capacitors in the corresponding circuits.
- the metal traces in the gate driving circuit can be fabricated by one patterning process.
- the so-called patterning process refers to a process for forming a predetermined pattern.
- the process may include: a photolithography process, or a photolithography process and an etching process.
- the photolithography process refers to a process of forming a photoresist pattern by using a photoresist, a mask, an exposure machine, or the like, including a plurality of steps of film formation, exposure, and development.
- the above-mentioned patterning process may also include other processes such as printing, inkjet, and the like.
- the corresponding patterning process may be selected according to the structure to be formed in the above display panel 01 provided by some embodiments of the present disclosure.
- the one-time patterning process in some embodiments of the present disclosure specifically includes a photolithography process (ie, using a mask) and at least one etching process to form a desired photoresist pattern by a photolithography process, at least once.
- the etch process etches the film underlying the photoresist pattern to form the desired structure and removes (eg, removes) the photoresist pattern (eg, using an ashing process).
- an inorganic insulating layer 42 and an organic insulating layer 41 are formed on the base substrate 10 on which the source (S) and the drain (D) are formed.
- the materials and thicknesses of the inorganic insulating layer 42 and the organic insulating layer 41 are set as described above, and are not described herein again.
- the organic encapsulating layer in the thin film encapsulation layer is blocked during the leveling process.
- the portion of the inorganic insulating film corresponding to the second region may be removed or thinned, so that the inorganic insulating layer 42 formed of the inorganic insulating film only corresponds to the first region, or is formed.
- the thickness of the portion of the inorganic insulating layer 42 corresponding to the first region is greater than the thickness of the portion corresponding to the second region.
- a portion of the organic insulating film corresponding to the second region may be removed or thinned, so that the organic insulating layer 41 formed of the organic insulating film corresponds only to the first region.
- the thickness of the portion of the organic insulating layer 41 formed corresponding to the first region is greater than the thickness of the portion corresponding to the second region.
- a semi-transmissive mask (Halftone) can be used in the process of removing or thinning.
- the organic insulating layer 41 and the inorganic insulating layer 42 have different thicknesses in different regions (or only correspond to one region), an uneven surface is formed, and the electrode power supply line 30 formed thereafter is formed.
- the convex portion on the side away from the base substrate 10 blocks the leveling of the above-described organic encapsulating layer, thereby functioning as a dam.
- ⁇ is a constant
- S is the facing area of the two electrodes in the capacitor
- d is the distance between the two electrodes in the capacitor
- k is the electrostatic constant
- the size of the opening 301 can be appropriately reduced, and/or the number of the openings 301 can be reduced, so that the electrode power supply line 30 can still maintain a good conduction state.
- a metal layer may be deposited on the base substrate 10 on which the at least one insulating layer 40 is formed, and the material of the metal layer may be the same as the material for making the source and the drain, of course, the metal layer The material can also be the same material as the gate.
- the metal layer is patterned to form the opening 301.
- the opening 301 can correspond to the position of the TFT and/or the metal trace in the gate driving circuit.
- the opening 301 corresponding to the position of the TFT and the opening 301 corresponding to the metal trace may be prepared by one patterning process or by two patterning processes respectively, and some embodiments of the present disclosure do not Make a limit.
- the conductive material above the TFT and/or the metal trace in the gate driving circuit can be removed, thereby reducing the gate driving circuit below the electrode power supply line 30 fabricated above the gate driving circuit.
- the influence of the TFT and the signal transmission on the metal trace can be reduced.
- the thin film encapsulation layer formed by the thin film encapsulation process may include two inorganic encapsulation layers and one organic encapsulation layer, and the organic encapsulation layer is located between the two inorganic encapsulation layers.
- each or part of the transistor TFTs in each circuit may also be a bottom gate type, that is, the gate is located on the other side of the active layer close to the substrate, and may be according to actual needs of the circuit.
- a transistor TFT having a corresponding structure is fabricated.
- the above manufacturing process is only as an example in which at least one insulating layer 40 shown in FIG. 19 includes an inorganic insulating layer 42 and an organic insulating layer 41, and the insulating layer is disposed as shown in FIG. 17 or as shown in FIG. In the manner shown in FIG. 18, only the corresponding adjustment in step S102 is required, and details are not described herein again.
- Some embodiments of the present disclosure also provide a display device, as shown in FIG. 22, which includes the display panel 01 provided by any of the embodiments described above.
- the display device 02 has the same technical effects as the display panel 01 provided in the foregoing embodiments, and details are not described herein again.
- the display panel 01 is represented by a single layer, and the specific structure in the display panel 01 is not depicted.
- the specific structure reference may be made to the foregoing description, and Narration.
- the above display device may be any product or component having a display function such as a display, a television, a digital photo frame, a mobile phone or a tablet computer.
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Abstract
Description
Claims (17)
- 一种显示面板,所述显示面板具有显示区,所述显示面板包括:衬底基板;位于所述衬底基板上的驱动电路和至少一条信号线;以及位于所述驱动电路与所述至少一条信号线之间的至少一层绝缘层;其中,所述驱动电路位于所述显示区的周边;以及至少一条所述信号线在所述衬底基板上的正投影与所述驱动电路在所述衬底基板上的正投影有重叠区域。
- 根据权利要求1所述的显示面板,还包括:位于所述显示区的多个发光器件;所述至少一条信号线为至少一条电极电源线,所述多个发光器件中的每个的第一电极均耦接于至少一条所述电极电源线;其中,所述第一电极为所述发光器件中远离所述衬底基板的电极。
- 根据权利要求2所述的显示面板,其中,所有发光器件的所述第一电极相互连接构成一个电极层,所有电极电源线均耦接于所述电极层。
- 根据权利要求3所述的显示面板,其中,所述电极电源线的数量为一条,且位于所述电极层的三个侧面处;所述驱动电路位于所述三个侧面处中的至少一个侧面处。
- 根据权利要求2-4任一项所述的显示面板,其中,对于在所述衬底基板上的正投影与所述驱动电路在所述衬底基板上的正投影有重叠区域的任一条电极电源线,该条电极电源线上设置有至少一个开孔,其中,至少有一个所述开孔在所述衬底基板上的正投影与所述驱动电路中的至少一个金属部在所述衬底基板上的正投影有重叠区域。
- 根据权利要求5所述的显示面板,其中,所述开孔的数量为多个,且每个所述开孔在所述衬底基板上的正投影与至少一个所述金属部在所述衬底基板上的正投影有重叠区域。
- 根据权利要求6所述的显示面板,其中,所述驱动电路包括:多个晶体管,每个所述晶体管的栅极为一个所述金属部、每个晶体管的源极为一个所述金属部、以及每个晶体管的漏极为一个所述金属部;其中,一个所述开孔对应于至少一个所述晶体管的栅极、源极和漏极中的至少一个。
- 根据权利要求6所述的显示面板,其中,所述驱动电路包括:至少一条金属走线,一条所述金属走线为一个所述金属部,其中,一个所述开孔对应于至少一条所述金属走线的至少一部分。
- 根据权利要求8所述的显示面板,其中,至少有一条所述金属走线对应于多个所述开孔,其中,与同一条所述金属走线相对应的多个所述开孔在所述衬底基板上的正投影与该条金属走线在所述衬底基板上的正投影相重叠区域的总面积,大于或等于该条金属走线在所述衬底基板上的正投影的面积的20%。
- 根据权利要求9所述的显示面板,其中,与同一条所述金属走线相对应的多个所述开孔在所述衬底基板上的正投影与该条金属走线在所述衬底基板上的正投影相重叠区域的总面积,等于该条金属走线在所述衬底基板上的正投影的面积的80%或90%。
- 根据权利要求2-4任一项所述的显示面板,其中,所述驱动电路、所述至少一层绝缘层、以及所述至少一条电极电源线依次层叠设置在所述衬底基板上。
- 根据权利要求2-4任一项所述的显示面板,其中,所述至少一层绝缘层包括:一层有机绝缘层和/或一层无机绝缘层。
- 根据权利要求12所述的显示面板,其中,所述至少一层绝缘层包括:一层所述有机绝缘层和一层所述无机绝缘层,其中,所述无机绝缘层靠近所述驱动电路设置,所述有机绝缘层靠近所述至少一条信号线设置。
- 根据权利要求12所述的显示面板,其中,所述有机绝缘层的厚度大于所述无机绝缘层的厚度。
- 根据权利要求2-14任一项所述的显示面板,其中,所述驱动电路具有第一区域和位于所述第一区域之外的第二区域;所述驱动电路中的金属部位于所述第一区域内;所有绝缘层均对应于所述第一区域;或者,所有绝缘层均对应于所述第一区域和所述第二区域,且所有绝缘层中对应于所述第一区域的部分的厚度大于所有绝缘层中对应于所述第二区域的部分的厚度。
- 根据权利要求2-4任一项所述的显示面板,其中,所述衬底基板为柔性衬底基板。
- 一种显示装置,其中,包括如权利要求1-16任一项所述的显示面板。
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CN108598118A (zh) | 2018-04-26 | 2018-09-28 | 京东方科技集团股份有限公司 | 一种显示面板及显示装置 |
CN109283733A (zh) * | 2018-11-09 | 2019-01-29 | 昆山龙腾光电有限公司 | 一种反射式显示面板、显示面板的制作方法及显示装置 |
CN109658824B (zh) * | 2019-02-28 | 2021-07-09 | 武汉天马微电子有限公司 | 显示面板和显示装置 |
CN110010078B (zh) * | 2019-03-14 | 2022-02-08 | 合肥京东方卓印科技有限公司 | 移位寄存器单元、栅极驱动电路和显示装置 |
CN111403447A (zh) * | 2020-03-24 | 2020-07-10 | 武汉华星光电半导体显示技术有限公司 | 一种显示面板、其制备方法以及显示装置 |
US11785814B2 (en) | 2020-08-31 | 2023-10-10 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and display device |
CN113097263B (zh) | 2021-03-25 | 2024-05-24 | 京东方科技集团股份有限公司 | 显示基板和显示装置 |
WO2022252024A1 (zh) * | 2021-05-31 | 2022-12-08 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
CN116670749A (zh) * | 2021-12-28 | 2023-08-29 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示装置 |
CN114446255B (zh) * | 2022-01-20 | 2023-02-28 | Tcl华星光电技术有限公司 | 显示面板及显示装置 |
WO2023168602A1 (zh) * | 2022-03-08 | 2023-09-14 | 京东方科技集团股份有限公司 | 显示装置、显示面板及制备方法 |
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