WO2023168602A1 - 显示装置、显示面板及制备方法 - Google Patents

显示装置、显示面板及制备方法 Download PDF

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Publication number
WO2023168602A1
WO2023168602A1 PCT/CN2022/079772 CN2022079772W WO2023168602A1 WO 2023168602 A1 WO2023168602 A1 WO 2023168602A1 CN 2022079772 W CN2022079772 W CN 2022079772W WO 2023168602 A1 WO2023168602 A1 WO 2023168602A1
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WIPO (PCT)
Prior art keywords
base substrate
shift register
circuit
display panel
metal layer
Prior art date
Application number
PCT/CN2022/079772
Other languages
English (en)
French (fr)
Inventor
宋二龙
颜海龙
张静丽
高雅瑰
张锴
成瑞
施昆雁
陈亚菲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/079772 priority Critical patent/WO2023168602A1/zh
Priority to CN202280000382.0A priority patent/CN117043838A/zh
Publication of WO2023168602A1 publication Critical patent/WO2023168602A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a display device, a display panel and a preparation method.
  • the screen border refers to the distance from the display area (Active Area, AA area) to the screen border.
  • AA area the display area
  • consumers are increasingly demanding display screen borders and expect display screens with narrower borders.
  • the frame of the display screen in the existing technology is still relatively wide, which cannot meet the needs of consumers.
  • the purpose of this disclosure is to provide a display device, a display panel and a preparation method that can reduce the width of the display panel frame and satisfy consumers' demand for narrow frames.
  • a display panel including a base substrate, a driving circuit provided on one side of the base substrate, and a multi-layer metal layer:
  • the base substrate includes a display area and a peripheral area located at the periphery of the display area;
  • the driving circuit includes a peripheral circuit and a pixel circuit, the peripheral circuit is located in the peripheral area, the pixel circuit is located in the display area, the peripheral circuit is connected to the pixel circuit, and is used to provide the pixel circuit with drive signal;
  • the peripheral circuit includes a plurality of signal lines, and the plurality of signal lines are distributed in at least two layers of the metal layer.
  • the peripheral circuit includes a gate driving circuit and a lighting control circuit, and both the gate driving circuit and the lighting control circuit include the plurality of signal lines;
  • the plurality of signal lines of the gate drive circuit are distributed in at least two layers of the metal layer;
  • the plurality of signal lines of the light emitting control circuit are distributed in at least two of the metal layers.
  • the multi-layer metal layer includes a first metal layer and a second metal layer sequentially arranged in a direction away from the base substrate;
  • some of the signal lines are distributed in the first metal layer, and some of the signal lines are distributed in the second metal layer;
  • the plurality of signal lines include clock signal lines and/or voltage signal lines.
  • the peripheral circuit includes a gate drive circuit including a plurality of cascaded first shift register units and the plurality of signal lines, and the The first shift register unit includes a transistor;
  • the clock signal line is used to transmit a clock signal to the first shift register unit, and the voltage signal line is used to transmit a voltage signal to the first shift register unit;
  • the first metal layer includes the source and drain of the transistor in the first shift register unit
  • the second metal layer is provided on a side of the first shift register unit away from the base substrate;
  • the orthographic projection of the signal lines distributed in the second metal layer in the gate driving circuit on the base substrate is at least partially the same as the orthographic projection of the first shift register unit on the base substrate. overlapping.
  • the peripheral circuit includes a lighting control circuit, the lighting control circuit includes a plurality of cascaded second shift register units and the plurality of signal lines, and the second The shift register unit includes a transistor;
  • the clock signal line is used to transmit a clock signal to the second shift register unit, and the voltage signal line is used to transmit a voltage signal to the second shift register unit;
  • the first metal layer includes the source and drain of the transistor in the second shift register unit;
  • the second metal layer is provided on a side of the second shift register unit away from the base substrate;
  • the orthographic projection of the signal lines distributed in the second metal layer in the light emitting control circuit on the base substrate at least partially overlaps the orthographic projection of the second shift register unit on the base substrate.
  • the display panel further includes an initial signal line, the initial signal line is located in the peripheral area, and the initial signal line is used to transmit an initial signal to the pixel circuit, so The initial signal lines are distributed in the second metal layer.
  • an orthographic projection of the initial signal line on the substrate substrate at least partially overlaps an orthographic projection of the first shift register unit on the substrate substrate.
  • the display panel further includes electrical connection lines, and the peripheral circuit is connected to the pixel circuit through the electrical connection lines;
  • the initial signal line is provided on the side of the electrical connection line away from the base substrate;
  • the orthographic projection of the initial signal line on the base substrate and the orthographic projection of the electrical connection line on the base substrate at least partially overlap.
  • the gate driving circuit includes a first gate driving circuit and a second gate driving circuit
  • the first shift register unit includes a first sub-shift register unit and a second sub-shift register unit
  • the first gate driving circuit includes the first sub-shift register unit
  • the second gate driving circuit includes a second sub-shift register unit
  • the second gate The driving circuit is located on a side of the first gate driving circuit close to the display area;
  • the orthographic projection of the initial signal line on the base substrate at least partially overlaps the orthographic projection of the second sub-shift register unit on the base substrate.
  • the pixel circuit includes a low temperature polysilicon transistor and an oxide transistor;
  • the first gate driving circuit is used to drive the oxide transistor, and the second gate driving circuit is used to drive the low temperature polysilicon transistor.
  • the display panel further includes:
  • a cathode signal line is provided on one side of the base substrate and located in the peripheral area, and the cathode signal line is distributed in the first metal layer;
  • a cathode bonding line, one end of the cathode bonding line is overlapped with the cathode signal line, and at least part of the cathode bonding line is distributed in the second metal layer.
  • the cathode signal line is provided on a side of the light-emitting control circuit away from the display area;
  • An orthographic projection of the cathode strap on the base substrate at least partially overlaps an orthographic projection of the second shift register cell on the base substrate.
  • the display panel further includes:
  • a planarization layer is provided between the first metal layer and the second metal layer, and the orthographic projection of the planarization layer on the base substrate covers the first sub-shift register unit and the A gap between orthographic projections of the second sub-shift register unit on the base substrate.
  • the display panel further includes:
  • An encapsulation layer located on the side of the driving circuit and the multi-layer metal layer away from the base substrate;
  • the encapsulation layer includes a first inorganic layer and a second inorganic layer sequentially arranged in a direction away from the base substrate, and the orthographic projection of the second inorganic layer on the base substrate covers the first inorganic layer on the base substrate.
  • the area of the orthographic projection of the second inorganic layer on the base substrate is greater than the area of the orthographic projection of the first inorganic layer on the base substrate.
  • the first inorganic layer has a first surface away from the base substrate and a first sidewall away from the display area;
  • the second inorganic layer contacts the first sidewall and at least a portion of the first surface.
  • a method for manufacturing a display panel including:
  • the base substrate including a display area and a peripheral area located at the periphery of the display area;
  • the driving circuit includes a peripheral circuit.
  • the driving circuit includes a peripheral circuit and a pixel circuit.
  • the peripheral circuit is located in the peripheral area.
  • the pixel The circuit is located in the display area, and the peripheral circuit is connected to the pixel circuit for providing driving signals to the pixel circuit;
  • the peripheral circuit includes a plurality of signal lines, and the plurality of signal lines are distributed on at least two layers. in the metal layer.
  • the preparation method further includes:
  • a second inorganic layer is formed on the side of the first inorganic layer away from the base substrate, and the orthographic projection of the second inorganic layer on the base substrate covers the first inorganic layer on the substrate.
  • the area of the orthographic projection of the second inorganic layer on the base substrate is greater than the area of the orthographic projection of the first inorganic layer on the base substrate.
  • a display device including the display panel as described in the first aspect.
  • the display panel provided by the present disclosure distributes multiple signal lines in the peripheral circuit in at least two metal layers to reduce the space occupied by the peripheral circuit in the direction parallel to the base substrate, thereby helping to reduce the space occupied by the peripheral circuit in the direction parallel to the substrate.
  • the size of the space occupied by the area is reduced, and the size of the peripheral area is reduced, that is, the width of the display panel frame is reduced to meet consumers' demand for narrow borders.
  • Figure 1 is a schematic structural diagram of peripheral circuits at the position of a display panel in an exemplary embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display panel gate drive circuit in an exemplary embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a display panel lighting control circuit in an exemplary embodiment of the present disclosure
  • Figure 4 is a schematic plan view of the distribution of multiple signal lines of the peripheral circuit in an exemplary embodiment of the present disclosure
  • Figure 5 is a schematic plan view of the distribution of multiple signal lines of the peripheral circuit in yet another exemplary embodiment of the present disclosure
  • Figure 6 is a schematic cross-sectional view of the distribution of multiple signal lines of the peripheral circuit in an exemplary embodiment of the present disclosure
  • Figure 7 is a schematic cross-sectional view of the distribution of multiple signal lines of the peripheral circuit in yet another exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of the display area of the display panel in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” placed on the other structure, or that the structure is “indirectly” placed on the other structure through another structure. on other structures.
  • the active layer of low-temperature polysilicon transistors uses low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), and the active layer of oxide thin film transistors uses oxide semiconductors (Oxide), such as indium gallium zinc oxide and indium gallium tin oxide. wait.
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display panel to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO) display panel can take advantage of both to achieve low-frequency drive, which can reduce power consumption and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the pixel circuit of the LTPO display panel includes low-temperature polysilicon transistors and oxide thin film transistors.
  • the gate drive circuit (Gate on array, GOA) needs to provide both high-level gate drive signals and low-level gate drive signals, which includes the number of transistors. There are many and they take up a lot of space. Therefore, the borders of LTPO display panels are wider and cannot meet consumers' demand for narrow borders.
  • the present disclosure provides a display panel, including a base substrate 01 , a driving circuit provided on one side of the base substrate 01 , and a multi-layer metal layer.
  • the base substrate 01 includes a display area 010 and a peripheral area 011 located outside the display area 010; the driving circuit includes a peripheral circuit 100 and a pixel circuit 200.
  • the peripheral circuit 100 is located in the peripheral area 011, and the pixel circuit 200 is located in the display area 010.
  • the peripheral circuit 100 and The pixel circuit 200 is connected to provide driving signals to the pixel circuit 200.
  • the peripheral circuit 100 includes a plurality of signal lines, and the plurality of signal lines are distributed in at least two metal layers.
  • the display panel provided by the present disclosure distributes multiple signal lines in the peripheral circuit 100 in at least two metal layers to reduce the space occupied by the peripheral circuit 100 in the direction parallel to the base substrate 01, thereby helping to reduce the number of peripheral circuits.
  • the size of the space occupied by the circuit 100 in the peripheral area 011 reduces the size of the peripheral area 011, that is, reduces the width of the display panel frame to meet consumers' demand for narrow frames.
  • the present disclosure provides a display panel, which may be an organic light-emitting diode (OLED) display panel, such as an AMOLED (Active-matrix organic light-emitting diode, active matrix organic light-emitting diode) display panel. It can also be a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel, a micro light emitting diode (Micro Light Emitting Diodes, Micro LED) display panel, etc. This disclosure does not specifically limit this.
  • OLED organic light-emitting diode
  • AMOLED Active-matrix organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • the display panel includes a base substrate 01 , a driving circuit provided on one side of the base substrate 01 , and multiple metal layers.
  • the base substrate 01 includes a display area 010 and a peripheral area 011 located at the periphery of the display area 010.
  • the display area 010 can be used to display images.
  • the base substrate 01 may be a base substrate of inorganic material or a base substrate of organic material.
  • the material of the base substrate 01 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate 01 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or combinations thereof.
  • PMMA polymethyl methacrylate
  • PVA polyvinyl alcohol
  • PVP polyvinyl phenol
  • PES polyether sulfone
  • polyimide polyamide
  • polyacetal polycarbonate
  • PC polyethylene terephthalate
  • PET polyethylene naphthalate
  • PEN Polyethylene naphthalate
  • the base substrate 01 may also be a flexible base substrate 01.
  • the material of the base substrate 01 may be polyimide (PI).
  • the base substrate 01 can also be a composite of multiple layers of materials.
  • the base substrate 01 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, and a pressure-sensitive adhesive layer that are stacked in sequence.
  • Bottom Film Bottom Film
  • a first polyimide layer and a second polyimide layer are stacked in sequence.
  • the drive circuit is located on one side of the base substrate 01.
  • the drive circuit includes a peripheral circuit 100 and a pixel circuit 200.
  • the peripheral circuit 100 is located in the peripheral area 011, and the pixel circuit 200 is located in the display area 010.
  • the pixel circuit 200 can be used to drive the light emission of the OLED display panel.
  • the device emits light.
  • the pixel circuit 200 may be a 7T1C, 7T2C, 6T1C or 6T2C pixel circuit 200, and its structure is not particularly limited here.
  • nTmC indicates that a pixel circuit 200 includes n transistors (indicated by the letter “T”) and m capacitors (indicated by the letter “C”).
  • the pixel circuits 200 can be arranged in the display area 010 in an array to form a matrix structure of multiple rows and columns.
  • the peripheral circuit 100 includes a gate driving circuit 110 and a light emission control circuit 120 .
  • the display panel also includes an electrical connection line LL through which the peripheral circuit 100 is connected to the pixel circuit 200 .
  • the electrical connection line LL may include a light emission control signal line EML and a gate line GAL.
  • the gate driving circuit 110 is connected to the pixel circuit 200 through the gate line GAL
  • the emission control circuit 120 is connected to the pixel circuit 200 through the emission control signal line EML.
  • both the gate driving circuit 110 and the light emitting control circuit 120 include a plurality of signal lines.
  • the plurality of signal lines of the gate driving circuit 110 and/or the light emitting control circuit 120 may be distributed in at least two metal layers.
  • the plurality of signal lines 112 of the gate driving circuit 110 are distributed in at least two metal layers.
  • the plurality of signal lines 122 of the light emission control circuit 120 are distributed in In at least two metal layers, in some embodiments, the plurality of signal lines 112 of the gate driving circuit 110 and the plurality of signal lines 122 of the light emission control circuit 120 are distributed in at least two metal layers.
  • the gate driving circuit 110 can be disposed on one side of the display area 010 , and provides gates to the pixel circuit 200 through each gate line GAL row by row from one side. The driving signal is driven by one side.
  • the gate driving circuit 110 can also be disposed on both sides of the display area 010, and the gate driving circuits 110 on both sides simultaneously provide gate driving signals to each pixel circuit 200 row by row from both sides, that is, using a bilateral Driving; of course, the gate driving circuits 110 on both sides can also alternately provide gate driving signals to each pixel circuit 200 row by row from both sides, that is, using cross driving.
  • the display panel includes multiple metal layers, and the multiple metal layers are disposed on one side of the base substrate 01 .
  • the display panel may include two, three or more metal layers.
  • the peripheral circuit 100 such as the gate driving circuit 110 and the light emission control circuit 120, includes a plurality of signal lines distributed in at least two metal layers.
  • multiple signal lines of the gate driving circuit 110 and the light emission control circuit 120 may be distributed in two, three or more metal layers.
  • the multi-layer metal layer includes a first metal layer 30 and a second metal layer 40 that are sequentially arranged in a direction away from the base substrate 01 .
  • Some of the plurality of signal lines are distributed in the first metal layer 30 , and some of the signal lines are distributed in the second metal layer 40 .
  • the plurality of signal lines may include clock signal lines and/or voltage signal lines, the clock signal lines are used to transmit clock signals, and the voltage signal lines are used to transmit voltage signals.
  • the clock signal lines are distributed in the first metal layer 30 and the voltage signal lines are distributed in the second metal layer 40; or several of the clock signal lines are distributed in the first metal layer 30, and the remaining clock signal lines are distributed in the first metal layer 30.
  • the signal lines are distributed in the second metal layer 40; or several voltage signal lines among the voltage signal lines are distributed in the first metal layer 30, and the remaining voltage signal lines are distributed in the second metal layer 40.
  • the specific disclosure is not limited. .
  • the present disclosure distributes multiple signal lines, such as clock signal lines and voltage signal lines, in the peripheral circuit 100, such as the gate driving circuit 110 and/or the light emitting control circuit 120, in at least two metal layers, that is, multiple signal lines Stacked arrangement, this design method helps to reduce the space occupied by clock signal lines and voltage signal lines in the direction parallel to the substrate substrate 01, and provides a basis for realizing narrow frame design.
  • the gate driving circuit 110 also includes a plurality of cascaded first shift register units 111.
  • the plurality of cascaded first shift register units 111 are connected to respective gate lines GAL in one-to-one correspondence to provide gate driving signals to the corresponding pixel circuits 200 .
  • the first shift register unit 111 independently sets a gate drive signal output terminal and a cascade signal output terminal.
  • the gate drive signal output terminal outputs the gate drive signal to the gate line GAL connected thereto, and the cascade signal output terminal outputs a gate drive signal to the gate line GAL connected thereto. link signal.
  • the signal input terminal of the first shift register unit 111 of the next stage is connected to the cascade signal output terminal of the first shift register unit 111 of the upper stage. connect.
  • the voltage signal line in the gate driving circuit 110 is used to transmit voltage to the first shift register unit 111 .
  • the number of voltage signal lines can be multiple.
  • the gate driving circuit 110 may include N voltage signal lines, which are respectively a first voltage signal line, a second voltage signal line, a third voltage signal line... and an Nth voltage signal line, different voltage signal lines. Transmits different voltage signals.
  • a single first shift register unit 111 can be connected to one or more voltage signal lines, which is not limited in this disclosure.
  • the clock signal line is used to transmit the clock signal to the first shift register unit 111.
  • the number of clock signal lines can be multiple.
  • the gate driving circuit 110 may include N clock signal lines, which are respectively a first clock signal line, a second clock signal line, a third clock signal line...
  • a single first shift register unit 111 can be connected to one or more clock signal lines, which is not limited in this disclosure.
  • the first shift register unit 111 outputs a gate drive signal to the gate line GAL according to the clock signal transmitted by the clock signal line and other signals transmitted by other signal lines, such as voltage signals, and then provides the gate drive signal to the corresponding pixel circuit 200 .
  • the first shift register unit 111 includes a transistor, and the first metal layer 30 includes the source and drain of the transistor in the first shift register unit 111 .
  • the two metal layers 40 are provided on the side of the first shift register unit 111 away from the base substrate 01 .
  • the orthographic projection of the signal lines 112 distributed in the second metal layer 40 in the gate driving circuit 110 on the base substrate 01 at least partially overlaps with the orthographic projection of the first shift register unit 111 on the base substrate 01 . That is, the signal lines 112 distributed in the second metal layer 40 are located above the first shift register unit 111 .
  • the orthographic projection of the clock signal line on the base substrate 01 at least partially overlaps with the orthographic projection of the first shift register unit 111 on the base substrate 01;
  • the orthographic projection of the voltage signal lines on the base substrate 01 and the orthographic projection of the first shift register unit 111 on the base substrate 01 at least partially overlap.
  • the lighting control circuit 120 further includes a plurality of cascaded second shift register units 121.
  • the plurality of cascaded second shift register units 121 The signal output terminals of 121 are connected to respective light-emitting control signal lines EML in one-to-one correspondence to provide light-emitting control signals to the corresponding pixel circuits 200 .
  • the signal output terminals of the second shift register units 121 of each stage are respectively adjacent to the next one.
  • the signal input terminal of the second shift register unit 121 of the stage is connected.
  • the voltage signal line in the lighting control circuit 120 is used to transmit voltage to the second shift register unit 121
  • the clock signal line is used to transmit a clock signal to the second shift register unit 121 .
  • the number of voltage signal lines and clock signal lines in the lighting control circuit 120 can also be multiple. Different clock signal lines can transmit different clock signals, and different voltage signal lines can transmit different voltage signals.
  • the second shift register unit 121 outputs a light-emitting control signal to the light-emitting control signal line EML according to the clock signal transmitted by the clock signal line and other signals transmitted by other signal lines, such as voltage signals, and then provides the light-emitting control signal to the corresponding pixel circuit 200 .
  • the second shift register unit 121 includes a transistor
  • the first metal layer 30 includes the source and drain of the transistor in the second shift register unit 121 .
  • the two metal layers 40 are provided on the side of the second shift register unit 121 away from the base substrate 01 .
  • the orthographic projection of the signal lines 122 distributed in the second metal layer 40 in the light emitting control circuit 120 on the base substrate 01 at least partially overlaps with the orthographic projection of the second shift register unit 121 on the base substrate 01 .
  • the pixel circuit 200 also includes a plurality of transistors, and the first metal layer 30 also includes the sources and drains of the transistors in the pixel circuit 200 .
  • Each circuit in the driving circuit such as the gate driving circuit 110, the light emission control circuit 120 and the pixel circuit 200, includes transistors formed on one side of the base substrate 01.
  • the transistors included in the pixel circuit 200 may include low-temperature polysilicon transistors, oxide transistors, or both low-temperature polysilicon transistors and oxide transistors. Taking the pixel circuit 200 including an oxide transistor and a low-temperature polysilicon transistor as an example, the structure of the display panel in this application will be further described.
  • the display panel also includes a first active layer 10, a first gate insulating layer 11, a first gate metal layer 12, a first interlayer dielectric layer 13, a buffer layer 14, a second active layer 20, The second gate insulating layer 21 , the second gate metal layer 22 and the second interlayer dielectric layer 23 .
  • the first active layer 10 is provided on one side of the base substrate 01 .
  • the material of the first active layer 10 includes polysilicon.
  • the active layer is used to form an active region of a low-temperature polysilicon transistor.
  • the first gate insulating layer 11 is provided on the side of the first active layer 10 away from the base substrate 01 , and the first gate insulating layer 11 covers the first active layer 10 .
  • the first gate metal layer 12 is provided on the side of the first gate insulating layer 11 away from the base substrate 01 .
  • the first gate metal layer 12 includes the gate electrode of the low-temperature polysilicon transistor.
  • the first interlayer dielectric layer 13 is provided on the side of the first gate metal layer 12 away from the base substrate 01 , and the first interlayer dielectric layer 13 covers the surface of the first gate metal layer 12 .
  • the buffer layer 14 is provided on the side of the first interlayer dielectric layer 13 away from the base substrate 01 .
  • the second active layer 20 is provided on the side of the buffer layer 14 away from the base substrate 01 .
  • the material of the second active layer 20 includes an oxide, such as indium gallium zinc oxide (IGZO).
  • the active layer is used to form an oxide.
  • the orthographic projection of the second active layer 20 on the base substrate 01 does not overlap with the orthographic projection of the first active layer 10 on the base substrate 01 .
  • the second gate insulating layer 21 is provided on the side of the second active layer 20 away from the base substrate 01 , and the second gate insulating layer 21 covers the second active layer 20 .
  • the second gate metal layer 22 is provided on the side of the second gate insulating layer 21 away from the base substrate 01 .
  • the second gate metal layer 22 includes the gate electrode of the oxide transistor.
  • the second interlayer dielectric layer 23 is provided on the side of the second gate metal layer 22 away from the base substrate 01 , and the second interlayer dielectric layer 23 covers the second gate metal layer 22 .
  • the first metal layer 30 is provided on a side of the second interlayer dielectric layer 23 away from the base substrate 01 .
  • the first metal layer 30 includes the source and drain electrodes of the low temperature polysilicon transistor and the source and drain electrodes of the oxide transistor.
  • the source and drain of the low-temperature polysilicon transistor are connected to the first active layer 10, and the source and drain of the oxide transistor are connected to the second active layer 20.
  • the transistors in the first shift register unit 111 and the second shift register unit 121 may be fabricated together with the transistors in the pixel circuit 200 .
  • the first active layer 10 may further include an active area of the transistor in the first shift register unit 111 and an active area of the transistor in the second shift register unit 121.
  • the first gate metal layer 12 may further include The gate electrode of the transistor in the first shift register unit 111 and the gate electrode of the transistor in the second shift register unit 121 .
  • the second active layer 20 may also include an active area of the transistor in the first shift register unit 111 and an active area of the transistor in the second shift register unit 121, and the second gate metal
  • the layer 22 may also include the gate electrode of the transistor in the first shift register unit 111 and the gate electrode of the transistor in the second shift register unit 121, which is not limited in this disclosure.
  • the first metal layer 30 may be disposed on a side of the first interlayer dielectric layer 13 away from the base substrate 01 and include a source of a low-temperature polycrystalline silicon transistor. pole and drain.
  • the display panel further includes a planarization layer 31 disposed on a side of the first metal layer 30 away from the base substrate 01 .
  • the planarization layer 31 covers the first metal layer 30 .
  • the second metal layer 40 is provided on the side of the first shift register unit 111 away from the base substrate 01 , that is, on the side of the transistor in the pixel circuit 200 away from the base substrate 01 .
  • the second metal layer 40 can be disposed on the side of the planarization layer 31 away from the base substrate 01 , that is, the planarization layer 31 is disposed between the first metal layer 30 and the second metal layer 40 .
  • the orthographic projection of the planarization layer 31 on the base substrate 01 covers between the orthographic projections of the first sub-shift register unit 1111 and the second sub-shift register unit 1112 on the base substrate 01 Clearance.
  • grooves are provided between the planarization layers 31 corresponding to each circuit included in the peripheral circuit 100, and the grooves will increase the size of the display panel frame to a certain extent.
  • the orthographic projection of the planarization layer 31 on the base substrate 01 may cover the gap between the orthographic projections of the light emission control circuit 120 and the gate driving circuit 110 on the base substrate 01 . That is, the gap between the orthographic projections of the first shift register unit 111 and the second shift register unit 121 on the base substrate 01 is covered.
  • the display panel also includes an initial signal line VIL.
  • the initial signal line VIL is located in the peripheral area 011.
  • the initial signal line VIL is used to transmit an initial signal to the pixel circuit 200.
  • the initial signal line VIL is The signal line VIL is distributed in the second metal layer 40 .
  • the initial signal lines VIL may be distributed at different positions of the second metal layer 40 .
  • the orthographic projection of the initial signal line VIL on the base substrate 01 at least partially overlaps with the orthographic projection of the first shift register unit 111 on the base substrate 01 .
  • the initial signal line VIL is arranged above the first shift register unit 111, which reduces the space occupied by the initial signal line VIL in the direction parallel to the base substrate 01, which helps to further reduce the size of the display panel. border.
  • the gate driving circuit 110 includes a first gate driving circuit 130 and a second gate driving circuit 140
  • the first shift register unit 111 includes a first sub-shift register unit 1111 and a second sub-shift register unit 1111.
  • the shift register unit 1112, the first gate driving circuit 130 includes a first sub-shift register unit 1111, the second gate driving circuit 140 includes a second sub-shift register unit 1112, and the second gate driving circuit 140 is located in the first
  • the gate driving circuit 130 is close to the side of the display area 010 .
  • the first gate driving circuit 130 and the second gate driving circuit 140 may be used to drive different types of transistors.
  • the plurality of signal lines 112 included in each of the first gate driving circuit 130 and the second gate driving circuit 140 may be distributed in at least two metal layers, or only the plurality of signals of the first gate driving circuit 130 may be distributed in at least two metal layers.
  • the lines 112 are distributed in at least two metal layers, or only the plurality of signal lines 112 of the second gate driving circuit 140 are distributed in at least two metal layers. This disclosure does not limit the specifics.
  • the orthographic projection of the initial signal line VIL on the base substrate 01 at least partially overlaps with the orthographic projection of the second sub-shift register unit 1112 on the base substrate 01 .
  • the orthographic projection of the initial signal line VIL on the base substrate 01 may also at least partially overlap with the orthographic projection of the first sub-shift register unit 1111 on the base substrate 01 .
  • the first gate driving circuit 130 and the second gate driving circuit 140 may be used to drive different types of transistors.
  • the first gate driving circuit 130 can be used to drive an N-type transistor
  • the second gate driving circuit 140 can be used to drive a P-type transistor.
  • the pixel circuit 200 includes a P-type transistor and an N-type transistor.
  • the pixel circuit 200 includes a low-temperature polysilicon transistor and an oxide transistor, wherein the low-temperature polysilicon transistor is a P-type transistor and the oxide transistor is an N-type transistor. transistor.
  • the first gate driving circuit 130 provides a high-level voltage signal for driving the oxide transistor
  • the second gate driving circuit 140 provides a low-level voltage signal for driving the low-temperature polysilicon transistor.
  • the initial signal line VIL is provided on the side of the electrical connection line LL away from the base substrate 01 . That is, the electrical connection line LL is located on the side of the second metal layer 40 close to the base substrate 01 .
  • the electrical connection lines LL may be distributed in the first gate metal layer 12, the second gate metal layer 22, or the first metal layer 30, which is not limited in this disclosure.
  • the electrical connection line LL includes the emission control signal line EML and the gate line GAL.
  • the emission control signal line EML and the gate line GAL may be distributed in the first gate metal layer 12 , the second gate metal layer 22 or the first metal layer 30 .
  • the gate line GAL is distributed in the first gate metal layer 12 or the second gate metal layer 22
  • the emission control signal line EML is distributed in the first metal layer 30 .
  • other distribution methods are also possible, and this disclosure does not specifically limit them.
  • the orthographic projection of the initial signal line VIL on the base substrate 01 at least partially overlaps the orthographic projection of the electrical connection line LL on the base substrate 01 , which can also reduce the risk of the initial signal line VIL being parallel to the base substrate.
  • the space occupied in the 01 direction helps to further reduce the frame of the display panel.
  • the orthographic projection of the planarization layer 31 of the present disclosure on the base substrate 01 can also cover the orthographic projection of the first sub-shift register unit 1111 and the second sub-shift register unit 1112 .
  • the gap between the first gate driving circuit 130 and the planarization layer 31 corresponding to the second gate driving circuit 140 is not provided with a groove, thereby helping to reduce the size of the display panel frame.
  • the frame of the display panel can be further reduced through other methods.
  • the display panel also includes a cathode signal line VSS and a cathode connecting line VSS1.
  • the cathode signal line VSS is provided on one side of the substrate substrate 01 and is located in the peripheral area 011 , the cathode signal line VSS is distributed in the first metal layer 30 .
  • the cathode signal line VSS is used to provide a cathode signal to the light-emitting device.
  • One end of the cathode bonding line VSS1 overlaps the cathode signal line VSS, and at least part of the cathode bonding line VSS1 is distributed in the second metal layer 40 .
  • the overlapping of the cathode signal line VSS1 and the cathode signal line VSS provides the possibility to reduce the width of the cathode signal line VSS, and also provides a certain basis for further reducing the frame of the display panel.
  • the cathode signal line VSS is provided on a side of the light emission control circuit 120 away from the display area 010 .
  • the orthographic projection of the cathode strap line VSS1 on the base substrate 01 at least partially overlaps the orthographic projection of the second shift register unit 121 on the base substrate 01 .
  • the display panel further includes an encapsulation layer 50 disposed on the side of the driving circuit and the multi-layer metal layer away from the base substrate 01;
  • the encapsulation layer 50 includes a first inorganic layer 51 and a second inorganic layer 52 arranged sequentially in a direction away from the base substrate 01 .
  • the orthographic projection of the second inorganic layer 52 on the base substrate 01 covers the first inorganic layer 51 on the base substrate 01 . 01, and the area of the orthographic projection of the second inorganic layer 52 on the base substrate 01 is larger than the area of the orthographic projection of the first inorganic layer 51 on the base substrate 01. That is, the distance between the boundary of the second inorganic layer 52 away from the display area 010 and the display area 010 is greater than the distance between the boundary of the first inorganic layer 51 away from the display area 010 and the display area 010 .
  • the first inorganic layer 51 has a first sidewall away from the display area 010 and a first surface away from the base substrate 01 , and the second inorganic layer 52 contacts the first sidewall and at least part of the first surface, thereby connecting the first sidewall to the first surface.
  • An inorganic layer 51 surrounds it.
  • the second inorganic layer 52 wraps the first inorganic layer 51, reducing or eliminating the contact length between the second inorganic layer 52 and the first inorganic layer 51 in the direction parallel to the base substrate 01, thereby This helps to improve the water and moisture-proof effect of the encapsulation layer 50 and further reduces the frame of the display panel.
  • the present disclosure also provides a method for preparing a display panel, including:
  • Step S100 provide a base substrate 01, which includes a display area 010 and a peripheral area 011 located at the periphery of the display area 010;
  • Step S200 forming a driving circuit and a multi-layer metal layer on one side of the base substrate 01.
  • the driving circuit includes a peripheral circuit 100.
  • the driving circuit includes a peripheral circuit 100 and a pixel circuit 200.
  • the peripheral circuit 100 is located in the peripheral area 011, and the pixel circuit 200 is located in the peripheral area 011.
  • the peripheral circuit 100 is connected to the pixel circuit 200 for providing driving signals to the pixel circuit 200;
  • the peripheral circuit 100 includes a plurality of signal lines, and the plurality of signal lines are distributed in at least two metal layers.
  • the preparation method of the display panel further includes:
  • Step S300 forming the first inorganic layer 51 on the side of the driving circuit and the multi-layer metal layer away from the base substrate 01;
  • Step S400 Form the second inorganic layer 52 on the side of the first inorganic layer 51 away from the base substrate 01.
  • the orthographic projection of the second inorganic layer 52 on the base substrate 01 covers the first inorganic layer 51 on the base substrate 01. and the area of the orthographic projection of the second inorganic layer 52 on the base substrate 01 is larger than the area of the orthographic projection of the first inorganic layer 51 on the base substrate 01 .
  • An embodiment of the present disclosure also provides a display device, including a display panel.
  • the display panel can be the display panel of any of the above embodiments.
  • the display device of the present disclosure may be an electronic device such as a mobile phone, a tablet computer, or a television, which will not be listed here.

Abstract

一种显示装置、显示面板及制备方法，属于显示技术领域。显示面板包括衬底基板(01)、设于衬底基板(01)一侧的驱动电路和多层金属层：衬底基板(01)包括显示区(010)和位于显示区(010)外围的外围区(011)；驱动电路包括外围电路(100)和像素电路(200)，外围电路(100)位于外围区(011)，像素电路(200)位于显示区(010)，外围电路(100)与像素电路(200)连接，用于向像素电路(200)提供驱动信号；外围电路(100)包括多条信号线，多条信号线至少分布于两层金属层中。可减小显示面板边框的宽度，满足消费者对窄边框的需求。

Description

显示装置、显示面板及制备方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及制备方法。
背景技术
随着显示技术的不断发展，人们对显示技术的要求逐渐提升。
屏幕边框是指显示区(Active Area，AA区)到屏幕边界的距离。目前，消费者对显示屏幕边框的要求越来越高，期望能拥有更窄边框的显示屏幕。然而，现有技术中显示屏幕的边框仍然较宽，无法满足消费者的需求。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示装置、显示面板及制备方法，可减小显示面板边框的宽度，满足消费者对窄边框的需求。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种显示面板，包括衬底基板、设于衬底基板一侧的驱动电路和多层金属层：
所述衬底基板包括显示区和位于所述显示区外围的外围区；
所述驱动电路包括外围电路和像素电路，所述外围电路位于所述外围区，所述像素电路位于所述显示区，所述外围电路与所述像素电路连接，用于向所述像素电路提供驱动信号；
所述外围电路包括多条信号线，所述多条信号线至少分布于两层所述金属层中。
在本公开的一种示例性实施例中，所述外围电路包括栅极驱动电路和发光控制电路，所述栅极驱动电路和所述发光控制电路均包括所述多 条信号线；
所述栅极驱动电路的所述多条信号线分布于至少两层所述金属层中；
或/和所述发光控制电路的所述多条信号线至少分布于两层所述金属层中。
在本公开的一种示例性实施例中，所述多层金属层包括沿远离衬底基板方向依次设置的第一金属层和第二金属层；
所述多条信号线中，部分所述信号线分布于所述第一金属层中，部分所述信号线分布于所述第二金属层中；
所述多条信号线包括时钟信号线和/或电压信号线。
在本公开的一种示例性实施例中，所述外围电路包括栅极驱动电路，所述栅极驱动电路包括多个级联的第一移位寄存器单元和所述多条信号线，所述第一移位寄存器单元包括晶体管；
所述时钟信号线用于向所述第一移位寄存器单元传输时钟信号，所述电压信号线用于向所述第一移位寄存器单元传输电压信号；
所述第一金属层包括所述第一移位寄存器单元中晶体管的源极和漏极；
所述第二金属层设于所述第一移位寄存器单元远离所述衬底基板的一侧；
所述栅极驱动电路中分布于所述第二金属层中的信号线在所述衬底基板上的正投影与所述第一移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述外围电路包括发光控制电路，所述发光控制电路包括多个级联的第二移位寄存器单元和所述多条信号线，所述第二移位寄存器单元包括晶体管；
所述时钟信号线用于向所述第二移位寄存器单元传输时钟信号，所述电压信号线用于向所述第二移位寄存器单元传输电压信号；
所述第一金属层包括所述第二移位寄存器单元中晶体管的源极和漏极；
所述第二金属层设于所述第二移位寄存器单元远离所述衬底基板的一侧；
所述发光控制电路中分布于所述第二金属层中的信号线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述显示面板还包括初始信号线，所述初始信号线位于所述外围区，所述初始信号线用于向所述像素电路传输初始信号，所述初始信号线分布于所述第二金属层中。
在本公开的一种示例性实施例中，所述初始信号线在所述衬底基板上的正投影与所述第一移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述显示面板还包括电连接线，所述外围电路通过电连接线与所述像素电路连接；
所述初始信号线设于所述电连接线远离所述衬底基板的一侧；
所述初始信号线在所述衬底基板上的正投影与所述电连接线在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述栅极驱动电路包括第一栅极驱动电路和第二栅极驱动电路，所述第一移位寄存器单元包括第一子移位寄存器单元和第二子移位寄存器单元，所述第一栅极驱动电路包括所述第一子移位寄存器单元，所述第二栅极驱动电路包括第二子移位寄存器单元，所述第二栅极驱动电路位于所述第一栅极驱动电路靠近所述显示区的一侧；
所述初始信号线在所述衬底基板上的正投影与所述第二子移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述像素电路包括低温多晶硅晶体管和氧化物晶体管；
所述第一栅极驱动电路用于驱动所述氧化物晶体管，所述第二栅极驱动电路用于驱动所述低温多晶硅晶体管。
在本公开的一种示例性实施例中，所述显示面板还包括：
阴极信号线，设于所述衬底基板的一侧并位于所述外围区，所述阴极信号线分布于所述第一金属层中；
阴极搭接线，所述阴极搭接线的一端搭接于所述阴极信号线，且所 述阴极搭接线的至少部分分布于所述第二金属层中。
在本公开的一种示例性实施例中，所述阴极信号线设于所述发光控制电路远离所述显示区的一侧；
所述阴极搭接线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
在本公开的一种示例性实施例中，所述显示面板还包括：
平坦化层，设于所述第一金属层和所述第二金属层之间，所述平坦化层在所述衬底基板上的正投影覆盖所述第一子移位寄存器单元和所述第二子移位寄存器单元在所述衬底基板上的正投影之间的间隙。
在本公开的一种示例性实施例中，所述显示面板还包括：
封装层，设于所述驱动电路和所述多层金属层远离所述衬底基板的一侧；
所述封装层包括沿远离衬底基板方向依次设置的第一无机层和第二无机层，所述第二无机层在所述衬底基板上的正投影覆盖所述第一无机层在所述衬底基板上的正投影，且所述第二无机层在所述衬底基板上的正投影的面积大于所述第一无机层在所述衬底基板上的正投影的面积。
在本公开的一种示例性实施例中，所述第一无机层具有远离所述衬底基板的第一表面和远离所述显示区的第一侧壁；
所述第二无机层接触所述第一侧壁和至少部分所述第一表面。
根据本公开第二个方面，提供一种显示面板的制备方法，包括：
提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的外围区；
于所述衬底基板的一侧形成驱动电路和多层金属层，所述驱动电路包括外围电路，所述驱动电路包括外围电路和像素电路，所述外围电路位于所述外围区，所述像素电路位于所述显示区，所述外围电路与所述像素电路连接，用于向所述像素电路提供驱动信号；所述外围电路包括多条信号线，所述多条信号线至少分布于两层所述金属层中。
在本公开的一种示例性实施例中，所述制备方法还包括：
于所述驱动电路和所述多层金属层远离所述衬底基板的一侧形成第一无机层；
于所述第一无机层远离所述衬底基板的一侧形成第二无机层，所述第二无机层在所述衬底基板上的正投影覆盖所述第一无机层在所述衬底基板上的正投影，且所述第二无机层在所述衬底基板上的正投影的面积大于所述第一无机层在所述衬底基板上的正投影的面积。
根据本公开第二个方面，提供一种显示装置，包括如第一方面所述的显示面板。
本公开提供的显示面板，将外围电路中的多条信号线分布于至少两层金属层中，以减少外围电路在平行于衬底基板方向上的占用空间，进而有助于减少外围电路在外围区所占空间的大小，减小外围区的尺寸，即减小显示面板边框的宽度，满足消费者对窄边框的需求。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开示例性实施例中外围电路在显示面板位置的结构示意图；
图2是本公开示例性实施例中显示面板栅极驱动电路结构示意图；
图3是本公开示例性实施例中显示面板发光控制电路结构示意图；
图4是本公开示例性实施例中外围电路多条信号线分布平面示意图；
图5是本公开又一示例性实施例中外围电路多条信号线分布平面示意图；
图6是本公开示例性实施例中外围电路多条信号线分布截面示意图；
图7是本公开又一示例性实施例中外围电路多条信号线分布截面示意图；
图8是本公开示例性实施例中显示面板显示区截面示意图。
图中主要元件附图标记说明如下：
01-衬底基板；010-显示区；011-外围区；100-外围电路；110-栅极驱动电路；111-第一移位寄存器单元；1111-第一子移位寄存器单元；1112-第二子移位寄存器单元；112-信号线；130-第一栅极驱动电路；140-第二栅极驱动电路；120-发光控制电路；121-第二移位寄存器单元；122-信号 线；200-像素电路；10-第一有源层；11-第一栅绝缘层；12-第一栅金属层；13-第一层间介质层；14-缓冲层；20-第二有源层；21-第二栅绝缘层；22-第二栅金属层；23-第二层间介质层；30-第一金属层；31-平坦化层；40-第二金属层；50-封装层；51-第一无机层；52-第二无机层；60-缓冲层；VSS-阴极信号线；VSS1-阴极搭接线；VIL-初始信号线；LL-电连接线；GAL-栅线；EML-发光控制信号线。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，低温多晶硅晶体管的有源层采用低温多晶硅(Low  Temperature Poly-Silicon，LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)，如氧化铟镓锌、氧化铟镓锡等。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)显示面板，可以利用两者的优势，实现低频驱动，可以降低功耗，提高显示质量。
LTPO显示面板的像素电路包含低温多晶硅晶体管和氧化物薄膜晶体管，栅极驱动电路(Gate on array，GOA)需同时提供高电平栅极驱动信号和低电平栅极驱动信号，其包含晶体管数量较多，占用空间大，因此，LTPO显示面板的边框较宽，无法满足消费者对窄边框的需求。
如图1、图4至图7所示，本公开提供一种显示面板，包括衬底基板01、设于衬底基板01一侧的驱动电路和多层金属层。衬底基板01包括显示区010和位于显示区010外围的外围区011；驱动电路包括外围电路100和像素电路200，外围电路100位于外围区011，像素电路200位于显示区010，外围电路100与像素电路200连接，用于向像素电路200提供驱动信号，外围电路100包括多条信号线，多条信号线分布于至少两层金属层中。
本公开提供的显示面板，将外围电路100中的多条信号线分布于至少两层金属层中，以减少外围电路100在平行于衬底基板01方向上的占用空间，进而有助于减少外围电路100在外围区011所占空间的大小，减小外围区011的尺寸，即减小显示面板边框的宽度，满足消费者对窄边框的需求。
下面结合附图对本公开实施方式提供的显示面板的各部件进行详细说明：
本公开提供一种显示面板，该显示面板可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，如AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极管)显示面板，也可以是量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板、微发光二极管(Micro Light Emitting Diodes， Micro LED)显示面板等，本公开对此不做具体限定。
如图1所示，显示面板包括衬底基板01、设于衬底基板01一侧的驱动电路和多层金属层。
衬底基板01包括显示区010和位于显示区010外围的外围区011，显示区010可用于显示图像。衬底基板01可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板01的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板01的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。衬底基板01也可以为柔性衬底基板01，举例而言，在本公开的一种实施方式中，衬底基板01的材料可以为聚酰亚胺(polyimide，PI)。衬底基板01还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板01可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
驱动电路设于衬底基板01的一侧，驱动电路包括外围电路100和像素电路200，外围电路100位于外围区011，像素电路200位于显示区010，像素电路200可用于驱动OLED显示面板的发光器件发光。像素电路200可以是7T1C、7T2C、6T1C或6T2C等像素电路200，在此不对其结构做特殊限定。其中，nTmC表示一个像素电路200包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。像素电路200可阵列排列于显示区010，形成多行多列的矩阵结构。
外围电路100包括栅极驱动电路110和发光控制电路120。显示面板还包括电连接线LL，外围电路100通过电连接线LL与像素电路200连接。举例而言，电连接线LL可包括发光控制信号线EML和栅线GAL。栅极驱动电路110通过栅线GAL与像素电路200连接，发光控制电路 120通过发光控制信号线EML与像素电路200连接。
如图4至图7所示，栅极驱动电路110和发光控制电路120均包括多条信号线。栅极驱动电路110和/或发光控制电路120的多条信号线可分布于至少两层金属层中。举例而言，在本公开一些实施例中，栅极驱动电路110的多条信号线112分布于至少两层金属层中，在又一些实施例中，发光控制电路120的多条信号线122分布于至少两层金属层中，在又一些实施例中，栅极驱动电路110的多条信号线112和发光控制电路120的多条信号线122均分布于至少两层金属层中。
如图1和图2所示，在本公开一些实施例中，栅极驱动电路110可设置于显示区010的单侧，从单侧逐行依次通过各栅线GAL向像素电路200提供栅极驱动信号，即采用单侧驱动。当然，也可以将栅极驱动电路110设置于显示区010的两侧，通过两侧的栅极驱动电路110同时从双侧逐行依次向各像素电路200提供栅极驱动信号，即采用双侧驱动；当然两侧的栅极驱动电路110也可交替从两侧逐行依次向各像素电路200提供栅极驱动信号，即采用交叉驱动。
显示面板包括多层金属层，多层金属层设于衬底基板01的一侧。具体地，显示面板可包括两层、三层或更多层金属层。外围电路100，如栅极驱动电路110和发光控制电路120，包括多条信号线，多条信号线分布于至少两层金属层中。如，栅极驱动电路110和发光控制电路120的多条信号线可分布于两层、三层或更多层金属层中。
如图6至图8所示，在本公开一些实施例中，多层金属层包括沿远离衬底基板01方向依次设置的第一金属层30和第二金属层40。多条信号线中部分信号线分布于第一金属层30中，部分信号线分布于第二金属层40中。多条信号线可以包括时钟信号线和/或电压信号线，时钟信号线用于传输时钟信号，电压信号线用于传输电压信号。举例而言，时钟信号线分布于第一金属层30中，电压信号线分布于第二金属层40中；或时钟信号线中的数条时钟信号线分布于第一金属层30中，其余时钟信号线分布于第二金属层40中；或电压信号线中的数条电压信号线分布于第一金属层30中，其余电压信号线分布于第二金属层40中，具体本公开不做限定。
本公开将外围电路100，如栅极驱动电路110和/或发光控制电路120中的多条信号线，如时钟信号线和电压信号线，分布于至少两层金属层中，即将多条信号线层叠设置，该设计方式有助于减少时钟信号线和电压信号线在平行于衬底基板01方向上的占用空间，为实现窄边框设计提供了基础。
如图2、图4和图5所示，在本公开一些实施例中，栅极驱动电路110还包括多个级联的第一移位寄存器单元111，多个级联的第一移位寄存器单元111分别一一对应连接至各个栅线GAL，以向对应像素电路200提供栅极驱动信号。
第一移位寄存器单元111独立设置栅极驱动信号输出端和级联信号输出端，通过栅极驱动信号输出端向与其连接的栅线GAL输出栅极驱动信号，通过级联信号输出端输出级联信号。举例而言，每相邻两个第一移位寄存器单元111中，下一级的第一移位寄存器单元111的信号输入端与上一级第一移位寄存器单元111的级联信号输出端连接。
栅极驱动电路110中的电压信号线用于向第一移位寄存器单元111传输电压。电压信号线的数量可以为多条。如，栅极驱动电路110可包括N条电压信号线，分别为第一电压信号线、第二电压信号线、第三电压信号线......第N电压信号线，不同电压信号线传输不同的电压信号。单个第一移位寄存器单元111可连接一条或多条电压信号线，具体本公开不做限定。时钟信号线用于向第一移位寄存器单元111传输时钟信号。时钟信号线的数量可以为多条。如，栅极驱动电路110可包括N条时钟信号线，分别为第一时钟信号线、第二时钟信号线、第三时钟信号线......第N时钟信号线，不同时钟信号线传输不同的时钟信号，单个第一移位寄存器单元111可连接一条或多条时钟信号线，具体本公开不做限定。第一移位寄存器单元111根据时钟信号线传输的时钟信号以及其他信号线传输的其他信号，如电压信号，向栅线GAL输出栅极驱动信号，进而向对应像素电路200提供栅极驱动信号。
如图6至图8所示，在本公开一些实施例中，第一移位寄存器单元111包括晶体管，第一金属层30包括第一移位寄存器单元111中晶体管的源极和漏极，第二金属层40设于第一移位寄存器单元111远离衬底基 板01的一侧。栅极驱动电路110中分布于第二金属层40中的信号线112在衬底基板01上的正投影与第一移位寄存器单元111在衬底基板01上的正投影至少部分重叠。即，分布于第二金属层40中的信号线112位于第一移位寄存器单元111的上方。举例而言，当时钟信号线分布于第二金属层40时，时钟信号线在衬底基板01上的正投影与第一移位寄存器单元111在衬底基板01上的正投影至少部分重叠；当电压信号线分布于第二金属层40时，电压信号线在衬底基板01上的正投影与第一移位寄存器单元111在衬底基板01上的正投影至少部分重叠。
如图3、图4和图5所示，在本公开一些实施例中，发光控制电路120还包括多个级联的第二移位寄存器单元121，多个级联的第二移位寄存器单元121的信号输出端分别一一对应地连接至各个发光控制信号线EML，以向对应像素电路200提供发光控制信号。多个级联的第二移位寄存器单元121中，除最后一级第二移位寄存器单元121外，其余每一级的第二移位寄存器单元121的信号输出端分别与其相邻的下一级的第二移位寄存器单元121的信号输入端连接。
发光控制电路120中的电压信号线用于向第二移位寄存器单元121传输电压，时钟信号线用于向第二移位寄存器单元121传输时钟信号。同上，发光控制电路120中的电压信号线和时钟信号线的数量也可以为多条，不同时钟信号线可传输不同的时钟信号，不同的电压信号线可传输不同的电压信号。第二移位寄存器单元121根据时钟信号线传输的时钟信号以及其他信号线传输的其他信号，如电压信号，向发光控制信号线EML输出发光控制信号，进而向对应像素电路200提供发光控制信号。
如图6至图8所示，在本公开一些实施例中，第二移位寄存器单元121包括晶体管，第一金属层30包括第二移位寄存器单元121中晶体管的源极和漏极，第二金属层40设于第二移位寄存器单元121远离衬底基板01的一侧。发光控制电路120中分布于第二金属层40中的信号线122在衬底基板01上的正投影与第二移位寄存器单元121在衬底基板01上的正投影至少部分重叠。
进一步地，像素电路200也包含多个晶体管，第一金属层30也包括像素电路200中晶体管的源极和漏极。
驱动电路中各个电路，如栅极驱动电路110、发光控制电路120和像素电路200，所包含的晶体管形成于衬底基板01的一侧。
在本公开一些实施例中，像素电路200所包含的晶体管可以低温多晶硅晶体管、或氧化物晶体管，或同时包含低温多晶硅晶体管和氧化物晶体管。以像素电路200包括氧化物晶体管和低温多晶硅晶体管为例，进一步说明本申请中显示面板的结构。
如图8所示，显示面板还包括第一有源层10、第一栅绝缘层11、第一栅金属层12、第一层间介质层13、缓冲层14、第二有源层20、第二栅绝缘层21、第二栅金属层22和第二层间介质层23。
第一有源层10设于衬底基板01的一侧，第一有源层10的材料包括多晶硅，该有源层用于形成低温多晶硅晶体管的有源区。第一栅绝缘层11设于第一有源层10远离衬底基板01的一侧，第一栅绝缘层11覆盖第一有源层10。第一栅金属层12设于第一栅绝缘层11远离衬底基板01的一侧，第一栅金属层12包括低温多晶硅晶体管的栅极。第一层间介质层13设于第一栅金属层12远离衬底基板01的一侧，第一层间介质层13覆盖第一栅金属层12的表面。缓冲层14设于第一层间介质层13远离衬底基板01的一侧。
第二有源层20设于缓冲层14远离衬底基板01的一侧，第二有源层20的材料包含氧化物，如氧化铟镓锌(IGZO)，该有源层用于形成氧化物晶体管的有源区。第二有源层20在衬底基板01上的正投影与第一有源层10在衬底基板01上的正投影不重叠。第二栅绝缘层21设于第二有源层20远离衬底基板01的一侧，第二栅绝缘层21覆盖第二有源层20。第二栅金属层22设于第二栅绝缘层21远离衬底基板01的一侧，第二栅金属层22包括氧化物晶体管的栅极。第二层间介质层23设于第二栅金属层22远离衬底基板01的一侧，第二层间介质层23覆盖第二栅金属层22。
在本公开一些实施例中，第一金属层30设于第二层间介质层23远离衬底基板01的一侧。第一金属层30包括低温多晶硅晶体管的源极和漏极，以及氧化物晶体管的源极和漏极。其中，低温多晶硅晶体管的源极和漏极连接于第一有源层10，氧化物晶体管的源极和漏极连接于第二 有源层20。
如图6至图8所示，第一移位寄存器单元111和第二移位寄存器单元121中的晶体管可同像素电路200中的晶体管一起制作而成。举例而言，第一有源层10还可以包括第一移位寄存器单元111中晶体管的有源区和第二移位寄存器单元121中晶体管的有源区，第一栅金属层12还可以包括第一移位寄存器单元111中晶体管的栅极和第二移位寄存器单元121中晶体管的栅极。当然，在一些实施例中，第二有源层20也还可以包括第一移位寄存器单元111中晶体管的有源区和第二移位寄存器单元121中晶体管的有源区，第二栅金属层22也还可以包括第一移位寄存器单元111中晶体管的栅极和第二移位寄存器单元121中晶体管的栅极，具体本公开不做限定。
在此需说明的是，当像素电路200不包含氧化物晶体管时，第一金属层30可设于第一层间介质层13远离衬底基板01的一侧，包含低温多晶体硅晶体管的源极和漏极。
在本公开一些实施例中，显示面板还包括平坦化层31，设于第一金属层30远离衬底基板01的一侧。平坦化层31覆盖第一金属层30。第二金属层40设于第一移位寄存器单元111远离衬底基板01的一侧，也即设于像素电路200中晶体管远离衬底基板01的一侧。具体地，第二金属层40可设于平坦化层31远离衬底基板01的一侧，即平坦化层31设于第一金属层30和第二金属层40之间。
在本公开一些实施例中，平坦化层31在衬底基板01上的正投影覆盖第一子移位寄存器单元1111和第二子移位寄存器单元1112在衬底基板01上的正投影之间的间隙。相关技术中，外围电路100中所包含的各个电路对应的平坦化层31之间会设置凹槽，该凹槽在一定程度上会增大显示面板边框的尺寸。
平坦化层31在衬底基板01上的正投影可覆盖发光控制电路120和栅极驱动电路110在衬底基板01上的正投影之间的间隙。即覆盖第一移位寄存器单元111和第二移位寄存器单元121在衬底基板01上的正投影之间的间隙。
如图4至图7所示，在本公开一些实施例中，显示面板还包括初始 信号线VIL，初始信号线VIL位于外围区011，初始信号线VIL用于向像素电路200传输初始信号，初始信号线VIL分布于第二金属层40中。
本公开中，初始信号线VIL可分布于第二金属层40的不同位置处。如图4和图6所示，在本公开一些实施例中，初始信号线VIL在衬底基板01上的正投影与第一移位寄存器单元111在衬底基板01上的正投影至少部分重叠。在该实施例中，将初始信号线VIL设于第一移位寄存器单元111的上方，减少了初始信号线VIL在平行于衬底基板01方向上的占用空间，有助于进一步减小显示面板的边框。
在本公开一些实施例中，栅极驱动电路110包括第一栅极驱动电路130和第二栅极驱动电路140，第一移位寄存器单元111包括第一子移位寄存器单元1111和第二子移位寄存器单元1112，第一栅极驱动电路130包括第一子移位寄存器单元1111，第二栅极驱动电路140包括第二子移位寄存器单元1112，第二栅极驱动电路140位于第一栅极驱动电路130靠近显示区010的一侧。第一栅极驱动电路130和第二栅极驱动电路140可用于驱动不同类型的晶体管。
第一栅极驱动电路130和第二栅极驱动电路140中各自所包含的多条信号线112可均至少分布于两层金属层中，也可只第一栅极驱动电路130的多条信号线112分布于至少两层金属层中，或只第二栅极驱动电路140的多条信号线112至少分布于两层金属层中，具体本公开不做限定。
在本公开一些实施例中，初始信号线VIL在衬底基板01上的正投影与第二子移位寄存器单元1112在衬底基板01上的正投影至少部分重叠。当然，初始信号线VIL在衬底基板01上的正投影也可与第一子移位寄存器单元1111在衬底基板01上的正投影至少部分重叠。
第一栅极驱动电路130和第二栅极驱动电路140可用于驱动不同类型的晶体管。举例而言，第一栅极驱动电路130可用于驱动N型晶体管，第二栅极驱动电路140可用于驱动P型晶体管。
在本公开一些实施例中，像素电路200包括P型晶体管和N型晶体管，如像素电路200中包括低温多晶硅晶体管和氧化物晶体管，其中，低温多晶硅晶体管为P型晶体管，氧化物晶体管为N型晶体管。第一栅 极驱动电路130提供高电平电压信号，用于驱动氧化物晶体管，第二栅极驱动电路140提供低电平电压信号，用于驱动低温多晶硅晶体管。
如图5和图7所示，在本公开另一些实施例中，初始信号线VIL设于电连接线LL远离衬底基板01的一侧。即，电连接线LL位于第二金属层40靠近衬底基板01的一侧。具体在一些实施例中，电连接线LL可分布于第一栅金属层12中、第二栅金属层22中或第一金属层30中，具体本公开不做限定。如上，电连接线LL包括发光控制信号线EML和栅线GAL，发光控制信号线EML和栅线GAL可分布于第一栅金属层12、第二栅金属层22或第一金属层30中。举例而言，栅线GAL分布于第一栅金属层12或第二栅金属层22中，发光控制信号线EML分布于第一金属层30中。当然，也可以有其他分布方式，具体本公开不做限定。
在该实施例中，初始信号线VIL在衬底基板01上的正投影与电连接线LL在衬底基板01上的正投影至少部分重叠，同样可减少初始信号线VIL在平行于衬底基板01方向上的占用空间，有助于进一步减小显示面板的边框。
此外，如图6和图7所示，本公开平坦化层31在衬底基板01上的正投影也可覆盖第一子移位寄存器单元1111和第二子移位寄存器单元1112的正投影之间的间隙，即第一栅极驱动电路130和第二栅极驱动电路140对应的平坦化层31之间不设置有凹槽，从而有助于减小显示面板边框的尺寸。
本公开中，还可通过其他方式进一步减少显示面板的边框。
如图6和图7所示，在本公开一些实施例中，显示面板还包括阴极信号线VSS和阴极搭接线VSS1，阴极信号线VSS设于衬底基板01的一侧并位于外围区011，阴极信号线VSS分布于第一金属层30中。阴极信号线VSS用于向发光器件提供阴极信号。阴极搭接线VSS1的一端搭接于阴极信号线VSS，阴极搭接线VSS1的至少部分分布于第二金属层40中。
在该实施例中，通过阴极搭接线VSS1与阴极信号线VSS搭接，为减少阴极信号线VSS的宽度提供可能，也为进一步减小显示面板的边框提供了一定的基础。
在本公开一些实施例中，阴极信号线VSS设于发光控制电路120远离显示区010的一侧。阴极搭接线VSS1在衬底基板01上的正投影与第二移位寄存器单元121在衬底基板01上的正投影至少部分重叠。
在本公开一些实施例中，显示面板还包括封装层50，设于驱动电路和多层金属层远离衬底基板01的一侧；
封装层50包括沿远离衬底基板01方向依次设置的第一无机层51和第二无机层52，第二无机层52在衬底基板01上的正投影覆盖第一无机层51在衬底基板01上的正投影，且第二无机层52在衬底基板01上的正投影的面积大于第一无机层51在衬底基板01上的正投影的面积。也即，第二无机层52的远离显示区010的边界与显示区010之间的距离大于第一无机层51远离显示区010的边界与显示区010之间的距离。具体地，第一无机层51具有远离显示区010的第一侧壁和远离衬底基板01的第一表面，第二无机层52接触该第一侧壁和至少部分第一表面，从而将第一无机层51予以包裹。在该实施例中，第二无机层52将第一无机层51予以包裹，减小或消除了第二无机层52和第一无机层51在平行于衬底基板01方向上的接触长度，从而有助于提升封装层50的阻水防潮效果，并有助于进一步减小显示面板的边框。
如图1、图4至图7所示，本公开还提供一种显示面板的制备方法，包括：
步骤S100，提供衬底基板01，衬底基板01包括显示区010和位于显示区010外围的外围区011；
步骤S200，于衬底基板01的一侧形成驱动电路和多层金属层，驱动电路包括外围电路100，驱动电路包括外围电路100和像素电路200，外围电路100位于外围区011，像素电路200位于显示区010，外围电路100与像素电路200连接，用于向像素电路200提供驱动信号；外围电路100包括多条信号线，多条信号线至少分布于两层金属层中。
如图6和图7所示，在本公开一些实施例中，显示面板的制备方法还包括：
步骤S300，于驱动电路和多层金属层远离衬底基板01的一侧形成第一无机层51；
步骤S400，于第一无机层51远离衬底基板01的一侧形成第二无机层52，第二无机层52在衬底基板01上的正投影覆盖第一无机层51在衬底基板01上的正投影，且第二无机层52在衬底基板01上的正投影的面积大于第一无机层51在衬底基板01上的正投影的面积。
本公开实施方式还提供一种显示装置，包括显示面板，该显示面板可为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、电视等电子设备，在此不再一一列举。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (18)

  1. 一种显示面板，包括衬底基板、设于衬底基板一侧的驱动电路和多层金属层：
    所述衬底基板包括显示区和位于所述显示区外围的外围区；
    所述驱动电路包括外围电路和像素电路，所述外围电路位于所述外围区，所述像素电路位于所述显示区，所述外围电路与所述像素电路连接，用于向所述像素电路提供驱动信号；
    所述外围电路包括多条信号线，所述多条信号线至少分布于两层所述金属层中。
  2. 根据权利要求1所述的显示面板，其中，所述外围电路包括栅极驱动电路和发光控制电路，所述栅极驱动电路和所述发光控制电路均包括所述多条信号线；
    所述栅极驱动电路的所述多条信号线分布于至少两层所述金属层中；
    或/和所述发光控制电路的所述多条信号线至少分布于两层所述金属层中。
  3. 根据权利要求2所述的显示面板，其中，所述多层金属层包括沿远离衬底基板方向依次设置的第一金属层和第二金属层；
    所述多条信号线中，部分所述信号线分布于所述第一金属层中，部分所述信号线分布于所述第二金属层中；
    所述多条信号线包括时钟信号线和/或电压信号线。
  4. 根据权利要求3所述的显示面板，其中，所述外围电路包括栅极驱动电路，所述栅极驱动电路包括多个级联的第一移位寄存器单元和所述多条信号线，所述第一移位寄存器单元包括晶体管；
    所述时钟信号线用于向所述第一移位寄存器单元传输时钟信号，所述电压信号线用于向所述第一移位寄存器单元传输电压信号；
    所述第一金属层包括所述第一移位寄存器单元中晶体管的源极和漏极；
    所述第二金属层设于所述第一移位寄存器单元远离所述衬底基板的一侧；
    所述栅极驱动电路中分布于所述第二金属层中的信号线在所述衬底 基板上的正投影与所述第一移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
  5. 根据权利要求3所述的显示面板，其中，所述外围电路包括发光控制电路，所述发光控制电路包括多个级联的第二移位寄存器单元和所述多条信号线，所述第二移位寄存器单元包括晶体管；
    所述时钟信号线用于向所述第二移位寄存器单元传输时钟信号，所述电压信号线用于向所述第二移位寄存器单元传输电压信号；
    所述第一金属层包括所述第二移位寄存器单元中晶体管的源极和漏极；
    所述第二金属层设于所述第二移位寄存器单元远离所述衬底基板的一侧；
    所述发光控制电路中分布于所述第二金属层中的信号线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求4所述的显示面板，其中，所述显示面板还包括初始信号线，所述初始信号线位于所述外围区，所述初始信号线用于向所述像素电路传输初始信号，所述初始信号线分布于所述第二金属层中。
  7. 根据权利要求6所述的显示面板，其中，所述初始信号线在所述衬底基板上的正投影与所述第一移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
  8. 根据权利要求6所述的显示面板，其中，所述显示面板还包括电连接线，所述外围电路通过电连接线与所述像素电路连接；
    所述初始信号线设于所述电连接线远离所述衬底基板的一侧；
    所述初始信号线在所述衬底基板上的正投影与所述电连接线在所述衬底基板上的正投影至少部分重叠。
  9. 根据权利要求7所述的显示面板，其中，所述栅极驱动电路包括第一栅极驱动电路和第二栅极驱动电路，所述第一移位寄存器单元包括第一子移位寄存器单元和第二子移位寄存器单元，所述第一栅极驱动电路包括所述第一子移位寄存器单元，所述第二栅极驱动电路包括第二子移位寄存器单元，所述第二栅极驱动电路位于所述第一栅极驱动电路靠 近所述显示区的一侧；
    所述初始信号线在所述衬底基板上的正投影与所述第二子移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
  10. 根据权利要求9所述的显示面板，其中，所述像素电路包括低温多晶硅晶体管和氧化物晶体管；
    所述第一栅极驱动电路用于驱动所述氧化物晶体管，所述第二栅极驱动电路用于驱动所述低温多晶硅晶体管。
  11. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    阴极信号线，设于所述衬底基板的一侧并位于所述外围区，所述阴极信号线分布于所述第一金属层中；
    阴极搭接线，所述阴极搭接线的一端搭接于所述阴极信号线，且所述阴极搭接线的至少部分分布于所述第二金属层中。
  12. 根据权利要求11所述的显示面板，其中，所述阴极信号线设于所述发光控制电路远离所述显示区的一侧；
    所述阴极搭接线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影至少部分重叠。
  13. 根据权利要求9所述的显示面板，其中，所述显示面板还包括：
    平坦化层，设于所述第一金属层和所述第二金属层之间，所述平坦化层在所述衬底基板上的正投影覆盖所述第一子移位寄存器单元和所述第二子移位寄存器单元在所述衬底基板上的正投影之间的间隙。
  14. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    封装层，设于所述驱动电路和所述多层金属层远离所述衬底基板的一侧；
    所述封装层包括沿远离衬底基板方向依次设置的第一无机层和第二无机层，所述第二无机层在所述衬底基板上的正投影覆盖所述第一无机层在所述衬底基板上的正投影，且所述第二无机层在所述衬底基板上的正投影的面积大于所述第一无机层在所述衬底基板上的正投影的面积。
  15. 根据权利要求14所述的显示面板，其中，所述第一无机层具有远离所述衬底基板的第一表面和远离所述显示区的第一侧壁；
    所述第二无机层接触所述第一侧壁和至少部分所述第一表面。
  16. 一种显示面板的制备方法，包括：
    提供衬底基板，所述衬底基板包括显示区和位于所述显示区外围的外围区；
    于所述衬底基板的一侧形成驱动电路和多层金属层，所述驱动电路包括外围电路，所述驱动电路包括外围电路和像素电路，所述外围电路位于所述外围区，所述像素电路位于所述显示区，所述外围电路与所述像素电路连接，用于向所述像素电路提供驱动信号；所述外围电路包括多条信号线，所述多条信号线至少分布于两层所述金属层中。
  17. 根据权利要求16所述的显示面板的制备方法，其中，所述制备方法还包括：
    于所述驱动电路和所述多层金属层远离所述衬底基板的一侧形成第一无机层；
    于所述第一无机层远离所述衬底基板的一侧形成第二无机层，所述第二无机层在所述衬底基板上的正投影覆盖所述第一无机层在所述衬底基板上的正投影，且所述第二无机层在所述衬底基板上的正投影的面积大于所述第一无机层在所述衬底基板上的正投影的面积。
  18. 一种显示装置，包括如权利要求1-15任一项所述的显示面板。
PCT/CN2022/079772 2022-03-08 2022-03-08 显示装置、显示面板及制备方法 WO2023168602A1 (zh)

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