WO2022061524A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2022061524A1
WO2022061524A1 PCT/CN2020/116858 CN2020116858W WO2022061524A1 WO 2022061524 A1 WO2022061524 A1 WO 2022061524A1 CN 2020116858 W CN2020116858 W CN 2020116858W WO 2022061524 A1 WO2022061524 A1 WO 2022061524A1
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Prior art keywords
layer
gate
base substrate
active layer
film transistor
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PCT/CN2020/116858
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English (en)
French (fr)
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王本莲
黄耀
龙跃
承天一
黄炜赟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202080002054.5A priority Critical patent/CN114788000A/zh
Priority to PCT/CN2020/116858 priority patent/WO2022061524A1/zh
Priority to US17/418,085 priority patent/US20220336555A1/en
Publication of WO2022061524A1 publication Critical patent/WO2022061524A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • LTPO Low Temperature Polycrystalline Oxide
  • LTPS TFTs low temperature Polysilicon thin film transistors
  • Oxide TFTs metal oxide thin film transistors
  • Metal oxide thin film transistors have The lower leakage current, combining the advantages of these two transistors, facilitates the development of high-resolution, low-power, and high-quality display products.
  • an embodiment of the present disclosure provides a display substrate, including:
  • the low temperature polysilicon thin film transistor is located on the base substrate; the low temperature polysilicon thin film transistor includes a first active layer and a first gate that are stacked on the base substrate;
  • an oxide thin film transistor which is located on the base substrate, and the oxide thin film transistor includes a second active layer on the side of the layer where the first gate electrode is located away from the base substrate;
  • first gate insulating layer located between the first active layer and the layer where the first gate is located, the first gate insulating layer comprising a hydrogen-containing insulating layer;
  • the first interlayer insulating layer is located between the layer where the first gate electrode is located and the second active layer, and the first interlayer insulating layer includes a hydrogen blocking material layer.
  • the first gate insulating layer includes: a silicon oxide layer, and a nitrided nitride layer located between the silicon oxide layer and the layer where the first gate electrode is located silicon layer.
  • the first interlayer insulating layer includes a silicon oxide layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a metal portion provided in the same layer as the first gate electrode;
  • the overlapping area of the orthographic projection of the metal portion on the base substrate and the orthographic projection of the first active layer on the base substrate is S1
  • the metal portion is on the base substrate
  • the overlapping area of the orthographic projection of the second active layer on the base substrate and the orthographic projection of the second active layer on the base substrate is S2, where S2 is greater than S1.
  • the first interlayer insulating layer includes: a first silicon oxide layer and a second silicon dioxide layer which are arranged in layers.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, it further comprises: a metal portion located between the first silicon oxide layer and the second silicon oxide layer;
  • the overlapping area of the orthographic projection of the metal portion on the base substrate and the orthographic projection of the first active layer on the base substrate is S1
  • the metal portion is on the base substrate
  • the overlapping area of the orthographic projection of the second active layer on the base substrate and the orthographic projection of the second active layer on the base substrate is S2, where S2 is greater than S1.
  • the metal portion is the second gate of the oxide thin film transistor.
  • the metal portion is a light-shielding layer
  • the orthographic projection of the light-shielding layer on the base substrate covers the second active layer on the backing Orthographic projection on the base substrate.
  • the low temperature polysilicon thin film transistor further includes: a first source electrode located on a side of the layer where the first gate electrode is located away from the first active layer; a first drain, the first source and the first drain are respectively electrically connected to the first active layer;
  • the oxide thin film transistor further includes: a third gate on a side of the second active layer away from the first interlayer insulating layer, and a third gate at a layer where the third gate is located away from the second gate a second source electrode and a second drain electrode on one side of the source layer; wherein the second source electrode and the second drain electrode are respectively electrically connected to the second active layer, and the second source electrode and the second drain electrode are respectively electrically connected to the second active layer.
  • the second drain electrode is disposed in the same layer as the first source electrode and the first drain electrode.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, it further comprises: a second gate insulating layer formed of silicon oxide located between the second active layer and the layer where the third gate is located, and A second interlayer insulating layer located between the layer where the third gate electrode is located and the layer where the second source electrode and the second drain electrode are located.
  • the second interlayer insulating layer includes a silicon oxide layer, or includes a stacked silicon oxide layer and a silicon nitride layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a barrier layer located between the base substrate and the first active layer, and a barrier layer located between the barrier layer and the first active layer Buffer layer between active layers.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another display substrate according to an embodiment of the present disclosure.
  • the entire production process of the driving backplane also includes a variety of high temperature processes. During the process, hydrogen is easily diffused into the hydrogen-sensitive second active layer contained in the metal oxide thin film transistor, thereby reducing the reliability of the driving backplane, and even causing the produced driving backplane to fail directly.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 and FIG. 2 , including:
  • the low temperature polysilicon thin film transistor 02 is located on the base substrate 01; the low temperature polysilicon thin film transistor 02 includes a first active layer 21 and a first gate electrode 22 that are stacked on the base substrate 01;
  • the oxide thin film transistor 03 is located on the base substrate 01, and the oxide thin film transistor 03 includes a second active layer 31 located on the side of the layer where the first gate electrode 22 is located away from the base substrate 01;
  • the first gate insulating layer 04 is located between the layer where the first active layer 21 and the first gate electrode 22 are located, and the first gate insulating layer 04 includes a hydrogen-containing insulating layer;
  • the first interlayer insulating layer 05 is located between the layer where the first gate electrode 22 is located and the second active layer 32 , and the first interlayer insulating layer 05 includes a hydrogen blocking material layer.
  • the first gate insulating layer 04 including the hydrogen-containing insulating layer can provide hydrogen to the first active layer 21, and the first interlayer insulating layer 05 including the hydrogen-blocking material layer can prevent hydrogen from entering the second active layer 21.
  • the source layer 31 is diffused, so that both the low temperature polysilicon thin film transistor 02 and the oxide thin film transistor 03 have better stability, thereby ensuring the reliability of the fabricated display substrate.
  • the active layer generally includes a channel region, and a source contact region and a drain contact region respectively located on both sides of the channel region, and the active layer specifically refers to the channel region in the present disclosure.
  • polysilicon materials have high mobility, low power consumption, and high reliability. Therefore, the low temperature polysilicon thin film transistor 02 may be applied to a gate driver and/or a multiplexer (MUX) for driving a driving element of a thin film transistor of a display device.
  • MUX multiplexer
  • the low temperature polysilicon thin film transistor 02 can be applied to a driving transistor in a pixel circuit of an organic light emitting display device.
  • the band gap of oxide semiconductor materials is larger than that of silicon materials, so that electrons cannot pass through the band gap in the off state, and the off current is low. Therefore, the oxide thin film transistor 03 is suitable for a thin film transistor that is kept on for a short time and off for a long time. In addition, since the off current is low, the size of the auxiliary capacitor can be reduced. Therefore, the oxide thin film transistor 03 is suitable for a high-resolution display element.
  • the oxide thin film transistor 03 may be applied to a switching transistor in a pixel circuit of an organic light emitting display device.
  • the base substrate 01 may be a flexible material substrate such as polyimide (PI), or a rigid material substrate such as glass, which is not limited herein.
  • the first gate insulating layer 04 includes: a silicon oxide (SiOx) layer 41 , and a layer located between the silicon oxide layer 41 and the first gate insulating layer 04 .
  • Silicon nitride (SiNx) layer 42 between layers where gate 22 is located.
  • the silicon nitride layer 41 is a hydrogen-rich material, and can provide hydrogen for the first active layer 21 .
  • generally low temperature polysilicon thin film transistors 02 have high mobility.
  • a large amount of hydrogen can be injected into the first active layer 21 by increasing the thickness of the silicon nitride layer 42 during the hydroprocessing. It is considered that there is a threshold thickness at which the hydrogen content injected into the first active layer 21 is saturated by the hydroprocessing. Therefore, during specific implementation, the thickness of the silicon nitride layer 42 may be appropriately selected according to the target mobility and threshold thickness of the low temperature polysilicon thin film transistor 02 . Alternatively, the thickness of the silicon nitride layer 42 may be greater than or equal to and less than or equal to For example, it can be Wait.
  • the silicon nitride layer 42 can be diffused into the first active layer 21 by heat treatment to fill vacancies of polysilicon, and the hydrogenation treatment of the first active layer 21 can be realized.
  • the thickness of the silicon oxide layer 41 may be greater than or equal to and less than or equal to For example, it can be Wait.
  • the first interlayer insulating layer 05 may be a single-layer or double-layer silicon oxide (SiOx) layer.
  • SiOx silicon oxide
  • 1 shows a single-layer silicon oxide layer
  • FIG. 2 shows a first silicon oxide layer 51 and a second silicon oxide layer 52 arranged in layers.
  • the thickness of the single-layer silicon oxide layer contained in the first interlayer insulating layer 05 in FIG. 1 may be greater than or equal to and less than or equal to Exemplarily, can be Wait.
  • the thickness of the first silicon oxide 51 contained in the first interlayer insulating layer 05 in FIG. 2 may be greater than or equal to and less than or equal to E.g etc.; the thickness of the second silicon dioxide 52 contained in the first interlayer insulating layer 05 may be greater than or equal to and less than or equal to E.g Wait.
  • the material of the second active layer 31 may be indium gallium zinc oxide (IGZO) or the like.
  • IGZO indium gallium zinc oxide
  • indium gallium zinc oxide is deposited at high temperature, which can improve its crystallization efficiency and reduce oxygen vacancies in the second active layer 31. If a large number of oxygen vacancies exist in the second active layer 31, tunneling may occur, so that the second active layer 31 becomes conductive, resulting in failure of the performance of the oxide thin film transistor.
  • the hydrogen content in the silicon nitride layer 42 is reduced, and the silicon oxide layer contained in the first interlayer insulating layer 05 can effectively prevent the Hydrogen diffuses into the second active layer 31 .
  • a metal portion 321 ′ provided in the same layer as the first gate electrode 22 may also be included; Between the silicon monoxide layer 51 and the second silicon dioxide layer 52 , as shown in FIG. 2 ; optionally, the orthographic projection of the metal portion 321 ′ on the base substrate 01 is the same as that of the first active layer 21 on the base substrate 01
  • the overlapping area of the orthographic projections on the substrate 01 is S1
  • the overlapping area of the orthographic projection of the metal portion 321' on the base substrate 01 and the orthographic projection of the second active layer 31 on the base substrate 01 is S2, where S2 Greater than S1, optionally S1 is 0.
  • the metal portion 321 ′ can be used as the second gate electrode 321 of the oxide thin film transistor 03 , and can also be used as a light shielding layer covering the second active layer 31 to prevent ambient light from entering the second active layer 31 .
  • the oxide thin film transistor 03 may be a double-gate thin film transistor (as shown in FIG. 1 and FIG. 2 ), and the metal portion 321 ′ can be loaded with the same scan signal as the third gate electrode 322 ; it can also be a bottom gate type thin film transistor (as shown in FIG. 3 and FIG. 4 ), which is not limited herein.
  • the oxide thin film transistor 03 is a top-gate thin film transistor (as shown in FIG. 1 and FIG. 2 ).
  • the light shielding layer or the second gate electrode 321 may not be provided on the display substrate.
  • the oxide thin film transistor 03 is a top-gate thin film transistor (as shown in FIG. 5 and FIG. 6 ).
  • the potential loaded by the light-shielding layer can be the same potential loaded by the power supply line VDD (voltage source potential); it can also be the same potential loaded by the initialization signal line; it can also be the same potential loaded by the cathode (cathode potential VSS); It can be other fixed potentials, for example, the range of the fixed potential is -10V ⁇ +10V, another example, the range of the fixed potential is -5V ⁇ +5V, another example, the range of the fixed potential is -3V ⁇ +3V, another example, The range of the fixed potential is -1V ⁇ +1V, another example, the range of the fixed potential is -0.5V ⁇ +0.5V, another example, the range of the fixed potential is 0V, another example, the range of the fixed potential is 0.1V, another example , the fixed potential range is 10.1V, another example, the fixed potential range is 0.2V, another example, the fixed potential range is -0.2V, another example, the fixed potential range is 0.3V, another example, the fixed potential
  • the potential loaded by the light shielding layer 35 may be greater than the potential loaded by the cathode (cathode potential VSS) and lower than the potential loaded by the power supply line VDD; or, the potential loaded by the light shielding layer 35 may be greater than the potential loaded by the initialization signal line and less than the power supply Potential of line VDD loaded.
  • the oxide thin film transistor 03 when the oxide thin film transistor 03 is a double-gate thin film transistor, as shown in FIG. 1 and FIG. 2 , the oxide thin film transistor 03 may specifically include: a second gate electrode disposed in the same layer as the first gate electrode 22 321, a third gate electrode 322 located on the side of the second active layer 31 away from the first interlayer insulating layer 05, and a second source electrode 33 located at the side of the layer where the third gate electrode 322 is located away from the second active layer 31 and the second drain electrode 34; wherein, the second source electrode 33 and the second drain electrode 34 are electrically connected to the second active layer 31 respectively.
  • the oxide thin film transistor 03 is a bottom-gate thin film transistor, as shown in FIG. 3 and FIG.
  • the oxide thin film transistor 03 may specifically include: a second gate electrode 321 disposed on the same layer as the first gate electrode 22 , a second gate electrode 321 located on the The second source electrode 33 and the second drain electrode 34 on the side of the two active layers 31 away from the first interlayer insulating layer 05 ; wherein, the second source electrode 33 and the second drain electrode 34 are respectively electrically connected to the second active layer 31 connect.
  • the oxide thin film transistor 03 is a top-gate thin film transistor, as shown in FIG. 5 and FIG.
  • the oxide thin film transistor 03 may specifically include: a side of the second active layer 31 away from the first interlayer insulating layer 05 The third gate electrode 322, and the second source electrode 33 and the second drain electrode 34 on the side of the layer where the third gate electrode 322 is located away from the second active layer 31; wherein the second source electrode 33 and the second drain electrode 34 They are respectively electrically connected to the second active layer 31 .
  • the oxide thin film transistor 03 is a top-gate thin film transistor, the influence of ambient light on the second active layer 31 can be avoided by setting the metal portion 321' as a light shielding layer, as shown in FIG. 1 and FIG. 2 .
  • the first interlayer insulating layer 05 acts as an isolation second gate at the oxide thin film transistor 03
  • the electrode 321 and the gate insulating layer of the second active layer 31 are used.
  • the low temperature polysilicon thin film transistor 01 may also include : the first source electrode 23 and the first drain electrode 24 located on the side of the layer where the first gate electrode 22 is located away from the first active layer 21 , the first source electrode 23 and the first drain electrode 24 are respectively connected to the first active layer 21 are electrically connected, and the first source electrode 23 and the first drain electrode 24 are arranged in the same layer as the second source electrode 33 and the second drain electrode 34 .
  • the materials of the first gate 22 , the metal part 321 ′ and the third gate 322 may be metals or alloys such as molybdenum, aluminum, copper, titanium/aluminum/titanium, etc., which are not described here. limited.
  • the display substrate may further include: a layer where the second active layer 31 and the third gate electrode 322 are located.
  • a second gate insulating layer 06 formed of silicon oxide therebetween, and a second interlayer insulating layer 07 between the layer where the third gate electrode 322 is located and the layer where the second source electrode 33 and the second drain electrode 34 are located.
  • the second gate insulating layer 06 which is in direct contact with the second active layer 31 and formed of silicon oxide, can prevent hydrogen from diffusing into the second active layer 31 during the subsequent formation of the inorganic encapsulation layer made of silicon nitride.
  • the second interlayer insulating layer 07 may include a silicon oxide layer, or may also be included in the second gate insulating layer 06 A silicon oxide layer and a silicon nitride layer are stacked in sequence.
  • other inorganic layers and/or organic layers such as oxide layers, nitride layers, polymer layers, etc. may also be used to form the second interlayer insulating layer 07, which is not limited herein.
  • the materials of the first interlayer insulating layer 05 , the second gate insulating layer 06 , and the second interlayer insulating layer 07 may be the same material, for example, they may all be silicon oxide (SiOx).
  • the oxygen content of each film layer may be the same or different; when the oxygen content of each film layer is the same, or approximately the same, there is no obvious film layer boundary between the film layers.
  • the display substrate may further include: a layer where the second source electrode 33 and the second drain electrode 34 are located in sequence and away from the base substrate 01
  • the arrangement of the contact electrode 09 is equivalent to increasing the contact area between the anode 11 and the corresponding first drain 24 in disguised form, thereby effectively reducing the contact resistance between the anode 11 and the corresponding first drain 24 .
  • the materials of the first flattening layer 08 and the second flattening layer 10 can be inorganic materials such as silicon nitride, or organic materials such as polymers, as long as they are insulating material layers that can play a planarization role.
  • the material of the contact electrode 09 can be a single-layer structure such as molybdenum, aluminum, and copper, or a three-layer structure composed of titanium/aluminum/titanium.
  • the display substrate may further include: a pixel definition layer 12 and an isolation layer 12 located in sequence on the side of the layer where the anode 11 is located away from the base substrate 01 . cushion layer 13;
  • the orthographic projection of the pixel definition layer 12 on the base substrate 01 overlaps with the orthographic projection edge of the anode 11 ; the orthographic projection of the spacer layer 13 on the base substrate 01 is located within the orthographic projection of the pixel definition layer 12 .
  • the pixel definition layer 12 has a pixel opening at the anode 11, which defines the sub-pixel area where the anode 11 is located; the spacer layer 13 is specifically used to support the microcavity structure formed by the subsequent encapsulation layer and the pixel definition layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in FIG. 1 to FIG. 6 , it may further include: a barrier layer 14 located between the base substrate 01 and the first active layer 21 , and a barrier layer 14 located between the base substrate 01 and the first active layer 21 .
  • the buffer layer 15 between the barrier layer 14 and the first active layer 21 is used to suppress the diffusion of moisture or hydrogen in the environment and the alkali metal elements discharged from the base substrate 01 to the first active layer through the barrier layer 14 and the buffer layer 15.
  • the active layer 21 is formed, and the adhesion between the first active layer 21 and the base substrate 01 is improved.
  • the barrier layer 14 and the buffer layer 15 may be formed as a single layer by depositing any one of silicon nitride or silicon oxide or as a multilayer by alternately stacking silicon nitride and silicon oxide; in addition, the barrier layer 14 and The buffer layer 15 can also be formed as a multi-layer by selecting any one of silicon nitride or silicon oxide having different characteristics (eg, density, etc.).
  • the buffer layer 15 is a single-layer structure composed of silicon oxide
  • the barrier layer 14 is a four-layer structure composed of stacked silicon oxide, silicon nitride, silicon oxide, and silicon nitride.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display panel may be an organic electroluminescent display panel (OLED), a quantum dot light-emitting display panel (QLED).
  • OLED organic electroluminescent display panel
  • QLED quantum dot light-emitting display panel
  • Other essential components of the display panel should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation of the present disclosure. Since the principle of solving the problem of the display panel is similar to the principle of solving the problem of the above-mentioned display substrate, the implementation of the display panel provided by the embodiment of the present disclosure may refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the repetition will not be repeated. Repeat.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure, and the display device may be: a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, Navigators, smart watches, fitness wristbands, personal digital assistants, and any other product or component that has a display function.
  • the display device may be: a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, Navigators, smart watches, fitness wristbands, personal digital assistants, and any other product or component that has a display function.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should it be regarded as a limitation of the present disclosure.
  • the implementation of the display device may refer to the above-mentioned embodiment of the display panel, and the repetition will not be repeated.
  • the above-mentioned display substrate, display panel, and display device provided by the embodiments of the present disclosure include: a base substrate; a low temperature polysilicon thin film transistor located on the base substrate; a source layer and a first gate; an oxide thin film transistor, located on the base substrate, the oxide thin film transistor includes a second active layer on the side of the layer where the first gate is located away from the base substrate; a first gate insulating layer , located between the first active layer and the layer where the first gate is located, the first gate insulating layer includes a hydrogen-containing insulating layer; the first interlayer insulating layer is located between the layer where the first gate is located and the second active layer , the first interlayer insulating layer includes a hydrogen blocking material layer.
  • the The first gate insulating layer including the hydrogen-containing insulating layer can supply hydrogen to the first active layer, and the first interlayer insulating layer including the hydrogen-blocking material layer can prevent hydrogen from diffusing to the second active layer, so that the low-temperature polysilicon thin film Both the transistors and the oxide thin film transistors have good stability, which further ensures the reliability of the fabricated display substrate.

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Abstract

一种显示基板、显示面板及显示装置，包括：衬底基板(01)；低温多晶硅薄膜晶体管(02)，位于衬底基板(01)之上；低温多晶硅薄膜晶体管(02)包括位于衬底基板(01)上层叠设置的第一有源层(21)和第一栅极(22)；氧化物薄膜晶体管(03)，位于衬底基板(01)之上，氧化物薄膜晶体管(03)包括位于第一栅极(22)所在层背离衬底基板(01)一侧的第二有源层(31)；第一栅绝缘层(04)，位于第一有源层(21)与第一栅极(22)所在层之间，第一栅绝缘层(04)包括含氢绝缘层；第一层间绝缘层(05)，位于第一栅极(22)所在层与第二有源层(31)之间，第一层间绝缘层(05)包括阻挡氢材料层。

Description

显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
随着显示技术的不断发展，人们对显示产品的分辨率、功耗和画质的要求越来越高。为了满足这些要求，目前经常采用低温多晶氧化物(英文：Low Temperature Polycrystalline Oxide，简称：LTPO)技术，来制作显示产品的驱动背板中的像素驱动电路，这种LTPO技术即：同时利用低温多晶硅薄膜晶体管(LTPS TFT)和金属氧化物薄膜晶体管(Oxide TFT)作为像素驱动电路中的功能管，由于低温多晶硅薄膜晶体管迁移率高，可以加快对像素电容的充电速度，金属氧化物薄膜晶体管具有更低的泄漏电流，将这两种晶体管的优势相结合，有助于高分辨率、低功耗、高画质的显示产品的开发。
发明内容
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板；
低温多晶硅薄膜晶体管，位于所述衬底基板之上；所述低温多晶硅薄膜晶体管包括位于所述衬底基板上层叠设置的第一有源层和第一栅极；
氧化物薄膜晶体管，位于所述衬底基板之上，所述氧化物薄膜晶体管包括位于所述第一栅极所在层背离所述衬底基板一侧的第二有源层；
第一栅绝缘层，位于所述第一有源层与所述第一栅极所在层之间，所述第一栅绝缘层包括含氢绝缘层；
第一层间绝缘层，位于所述第一栅极所在层与所述第二有源层之间，所述第一层间绝缘层包括阻挡氢材料层。
可选地，在本公开实施例提供的上述显示基板中，所述第一栅绝缘层包括：氧化硅层，以及位于所述氧化硅层与所述第一栅极所在层之间的氮化硅层。
可选地，在本公开实施例提供的上述显示基板中，所述第一层间绝缘层包括氧化硅层。
可选地，在本公开实施例提供的上述显示基板中，还包括与所述第一栅极同层设置的金属部；
所述金属部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影的交叠面积为S1，且所述金属部在所述衬底基板上的正投影与所述第二有源层在所述衬底基板上的正投影的交叠面积为S2，其中S2大于S1。
可选地，在本公开实施例提供的上述显示基板中，所述第一层间绝缘层包括：层叠设置的第一氧化硅层和第二氧化硅层。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述第一氧化硅层与所述第二氧化硅层之间的金属部；
所述金属部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影的交叠面积为S1，且所述金属部在所述衬底基板上的正投影与所述第二有源层在所述衬底基板上的正投影的交叠面积为S2，其中S2大于S1。
可选地，在本公开实施例提供的上述显示基板中，所述金属部为所述氧化物薄膜晶体管的第二栅极。
可选地，在本公开实施例提供的上述显示基板中，所述金属部为遮光层，所述遮光层在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影。
可选地，在本公开实施例提供的上述显示基板中，所述低温多晶硅薄膜晶体管还包括：位于所述第一栅极所在层背离所述第一有源层一侧的第一源极和第一漏极，所述第一源极和所述第一漏极分别与所述第一有源层电连接；
所述氧化物薄膜晶体管还包括：位于所述第二有源层背离所述第一层间绝缘层一侧的第三栅极，以及位于所述第三栅极所在层背离所述第二有源层一侧的第二源极和第二漏极；其中，所述第二源极和所述第二漏极分别与所述第二有源层电连接，且所述第二源极和所述第二漏极与所述第一源极和所述第一漏极同层设置。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述第二有源层与所述第三栅极所在层之间由氧化硅形成的第二栅绝缘层，以及位于所述第三栅极所在层与所述第二源极、所述第二漏极所在层之间的第二层间绝缘层。
可选地，在本公开实施例提供的上述显示基板中，所述第二层间绝缘层包括氧化硅层，或者，包括层叠设置的氧化硅层和氮化硅层。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述衬底基板和所述第一有源层之间的阻挡层，以及位于所述阻挡层和所述第一有源层之间的缓冲层。
另一方面，本公开实施例还提供了一种显示面板，包括上述显示基板。
另一方面，本公开实施例还提供了一种显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的一种显示基板的结构示意图；
图2为本公开实施例提供的又一种显示基板的结构示意图；
图3为本公开实施例提供的又一种显示基板的结构示意图；
图4为本公开实施例提供的又一种显示基板的结构示意图；
图5为本公开实施例提供的又一种显示基板的结构示意图；
图6为本公开实施例提供的又一种显示基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
由于低温多晶硅薄膜晶体管在制作过程中，在制作其所含第一有源层时，需要引入大量的氢，而在驱动背板的整个制作过程中，还包括多种高温工艺，在经历这些高温工艺时，容易使氢向金属氧化物薄膜晶体管中所含对氢比较敏感的第二有源层扩散，进而导致驱动背板的可靠性降低，甚至导致生产出的驱动背板直接失效。
针对相关技术中存在的上述问题，本公开实施例提供了一种显示基板，如图1和图2所示，包括：
衬底基板01；
低温多晶硅薄膜晶体管02，位于衬底基板01之上；低温多晶硅薄膜晶体管02包括位于衬底基板01上层叠设置的第一有源层21和第一栅极22；
氧化物薄膜晶体管03，位于衬底基板01之上，氧化物薄膜晶体管03包括位于第一栅极22所在层背离衬底基板01一侧的第二有源层31；
第一栅绝缘层04，位于第一有源层21与第一栅极22所在层之间，第一栅绝缘层04包括含氢绝缘层；
第一层间绝缘层05，位于第一栅极22所在层与第二有源层32之间，第一层间绝缘层05包括阻挡氢材料层。
通过将第一栅绝缘层04设置于第一有源层21与第一栅极22所在层之间，并将第一层间绝缘层05设置于第一栅极22所在层与第二有源层31之间，使得包括含氢绝缘层的第一栅绝缘层04可为第一有源层21提供氢，而包括阻挡氢材料层的第一层间绝缘层05可避免氢向第二有源层31扩散，从而使得低温多晶硅薄膜晶体管02与氧化物薄膜晶体管03的稳定性均较好，进而很好的保证了所制作显示基板的可靠性。
需要说明的是，有源层一般包括沟道区，以及分别位于沟道区两侧的源极接触区和漏极接触区，在本公开中有源层具体指沟道区。另外，多晶硅材料具有高迁移率、低能耗、高可靠性。因此，低温多晶硅薄膜晶体管02可以应用于驱动显示装置的薄膜晶体管的驱动元件的栅极驱动器和/或复用器(MUX)。优选地，低温多晶硅薄膜晶体管02可以应用于有机发光显示装置的像素电路内的驱动晶体管。氧化物半导体材料的带隙比硅材料的大，使得电子不能在断开状态下穿过带隙，并且截止电流低。因此，氧化物薄膜晶体管03适用于保持短时间接通并且长时间断开的薄膜晶体管。此外，由于截止电流低，所以辅助电容的尺寸可以减小。因此，氧化物薄膜晶体管03适用于高分辨率显示元件。示例性地，氧化物薄膜晶体管03可以应用于有机发光显示装置的像素电路内的开关晶体管。另外，衬底基板01可以为聚酰亚胺(PI)等柔性材质衬底，也可以为玻璃等刚性材质衬底，在此不做限定。
可选地，在本公开实施例提供的上述显示基板中，如图1和图2所示，第一栅绝缘层04包括：氧化硅(SiOx)层41，以及位于氧化硅层41与第一栅极22所在层之间的氮化硅(SiNx)层42。其中，氮化硅层41为富氢材料，可为第一有源层21提供氢。可选地，通常低温多晶硅薄膜晶体管02具有高迁移率。因此，为了增加低温多晶硅薄膜晶体管02的迁移率，优选地，在加 氢处理期间可通过增加氮化硅层42的厚度来将大量的氢注入到第一有源层21中。考虑到存在通过加氢处理使注入到第一有源层21中的含氢量饱和的阈值厚度。因此，具体实施时，可根据低温多晶硅薄膜晶体管02的目标迁移率和阈值厚度，适当地选择氮化硅层42的厚度。可选地，氮化硅层42的厚度可以大于或等于
Figure PCTCN2020116858-appb-000001
且小于或等于
Figure PCTCN2020116858-appb-000002
例如具体可以为
Figure PCTCN2020116858-appb-000003
Figure PCTCN2020116858-appb-000004
Figure PCTCN2020116858-appb-000005
Figure PCTCN2020116858-appb-000006
等。另外，可通过热处理使氮化硅层42中所含的氢进行扩散至第一有源层21中来填充多晶硅的空位，实现对第一有源层21的加氢处理。此外，可选地，氧化硅层41的厚度可以大于或等于
Figure PCTCN2020116858-appb-000007
且小于或等于
Figure PCTCN2020116858-appb-000008
例如具体可以为
Figure PCTCN2020116858-appb-000009
Figure PCTCN2020116858-appb-000010
Figure PCTCN2020116858-appb-000011
Figure PCTCN2020116858-appb-000012
等。
可选地，在本公开实施例提供的上述显示基板中，如图1和图2所示，第一层间绝缘层05可以为单层或双层氧化硅(SiOx)层，具体地，图1示出了单层氧化硅层，图2示出了层叠设置的第一氧化硅层51和第二氧化硅层52。可选地，图1中第一层间绝缘层05所含单层氧化硅层的厚度可以大于或等于
Figure PCTCN2020116858-appb-000013
且小于或等于
Figure PCTCN2020116858-appb-000014
示例性的，可以为
Figure PCTCN2020116858-appb-000015
Figure PCTCN2020116858-appb-000016
等。图2中第一层间绝缘层05所含的第一氧化硅51的厚度可以大于或等于
Figure PCTCN2020116858-appb-000017
且小于或等于
Figure PCTCN2020116858-appb-000018
例如
Figure PCTCN2020116858-appb-000019
Figure PCTCN2020116858-appb-000020
Figure PCTCN2020116858-appb-000021
Figure PCTCN2020116858-appb-000022
等；第一层间绝缘层05所含的第二氧化硅52的厚度可以大于或等于
Figure PCTCN2020116858-appb-000023
且小于或等于
Figure PCTCN2020116858-appb-000024
例如
Figure PCTCN2020116858-appb-000025
Figure PCTCN2020116858-appb-000026
等。
可选地，第二有源层31的材料可以为铟镓锌氧化物(IGZO)等。一般在 高温下沉积铟镓锌氧化物，可提高其结晶效率，减少第二有源层31中的氧空位。如果在第二有源层31中存在大量的氧空位，则会发生隧穿，使第二有源层31变成导电的，致使氧化物薄膜晶体管的性能失效。本实施例中，采用氮化硅层42对第一有源层21补氢后，氮化硅层42中的含氢量降低，同时第一层间绝缘层05所含氧化硅层可有效防止氢扩散至第二有源层31中。
可选地，在本公开实施例提供的上述显示基板中，如图1所示，还可以包括与第一栅极22同层设置的金属部321’；当然，金属部321’还可以位于第一氧化硅层51与第二氧化硅层52之间，如图2所示；可选地，金属部321’在衬底基板01上的正投影与第一有源层21在衬底基板01上的正投影的交叠面积为S1，且金属部321’在衬底基板01上的正投影与第二有源层31在衬底基板01上的正投影的交叠面积为S2，其中S2大于S1，可选地S1为0。具体地，该金属部321’可以做为氧化物薄膜晶体管03的第二栅极321，也可以作为覆盖第二有源层31以阻止环境光入射至第二有源层31的遮光层。
需要说明的是，在金属部321’做为氧化物薄膜晶体管03的第二栅极321时，氧化物薄膜晶体管03可以为双栅型薄膜晶体管(如图1和图2所示)，金属部321’可以加载与第三栅极322相同的扫描信号；也可以为底栅型薄膜晶体管(如图3和图4所示)，在此不做限定。在金属部321’做为遮挡第二有源层31的遮光层时，氧化物薄膜晶体管03为顶栅型薄膜晶体管(如图1和图2所示)。当然，显示基板上还可以不设置遮光层或第二栅极321，此时，氧化物薄膜晶体管03为顶栅型薄膜晶体管(如图5和图6所示)。
具体实施时，遮光层加载的电位可以是电源线VDD(电压源电位)加载的电位相同；也可以是初始化信号线加载的电相同；也可以是阴极(阴极电位VSS)加载的电位相同；也可以是其它固定电位，例如，固定电位的范围为-10V～+10V，又例如，固定电位的范围为-5V～+5V，又例如，固定电位的范围为-3V～+3V，又例如，固定电位的范围为-1V～+1V，又例如，固定电位的范围为-0.5V～+0.5V，又例如，固定电位的范围为0V，又例如，固定电位的范围为0.1V，又例如，固定电位的范围为10.1V，又例如，固定电位 的范围为0.2V，又例如，固定电位的范围为-0.2V，又例如，固定电位的范围为0.3V，又例如，固定电位的范围为-0.3V。
具体的，遮光层35加载的电位可以大于阴极(阴极电位VSS)加载的电位，且小于电源线VDD加载的电位；或者，遮光层35加载的电位可以大于初始化信号线加载的电位，且小于电源线VDD加载的电位。
可选地，在氧化物薄膜晶体管03为双栅型薄膜晶体管时，如图1和图2所示，氧化物薄膜晶体管03具体可以包括：与第一栅极22同层设置的第二栅极321、位于第二有源层31背离第一层间绝缘层05一侧的第三栅极322，以及位于第三栅极322所在层背离第二有源层31一侧的第二源极33和第二漏极34；其中，第二源极33和第二漏极34分别与第二有源层31电连接。在氧化物薄膜晶体管03为底栅型薄膜晶体管时，如图3和图4所示，氧化物薄膜晶体管03具体可以包括：与第一栅极22同层设置的第二栅极321、位于第二有源层31背离第一层间绝缘层05一侧的第二源极33和第二漏极34；其中，第二源极33和第二漏极34分别与第二有源层31电连接。在氧化物薄膜晶体管03为顶栅型薄膜晶体管时，如图5和图6所示，氧化物薄膜晶体管03具体可以包括：位于第二有源层31背离第一层间绝缘层05一侧的第三栅极322，以及位于第三栅极322所在层背离第二有源层31一侧的第二源极33和第二漏极34；其中，第二源极33和第二漏极34分别与第二有源层31电连接。优选地，在氧化物薄膜晶体管03为顶栅型薄膜晶体管时，可通过设置金属部321’作为遮光层来避免环境光对第二有源层31的影响，如图1和图2所示。另外，如图1至图4所示，在氧化物薄膜晶体管03为双栅型薄膜晶体管或底栅型薄膜晶体管时，第一层间绝缘层05在氧化物薄膜晶体管03处作为隔离第二栅极321与第二有源层31的栅绝缘层使用。
可选地，在本公开实施例提供的上述显示基板中，如图1至图6所示，低温多晶硅薄膜晶体管01除了包括第一有源层21和第一栅极22之外，还可以包括：位于第一栅极22所在层背离第一有源层21一侧的第一源极23和第一漏极24，第一源极23和第一漏极24分别与第一有源层21电连接，并且第 一源极23和第一漏极24与第二源极33和第二漏极34同层设置。可选地，在本公开了中、第一栅极22、金属部321’和第三栅极322的材料可以为钼、铝、铜、钛/铝/钛等金属或合金，在此不做限定。
可选地，在本公开实施例提供的上述显示基板中，如图1、图2、图5和图6所示，还可以包括：位于第二有源层31与第三栅极322所在层之间由氧化硅形成的第二栅绝缘层06，以及位于第三栅极322所在层与第二源极33、第二漏极34所在层之间的第二层间绝缘层07。与第二有源层31直接接触且由氧化硅形成的第二栅绝缘层06可阻挡后续氮化硅材质的无机封装层形成过程中，氢扩散至第二有源层31。可选地，为进一步提高对后续氮化硅材质的无机封装层形成过程中氢的阻挡作用，第二层间绝缘层07可以包括氧化硅层，或者，还可以包括在第二栅绝缘层06上依次层叠设置的氧化硅层和氮化硅层。可选地，在具体实施时，还可以采用氧化物层、氮化物层、聚合物层等其他无机层和/或有机层来形成第二层间绝缘层07，在此不做限定。
具体实施例中，第一层间绝缘层05、第二栅绝缘层06、第二层间绝缘层07的材质可以为相同材质，例如可以均是氧化硅(SiOx)。例如各膜层含氧量可以相同，也可以不同；当各膜层含氧量相同，或者大致相同时，此时各个膜层之间没有明显的膜层界限。
需要说明的是，本公开中的“大致”指误差不超过10％以内。
可选地，在本公开实施例提供的上述显示基板中，如图1至图6所示，还可以包括：依次位于第二源极33和第二漏极34所在层背离衬底基板01一侧的第一平坦层08、接触电极09、第二平坦层10和阳极11；其中，接触电极09通过贯穿第一平坦层10的过孔与第一漏极24电连接，阳极11通过贯穿第二平坦层10的过孔与接触电极09电连接，使得阳极11通过接触电极09实现与对应第一漏极24的电连接。接触电极09的设置，相当于变相增大了阳极11与对应第一漏极24的接触面积，从而有效降低阳极11与对应第一漏极24的接触电阻。可选地，第一平坦层08和第二平坦层10的材料可以为氮化硅等无机材料，也可以为聚合物等有机材料，只要是可以起到平坦化作用 的绝缘材料层即可。接触电极09的材料可以为钼、铝、铜等单层结构，也可以为钛/铝/钛构成的三层结构。
可选地，在本公开实施例提供的上述显示基板中，如图1至图6所示，一般还可以包括：依次位于阳极11所在层背离衬底基板01一侧的像素定义层12和隔垫物层13；
像素定义层12在衬底基板01上的正投影与阳极11的正投影边缘相互交叠；隔垫物层13在衬底基板01上的正投影位于像素定义层12的正投影内。其中，像素定义层12在阳极11处具有像素开口，限定出了阳极11所在的子像素区域；隔垫物层13具体用于对后续封装层与像素定义层构成的微腔结构进行支撑。
可选地，在本公开实施例提供的上述显示基板中，如图1至图6所示，还可以包括：位于衬底基板01和第一有源层21之间的阻挡层14，以及位于阻挡层14和第一有源层21之间的缓冲层15，以通过阻挡层14和缓冲层15抑制环境中的水分或氢、以及从衬底基板01排出的碱金属元素扩散至第一有源层21，并改善第一有源层21与衬底基板01之间的粘合力。可选地，阻挡层14和缓冲层15可以通过沉积氮化硅或氧化硅中的任意一种形成为单层或通过交替层叠氮化硅和氧化硅形成为多层；另外，阻挡层14和缓冲层15还可以通过选择具有不同特性(例如密度等)的氮化硅或氧化硅中的任意一种来形成为多层。示例性地，缓冲层15为氧化硅构成的单层结构，阻挡层14为层叠设置的氧化硅、氮化硅、氧化硅、氮化硅构成的四层结构。
基于同一发明构思，本公开实施例提供了一种显示面板，包括本公开实施例提供的上述显示基板。该显示面板可以为有机电致发光显示面板(OLED)、量子点发光显示面板(QLED)。对于显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。由于该显示面板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示面板的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。另外，由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的上述显示基板、显示面板及显示装置，包括：衬底基板；低温多晶硅薄膜晶体管，位于衬底基板之上；低温多晶硅薄膜晶体管包括位于衬底基板上层叠设置的第一有源层和第一栅极；氧化物薄膜晶体管，位于衬底基板之上，氧化物薄膜晶体管包括位于第一栅极所在层背离衬底基板一侧的第二有源层；第一栅绝缘层，位于第一有源层与第一栅极所在层之间，第一栅绝缘层包括含氢绝缘层；第一层间绝缘层，位于第一栅极所在层与第二有源层之间，第一层间绝缘层包括阻挡氢材料层。通过将第一栅绝缘层设置于第一有源层与第一栅极所在层之间，并将第一层间绝缘层设置于第一栅极所在层与第二有源层之间，使得包括含氢绝缘层的第一栅绝缘层可为第一有源层提供氢，而包括阻挡氢材料层的第一层间绝缘层可避免氢向第二有源层扩散，从而使得低温多晶硅薄膜晶体管与氧化物薄膜晶体管的稳定性均较好，进而很好的保证了所制作显示基板的可靠性。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示基板，其中，包括：
    衬底基板；
    低温多晶硅薄膜晶体管，位于所述衬底基板之上；所述低温多晶硅薄膜晶体管包括位于所述衬底基板上层叠设置的第一有源层和第一栅极；
    氧化物薄膜晶体管，位于所述衬底基板之上，所述氧化物薄膜晶体管包括位于所述第一栅极所在层背离所述衬底基板一侧的第二有源层；
    第一栅绝缘层，位于所述第一有源层与所述第一栅极所在层之间，所述第一栅绝缘层包括含氢绝缘层；
    第一层间绝缘层，位于所述第一栅极所在层与所述第二有源层之间，所述第一层间绝缘层包括阻挡氢材料层。
  2. 如权利要求1所述的显示基板，其中，所述第一栅绝缘层包括：氧化硅层，以及位于所述氧化硅层与所述第一栅极所在层之间的氮化硅层。
  3. 如权利要求1所述的显示基板，其中，所述第一层间绝缘层包括氧化硅层。
  4. 如权利要求3所述的显示基板，其中，还包括与所述第一栅极同层设置的金属部；
    所述金属部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影的交叠面积为S1，且所述金属部在所述衬底基板上的正投影与所述第二有源层在所述衬底基板上的正投影的交叠面积为S2，其中S2大于S1。
  5. 如权利要求1所述的显示基板，其中，所述第一层间绝缘层包括：层叠设置的第一氧化硅层和第二氧化硅层。
  6. 如权利要求5所述的显示基板，其中，还包括：位于所述第一氧化硅层与所述第二氧化硅层之间的金属部；
    所述金属部在所述衬底基板上的正投影与所述第一有源层在所述衬底基 板上的正投影的交叠面积为S1，且所述金属部在所述衬底基板上的正投影与所述第二有源层在所述衬底基板上的正投影的交叠面积为S2，其中S2大于S1。
  7. 如权利要求4或6所述的显示基板，其中，所述金属部为所述氧化物薄膜晶体管的第二栅极。
  8. 如权利要求4或6所述的显示基板，其中，所述金属部为遮光层，所述遮光层在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影。
  9. 如权利要求1-8任一项所述的显示基板，其中，所述低温多晶硅薄膜晶体管还包括：位于所述第一栅极所在层背离所述第一有源层一侧的第一源极和第一漏极，所述第一源极和所述第一漏极分别与所述第一有源层电连接；
    所述氧化物薄膜晶体管还包括：位于所述第二有源层背离所述第一层间绝缘层一侧的第三栅极，以及位于所述第三栅极所在层背离所述第二有源层一侧的第二源极和第二漏极；其中，所述第二源极和所述第二漏极分别与所述第二有源层电连接，且所述第二源极和所述第二漏极与所述第一源极和所述第一漏极同层设置。
  10. 如权利要求9所述的显示基板，其中，还包括：位于所述第二有源层与所述第三栅极所在层之间由氧化硅形成的第二栅绝缘层，以及位于所述第三栅极所在层与所述第二源极、所述第二漏极所在层之间的第二层间绝缘层。
  11. 如权利要求10所述的显示基板，其中，所述第二层间绝缘层包括氧化硅层，或者，包括层叠设置的氧化硅层和氮化硅层。
  12. 如权利要求1-11任一项所述的显示基板，其中，还包括：位于所述衬底基板和所述第一有源层之间的阻挡层，以及位于所述阻挡层和所述第一有源层之间的缓冲层。
  13. 一种显示面板，其中，包括如权利要求1-12任一项所述的显示基板。
  14. 一种显示装置，其中，包括如权利要求13所述的显示面板。
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CN109841632A (zh) * 2019-01-31 2019-06-04 合肥京东方光电科技有限公司 显示基板、显示面板和显示基板的制作方法
CN110299322A (zh) * 2019-07-03 2019-10-01 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116367596A (zh) * 2023-05-11 2023-06-30 惠科股份有限公司 显示面板及其制备方法
CN116367596B (zh) * 2023-05-11 2023-08-11 惠科股份有限公司 显示面板及其制备方法

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