WO2021239061A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021239061A1
WO2021239061A1 PCT/CN2021/096444 CN2021096444W WO2021239061A1 WO 2021239061 A1 WO2021239061 A1 WO 2021239061A1 CN 2021096444 W CN2021096444 W CN 2021096444W WO 2021239061 A1 WO2021239061 A1 WO 2021239061A1
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WIPO (PCT)
Prior art keywords
line
data line
shielding
electrically connected
display panel
Prior art date
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PCT/CN2021/096444
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English (en)
French (fr)
Inventor
马倩
高静
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/786,079 priority Critical patent/US20230028604A1/en
Publication of WO2021239061A1 publication Critical patent/WO2021239061A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • Two data lines are provided for each sub-pixel corresponding to each column.
  • One of the two data lines is electrically connected to the sub-pixels in odd rows, and the other second data line is electrically connected to the sub-pixels in even rows.
  • the source drive architecture can increase the time to write data and the time to compensate for the threshold voltage.
  • a display panel in one aspect, includes a substrate, a plurality of pixel driving circuits, a plurality of first data lines, a plurality of second data lines, and at least one shielding line.
  • the plurality of pixel driving circuits are distributed in an array.
  • the first data line is electrically connected with pixel driving circuits in even rows in the same column of pixel driving circuits.
  • the second data line is electrically connected with pixel driving circuits in odd rows in the same column of pixel driving circuits; the adjacently arranged first data line and the second data line have a facing area.
  • At least one shielding line is configured to transmit a fixed voltage; the shielding line forms a first capacitor with the first data line of the adjacently arranged first data line and second data line, and/or, the shielding line and the phase
  • the second data line of the adjacently arranged first data line and the second data line forms a second capacitor.
  • the capacitance of the first capacitor is approximately equal to the capacitance of the second capacitor.
  • the shielding line and the first data line form a first capacitor, and the orthographic projection of the shielding line on the substrate and the orthographic projection of the first data line on the substrate are at least Partially overlapped.
  • the shielding line and the second data line form a second capacitor, and the orthographic projection of the shielding line on the substrate and the orthographic projection of the second data line on the substrate are at least Partially overlapped.
  • the display panel includes a plurality of shielding lines, and the plurality of shielding lines includes at least one first shielding line and at least one second shielding line.
  • the first shielding line and the first data line of the first data line and the second data line adjacently arranged form the first capacitor.
  • the second shielding line and the second data line of the first data line and the second data line adjacently arranged form a second capacitor.
  • the display panel further includes: a component to be driven, a first power line, a second power line, and an initialization signal line.
  • the first pole of the component to be driven is electrically connected to the pixel driving circuit.
  • the first power line is electrically connected to the pixel drive circuit, and the first power line is configured to transmit a first voltage signal to the pixel drive circuit.
  • the second power line is electrically connected to the second pole of the element to be driven, and the second power line is configured to transmit a second voltage signal to the element to be driven.
  • the initialization signal line is electrically connected to the pixel drive circuit, and the initialization signal line is configured to transmit an initialization signal to the pixel drive circuit.
  • the shielding line is electrically connected to the first power line, the second power line, the second pole of the component to be driven, or the initialization signal line.
  • the display panel includes a display area and a peripheral area.
  • the first power line includes a sub power line located in the display area, and a power bus located in the peripheral area and electrically connected to the sub power line.
  • the sub-power supply line is electrically connected to the pixel driving circuit.
  • the shielding wire is electrically connected to the sub power line and/or the power bus.
  • the shielding line is electrically connected to the sub-power supply line closest to the shielding line; and/or, the shielding line is electrically connected to the power bus through a via provided in the peripheral area.
  • the display panel includes a display area and a peripheral area; the shielding line is electrically connected to the second power line through a via provided in the peripheral area.
  • the display panel includes a display area and a peripheral area.
  • the initialization signal line includes a sub initialization signal line located in the display area, and an initialization signal bus located in the peripheral area and electrically connected to the sub initialization signal line.
  • the sub-initialization signal line is electrically connected to the pixel driving circuit.
  • the shielding line is electrically connected to the sub-initialization signal line and/or the initialization signal bus.
  • the shielding line is electrically connected to the sub-initialization signal line closest to the shielding line; and/or, the shielding line is electrically connected to the initialization signal bus through a via hole provided in the peripheral area. connect.
  • the at least one shielding line is disposed between the film layer where the first data line and the second data line are located and the substrate.
  • the display panel further includes a light shielding pattern.
  • the light shielding pattern is arranged between the film layer where the pixel driving circuit is located and the substrate.
  • the shielding wire and the light shielding pattern are made of the same material and arranged in the same layer.
  • the distance between the adjacently disposed first data line and the second data line is greater than the vertical distance between the shielding line and the film layer where the first data line and the second data line are located.
  • the vertical distance between the shielding line and the film layer where the first data line and the second data line are located is 0.75 ⁇ m to 1 ⁇ m; and/or, the first data line and the second data line that are adjacently arranged The distance between the lines is 4 ⁇ m to 8 ⁇ m.
  • the shielding line is arranged in the same layer as the first data line and the second data line, and is located between the adjacently arranged first data line and the second data line.
  • the parasitic capacitance generated between the adjacently disposed first data line and the second data line is smaller than the capacitance of the first capacitor and/or the capacitance of the second capacitor.
  • the plurality of first data lines and the plurality of second data lines are alternately arranged along the row direction in which the plurality of pixel driving circuits are arranged, and the first data line and the second data line are arranged adjacently.
  • the data line is located between two adjacent columns of pixel driving circuits.
  • the first data line and the second data line arranged adjacently are electrically connected to pixel driving circuits in different rows.
  • a display device including the display panel described in any one of the above.
  • FIG. 1A is a schematic diagram of a display device according to some embodiments.
  • FIG. 1B is a cross-sectional view of the display panel shown in FIG. 1A along the CC' direction;
  • 2A is a diagram of a source driving structure of a display panel according to some embodiments.
  • FIG. 2B is a diagram of another source driving structure of a display panel according to some embodiments.
  • Fig. 3 is a circuit structure diagram of area B in Fig. 2A;
  • FIG. 4A is a structural diagram corresponding to the E area in FIG. 3;
  • 4B is an equivalent circuit diagram corresponding to the first data line and the second data line in FIG. 4A;
  • FIG. 5A is another structural diagram corresponding to area E in FIG. 3;
  • Fig. 5B is a cross-sectional view along the FF' direction in Fig. 5A;
  • 5C is a corresponding equivalent circuit diagram of the first data line, the second data line, and the shielding line in FIG. 5A;
  • FIG. 6A is another structural diagram corresponding to area E in FIG. 3;
  • Fig. 6B is a cross-sectional view along the GG' direction in Fig. 6A;
  • 6C is a corresponding equivalent circuit diagram of the first data line, the second data line, and the shielding line in FIG. 6A;
  • FIG. 7A is another structural diagram corresponding to the E area in FIG. 3;
  • Fig. 7B is a cross-sectional view along the HH' direction in Fig. 7A;
  • FIG. 7C is a corresponding equivalent circuit diagram of the first data line, the second data line, and the shielding line in FIG. 7A;
  • FIG. 8A is another structural diagram corresponding to the E area in FIG. 3;
  • Fig. 8B is a cross-sectional view along the II' direction in Fig. 8A;
  • FIG. 9A is another structural diagram corresponding to the E area in FIG. 3;
  • Fig. 9B is a cross-sectional view along the JJ' direction in Fig. 8A;
  • Fig. 10 is a structural diagram of a shielded wire connected to a first power wire according to some embodiments.
  • Figure 11 is another structural diagram of a shielded wire connected to a first power wire according to some embodiments.
  • Figure 12 is a structural diagram of a shielded wire connected to a second power wire according to some embodiments.
  • FIG. 13 is a structural diagram of the connection of the shielded line and the initialization signal line according to some embodiments.
  • FIG. 14 is another structural diagram of the connection of the shielded line and the initialization signal line according to some embodiments.
  • 15 is a structural diagram of a shielded wire connected to a second pole of a component to be driven according to some embodiments
  • 16 is a simulation diagram of the potential of the first data line and the second data line when the shielding line is not provided on the display panel according to some embodiments;
  • FIG. 17 is a simulation diagram of the potential of the first data line and the second data line when the shielding line is provided on the display panel according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • the etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device 100 may be a TV, a mobile phone, a computer, a notebook computer, a tablet computer, a personal digital assistant (English: Personal Digital Assistant, PDA for short), On-board computer, etc.
  • the display device 100 includes a display panel 101.
  • the display panel 101 may be a liquid crystal display (LCD); the display panel 101 may also be an electroluminescence display panel or a photoluminescence display panel.
  • the electroluminescence display panel may be an organic light-emitting diode (OLED) display panel or a quantum dot electroluminescence (quantum dot light emitting diode) display panel. , QLED for short) display panel.
  • the photoluminescence display device may be a quantum dot photoluminescence display panel.
  • the display panel 101 includes a plurality of sub-pixels arranged in an array.
  • the display panel 101 as an OLED display panel as an example, the cross-sectional structure of a sub-pixel in the display panel 101 is introduced.
  • the display panel 101 includes a display substrate 31 and an encapsulation layer 32 for encapsulating the display substrate 31.
  • the packaging layer 32 may be a packaging film or a packaging substrate.
  • each sub-pixel of the above-mentioned display substrate 31 includes a light-emitting device L and a pixel driving circuit 40 provided on the substrate 10, and the pixel driving circuit 40 includes a plurality of thin film transistors TFT.
  • the light emitting device L includes an anode L1, a light emitting functional layer L2, and a cathode L3, and the anode L1 is electrically connected to the drain of one of the plurality of thin film transistors TFT.
  • the thin film transistor TFT includes a gate gate, a source source, a drain drain, and a semiconductor active layer 20.
  • a gate gate is used to perform self-alignment process control, and a channel CH and source contacts Source' and source contacts are formed on the semiconductor active layer 20.
  • the drain contact Drain' at this time, the source contact Source' is equivalent to the source Source, and the drain contact Drain' is equivalent to the drain Drain.
  • the display substrate 31 sequentially includes a semiconductor layer (that is, the film layer where the semiconductor active layer 20 is located), a gate conductive layer (that is, The film layer where the gate Gate is located) and the source-drain conductive layer (that is, the film layer where the source Source and the drain Drain are located).
  • a semiconductor layer that is, the film layer where the semiconductor active layer 20 is located
  • a gate conductive layer that is, The film layer where the gate Gate is located
  • the source-drain conductive layer that is, the film layer where the source Source and the drain Drain are located.
  • the display substrate 31 further includes a pixel defining layer 314.
  • the pixel defining layer 314 includes a plurality of opening regions, and one light emitting device L is disposed in one opening region.
  • the light-emitting functional layer L2 includes a light-emitting layer.
  • the light-emitting function layer L2 in addition to the light-emitting layer, also includes an electron transport layer (election transporting layer, ETL), an electron injection layer (election injection layer, EIL), and a hole transporting layer (hole transporting layer). layer, HTL for short) and one or more of the hole injection layer (HIL for short).
  • the display substrate 31 further includes a flat layer 315 provided between the thin film transistor TFT and the anode L1.
  • the display substrate 31 may further include: a buffer layer Buffer between the substrate 10 and the semiconductor layer, a gate insulating layer GI between the semiconductor layer and the gate conductive layer, and a gate insulating layer GI between the gate conductive layer and the source and drain.
  • the display substrate 31 includes two gate conductive layers, namely a first gate conductive layer and a second gate conductive layer.
  • the display substrate 31 includes two gate insulating layers GI, namely the first gate. An insulating layer and a second gate insulating layer.
  • the display substrate 31 sequentially includes a semiconductor layer, a first gate insulating layer, a first gate conductive layer, and a second gate.
  • the display device 100 When the display device 100 is an electroluminescence display device or a photoluminescence display device, the display device 100 may be a top emission display device. In this case, the anode L1 close to the substrate 10 is opaque, and the cathode L3 far away from the substrate 10 is opaque. Transparent or translucent; the display device 100 can also be a bottom emission display device, in this case, the anode L1 close to the substrate 10 is transparent or translucent, and the cathode L3 far away from the substrate 10 is opaque; the display device 100 can also be a double In the surface-emission display device, in this case, the anode L1 close to the substrate 10 and the cathode L3 far from the substrate 10 are both transparent or semi-transparent.
  • the display panel 101 has a display area (Active Area, AA area for short) and a peripheral area S.
  • the peripheral area S is located on at least one side of the AA area.
  • the peripheral area S may be located in a circle of the AA area.
  • the display panel 101 includes a plurality of sub-pixels P, and the plurality of sub-pixels P are located in the AA area.
  • the plurality of sub-pixels P include at least a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel, and the first, second, and third colors are three primary colors (for example, red, green, and blue).
  • FIG. 2A and FIG. 2B take the above-mentioned multiple sub-pixels P arranged in an array of n rows and m columns as an example for illustration, where n and m are both positive integers.
  • each sub-pixel P includes a pixel drive circuit 40 (refer to FIGS. 1A and 1B) and an element to be driven (for example, a light-emitting device L, refer to FIGS. 1A and 1B).
  • the pixel driving circuit 40 is electrically connected to the corresponding light-emitting device L, and the pixel driving circuit 40 is used to drive the light-emitting device L to work.
  • the light emitting device L is also electrically connected to the second power supply line VSS (refer to FIG. 15).
  • the light emitting device L may be a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED).
  • Micro LED Micro Light Emitting Diode
  • Mini LED Mini Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • each column of sub-pixels P is electrically connected to two data lines.
  • the display panel 101 includes a scan driver 11, a source driver 12, a timing controller 13, and a plurality of gates 14 disposed in the peripheral area S.
  • one gate 14 corresponds to one column of sub-pixels P.
  • the scan driver 11 is electrically connected to the gate line GATE and the timing controller 13.
  • the source driver 12 is electrically connected to the gate 14 and the timing controller 13.
  • the gate 14 is also electrically connected to the timing controller 13 and two data lines electrically connected to the pixel driving circuit 40 in the same column of sub-pixels P corresponding to the gate 14.
  • each gate 14 is connected to a source driver via a data line bus D. 12 is electrically connected, the number of the data bus D is m.
  • the gate 14 corresponding to the sub-pixel P in the first column is electrically connected to the source driver 12 through a data bus D(1)
  • the gate corresponding to the sub-pixel P in the second column is electrically connected to the source driver 12 through a data bus D(1)
  • the device 14 is electrically connected to the source driver 12 through a data bus D(2)
  • the gate 14 corresponding to the sub-pixel in the m-th column is electrically connected to the source driver 12 through a data bus D(m).
  • the pixel driving circuit 40 in the sub-pixel P in the same column is electrically connected to the first data line D1 and the second data line D2, and the first data line D1 is electrically connected to the pixel driving circuit 40 in the even-numbered row sub-pixel P.
  • the second data line D2 is electrically connected to the pixel driving circuit 40 in the odd-numbered row of sub-pixels P.
  • the pixel driving circuit 40 in the odd-numbered rows of sub-pixels P and the gate 14 corresponding to this column of sub-pixels P are electrically connected through the second data line D2, and in the even-numbered rows of sub-pixels P
  • the pixel driving circuit 40 and the gate 14 corresponding to this column of sub-pixels P are electrically connected through the first data line D1.
  • the pixel driving circuit 40 in the odd-numbered rows of sub-pixels P corresponds to the first column of sub-pixels P through the second data line D2(1)
  • the gate 14 is electrically connected, and the pixel driving circuit 40 in the even-numbered row of sub-pixels P is electrically connected to the gate 14 corresponding to the first column of sub-pixels P through the first data line D1 (1).
  • the pixel driving circuit 40 in the odd-numbered rows of sub-pixels P is electrically connected to the gate 14 corresponding to the second column of sub-pixels P through the second data line D2(2), and in the even-numbered rows of sub-pixels P
  • the pixel driving circuit 40 is electrically connected to the gate 14 corresponding to the sub-pixel P in the second column through the first data line D1(2).
  • the pixel driving circuit 40 in the odd-numbered sub-pixel P is electrically connected to the gate 14 corresponding to the m-th sub-pixel P through the second data line D2(m), and in the even-numbered sub-pixel P
  • the pixel driving circuit 40 is electrically connected to the gate 14 corresponding to the sub-pixel P in the m-th column through the first data line D1(m).
  • the scan driver 11 is configured to output the gate scan signal to the gate line GATE row by row under the control of the signal from the timing controller 13.
  • the scan driver 11 outputs sequentially from the first row to the nth row (GATE_1 to GATE_n) under the control of the signal from the timing controller 13 Gate scan signal.
  • the source driver 12 is configured to output a data signal to the gate 14 under the control of a signal from the timing controller 13.
  • the gate 14 is configured to transmit the data signal from the source driver 12 to the sub-pixels P in the same column corresponding to the gate 14 in different time periods under the control of the signal from the timing controller 13
  • the gate 14 transmits the data signal from the source driver 12 to the sub-pixel P under the control of the timing controller 13
  • the second data line D2(m) electrically connected to the gate 14 allows the odd-numbered rows of sub-pixels P electrically connected to the data bus D(m) to write data.
  • the gate 14 transmits the data signal from the source driver 12 to the first data line D1 electrically connected to the gate 14 under the control of the timing controller 13 ( In m), the even-numbered rows of sub-pixels P electrically connected to the data bus D(m) are caused to write data.
  • the gate 14 includes a first transistor S1 and a second transistor S2.
  • the gate of the first transistor S1 is electrically connected to the timing controller 13
  • the first electrode of the first transistor S1 is electrically connected to the data bus D corresponding to the gate 14
  • the second electrode of the first transistor S1 is connected to the gate
  • the first data line D1 electrically connected to the pixel driving circuit 40 in the sub-pixel P in the same column corresponding to the device 14 is electrically connected.
  • the gate of the second transistor S2 is electrically connected to the timing controller 13, the first electrode of the second transistor S2 is electrically connected to the data bus D corresponding to the gate 14, and the second electrode of the second transistor S1 is connected to the gate
  • the second data line D2 electrically connected to the pixel driving circuit 40 in the sub-pixel P in the same column corresponding to the device 14 is electrically connected.
  • the second electrode of the first transistor S1 is electrically connected to the first data line D1(m) electrically connected to the even-numbered row of sub-pixels P, and the second electrode of the second transistor S2 and The second data line D2(m) electrically connected to the odd-numbered rows of sub-pixels P is electrically connected.
  • the second transistor S2 is turned on, the first transistor S1 is turned off, and the data signal from the source driver 12 is transmitted to the second transistor S2 through the second transistor S2.
  • the second data line D2(m) electrically connected to the two transistors S2 data is written in the odd-numbered rows of sub-pixels P electrically connected to the second data line D2(m).
  • the first transistor S1 is turned on, the second transistor S2 is turned off, and the data signal from the source driver 12 is transmitted to the second transistor through the first transistor S1.
  • the first data line D1(m) electrically connected to a transistor S1 data is written in the even-numbered rows of sub-pixels P electrically connected to the first data line D1(m).
  • FIG. 3 is a structural diagram of the pixel driving circuit 40 corresponding to area B in FIG. 2A.
  • Fig. 3 illustrates that the pixel drive circuit 40 has a 7T1C (ie, 7 transistors, one storage capacitor) structure.
  • the pixel drive circuit 40 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a second transistor.
  • the fifth transistor T5 is a driving transistor.
  • FIG. 4A is a layout diagram corresponding to the pixel driving circuit 40 in the E area in FIG. 3.
  • the gate 211 of the first transistor T1 is electrically connected to the enable signal line EM
  • the first electrode 212 is electrically connected to the first power line VDD and to the first electrode Cst1 of the storage capacitor C
  • the second electrode 213 is electrically connected to the first electrode Cst1 of the third transistor T3.
  • the second pole 233 and the first pole 252 of the fifth transistor T5 are electrically connected.
  • the gate 221 of the second transistor T2 is electrically connected to the enable signal line EM, and the first electrode 222 is electrically connected to the first electrode 242 of the fourth transistor T4 and the second electrode 253 of the fifth transistor T5.
  • the gate 231 of the third transistor T3 is electrically connected to the gate line GATE, and the first electrode 232 is electrically connected to the first data line D1.
  • the fourth transistor T4 and the fourth transistor T4 are double-gate transistors.
  • the gate 241 of the fourth transistor T4 is electrically connected to the gate line GATE, and the second electrode 243 is electrically connected to the second electrode Cst2 of the storage capacitor C.
  • the fourth transistor T4 is configured to compensate the threshold voltage of the fifth transistor T5.
  • the gate 261 of the sixth transistor T6 is electrically connected to the reset signal line RESET, the first electrode 262 is electrically connected to the initialization signal line VINT, and the second electrode 263 is electrically connected to the second electrode Cst2 of the storage capacitor C.
  • the sixth transistor T6 is configured to initialize the second pole Cst2 of the storage capacitor C and the gate 251 of the fifth switching transistor T5 through the initialization signal line VINT under the control of the reset signal line RESET.
  • the second pole Cst2 of the storage capacitor C serves as the gate 251 of the fifth transistor T5 at the same time, and the first pole Cst1 of the storage capacitor C is connected to the first power line VDD through a via hole.
  • the pixel driving circuit 40 is configured to drive the light emitting device L (please refer to FIG. 3) to operate.
  • the first electrode of the light emitting device L is electrically connected to the first electrode 28 (please refer to FIG. 4A) through the via hole
  • the second electrode of the light emitting device L is electrically connected to the second power line VSS
  • the first electrode 28 is electrically connected to the first electrode 28 through the via hole.
  • the second pole 223 of the two transistors T2 is electrically connected.
  • the gate 271 of the seventh transistor T7 is electrically connected to the reset signal line RESET, the first electrode 272 is electrically connected to the initialization signal line VINT, and the second electrode 273 is electrically connected to the first electrode of the light emitting device L (not shown).
  • the seventh transistor T7 is configured to initialize the first pole of the light emitting device L through the initialization signal line VINT under the control of the reset signal line RESET.
  • the first pole of each transistor included in the pixel driving circuit 40 is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain,
  • the second pole is the source.
  • FIG. 4A FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A and FIG.
  • the material of the light shielding pattern 30 is metal.
  • the performance of the driving transistor has a great influence on the performance of the pixel driving circuit 40.
  • the influence of light incident on the pixel driving circuit 40 from the outside on the driving transistor can be avoided, and the stability of the driving transistor can be ensured.
  • the parasitic capacitance formed between adjacent data lines is relatively large, so the change of the signal on one data line is likely to affect the adjacent data line in a floating state. Affects the signal, causing horizontal crosstalk and poor display.
  • the adjacent data lines here are, for example, the first data line D1 and the second data line D2 arranged adjacently; the first data line D1 and the second data line D2 arranged adjacently include the following situations: 1. As shown in FIG. 2A As shown, the first data line D1 and the second data line D2 between the two adjacent columns of sub-pixels P are electrically connected to the corresponding sub-pixels P in the two columns of sub-pixels P; 2. As shown in 2B, the first data line D and the second data line D2 located on both sides of the sub-pixel P in the same column are electrically connected to the corresponding sub-pixel P in the sub-pixel P in the same column.
  • a plurality of first data lines (D1(1) ⁇ D1(m)) and a plurality of second data lines (D2(1) ⁇ D2(m)) are driven along the pixels
  • the circuit 40 is arranged alternately in the row direction, that is, alternately arranged along the row direction in which the sub-pixels P are arranged.
  • a first data line D1 and a second data line D2 are arranged between two adjacent columns of sub-pixels P.
  • the row direction is the X direction
  • the column direction is the Y direction.
  • the first data line D1(1) is arranged on the left side of the pixel driving circuit 40 in the first column, and the second data line D2(1) is arranged on the right side of the pixel driving circuit 40 in the first column;
  • the data line D1(2) is arranged on the left side of the second column pixel driving circuit 40, and the second data line D2(2) is arranged on the right side of the second column pixel driving circuit 40;
  • a data line D1(2) is adjacently arranged between the pixel driving circuit 40 in the first column and the pixel driving circuit 40 in the second column.
  • the first data line D1(m-1) is arranged on the left side of the pixel driving circuit 40 in the m-1th column, and the second data line D2(m-1) is arranged on the pixel driving circuit 40 in the m-1th column.
  • the first data line D1 (m) is set on the left side of the m-th column pixel driving circuit 40, and the second data line D2 (m) is set on the right side of the m-th column pixel driving circuit 40; the second data line D2(m-1) and the first data line D1(m) are adjacently arranged between the pixel driving circuit 40 in the m-1th column and the pixel driving circuit 40 in the m-th column.
  • the adjacently arranged first data line D1 and the second data line D2 are arranged in parallel, the first data line D1 and the second data line D2 have a facing area, and the adjacent first data line D1 and The portion facing the area of the second data line D2 forms a parasitic capacitor Cp as shown in FIG. 4B, that is, the first data line D1 and the second data line D2 respectively serve as two plates of the parasitic capacitor Cp, the first data line D1 and The insulating layer between the second data line D2 serves as the dielectric of the parasitic capacitor Cp, and the capacitance of the parasitic capacitor Cp is
  • ⁇ rp1 relative permittivity of the insulating layer between the first data line D1 and the second data line D2
  • S p is the first data line D1 and the second data line D2 of the alignment area
  • d p is the first The distance between the borders of one data line D1 and the second data line D2 that are close to each other
  • k is the electrostatic force constant
  • ⁇ is the pi.
  • two adjacent columns of sub-pixels P are both first data lines D1 or both It is the second data line D2.
  • the first data line D1(1) is arranged on the left side of the pixel driving circuit 40 in the first column, and the second data line D2(1) is arranged on the right side of the pixel driving circuit 40 in the first column;
  • the data line D2(2) is arranged on the left side of the pixel driving circuit 40 in the second column, and the first data line D1(2) is arranged on the right side of the pixel driving circuit 40 in the second column.
  • the first data line D1(m-1) is arranged on the left side of the pixel driving circuit 40 in the m-1th column
  • the second data line D2(m-1) is arranged on the pixel driving circuit 40 in the m-1th column.
  • the second data line D2(m) is provided on the left side of the pixel driving circuit 40 in the mth column
  • the first data line D1(m) is provided on the right side of the pixel driving circuit 40 in the mth column.
  • the first data line D1 and the second data line D2 which are separately arranged on both sides of the pixel driving circuit 40 in the same column, are arranged in parallel.
  • the first data line D1 and the second data line D2 have a facing area, which
  • the parasitic capacitor Cp as shown in FIG. 4B is also formed for the area portion, that is, the first data line D1 and the second data line D2 are respectively used as the two plates of the parasitic capacitor Cp, the first data line D1 and the second data line D2
  • the insulating layer between and the pixel drive circuit 40 serves as the dielectric of the parasitic capacitor Cp, and the capacitance of the parasitic capacitor Cp is
  • ⁇ rp2 is the relative permittivity of the insulating layer 40 and the pixel driving circuit between the first data line D1 and the second data line D2
  • S p is the first data line D1 and the second data line D2 of the alignment area
  • D p is the distance between the first data line D1 and the second data line D2
  • k is the electrostatic force constant
  • ⁇ is the circumference ratio.
  • the capacitance of the parasitic capacitor Cp is a parasitic capacitance, that is, originally there is no capacitance designed between the adjacent first data line D1 and the second data line D2, but due to the adjacent first data line D1 and the second data line D1 There is mutual capacitance between the data lines D2, so parasitic capacitances are generated on the adjacent first data line D1 and the second data line D2.
  • FIG. 4B shows an equivalent circuit diagram of a parasitic capacitor Cp formed between the first data line D1 and the second data line D2.
  • the second data line D2 is in a floating state. Since a parasitic capacitor Cp is formed between the second data line D2 and other layers of the display panel 101, the parasitic capacitor Cp continues to write data to the odd-numbered rows of sub-pixels P to increase the data writing time. At the same time, the parasitic capacitor Cp also passes through the A data line D1 writes data to the even-numbered sub-pixels P, that is, at this time, the potential of the first data line D1 will jump, and the jump amount is ⁇ V.
  • the display panel 101 includes an array of multiple One pixel driving circuit 40, a plurality of first data lines D1, a plurality of second data lines D2, and at least one shielding line LS.
  • the first data line D1 is electrically connected to pixel driving circuits 40 in even rows in the same column of pixel driving circuits 40 (ie, the same column of sub-pixels P).
  • the second data line D2 is electrically connected to pixel driving circuits 40 in odd rows in the same column of pixel driving circuits 40 (ie, the same column of sub-pixels P).
  • a parasitic capacitor Cp is formed between the adjacent first data line D1 and the second data line D2.
  • the shielding line LS is configured to transmit a fixed voltage, for example, the shielding line LS is directly connected to the fixed voltage, or the shielding line LS is electrically connected to the original signal line (such as the initialization signal line VINT) in the display panel that transmits the fixed voltage, or the shielding line LS It is electrically connected to the fixed potential terminal U that transmits a fixed voltage, where the fixed voltage can be 0V, 5V, or 15V, as long as the voltage remains unchanged during the operation of the display panel 101, and the value of the fixed voltage is not required .
  • the shielding line LS and the first data line of the adjacent first data line D1 and second data line D2 form a first capacitor C1.
  • the shielding line LS and the second data line D2 of the adjacent first data line D1 and the second data line D2 form a second capacitor C2.
  • the same shield line LS forms a first capacitor C1 with the adjacent first data line D1 and the second data line D2, and is connected to the adjacent first data line D1 and D2.
  • the data line D1 and the second data line D2 of the second data line D2 form a second capacitor C2.
  • shielding lines LS there are two shielding lines LS: a first shielding line LS1 and a second shielding line LS2; among them, the first shielding line LS1 is connected to the adjacent first data line D1 and second data line LS2.
  • the first data line D1 in the line D2 forms a first capacitor C1
  • the second shield line LS2 and the adjacent first data line D1 and the second data line D2 of the second data line form a second capacitor C2.
  • the shielding line LS is arranged in the same layer as the first data line D1 and the second data line D2, and is arranged between the first data line D1 and the second data line D2.
  • the same shield line LS forms a first capacitor C1 with the adjacent first data line D1 and the second data line D2, and is connected to the adjacent first data line D1 and the second data line D2.
  • the second data line D2 forms a second capacitor C2.
  • the parasitic capacitor Cp and the second capacitor C2 are connected in series, and the second plate of the parasitic capacitor Cp serves as the first plate of the second capacitor C2.
  • the second plate jump amount of the parasitic capacitor Cp is [Cp/(Cp+C2)] ⁇ V ⁇ ⁇ V, that is, the jump amount of the potential on the second data line D2 is [Cp/(Cp+C2)] ⁇ V, which can reduce the influence on the potential of the second data line D2, thereby reducing lateral crosstalk and improving poor display .
  • the parasitic capacitor Cp and the first capacitor C1 are connected in series, and the first plate of the parasitic capacitor Cp serves as the first plate of the first capacitor C1.
  • the jump amount is ⁇ V
  • the jump value of the first plate of the parasitic capacitor Cp is [Cp/(Cp+C1)] ⁇ V ⁇ V, that is, the jump value of the potential on the first data line D1 is [Cp/( Cp+C1)] ⁇ V, thus reducing the influence on the potential of the first data line D1, thereby reducing lateral crosstalk and improving poor display.
  • the shielding line LS and the first data line D1 of the first data line D1 and the second data line D2 form a first capacitor C1
  • the same shielding line LS is the same as the first data line D1 and the second data line D1.
  • the second data line D2 in D2 forms a second capacitor C2, that is, the same shield line LS corresponds to a group of adjacent first data lines D1 and D2 connected to different rows of sub-pixels P.
  • the number of shielding lines LS corresponding to a group of adjacent first data line D1 and second data line D2 connected to different rows of sub-pixels P is two.
  • the same shielding line LS corresponds to a group of adjacent first data lines D1 and D2 that are connected to different rows of sub-pixels P, and the shielding line LS is disposed on the adjacent first data lines D1 and D2. Between the second data lines D2.
  • FIG. 7C The equivalent circuit diagrams of FIG. 7B, FIG. 8B and FIG. 9B are all shown in FIG. 7C, which is equivalent to that the first capacitor C1 and the second capacitor C2 are respectively connected in series with the parasitic capacitor Cp.
  • the function principle of the shielded line LS is as described above, and will not be repeated here. On this basis, the influence between the adjacent first data line D1 and the second data line D2 can be reduced, lateral crosstalk can be reduced, and poor display can be improved.
  • the capacitance of the first capacitor C1 is approximately equal to the capacitance of the second capacitor C2, so as to ensure that the first data line D1 and the second data line D2 are approximately the same amount of jump when they are affected by the potential, so that the lateral crosstalk of the two data lines
  • the first data line D1 and the second data line D2 are approximately the same degree of reduction in the amount of jump when affected by the potential, so that the display of the display panel 101 is uniform.
  • the adjacent first data line D1 and the second data line D2 are relatively close, resulting in a large capacitance of the parasitic capacitor Cp, and the adjacent first data line D1 and the second data line D2 affect each other more seriously
  • the shielding line LS By providing the shielding line LS, the influence between the adjacent first data line D1 and the second data line D2 can be reduced, lateral crosstalk can be reduced, and poor display can be improved.
  • the orthographic projection of the shield line LS on the substrate 10 and The orthographic projection of the first data line D1 on the substrate 10 at least partially overlaps, and the area of the overlapped portion is S 1 , then the capacitance of the first capacitor C1 is
  • ⁇ r1 is the relative permittivity of the insulating layer between the first data line D1 and the shielding line LS
  • d 1 is the distance between the shielding lines LS of the first data line D1
  • k is the electrostatic force constant.
  • the orthographic projection of the shielding line LS on the substrate 10 and the second data line D2 are The orthographic projections on the substrate 10 at least partially overlap, and the area of the overlap portion is S 2 , then the capacitance of the second capacitor C2 is Where ⁇ r1 is the relative permittivity of the insulating layer between the second data line D2 and the shielding line LS, d 2 is the distance between the second data line D2 and the shielding line LS, and k is the electrostatic force constant.
  • the shield line LS is configured to transmit a fixed voltage.
  • the first shielding line LS1 and the second shielding line LS2 are connected to the same fixed voltage; for example, both the first shielding line LS1 and the second shielding line LS2 are electrically connected to the second power line VSS.
  • VSS the second power line
  • the first shielding line LS1 and the second shielding line LS2 can be respectively connected to different fixed voltages; for example, the first shielding line LS1 is electrically connected to the initialization signal line VINT, and the second shielding line LS2 is connected to the first power line VDD. Electric connection.
  • the lines in the display panel 101 can be flexibly arranged to avoid excessive local wiring.
  • some of the original components in the display panel 101 transmit a fixed voltage. Therefore, the original components of the display panel 101 (such as signal lines or terminals) that transmit a fixed voltage can be used to fix the shielding line LS. In this way, there is no need to provide an additional structure for transmitting a fixed voltage to the shielding line LS, which can simplify the manufacturing process and simplify the internal structure of the display panel.
  • the following introduces several possible designs for using the existing structure in the display panel 101 to connect the shielded line LS with a fixed voltage.
  • the display panel 101 further includes a first power supply line VDD connected to a plurality of pixel driving circuits 40, and the first power supply line VDD is configured to transmit the first power supply line VDD to the pixel driving circuit 40.
  • a voltage signal; the shield line LS is electrically connected to the first power line VDD.
  • the first power line VDD includes a sub power line VDD2 located in the display area AA, and a power bus VDD1 located in the peripheral area S and electrically connected to the sub power line VDD2 ;
  • the sub-power supply line VDD2 is electrically connected to the pixel driving circuit 40.
  • the shield line LS is electrically connected to the power bus VDD1.
  • the shield line LS is electrically connected to the power bus VDD1 through a via H1 provided in the peripheral area S Therefore, it is avoided that holes are punched in the display area AA of the display panel 101, and the effective light-emitting area of the display area AA is prevented from being occupied by via holes.
  • only one via is schematically drawn, and there may be one or more vias connecting the two.
  • the shielding line LS is electrically connected to the sub-power supply line VDD2.
  • the shielding line LS and the sub-power supply line VDD2 closest to the shielding line LS are electrically connected through the via H2. This simplifies the structure of electrically connecting the shield line LS and the sub-power supply line VDD2.
  • the molecular power supply line VDD2 and the power supply bus VDD1 are not distinguished in Figure 5A. Since the sub-power supply line VDD2 and the power supply bus VDD1 both transmit VDD signals, the line that transmits the VDD signal in the figure is marked as VDD. In fact The VDD line in FIG. 5A corresponds to the sub-power supply line VDD2 in FIG. 10.
  • the display panel 101 further includes a second power line VSS.
  • the second power line VSS is electrically connected to the second electrode of the element to be driven (for example, the light emitting device L), and is configured to The driving element transmits the second voltage signal, so that there is a voltage difference between the first pole and the second pole of the element to be driven, and the element to be driven works (for example, emits light) under the action of the pressure difference;
  • the shielding line LS is in the peripheral area S It is electrically connected to the second power line VSS through the via hole H3 to avoid punching a via hole in the display area AA and avoid the via hole occupying the effective light-emitting area of the display area AA.
  • only one via is schematically drawn, and there may be one or more vias connecting the two.
  • the circuit boards such as the first power line VDD and the second power line VSS are bonded through the bonding pad CP (that is, COF PAD).
  • the bonding pad CP that is, COF PAD
  • the first data line D1 and the second power line D1 are bonded together.
  • the second data line D2 is connected to the binding pad CP through the fan-out area DF (that is, Data Fanout) for binding.
  • the display panel 101 further includes an initialization signal line VINT.
  • the initialization signal line VINT is electrically connected to the pixel drive circuit 40 and is configured to transmit an initialization signal to the pixel drive circuit 40, for example As shown in FIG. 3, the initialization signal line VINT is used to initialize the potential of the gate 251 of the fifth transistor T5 and the anode of the light emitting device L; the shield line LS is electrically connected to the initialization signal line VINT.
  • the initialization signal line VINT includes a sub initialization signal line VINT2 located in the display area AA, and an initialization signal bus VINT1 located in the peripheral area S and electrically connected to the sub initialization signal line VINT2; the sub initialization signal line VINT2 and The pixel driving circuit 40 is electrically connected.
  • the shielding line LS is electrically connected to the initialization signal bus VINT1.
  • the shielding line LS is connected to the initialization signal bus VINT1 through the via H4 provided in the peripheral area S. It is electrically connected, so as to avoid punching holes in the display area AA of the display panel 101, and prevent via holes from occupying the effective light-emitting area of the display area AA.
  • only one via is schematically drawn, and there may be one or more vias connecting the two.
  • the shielding line LS is electrically connected to the sub-initialization signal line VINT2.
  • the shielding line LS and the sub-initialization signal line VINT2 closest to the shielding line LS pass through the via hole.
  • H5 is electrically connected to simplify the structure of electrically connecting the shielding line LS and the sub-initialization signal line VINT2.
  • the molecular initialization signal line VINT2 and the initialization signal bus VINT1 are not distinguished in Figure 5A. Since the sub-initialization signal line VINT2 and the initialization signal bus VINT1 both transmit the VINT signal, the line that transmits the VINT signal in the figure is marked as VINT, in fact, the VINT line in FIG. 5A corresponds to the sub-initialization signal line VINT2 in FIG. 13.
  • the display panel further includes an element to be driven (please refer to the light emitting device L in FIG. 1B), and the shielding line LS is electrically connected to the second pole of the element to be driven through a via H6.
  • the element to be driven may be, for example, an OLED.
  • the component to be driven includes a first pole and a second pole.
  • the first pole may be an anode L2, and the second pole may be a cathode L3 (refer to FIG. 1B).
  • the shielding line can be set in the same layer as some original film layers of the display panel 101 during the specific setting process, thereby reducing the process steps and simplifying the manufacturing process.
  • the following are some embodiments when the shielding wires are arranged on different layers of the display panel 101.
  • the same layer setting refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a patterning process.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the shielding line LS is arranged on the film layer where the light shielding pattern between the source and drain conductive layer and the substrate 10 is located, and the shielding line LS and the light shielding pattern 30 material Same and same layer settings.
  • the shielding line LS and the light shielding pattern 30 can be made at the same time as the light shielding pattern 30 is made, which simplifies the manufacturing process.
  • the distance d1 between the adjacently arranged first data line D1 and the second data line D2 is greater than the vertical distance d2 between the shielding line and the film layer where the first data line D1 and the second data line D2 are located, Therefore, by controlling the distance between the plates, the capacitance of the parasitic capacitor Cp is controlled to be smaller than the capacitance of the first capacitor C1 and the second capacitor C2, and the voltage division effect of the first capacitor C1 and the second capacitor C2 is enhanced, and the pair of parasitic capacitor Cp is reduced.
  • the influence of the status of the data line reduces the jump of the data line voltage.
  • the distance d1 between the adjacent first data line D1 and the second data line D2 is between the adjacent first data line D1 and the second data line D2, the center line of the first data line D1 to And the distance between the center line of the second data line D2.
  • the parasitic capacitance generated between the adjacently arranged first data line D1 and the second data line D2 is smaller than the capacitance of the first capacitor C1 and/or the capacitance of the second capacitor C2, thereby ensuring that the first capacitor C1 and The voltage dividing effect of the second capacitor C2 is obvious, and the effect of the parasitic capacitor Cp on the data line in the floating state is reduced.
  • the means for controlling the capacitance of the parasitic capacitor to be smaller than the capacitance of the first capacitor C1 and the second capacitor C2 includes increasing the area of the shield line LS directly facing the first data line D1 and/or the second data line D2.
  • the vertical distance d2 between the shielding line LS and the film layer where the first data line D1 and the second data line D2 are located ranges from 0.75 ⁇ m to 1 ⁇ m, for example, 0.75 ⁇ m, 0.8 ⁇ m, 0.85 ⁇ m, 0.9 ⁇ m, 1 ⁇ m.
  • the distance d1 between the adjacent first data line D1 and the second data line D2 is 4 ⁇ m to 8 ⁇ m, for example, 4 ⁇ m, 4.8 ⁇ m, 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m, 6.3 ⁇ m, 7 ⁇ m, 8 ⁇ m.
  • the shielding line LS and the light shielding pattern 30 are arranged in the same layer, and the vertical distance d2 between the shielding line LS and the film layer where the first data line D1 and the second data line D2 are located ranges from 0.8 ⁇ m to 0.9 ⁇ m , For example, 0.8 ⁇ m, 0.85 ⁇ m, or 0.9 ⁇ m.
  • the shielding line LS and the light shielding pattern 30 are arranged in the same layer, and the distance d1 between the adjacent first data line D1 and the second data line D2 is 5 ⁇ m-7 ⁇ m, for example, 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m or 7 ⁇ m.
  • first data line D1 and the second data line D2 are arranged in the same layer, and the shielding line LS is arranged between the film layer (that is, the source-drain conductive layer) where the first data line and the second data line are located and the substrate 10
  • At least an interlayer dielectric layer ILD and a gate insulating layer GI should be arranged between the source and drain conductive layer and the shielding line LS.
  • the thickness of the interlayer dielectric layer ILD is at least 0.5 ⁇ m
  • the thickness of the gate insulating layer GI is at least 0.25 ⁇ m
  • the distance d2 between the source-drain conductive layer and the shield line LS is at least 0.75 ⁇ m.
  • the source and drain conductive layer is between the shielding line LS
  • the distance d2 is at least 1 ⁇ m.
  • the shielding line LS and the adjacent first data line D1 and the second data line D2 have the same film layer material and are arranged in the same layer.
  • the adjacent first data line D1 and the second data line D2 are connected to the sub-pixels in different rows, and the shield line LS is located between the adjacent first data line D1 and the second data line D2.
  • a side surface of a data line D1 opposite to the first data line D1 forms a first capacitor C1
  • a side surface of the shield line LS opposite to the second data line D2 forms a second capacitor C2 with the second data line D2.
  • the shielding line LS can be manufactured at the same time as the first data line D1 and the second data line D2, which simplifies the manufacturing process.
  • the shielding line LS is disposed on a side of the film layer where the first data line D1 and the second data line D2 are located away from the substrate 10.
  • the horizontal crosstalk of the data line is detected on the display panel 101 without the shield line LS and the display panel 101 with the shield line LS, and the results are as follows:
  • the shielding layer LS when the shielding layer LS is provided under the adjacent first data line D1 and the second data line D2, and the shielding layer LS and the first data line D1 form a first capacitor C2, when the second data line
  • the shielding layer LS can reduce the impact on the first data line D1.
  • the influence of the potential on the upper side reduces lateral crosstalk and improves poor display.
  • an embodiment of the present disclosure provides a display device 100 including the above-mentioned display panel 101.
  • the display device 100 may be any device that displays images, whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (PDAs).
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.

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Abstract

一种显示面板及显示装置，显示面板（101）包括衬底（10）、多个像素驱动电路（40）、多条第一数据线（D1）、多条第二数据线（D2）和至少一条屏蔽线（LS），多个像素驱动电路（40）阵列分布，第一数据线（D1）与同一列像素驱动电路（40）中处于偶数行的像素驱动电路（40）电连接，第二数据线（D2）与同一列像素驱动电路（40）中处于奇数行的像素驱动电路（40）电连接；相邻设置的第一数据线（D1）和第二数据线（D2）之间具有正对面积，至少一条屏蔽线（LS）被配置为传输固定电压；屏蔽线（LS）与相邻设置的第一数据线（D1）和第二数据线（D2）中的第一数据线（D1）形成第一电容器（C1），和/或，所述屏蔽线（D2）与相邻设置的第一数据线（D1）和第二数据线（D2）中的第二数据线（D2）形成第二电容器（C2）。显示装置包括显示面板。

Description

显示面板及显示装置
本申请要求于2020年05月28日提交的、申请号为202010470315.8、申请名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示面板向高分辨率和高刷新频率的方向发展，每一行亚像素对应的写入数据的时间和补偿阈值电压的时间减少。
针对每列亚像素对应的设置两条数据线，将两条数据线中的一条数据线与处于奇数行的亚像素电连接，另一条第二数据线与处于偶数行的亚像素电连接，这样的源极驱动架构可以增加写入数据的时间和补偿阈值电压的时间。
发明内容
一方面，提供一种显示面板，所述显示面板包括衬底、多个像素驱动电路、多条第一数据线、多条第二数据线和至少一条屏蔽线。
所述多个像素驱动电路阵列分布。第一数据线与同一列像素驱动电路中处于偶数行的像素驱动电路电连接。第二数据线与同一列像素驱动电路中处于奇数行的像素驱动电路电连接；相邻设置的第一数据线和第二数据线之间具有正对面积。至少一条屏蔽线被配置为传输固定电压；所述屏蔽线与相邻设置的第一数据线和第二数据线中的第一数据线形成第一电容器，和/或，所述屏蔽线与相邻设置的第一数据线和第二数据线中的第二数据线形成第二电容器。
在一些实施例中，所述第一电容器的电容与所述第二电容器的电容大致相等。
在一些实施例中，所述屏蔽线与第一数据线形成第一电容器，所述屏蔽线在所述衬底上的正投影与所述第一数据线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述屏蔽线与第二数据线形成第二电容器，所述屏蔽线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述显示面板包括多条屏蔽线，所述多条屏蔽线 包括至少一条第一屏蔽线和至少一条第二屏蔽线。所述第一屏蔽线与相邻设置的第一数据线和第二数据线中的第一数据线形成所述第一电容器。所述第二屏蔽线与相邻设置的第一数据线和第二数据线中的第二数据线形成第二电容器。
在一些实施例中，所述显示面板还包括：待驱动元件、第一电源线、第二电源线和初始化信号线。
所述待驱动元件的第一极与所述像素驱动电路电连接。所述第一电源线与所述像素驱动电路电连接，所述第一电源线被配置为向所述像素驱动电路传输第一电压信号。所述第二电源线与所述待驱动元件的第二极电连接，所述第二电源线被配置为向所述待驱动元件传输第二电压信号。所述初始化信号线与所述像素驱动电路电连接，所述初始化信号线被配置为向所述像素驱动电路传输初始化信号。
其中，所述屏蔽线与所述第一电源线、所述第二电源线、所述待驱动元件的第二极或所述初始化信号线电连接。
在一些实施例中，所述显示面板包括显示区和周边区。所述第一电源线包括位于所述显示区的子电源线，及位于所述周边区且与所述子电源线电连接的电源总线。所述子电源线与所述像素驱动电路电连接。其中，所述屏蔽线与所述子电源线和/或所述电源总线电连接。
在一些实施例中，所述屏蔽线与距离所述屏蔽线最近的子电源线电连接；和/或，所述屏蔽线通过设置于所述周边区的过孔与所述电源总线电连接。
在一些实施例中，所述显示面板包括显示区和周边区；所述屏蔽线通过设置于所述周边区的过孔与所述第二电源线电连接。
在一些实施例中，所述显示面板包括显示区和周边区。所述初始化信号线包括位于所述显示区的子初始化信号线，及位于所述周边区且与所述子初始化信号线电连接的初始化信号总线。所述子初始化信号线与所述像素驱动电路电连接。其中，所述屏蔽线与所述子初始化信号线和/或所述初始化信号总线电连接。
在一些实施例中，所述屏蔽线与距离所述屏蔽线最近的子初始化信号线电连接；和/或，所述屏蔽线通过设置于所述周边区的过孔与所述初始化信号总线电连接。
在一些实施例中，所述至少一条屏蔽线设置于第一数据线和第二数据线所在膜层与所述衬底之间。
在一些实施例中，所述显示面板还包括遮光图案。所述遮光图案设置于像素驱动电路所在膜层与所述衬底之间。其中，所述屏蔽线与所述遮光图案材料相同且同层设置。
在一些实施例中，相邻设置的第一数据线与第二数据线之间的距离，大于所述屏蔽线与第一数据线和第二数据线所在膜层之间的垂直距离。
在一些实施例中，所述屏蔽线与第一数据线和第二数据线所在膜层之间的垂直距离为0.75μm～1μm；和/或，相邻设置的第一数据线和第二数据线之间的距离为4μm～8μm。
在一些实施例中，所述屏蔽线与第一数据线和第二数据线同层设置，且位于相邻设置的第一数据线和第二数据线之间。
在一些实施例中，相邻设置的第一数据线和第二数据线之间所产生的寄生电容小于所述第一电容器的电容和/或所述第二电容器的电容。
在一些实施例中，所述多条第一数据线与所述多条第二数据线沿所述多个像素驱动电路排列的行方向交替设置，且相邻设置的第一数据线和第二数据线位于相邻两列像素驱动电路之间。
在一些实施例中，相邻设置的第一数据线和第二数据线分别与处于不同行的像素驱动电路电连接。
另一方面，提供了一种显示装置，包括上述任一项所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的显示装置的示意图；
图1B为图1A中所示的显示面板沿CC’向的剖面图；
图2A为根据一些实施例的显示面板的一种源极驱动架构图；
图2B为根据一些实施例的显示面板的另一种源极驱动架构图；
图3为图2A中B区域的电路结构图；
图4A为图3中的E区域对应的一种结构图；
图4B为图4A中的第一数据线和第二数据线对应的等效电路图；
图5A为图3中的E区域对应的另一种结构图；
图5B为图5A中沿FF’向的剖面图；
图5C为图5A中第一数据线、第二数据线以及屏蔽线部分对应的等效电路图；
图6A为图3中的E区域对应的再一种结构图；
图6B为图6A中沿GG’向的剖面图；
图6C为图6A中第一数据线、第二数据线以及屏蔽线部分对应的等效电路图；
图7A为图3中的E区域对应的又一种结构图；
图7B为图7A中沿HH’向的剖面图；
图7C为图7A中第一数据线、第二数据线以及屏蔽线部分对应的等效电路图；
图8A为图3中的E区域对应的再一种结构图；
图8B为图8A中沿II’向的剖面图；
图9A为图3中的E区域对应的又一种结构图；
图9B为图8A中沿JJ’向的剖面图；
图10为根据一些实施例的屏蔽线与第一电源线连接的一种结构图；
图11为根据一些实施例的屏蔽线与第一电源线连接的另一种结构图；
图12为根据一些实施例的屏蔽线与第二电源线连接的一种结构图；
图13为根据一些实施例的屏蔽线与初始化信号线连接的一种结构图；
图14根据一些实施例的屏蔽线与初始化信号线连接的另一种结构图；
图15为根据一些实施例的屏蔽线与待驱动元件的第二极连接的一种结构图；
图16为根据一些实施例的显示面板没有设置屏蔽线时第一数据线和第二数据线上电位的仿真图；
图17为根据一些实施例的显示面板设置屏蔽线时第一数据线和第二数据线上电位的仿真图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获 得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1A所示，本公开的一些实施例提供一种显示装置，该显示装置100可以为电视、手机、电脑、笔记本电脑、平板电脑、个人数字助理(英文：Personal Digital Assistant，简称PDA)、车载电脑等。
该显示装置100包括显示面板101。该显示面板101可以为液晶显示面板(Liquid Crystal Display，简称LCD)；该显示面板101也可以为电致 发光显示面板或光致发光显示面板。在该显示面板101为电致发光显示面板的情况下，电致发光显示面板可以为有机电致发光(Organic Light-Emitting Diode，简称OLED)显示面板或量子点电致发光(Quantum Dot Light Emitting Diode，简称QLED)显示面板。在该显示面板101为光致发光显示面板的情况下，光致发光显示装置可以为量子点光致发光显示面板。
显示面板101包括阵列式排布的多个亚像素。以下以显示面板101为OLED显示面板为例，介绍显示面板101中一个亚像素的剖面结构。
如图1B所示，其中，显示面板101包括显示用基板31和用于封装显示用基板31的封装层32。此处，封装层32可以为封装薄膜，也可以为封装基板。
如图1B所示，上述显示用基板31的每个亚像素包括设置在衬底10上的发光器件L和像素驱动电路40，像素驱动电路40包括多个薄膜晶体管TFT。发光器件L包括阳极L1、发光功能层L2以及阴极L3，阳极L1和多个薄膜晶体管TFT中的一个的漏极电连接。
如图1B所示，薄膜晶体管TFT包括栅极Gate、源极Source、漏极Drain以及半导体有源层20。可选地，在一些顶栅结构的薄膜晶体管TFT(如图5B)中，利用栅极Gate进行自对准工艺控制，在半导体有源层20上形成沟道CH以及源极接触部Source’和漏极接触部Drain’，此时，源极接触部Source’等同于源极Source，漏极接触部Drain’等同于漏极Drain。
在此基础上，沿显示用基板31的厚度方向，且远离所述显示用基板31的方向，显示用基板31依次包括半导体层(即半导体有源层20所在膜层)、栅导电层(即栅极Gate所在膜层)和源漏导电层(即源极Source、漏极Drain所在膜层)。
显示用基板31还包括像素界定层314，像素界定层314包括多个开口区，一个发光器件L设置在一个开口区中。在一些实施例中，发光功能层L2包括发光层。在另一些实施例中，发光功能层L2除包括发光层外，还包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)中的一层或多层。
如图1B所示，显示用基板31还包括设置在薄膜晶体管TFT和阳极L1之间的平坦层315。
除此之外，显示用基板31还可包括：位于衬底10与半导体层之间的缓冲层Buffer，位于半导体层与栅导电层之间的栅极绝缘层GI，位于栅导电层与源漏导电层之间的层间介质层ILD，及位于源漏导电层与平坦层315之间的钝化层PVX。在一些实施例中，显示用基板31包括两层栅导电层，即第一栅导电层和第二栅导电层，此时显示用基板31包括两层栅极绝缘层GI，即第一栅极绝缘层和第二栅极绝缘层。在此情况下，沿显示用基板31的厚度方向，且远离所述显示用基板31的方向，显示用基板31依次包括半导体层、第一栅极绝缘层、第一栅导电层、第二栅极绝缘层、第二栅导电层、层间介质层ILD、源漏导电层、钝化层PVX和平坦层315等。
当显示装置100为电致发光显示装置或光致发光显示装置时，显示装置100可以是顶发射型显示装置，在此情况下，靠近衬底10的阳极L1不透明，远离衬底10的阴极L3透明或半透明；显示装置100也可以是底发射型显示装置，在此情况下，靠近衬底10的阳极L1透明或半透明，远离衬底10的阴极L3不透明；显示装置100也可以为双面发光型显示装置，在此情况下，靠近衬底10的阳极L1和远离衬底10的阴极L3均透明或半透明。
如图2A和图2B所示，在一些实施例中，显示面板101具有显示区(Active Area，简称AA区)和周边区S。
其中，周边区S位于AA区至少一侧。
示例性地，周边区S可以位于AA区一圈设置。
显示面板101包括多个亚像素P，多个亚像素P位于AA区。该多个亚像素P至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
其中，图2A和图2B以上述多个亚像素P呈n行m列的阵列形式排列为例进行示意，其中n和m均为正整数。
在此基础上，每个亚像素P中均包括像素驱动电路40(参照图1A和图1B)和待驱动元件(例如发光器件L，参照图1A和1B，以下以待驱动元件为发光器件L为例进行说明)，该像素驱动电路40与其对应的发光器件L电连接，像素驱动电路40用于驱动发光器件L工作。该发光器件L还与第二电源线VSS(参照图15)电连接。
示例性地，发光器件L可以为微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode， Mini LED)或者有机电致发光二极管(Organic Light Emitting Diode，OLED)。
为了增加写入数据的时间和补偿阈值电压的时间，提出了双数据线的源极驱动架构，在这种源极驱动架构中，每一列亚像素P与两条数据线电连接。下面对该源极驱动架构进行介绍。
如图2A和图2B所示，显示面板101包括设置于周边区S的扫描驱动器11、源极驱动器12、时序控制器13和多个选通器14。
其中，一个选通器14对应一列亚像素P。
扫描驱动器11与栅线GATE和时序控制器13电连接。
可以理解的是，如图2A和图2B所示，在显示面板101有n行亚像素P的情况下，从与第一行亚像素P中的像素驱动电路40电连接的栅线GATE_(1)至与第n行亚像素P中的像素驱动电路40电连接的栅线GATE_(n)，均与扫描驱动器11电连接。
源极驱动器12与选通器14和时序控制器13电连接。
选通器14还与时序控制器13，以及与该选通器14对应的同一列亚像素P中的像素驱动电路40电连接的两根数据线电连接。
可以理解的是，在显示面板101有m列亚像素P的情况下，选通器14的个数相应为m个，且每个选通器14分别通过一根数据线总线D与源极驱动器12电连接，该数据总线D的个数为m个。
例如，如图2A和图2B所示，第一列亚像素P对应的选通器14通过一根数据总线D(1)与源极驱动器12电连接，第二列亚像素P对应的选通器14通过一根数据总线D(2)与源极驱动器12电连接，第m列亚像素对应的选通器14通过一根数据总线D(m)与源极驱动器12电连接。
在此情况下，同一列亚像素P中的像素驱动电路40与第一数据线D1和第二数据线D2电连接，其中第一数据线D1与偶数行亚像素P中的像素驱动电路40电连接，第二数据线D2与奇数行亚像素P中的像素驱动电路40电连接。
可以理解的是，一列亚像素P中，奇数行亚像素P中的像素驱动电路40和与这一列亚像素P对应的选通器14通过第二数据线D2电连接，偶数行亚像素P中的像素驱动电路40和与这一列亚像素P对应的选通器14通过第一数据线D1电连接。
示例性地，如图2A和图2B所示，第一列亚像素P中，奇数行亚像 素P中的像素驱动电路40通过第二数据线D2(1)与第一列亚像素P对应的选通器14电连接，偶数行亚像素P中的像素驱动电路40通过第一数据线D1(1)与第一列亚像素P对应的选通器14电连接。
第二列亚像素中，奇数行亚像素P中的像素驱动电路40通过第二数据线D2(2)和与第二列亚像素P对应的选通器14电连接，偶数行亚像素P中的像素驱动电路40通过第一数据线D1(2)和与第二列亚像素P对应的选通器14电连接。
第m列亚像素中，奇数行亚像素P中的像素驱动电路40通过第二数据线D2(m)和与第m列亚像素P对应的选通器14电连接，偶数行亚像素P中的像素驱动电路40通过第一数据线D1(m)与第m列亚像素P对应的选通器14电连接。
在此基础上，扫描驱动器11被配置为在来自时序控制器13的信号的控制下，向栅线GATE逐行输出栅极扫描信号。
可以理解的是，在显示面板有n行亚像素P的情况下，扫描驱动器11在来自时序控制器13的信号的控制下，从第一行至第n行(GATE_1～GATE_n)逐行依次输出栅极扫描信号。
源极驱动器12被配置为在来自时序控制器13的信号的控制下，向选通器14输出数据信号。
选通器14被配置为在来自时序控制器13的信号的控制下，在不同时间段，将来自源极驱动器12的数据信号传输至与该选通器14对应的同一列亚像素P中的像素驱动电路40电连接的两根数据线中的第一数据线D1、以及与该选通器14对应的同一列亚像素P中的像素驱动电路40电连接的两根数据线中的第二数据线D2。
可以理解的是，对于第m列亚像素P，在奇数行亚像素P写入数据时，选通器14在时序控制器13的控制下，将来自源极驱动器12的数据信号传输至与该选通器14电连接的第二数据线D2(m)中，使得与数据总线D(m)电连接的奇数行亚像素P写入数据。在偶数行亚像素P写入数据时，选通器14在时序控制器13的控制下，将来自源极驱动器12的数据信号传输至与该选通器14电连接的第一数据线D1(m)中，使得与数据总线D(m)电连接的偶数行亚像素P写入数据。
在本公开的一些实施例中，如图2A和图2B所示，选通器14包括第一晶体管S1和第二晶体管S2。第一晶体管S1的栅极与时序控制器13电连接，第一晶体管S1的第一极与该选通器14对应的数据总线D电连 接，第一晶体管S1的第二极和与该选通器14对应的同一列亚像素P中的像素驱动电路40电连接的第一数据线D1电连接。第二晶体管S2的栅极与时序控制器13电连接，第二晶体管S2的第一极与该选通器14对应的数据总线D电连接，第二晶体管S1的第二极和与该选通器14对应的同一列亚像素P中的像素驱动电路40电连接的第二数据线D2电连接。
示例性地，对于第m列亚像素，第一晶体管S1的第二极和与偶数行亚像素P电连接的第一数据线D1(m)电连接，第二晶体管S2的第二极和与奇数行亚像素P电连接的第二数据线D2(m)电连接。在奇数行亚像素P写入数据时，在时序控制器13的控制下，第二晶体管S2打开，第一晶体管S1截止，来自源极驱动器12的数据信号通过第二晶体管S2传输至与该第二晶体管S2电连接的第二数据线D2(m)中，使得与第二数据线D2(m)电连接的奇数行亚像素P写入数据。在偶数行亚像素P写入数据时，在时序控制器13的控制下，第一晶体管S1打开，第二晶体管S2截止，来自源极驱动器12的数据信号通过第一晶体管S1传输至与该第一晶体管S1电连接的第一数据线D1(m)中，使得与第一数据线D1(m)电连接的偶数行亚像素P写入数据。
图3为图2A中B区域所对应的像素驱动电路40的结构图。图3以像素驱动电路40为7T1C(即7个晶体管，一个存储电容器)结构进行示意，该像素驱动电路40包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容器C。其中，第五晶体管T5为驱动晶体管。
图4A为图3中E区域的像素驱动电路40对应的版图。第一晶体管T1的栅极211与使能信号线EM电连接，第一极212与第一电源线VDD以及与存储电容器C的第一极Cst1电连接，第二极213与第三晶体管T3的第二极233以及第五晶体管T5的第一极252电连接。
第二晶体管T2的栅极221与使能信号线EM电连接，第一极222与第四晶体管T4的第一极242以及第五晶体管T5的第二极253电连接。
第三晶体管T3的栅极231与栅线GATE电连接，第一极232和第一数据线D1电连接。
第四晶体管T4，第四晶体管T4为双栅型晶体管，第四晶体管T4的栅极241与栅线GATE电连接，第二极243与存储电容器C的第二极Cst2电连接。第四晶体管T4被配置为对第五晶体管T5的阈值电压进行补偿。
第六晶体管T6的栅极261与重置信号线RESET电连接，第一极262与初始化信号线VINT电连接，第二极263与存储电容器C的第二极Cst2电连接。第六晶体管T6被配置为在重置信号线RESET的控制下，通过初始化信号线VINT对存储电容器C的第二极Cst2和第五开关晶体管T5的栅极251进行初始化。
存储电容C器的第二极Cst2同时作为第五晶体管T5的栅极251，存储电容器C的第一极Cst1通过过孔连接至第一电源线VDD。
像素驱动电路40被配置为驱动发光器件L(请参照图3)工作。发光器件L的第一极通过过孔与第一电极28(请参照图4A)电连接，发光器件L的第二极与第二电源线VSS电连接，且第一电极28通过过孔与第二晶体管T2的第二极223电连接。
第七晶体管T7的栅极271与重置信号线RESET电连接，第一极272与初始化信号线VINT电连接，第二极273与发光器件L的第一极电连接(图中未示)。第七晶体管T7被配置为在重置信号线RESET的控制下，通过初始化信号线VINT对发光器件L的第一极进行初始化。
需要说明的是，像素驱动电路40所包括的各晶体管的第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
可选的，如图4A、图5A、图6A、图7A、图8A和图9A所示，在一些实施例中，显示面板101还包括遮光图案30，遮光图案30在衬底10上的投影覆盖第五晶体管T5(驱动晶体管)的半导体有源层20在衬底10上的正投影。示例性地，遮光图案30的材料为金属。驱动晶体管的性能对像素驱动电路40的性能有较大影响，通过设置遮光图案30，可以避免外界入射至像素驱动电路40的光线对驱动晶体管产生的影响，保证驱动晶体管的稳定性。
在上述双数据线的源极驱动架构中，相邻的数据线之间形成的寄生电容较大，因此一条数据线上信号的变化容易对与其相邻的处于浮置状态的另一条数据线上的信号产生影响，从而造成横向串扰，出现显示不良。
此处相邻的数据线例如为相邻设置的第一数据线D1和第二数据线D2；相邻设置的第一数据线D1和第二数据线D2包括如下情形：一、如图2A所示，处于相邻两列亚像素P之间的第一数据线D1和第二数据线D2，这两条数据线分别与两列亚像素P中相应的亚像素P电连接；二、如图2B所示，位于同一列亚像素P两侧的第一数据线D和第二数据线D2，这两条数据线与同一列亚像素P中相应的亚像素P电连接。
如图2A所示，在一些实施例中，多条第一数据线(D1(1)～D1(m))与多条第二数据线(D2(1)～D2(m))沿像素驱动电路40排列的行方向交替设置，即沿亚像素P排列的行方向交替设置，相邻两列亚像素P之间设置有一条第一数据线D1和一条第二数据线D2。
需要说明的是，如图2A和图2B所示，行方向即为X方向，列方向即为Y方向。
如图2A所示，第一数据线D1(1)设于第1列像素驱动电路40的左侧，第二数据线D2(1)设于第1列像素驱动电路40的右侧；第一数据线D1(2)设于第2列像素驱动电路40的左侧，第二数据线D2(2)设于第2列像素驱动电路40的右侧；第二数据线D2(1)与第一数据线D1(2)在第1列像素驱动电路40和第2列像素驱动电路40之间相邻设置。以此类推，第一数据线D1(m-1)设于第m-1列像素驱动电路40的左侧，第二数据线D2(m-1)设于第m-1列像素驱动电路40的右侧；第一数据线D1(m)设于第m列像素驱动电路40的左侧，第二数据线D2(m)设于第m列像素驱动电路40的右侧；第二数据线D2(m-1)与第一数据线D1(m)在第m-1列像素驱动电路40和第m列像素驱动电路40之间相邻设置。
在此基础上，相邻设置的第一数据线D1和第二数据线D2之间平行设置，第一数据线D1和第二数据线D2具有正对面积，相邻的第一数据线D1和第二数据线D2的正对面积的部分形成如图4B所示的寄生电容器Cp即第一数据线D1和第二数据线D2分别作为寄生电容器Cp的两个极板，第一数据线D1和第二数据线D2之间的绝缘层作为寄生电容器Cp的电介质，则寄生电容器Cp的电容为
Figure PCTCN2021096444-appb-000001
其中，ε rp1为第一数据线D1和第二数据线D2之间的绝缘层的相对 介电常数，S p为第一数据线D1和第二数据线D2的正对面积，d p为第一数据线D1和第二数据线D2的相互靠近的边界之间的距离，k为静电力常量，π为圆周率。
同理，如图2B所示，在一些实施例中，对于另一种双数据线的源极驱动结构，相邻两列亚像素P之间设置的两条均为第一数据线D1或均为第二数据线D2。
如图2B所示，第一数据线D1(1)设于第1列像素驱动电路40的左侧，第二数据线D2(1)设于第1列像素驱动电路40的右侧；第二数据线D2(2)设于第2列像素驱动电路40的左侧，第一数据线D1(2)设于第2列像素驱动电路40的右侧。以此类推，第一数据线D1(m-1)设于第m-1列像素驱动电路40的左侧，第二数据线D2(m-1)设于第m-1列像素驱动电路40的右侧；第二数据线D2(m)设于第m列像素驱动电路40的左侧，第一数据线D1(m)设于第m列像素驱动电路40的右侧。
在此基础上，分设于同一列像素驱动电路40两侧的第一数据线D1和第二数据线D2之间平行设置，第一数据线D1和第二数据线D2具有正对面积，其正对面积的部分同样形成如图4B所示的寄生电容器Cp，即第一数据线D1和第二数据线D2分别作为寄生电容器Cp的两个极板，第一数据线D1和第二数据线D2之间的绝缘层和像素驱动电路40作为寄生电容器Cp的电介质，则寄生电容器Cp的电容为
Figure PCTCN2021096444-appb-000002
其中，ε rp2为第一数据线D1和第二数据线D2之间的绝缘层和像素驱动电路40的相对介电常数，S p为第一数据线D1和第二数据线D2的正对面积，d p为第一数据线D1和第二数据线D2之间的距离，k为静电力常量，π为圆周率。
需要说明的是，寄生电容器Cp的电容为寄生电容，即原本在相邻的第一数据线D1和第二数据线D2之间没有设计电容，但是由于相邻的第一数据线D1和第二数据线D2之间存在互容作用，因此在相邻的第一数据线D1和第二数据线D2产生了寄生电容。
图4B示出了第一数据线D1和第二数据线D2之间形成寄生电容器Cp的等效电路图。
在上述基础上，在通过第二数据线D2向奇数行亚像素P写完数据后，第二数据线D2处于浮置状态。由于第二数据线D2与显示面板101其他层之间形成寄生电容器Cp，该寄生电容器Cp继续向奇数行亚像素P写入数据，以增长数据写入的时间，同时该寄生电容器Cp还通过第一数据线D1向偶数行亚像素P写入数据，即此时第一数据线D1的电位会发生跳变，跳变量为ΔV。
此时当第一数据线D1向偶数行亚像素P写数据时，由于第一数据线D1和第二数据线D2形成的寄生电容器Cp的作用，处于浮置状态的第二数据线D2的电位也会受到影响发生跳变，跳变量为ΔV。
同理，当第二数据线D2向奇数行亚像素P写数据时，处于浮置状态的第一数据线D1的电位也会受到第二数据线D2电位变化的影响发生跳变。因此造成横向串扰，出现显示不良。
为了解决上述问题，如图2A、图2B、图5A、图6A、图7A、图8A以及图9A所示，本公开的一些实施例提供一种显示面板，该显示面板101包括阵列分布的多个像素驱动电路40、多条第一数据线D1、多条第二数据线D2和至少一条屏蔽线LS。
第一数据线D1与同一列像素驱动电路40(即同一列亚像素P)中处于偶数行的像素驱动电路40电连接。
第二数据线D2与同一列像素驱动电路40(即同一列亚像素P)中处于奇数行的像素驱动电路40电连接。
相邻的第一数据线D1和第二数据线D2之间形成寄生电容器Cp。
屏蔽线LS被配置为传输固定电压，例如屏蔽线LS直接接入固定电压，或屏蔽线LS与显示面板中原有的传输固定电压的信号线(例如初始化信号线VINT)电连接，或屏蔽线LS与传输固定电压的固定电位端U电连接，其中，固定电压可以为0V，5V或者15V等，只要该电压在显示面板101工作过程中保持不变即可，对该固定电压的数值不做要求。
请参照图5A、图5B、图5C，屏蔽线LS与相邻的第一数据线D1和第二数据线D2中的第一数据线形成第一电容器C1。
请参照图6A、图6B、图6C，屏蔽线LS与相邻的第一数据线D1和第二数据线D2中的第二数据线D2形成第二电容器C2。
请参照图7A、图7B、图7C，同一条屏蔽线LS与相邻的第一数据线D1和第二数据线D2中的第一数据线形成第一电容器C1，且与相邻的第一数据线D1和第二数据线D2中的第二数据线D2形成第二电容器 C2。
请参照图8A、图8B、图8C，屏蔽线LS为两条：第一屏蔽线LS1和第二屏蔽线LS2；其中，第一屏蔽线LS1与相邻的第一数据线D1和第二数据线D2中的第一数据线D1形成第一电容器C1，第二屏蔽线LS2与相邻的第一数据线D1和第二数据线中的第二数据线D2形成第二电容器C2。
请参照图9A和图9B，屏蔽线LS与第一数据线D1和第二数据线D2同层设置，且设置于第一数据线D1和第二数据线D2之间。同一条屏蔽线LS与相邻的第一数据线D1和第二数据线D2中的第一数据线形成第一电容器C1，且与相邻的第一数据线D1和第二数据线D2中的第二数据线D2形成第二电容器C2。
如图5C所示，当通过第二数据线D2向奇数行亚像素P写完数据后，通过第一数据线D1向偶数行亚像素P写入数据时，第一数据线D1的电位会发生跳变，即寄生电容器Cp的第一极的电位发生跳变，跳变量为ΔV。通过设置与第二数据线D2对应的屏蔽线LS，并将屏蔽线LS与固定电位端U电连接，则寄生电容器Cp、屏蔽线LS与第二数据线D2形成的第二电容器C2和固定电位端U的等效电路图如图5C所示，此时寄生电容器Cp和第二电容器C2串联，寄生电容器Cp的第二极板充当第二电容器C2的第一极板。当寄生电容器Cp的第一极的电位发生跳变，且跳变量为ΔV时，基于电容的分压原理，寄生电容器Cp的第二极板跳变量为[Cp/(Cp+C2)]ΔV<ΔV，即第二数据线D2上的电位的跳变量为[Cp/(Cp+C2)]ΔV，因而可以减小第二数据线D2的电位受到的影响，从而减小横向串扰，改善显示不良。
如图6C所示，基于电容的分压原理，当通过第二数据线D2向奇数行亚像素P写完数据后，通过第一数据线D1向偶数行亚像素P写入数据时，第二数据线D2的电位会发生跳变，即寄生电容器Cp的第二极的电位发生跳变，跳变量为ΔV。通过设置与第一数据线D对应的屏蔽线LS，并将屏蔽线LS与固定电位端U电连接，则寄生电容器Cp、屏蔽线LS与第一数据线D1形成的第一电容器C1和固定电位端U的等效电路图如图6C所示。此时寄生电容器Cp和第一电容器C1串联，寄生电容器Cp的第一极板充当第一电容器C1的第一极板，当寄生电容器Cp的第二极的电位发生跳变，且跳变量为ΔV时，基于电容的分压原理，寄生电容器Cp的第一极板跳变量为[Cp/(Cp+C1)]ΔV<ΔV，即第一数据线D1 上的电位的跳变量为[Cp/(Cp+C1)]ΔV，因而可以减小第一数据线D1的电位受到的影响，从而减小横向串扰，改善显示不良。
如图7C所示，屏蔽线LS与第一数据线D1和第二数据线D2中的第一数据线D1形成第一电容器C1，且同一屏蔽线LS与第一数据线D1和第二数据线D2中的第二数据线D2形成第二电容器C2，即同一屏蔽线LS与连接不同行亚像素P且相邻的一组第一数据线D1和第二数据线D2对应。
如图8B所示，连接不同行亚像素P且相邻的一组第一数据线D1和第二数据线D2对应的屏蔽线LS的数量为两根。
如图9B所示，同一屏蔽线LS与连接不同行亚像素P且相邻的一组第一数据线D1和第二数据线D2对应，屏蔽线LS设置于相邻的第一数据线D1和第二数据线D2之间。
图7B、图8B和图9B的等效电路图均如图7C所示，即相当于第一电容器C1和第二电容器C2分别与寄生电容器Cp串联。屏蔽线LS的作用原理如前文所述，在此不再赘述。在此基础上，可以减小相邻的第一数据线D1和第二数据线D2之间的影响，减小横向串扰，改善显示不良。
可选的，第一电容器C1的电容大致等于第二电容器C2的电容，从而保证第一数据线D1和第二数据线D2在受到电位影响时跳变量大致相同，使得两条数据线的横向串扰程度相当，这样在利用屏蔽线LS改善横向串扰问题时，第一数据线D1和第二数据线D2在受到电位影响时跳变量的减小程度大致相同，使得显示面板101的显示均匀。
由上文可知，相邻的第一数据线D1和第二数据线D2距离较近，造成寄生电容器Cp的电容较大，相邻的第一数据线D1和第二数据线D2互相影响较为严重，通过设置屏蔽线LS，可以减小相邻的第一数据线D1和第二数据线D2之间的影响，减小横向串扰，改善显示不良。
在示例性实施例中，如图6B、图7B、图8B所示，在屏蔽线LS与第一数据线D1形成第一电容器C1的情况下，屏蔽线LS在衬底10上的正投影与第一数据线D1在衬底10上的正投影至少部分重叠，该重叠部分的面积为S 1，则第一电容器C1的电容为
Figure PCTCN2021096444-appb-000003
其中，ε r1为第一数据线D1和屏蔽线LS之间的绝缘层的相对介电常数，d 1为第一数据线D1屏蔽线LS之间的距离，k为静电力常量。
如图5B、图7B、图8B所示，在屏蔽线LS与第二数据线D2形成的第二电容器C2的情况下，屏蔽线LS在衬底10上的正投影与第二数据线D2在衬底10上的正投影至少部分重叠，该重叠部分的面积为S 2，则第二电容器C2的电容为
Figure PCTCN2021096444-appb-000004
其中，ε r1为第二数据线D2和屏蔽线LS之间的绝缘层的相对介电常数，d 2为第二数据线D2屏蔽线LS之间的距离，k为静电力常量。
屏蔽线LS被配置为传输固定电压。可选地，第一屏蔽线LS1和第二屏蔽线LS2接入相同的固定电压；例如，第一屏蔽线LS1和第二屏蔽线LS2均于第二电源线VSS电连接。以此保证第一屏蔽线LS1和第二屏蔽线LS2上的电压相同，从而控制第一数据线D1和第二数据线D2的电压的跳变量尽可能一致，提高显示品质。
可选地，第一屏蔽线LS1和第二屏蔽线LS2可以分别接入不同的固定电压；例如，第一屏蔽线LS1与初始化信号线VINT电连接，第二屏蔽线LS2与第一电源线VDD电连接。以此灵活布置显示面板101中的线路，避免局部布线过于密集。
在一些实施例中，显示面板101中原有一些部件本身便传输固定电压，因此可以合理利用显示面板101原有的传输固定电压的部件(例如信号线或端子等)来为屏蔽线LS接入固定电压，这样无需额外设置用于为屏蔽线LS传输固定电压的结构，可以简化制作工艺，简化显示面板内部结构。以下介绍几种利用显示面板101中既有结构来为屏蔽线LS接入固定电压的可能设计。
在一些实施例中，如图10和图11所示，显示面板101还包括与多个像素驱动电路40连接的第一电源线VDD，第一电源线VDD被配置为向像素驱动电路40传输第一电压信号；屏蔽线LS与第一电源线VDD电连接。
在可选的实施例中，如图10和图11所示，第一电源线VDD包括位于显示区AA的子电源线VDD2，及位于周边区S且与子电源线VDD2电连接的电源总线VDD1；子电源线VDD2与像素驱动电路40电连接。
基于此，在示例性的实施例中，如图10所示，屏蔽线LS与电源总线VDD1电连接，可选地，屏蔽线LS通过设置于周边区S的过孔H1与 电源总线VDD1电连接，从而避免在显示面板101的显示区AA打孔，避免过孔占用显示区AA的有效发光面积。图中仅示意性的画出了一个过孔，二者连接的过孔可以是一个，也可以多个。
在另一示例性的实施例中，如图11所示，屏蔽线LS与子电源线VDD2电连接，可选地，屏蔽线LS与距离屏蔽线LS最近的子电源线VDD2通过过孔H2电连接，以此简化屏蔽线LS与子电源线VDD2电连接的结构。
需要说明的是，在图5A中并未区分子电源线VDD2与电源总线VDD1，由于子电源线VDD2和电源总线VDD1均传输VDD信号，因此将图中传输VDD信号的线标成VDD，事实上图5A中的VDD线对应的是图10中的子电源线VDD2。
在一些实施例中，如图12所示，显示面板101还包括第二电源线VSS，第二电源线VSS与待驱动元件(例如发光器件L)的第二极电连接，被配置为向待驱动元件传输第二电压信号，从而使得待驱动元件的第一极和第二极之间具有压差，待驱动元件在该压差的作用下工作(例如发光)；屏蔽线LS在周边区S与第二电源线VSS通过过孔H3电连接，避免在显示区AA打过孔，避免过孔占用显示区AA的有效发光面积。图中仅示意性的画出了一个过孔，二者连接的过孔可以是一个，也可以多个。
示例性的，如图10所示，第一电源线VDD和第二电源线VSS等线路板通过绑定衬垫CP(即为COF PAD)进行绑定，同样的，第一数据线D1和第二数据线D2通过扇出区DF(也即Data Fanout)连接至绑定衬垫CP进行绑定。
在一些实施例中，如图13和图14所示，显示面板101还包括初始化信号线VINT，初始化信号线VINT与像素驱动电路40电连接，被配置为向像素驱动电路40传输初始化信号，例如图3所示，初始化信号线VINT用于对第五晶体管T5的栅极251以及发光器件L的阳极的电位进行初始化；屏蔽线LS与初始化信号线VINT电连接。
在可选的实施例中，初始化信号线VINT包括位于显示区AA的子初始化信号线VINT2，及位于周边区S且与子初始化信号线VINT2电连接的初始化信号总线VINT1；子初始化信号线VINT2与像素驱动电路40电连接。
基于此，在示例性的实施例中，如图13所示，屏蔽线LS与初始化 信号总线VINT1电连接，可选地，屏蔽线LS通过设置于周边区S的过孔H4与初始化信号总线VINT1电连接，从而避免在显示面板101的显示区AA打孔，避免过孔占用显示区AA的有效发光面积。图中仅示意性的画出了一个过孔，二者连接的过孔可以是一个，也可以多个。
在另一示例性的实施例中，如图14所示，屏蔽线LS与子初始化信号线VINT2电连接，可选地，屏蔽线LS与距离屏蔽线LS最近的子初始化信号线VINT2通过过孔H5电连接，以此简化屏蔽线LS与子初始化信号线VINT2电连接的结构。
需要说明的是，在图5A中并未区分子初始化信号线VINT2与初始化信号总线VINT1，由于子初始化信号线VINT2和初始化信号总线VINT1均传输VINT信号，因此将图中传输VINT信号的线标成VINT，事实上图5A中的VINT线对应的是图13中的子初始化信号线VINT2。
在一些实施例中，如图15所示，显示面板还包括待驱动元件(请参照图1B中的发光器件L)，屏蔽线LS与待驱动元件的第二极通过过孔H6电连接。此处，待驱动元件例如可OLED。该待驱动元件包括第一极和第二极，第一极可为阳极L2，第二极可为阴极L3(参照图1B)。
基于以上所述的显示面板101，屏蔽线在具体设置过程中可与显示面板101原有的一些膜层同层设置，从而减少工艺步骤，简化制备过程。以下为屏蔽线设置于显示面板101不同层时的一些实施例。
需要说明的是，同层设置指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
在一些实施例中，如图5A、图5B、图6A、图6B、图7A、图7B、图8A和图8B所示，屏蔽线LS设置于第一数据线D1和第二数据线D2所在膜层(即源漏导电层)与衬底10之间，例如，屏蔽线LS设置于源漏导电层与衬底10之间的遮光图案所在的膜层上，屏蔽线LS与遮光图案30材料相同且同层设置。
在此基础上，通过设置屏蔽线LS与遮光图案30同层，可以在制作遮光图案30的同时制作屏蔽线LS，简化了制作工艺。
示例性地，相邻设置的第一数据线D1与第二数据线D2之间的距离d1，大于屏蔽线与第一数据线D1和第二数据线D2所在膜层之间的垂直 距离d2，从而通过控制极板间的距离控制寄生电容器Cp的电容小于第一电容器C1和第二电容器C2的电容，增强第一电容器C1和第二电容器C2的分压作用，降低寄生电容器Cp对处于浮置状态的数据线的影响，减少数据线电压的跳变量。
需要说明的是，相邻的第一数据线D1和第二数据线D2之间的距离d1为相邻的第一数据线D1和第二数据线D2中，第一数据线D1的中心线至和第二数据线D2的中心线之间的距离。
示例性地，相邻设置的第一数据线D1和第二数据线D2之间所产生的寄生电容小于第一电容器C1的电容和/或第二电容器C2的电容，从而保证第一电容器C1和第二电容器C2的分压作用效果明显，实现降低寄生电容器Cp对处于浮置状态的数据线的影响的目的。可选地，控制寄生电容器的电容小于第一电容器C1和第二电容器C2的电容的手段包括，增大屏蔽线LS与第一数据线D1和/或第二数据线D2的正对面积。
示例性地，屏蔽线LS与第一数据线D1和第二数据线D2所在膜层之间的垂直距离d2的范围为0.75μm～1μm，例如，0.75μm、0.8μm、0.85μm、0.9μm、1μm。相邻的第一数据线D1和第二数据线D2之间的距离d1为4μm～8μm，例如，4μm、4.8μm、5μm、5.5μm、6μm、6.3μm、7μm、8μm。
在示例性实施例中，屏蔽线LS与遮光图案30同层设置，屏蔽线LS与第一数据线D1和第二数据线D2所在膜层之间的垂直距离d2的范围为0.8μm～0.9μm，例如，为0.8μm、0.85μm或者0.9μm。
在示例性实施例中，屏蔽线LS与遮光图案30同层设置，相邻的第一数据线D1和第二数据线D2之间的距离d1为5μm～7μm，例如，为5μm、5.5μm、6μm或者7μm。
需要说明的是，第一数据线D1和第二数据线D2同层设置，屏蔽线LS设置于第一数据线和第二数据线所在膜层(即源漏导电层)与衬底10之间，源漏导电层与屏蔽线LS之间至少要设置层间介质层ILD和栅极绝缘层GI，层间介质层ILD的厚度至少为0.5μm，栅极绝缘层GI的厚度至少为0.25μm，则源漏导电层与屏蔽线LS之间的距离d2至少为0.75μm。当源漏导电层与屏蔽线LS之间还设置有第二层栅极绝缘层GI时，第二层栅极绝缘层GI的厚度至少为0.25μm，则源漏导电层与屏蔽线LS之间的距离d2至少为1μm。
在一些实施例中，如图9A和图9B所示，屏蔽线LS与相邻的第一数据线D1和第二数据线D2所在膜层材料相同且同层设置。相邻的第一 数据线D1和第二数据线D2至连接不同行的亚像素，屏蔽线LS位于相邻的第一数据线D1和第二数据线D2之间，此时屏蔽线LS与第一数据线D1相对的侧面与第一数据线D1形成第一电容器C1，屏蔽线LS与第二数据线D2相对的侧面与第二数据线D2形成第二电容器C2。
基于此，可以在制作第一数据线D1和第二数据线D2的同时制作屏蔽线LS，简化了制作工艺。
在一些实施例中，屏蔽线LS设置于第一数据线D1和第二数据线D2所在膜层背离衬底10的一侧。
基于前述实施例，分别对不设置屏蔽线LS和设置屏蔽线LS的显示面板101进行数据线的横向串扰的检测，结果如下：
如图16所示，在相邻的第一数据线D1和第二数据线D2的下方没有设置屏蔽层LS时，当第二数据线D2上的电位发生跳变时，第一数据线D1上的电位发生跳变，且跳变量较大(如图中虚线圈所示)，对第一数据线D1上的电位的稳定性产生较大影响，造成横向串扰，出现显示不良。
如图17所示，在相邻的第一数据线D1和第二数据线D2的下方设置屏蔽层LS，且屏蔽层LS与第一数据线D1形成第一电容器C2时，当第二数据线D2上的电位发生跳变时，第一数据线D1上的电位发生跳变，但跳变量较小(如图中虚线圈所示)，因此设置屏蔽层LS可以减小对第一数据线D1上的电位的影响，减小横向串扰，改善显示不良。
另一方面，如图1A所示，本公开实施例提供一种显示装置100，包括上述显示面板101。
其中，显示装置100可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内， 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示面板，包括：
    衬底；
    阵列分布的多个像素驱动电路；
    多条第一数据线，第一数据线与同一列像素驱动电路中处于偶数行的像素驱动电路电连接；
    多条第二数据线，第二数据线与同一列像素驱动电路中处于奇数行的像素驱动电路电连接；相邻设置的第一数据线和第二数据线之间具有正对面积；和
    至少一条屏蔽线，被配置为传输固定电压，所述屏蔽线与相邻设置的第一数据线和第二数据线中的第一数据线形成第一电容器，和/或，所述屏蔽线与相邻设置的第一数据线和第二数据线中的第二数据线形成第二电容器。
  2. 根据权利要求1所述的显示面板，其中，所述第一电容器的电容与所述第二电容器的电容大致相等。
  3. 根据权利要求1或2所述的显示面板，其中，所述屏蔽线与第一数据线形成第一电容器，所述屏蔽线在所述衬底上的正投影与所述第一数据线在所述衬底上的正投影至少部分重叠；
    所述屏蔽线与第二数据线形成第二电容器，所述屏蔽线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影至少部分重叠。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述显示面板包括多条屏蔽线，所述多条屏蔽线包括至少一条第一屏蔽线和至少一条第二屏蔽线；
    所述第一屏蔽线与相邻设置的第一数据线和第二数据线中的第一数据线形成所述第一电容器；
    所述第二屏蔽线与相邻设置的第一数据线和第二数据线中的第二数据线形成第二电容器。
  5. 根据权利要求1～4中任一项所述的显示面板，还包括：
    待驱动元件，所述待驱动元件的第一极与所述像素驱动电路电连接；
    第一电源线，与所述像素驱动电路电连接，被配置为向所述像素驱动电路传输第一电压信号；
    第二电源线，与所述待驱动元件的第二极电连接，被配置为向所述待驱动元件传输第二电压信号；和
    初始化信号线，与所述像素驱动电路电连接，被配置为向所述像素驱动电路传输初始化信号；
    其中，所述屏蔽线与所述第一电源线、所述第二电源线、所述待驱动元件的第二极或所述初始化信号线电连接。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板包括显示区和周边区；
    所述第一电源线包括位于所述显示区的子电源线，及位于所述周边区且与所述子电源线电连接的电源总线；所述子电源线与所述像素驱动电路电连接；
    其中，所述屏蔽线与所述子电源线和/或所述电源总线电连接。
  7. 根据权利要求6所述的显示面板，其中，所述屏蔽线与距离所述屏蔽线最近的子电源线电连接；和/或，
    所述屏蔽线通过设置于所述周边区的过孔与所述电源总线电连接。
  8. 根据权利要求5所述的显示面板，其中，所述显示面板包括显示区和周边区；
    所述屏蔽线通过设置于所述周边区的过孔与所述第二电源线电连接。
  9. 根据权利要求5所述的显示面板，其中，所述显示面板包括显示区和周边区；
    所述初始化信号线包括位于所述显示区的子初始化信号线，及位于所述周边区且与所述子初始化信号线电连接的初始化信号总线；所述子初始化信号线与所述像素驱动电路电连接；
    其中，所述屏蔽线与所述子初始化信号线和/或所述初始化信号总线电连接。
  10. 根据权利要求9所述的显示面板，其中，所述屏蔽线与距离所述屏蔽线最近的子初始化信号线电连接；和/或，
    所述屏蔽线通过设置于所述周边区的过孔与所述初始化信号总线电连接。
  11. 根据权利要求1～10中任一项所述的显示面板，其中，所述至少一条屏蔽线设置于第一数据线和第二数据线所在膜层与所述衬底之间。
  12. 根据权利要求11所述的显示面板，还包括：
    遮光图案，设置于像素驱动电路所在膜层与所述衬底之间；其中，
    所述屏蔽线与所述遮光图案材料相同且同层设置。
  13. 根据权利要求11或12所述的显示面板，其中，相邻设置的第 一数据线与第二数据线之间的距离，大于所述屏蔽线与第一数据线和第二数据线所在膜层之间的垂直距离。
  14. 根据权利要求1～13中任一项所述的显示面板，其中，所述屏蔽线与第一数据线和第二数据线所在膜层之间的垂直距离为0.75μm～1μm；和/或
    相邻设置的第一数据线和第二数据线之间的距离为4μm～8μm。
  15. 根据权利要求1～14中任一项所述的显示面板，其中，所述屏蔽线与第一数据线和第二数据线同层设置，且位于相邻设置的第一数据线和第二数据线之间。
  16. 根据权利要求1～15中任一项所述的显示面板，其中，相邻设置的第一数据线和第二数据线之间所产生的寄生电容小于所述第一电容器的电容和/或所述第二电容器的电容。
  17. 根据权利要求1～16中任一项所述的显示面板，其中，所述多条第一数据线与所述多条第二数据线沿所述多个像素驱动电路排列的行方向交替设置，且相邻设置的第一数据线和第二数据线位于相邻两列像素驱动电路之间。
  18. 根据权利要求1～17中任一项所述的显示面板，其中，相邻设置的第一数据线和第二数据线分别与处于不同行的像素驱动电路电连接。
  19. 一种显示装置，包括如权利要求1～18中任一项所述的显示面板。
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