WO2022041227A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2022041227A1
WO2022041227A1 PCT/CN2020/112646 CN2020112646W WO2022041227A1 WO 2022041227 A1 WO2022041227 A1 WO 2022041227A1 CN 2020112646 W CN2020112646 W CN 2020112646W WO 2022041227 A1 WO2022041227 A1 WO 2022041227A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
active layer
base substrate
layer
signal line
Prior art date
Application number
PCT/CN2020/112646
Other languages
English (en)
French (fr)
Inventor
尚庭华
张毅
刘庭良
张顺
杨慧娟
韩林宏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080001755.7A priority Critical patent/CN115485847A/zh
Priority to US17/418,519 priority patent/US11751450B2/en
Priority to PCT/CN2020/112646 priority patent/WO2022041227A1/zh
Publication of WO2022041227A1 publication Critical patent/WO2022041227A1/zh
Priority to US18/358,419 priority patent/US20230371333A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and more particularly, to a display panel and a display device.
  • OLED display panels have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed, and have been increasingly used in various electronic devices.
  • the present disclosure provides a display panel, wherein the display panel includes: a base substrate, and a plurality of sub-pixels located on the base substrate;
  • the sub-pixels include:
  • the semiconductor layer located on the base substrate; the semiconductor layer includes: a first active layer of an initialization transistor, a second active layer of a reset transistor, and a third active layer of a data writing transistor;
  • the first conductive layer located on the side of the semiconductor layer away from the base substrate; the first conductive layer includes: a data signal line extending along a first direction;
  • the second conductive layer is located on the base substrate; the second conductive layer includes: a driving gate of a driving transistor;
  • the drive gate is electrically connected to the first conductive region of the first active layer
  • the data signal line is electrically connected to the first conductive region of the third active layer
  • the orthographic projection of the second active layer on the base substrate is located between the orthographic projection of the first active layer on the base substrate and the data signal line on the base substrate. between orthographic projections.
  • the orthographic projection of the channel region of the second active layer on the base substrate, the channel region of the first active layer is located on the substrate between the orthographic projection on the substrate and the orthographic projection of the data signal line on the base substrate.
  • a third conductive layer is located on the base substrate; the third conductive layer includes: an initialization signal line extending along a second direction; the second direction is a direction crossing the first direction;
  • the initialization signal line is electrically connected to the first conductive region of the second active layer
  • the first conductive region of the second active layer is located at an end of the second active layer away from the first active layer.
  • it further includes: a shielding structure located on the base substrate;
  • the orthographic projection of the shielding structure on the base substrate the orthographic projection of the first conductive region located in the first active layer on the base substrate and the first conductive area of the three active layers between the orthographic projections on the base substrate.
  • it further comprises: a fourth conductive layer located on a side of the semiconductor layer away from the base substrate;
  • the fourth conductive layer includes: a fixed potential signal line extending along the first direction;
  • the shielding structure is electrically connected to the fixed potential signal line.
  • the shielding structure and the initialization signal line are disposed on the same layer.
  • the third conductive layer further includes: a conductive connection structure connected to the shielding structure;
  • the fixed potential signal line is electrically connected to the shielding structure through the conductive connection structure.
  • the fourth conductive layer further includes: a first conductive connection portion, a second conductive connection portion, and a third conductive connection portion that are insulated from each other;
  • the drive gate is electrically connected to the first conductive region of the first active layer through the first conductive connection;
  • the data signal line is electrically connected to the first conductive region of the third active layer through the second conductive connection part;
  • the initialization signal line is electrically connected to the first conductive region of the second active layer through the third conductive connection portion.
  • the first active layer includes: a first bending part, and a second bending part;
  • One end of the first bending portion is the first conductive region of the first active layer, and the other end is connected to the second bending portion, and is bent toward the side away from the data signal line;
  • the second bending part is "n"-shaped, one end of the second bending part is connected to the first bending part, and the other end is connected to the second active layer.
  • the second active layer includes: a first branch part, and a second branch part;
  • One end of the first branch portion is the first conductive region of the second active layer, and the other end is connected to the second branch portion;
  • the first branch portion extends along the second direction, and the second branch portion extends along the first direction.
  • the third active layer includes: a conductive protrusion, and a conductive extension extending along the first direction;
  • One end of the conductive protrusion is the first conductive region of the third active layer, and the other end is connected to the conductive extension.
  • the plurality of sub-pixels in the display panel are arranged in an array in the first direction and the second direction;
  • the display panel includes a plurality of the data signal lines, and the data signal lines are divided into a first data signal line and a second data signal line;
  • the sub-pixels in odd-numbered rows share one of the first data signal lines, and the sub-pixels in even-numbered rows share one of the second data signal lines.
  • an embodiment of the present disclosure further provides a display device, comprising: the above-mentioned display panel.
  • FIG. 1 is a schematic top-view structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure
  • FIG. 3 is a signal timing diagram corresponding to the pixel driving circuit shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a layout structure of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure
  • Fig. 5 is the cross-sectional schematic diagram at dotted line A1-A2 in Fig. 4;
  • FIG. 6 is a schematic diagram of a layout structure of a sub-pixel in a display panel according to an embodiment of the present disclosure
  • FIG. 7 to 9 are schematic top-view structural diagrams of a plurality of film layers in a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic top-view structural diagram of a semiconductor layer corresponding to a plurality of sub-pixels
  • FIG. 11 is an enlarged schematic view of a semiconductor layer corresponding to one sub-pixel in FIG. 10;
  • FIG. 12 is a schematic top-view structural diagram of a first conductive layer corresponding to a plurality of sub-pixels
  • FIG. 13 is an enlarged schematic view of the first conductive layer corresponding to one sub-pixel in FIG. 12;
  • FIG. 14 is a schematic top-view structural diagram of a second conductive layer corresponding to a plurality of sub-pixels
  • FIG. 15 is an enlarged schematic view of a second conductive layer corresponding to one sub-pixel in FIG. 14;
  • 16 is a schematic top-view structural diagram of a third conductive layer corresponding to a plurality of sub-pixels
  • FIG. 17 is an enlarged schematic view of a third conductive layer corresponding to one sub-pixel in FIG. 16;
  • FIG. 18 is a schematic top-view structural diagram of a fourth conductive layer corresponding to a plurality of sub-pixels
  • FIG. 19 is an enlarged schematic view of the fourth conductive layer corresponding to one sub-pixel in FIG. 18;
  • FIG. 20 is a schematic top-view structural diagram of a fifth conductive layer corresponding to a plurality of sub-pixels.
  • FIG. 1 is a schematic top-view structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel provided by an embodiment of the present disclosure may include: a base substrate 10 and a plurality of sub-pixels located on the base substrate 10 spx, a plurality of sub-pixels spx are arranged in an array in the first direction F1 and the second direction F2.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present disclosure.
  • at least one sub-pixel spx in the plurality of sub-pixels spx may include: a pixel driving circuit 121 and a light-emitting The device 120, wherein the pixel driving circuit 121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, the generated electrical signal is input to the anode of the light-emitting device 120, and a corresponding voltage is applied to the cathode of the light-emitting device 120 , the light emitting device 120 can be driven to emit light.
  • the pixel driving circuit 121 may include: a driving control circuit 122 , a first lighting control circuit 123 , a second lighting control circuit 124 , a data writing circuit 125 , a storage circuit 126 , a threshold compensation circuit 127 and a reset circuit 128 .
  • the driving control circuit 122 may include a control terminal, a first terminal and a second terminal. And the driving control circuit 122 is configured to provide a driving current to the light emitting device 120 to drive the light emitting device 120 to emit light.
  • the first lighting control circuit 123 is connected to the first terminal of the driving control circuit 122 and the first voltage terminal VDD, and the first lighting control circuit 123 is configured to realize the connection between the driving control circuit 122 and the first voltage terminal VDD on or off.
  • the second light emitting control circuit 124 is electrically connected to the second end of the driving control circuit 122 and the anode of the light emitting device 120, and the second light emitting control circuit 124 is configured to realize the connection between the driving control circuit 122 and the light emitting device 120 to be turned on or disconnect.
  • the data writing circuit 125 is electrically connected to the first terminal of the driving control circuit 122 .
  • the second light emission control circuit 124 is configured to write the signal on the data signal line VD into the memory circuit 126 .
  • the storage circuit 126 is electrically connected to the control terminal of the driving control circuit 122 and the first voltage terminal VDD. And the storage circuit 126 is configured to store the data signal.
  • the threshold compensation circuit 127 is electrically connected to the control terminal and the second terminal of the driving control circuit 122, respectively. And the threshold compensation circuit 127 is configured to perform threshold compensation on the drive control circuit 122 .
  • the reset circuit 128 is electrically connected to the control terminal of the driving control circuit 122 and the anode of the light emitting device 120, respectively. And the reset circuit 128 is configured to reset the anode of the light emitting device 120 and reset the control terminal of the driving control circuit 122 .
  • the light emitting device 120 may be configured as an electroluminescent diode, such as at least one of OLED and QLED.
  • the light-emitting device 120 may include a stacked anode, a light-emitting functional layer, and a cathode.
  • the light-emitting functional layer may include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.
  • the light emitting device 120 can be designed and determined according to the requirements of the actual application environment, which is not limited herein.
  • the drive control circuit 122 may include: a drive transistor T4 , the control end of the drive control circuit 122 includes the drive gate of the drive transistor T4 , and the first end of the drive control circuit 122 includes the drive gate of the drive transistor T4 .
  • the first pole, the second terminal of the driving control circuit 122 includes the second pole of the driving transistor T4.
  • the data writing circuit 125 may include a data writing transistor T3 .
  • the storage circuit 126 may include a storage capacitor CST.
  • the threshold compensation circuit 127 includes a threshold compensation transistor T7.
  • the first light emission control circuit 123 may include a first light emission control transistor T5.
  • the second light emission control circuit 124 may include a second light emission control transistor T6.
  • the reset circuit 128 may include an initialization transistor T1 and a reset transistor T2.
  • the first pole of the data writing transistor T3 is electrically connected to the first pole of the driving transistor T4, and the second pole of the data writing transistor T3 is configured to be electrically connected to the data signal line VD to receive the data signal, and the data writing The gate of the input transistor T3 is configured to be electrically connected to the scan line GA to receive a signal.
  • the first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor CST is electrically connected to the driving gate of the driving transistor T4.
  • the first pole of the threshold compensation transistor T7 is electrically connected to the second pole of the driving transistor T4, the second pole of the threshold compensation transistor T7 is electrically connected to the gate of the driving transistor T4, and the gate of the threshold compensation transistor T7 is configured to be connected to the scan line.
  • the GA is electrically connected to receive the signal.
  • the first pole of the initialization transistor T1 is configured to be electrically connected to the initialization signal line VINIT to receive the reset signal
  • the second pole of the initialization transistor T1 is electrically connected to the drive gate of the drive transistor T4
  • the gate of the initialization transistor T1 is configured to be It is electrically connected to the reset line RST to receive a signal.
  • the first electrode of the reset transistor T2 is configured to be electrically connected to the initialization signal line VINIT to receive the reset signal
  • the second electrode of the reset transistor T2 is electrically connected to the anode of the light emitting device 120
  • the gate of the reset transistor T2 is configured to be connected to the reset signal.
  • Line RST is electrically connected to receive the signal.
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply terminal VDD
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T4
  • the gate of the first light-emitting control transistor T5 is It is configured to be electrically connected to the lighting control line EM to receive lighting control signals.
  • the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T4, the second electrode of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting device 120, and the gate of the second light-emitting control transistor T6 is It is configured to be electrically connected to the lighting control line EM to receive lighting control signals.
  • the cathode of the light emitting device 120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage
  • the second voltage is a negative voltage
  • the second power supply terminal VSS may be grounded.
  • the working process of the pixel driving circuit may have three stages: T10 stage, T20 stage, and T30 stage.
  • rst represents the signal transmitted on the reset line RST
  • ga represents the signal transmitted on the scan line GA
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal rst controls the initialization transistor T1 to be turned on, so that the signal transmitted on the initialization signal line VINIT can be supplied to the gate of the driving transistor T4 to reset the driving gate of the driving transistor T4.
  • the signal rst controls the reset transistor T2 to be turned on, so as to provide the signal transmitted on the initialization signal line VINIT to the anode of the light emitting device 120 to reset the anode of the light emitting device 120 .
  • the signal ga controls the data writing transistor T3 and the threshold compensation transistor T7 to be turned off.
  • the signal em controls both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the signal ga controls the data writing transistor T3 and the threshold compensation transistor T7 to be turned on, and the turned-on data writing transistor T3 makes the data signal transmitted on the data signal line VD charge the driving gate of the driving transistor T4 to The voltage of the driving gate of the driving transistor T4 becomes: Vdata+
  • the signal rst controls both the initialization transistor T1 and the reset transistor T2 to be turned off.
  • the signal em controls both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the signal em controls both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on.
  • the turned-on first light-emitting control transistor T5 supplies the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T4, so that the voltage of the first electrode of the driving transistor T4 is Vdd.
  • the driving transistor T4 generates a driving current according to the voltage Vdata+
  • the signal rst controls the initialization transistor T1 and the reset transistor T2 to be turned off.
  • the signal ga controls the data writing transistor T3 and the threshold compensation transistor T7 to be turned off.
  • the sub-pixels in the embodiment of the present disclosure may also include pixel driving circuits of other structures, that is, may also include other numbers of transistors structure, which is not limited in this embodiment of the present disclosure.
  • the display panel may include: a base substrate 10 , and a plurality of sub-pixels spx located on the base substrate 10 .
  • a limited number of sub-pixels spx The number and arrangement of sub-pixels spx are not limited.
  • FIG. 4 is a schematic diagram of a layout structure of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view at the dotted line A1-A2 in FIG. 4
  • FIG. 6 is a sub-pixel in the display panel according to an embodiment of the present disclosure.
  • Schematic diagram of the layout structure, in order to illustrate the structure of each film layer more clearly FIG. 7 to FIG. 9 show the top-view structure schematic diagram of some of the film layers in FIG. 6 , as shown in FIG. 4 to FIG.
  • the above-mentioned sub-pixels may include:
  • the semiconductor layer 20 is located on the base substrate;
  • FIG. 10 is a schematic top view of the semiconductor layer 20 corresponding to a plurality of sub-pixels
  • FIG. 11 is an enlarged schematic view of the semiconductor layer 20 corresponding to a sub-pixel in FIG. 11, the semiconductor layer 20 includes: a first active layer 201 of an initialization transistor, a second active layer 202 of a reset transistor, and a third active layer 203 of a data writing transistor;
  • the semiconductor layer 20 may be formed by patterning a semiconductor material, and each active layer in the semiconductor layer 20 may include a first conductive region, a second conductive region and a channel region, and the channel region may be located in the first conductive region Between the conductive region and the second conductive region, the first conductive region and the second conductive region can be obtained by conducting the semiconductor layer 20.
  • n-type impurities and p-type impurities can be doped into the semiconductor layer 20. The impurities are used to conduct the semiconductor layer 20 to obtain a first conductive region and a second conductive region.
  • the first conductive region is used as the source of the transistor, and the second conductive region is used as the drain of the transistor; or, the first conductive region is used as the drain of the transistor, and the second conductive region is used as the source of the transistor, There is no limitation here.
  • the first conductive layer 21 is located on the side of the semiconductor layer 20 away from the base substrate;
  • FIG. 12 is a schematic top view of the first conductive layer 21 corresponding to a plurality of sub-pixels
  • FIG. 13 is a first conductive layer corresponding to one sub-pixel in FIG. 12 .
  • An enlarged schematic diagram of the layer 21, as shown in FIG. 12 and FIG. 13, the first conductive layer 21 includes: a data signal line VD extending along the first direction F;
  • the second conductive layer 22 is located on the base substrate;
  • FIG. 14 is a schematic top view of the second conductive layer 22 corresponding to a plurality of sub-pixels
  • FIG. 15 is an enlarged schematic view of the second conductive layer corresponding to one sub-pixel in FIG. 14 ,
  • the second conductive layer 22 includes: the driving gate G1 of the driving transistor;
  • the driving gate G1 is electrically connected to the first conductive region 201a of the first active layer 201;
  • the data signal line VD is electrically connected to the first conductive region 203a of the third active layer 203;
  • the orthographic projection of the second active layer 202 on the base substrate is located between the orthographic projection of the first active layer 201 on the base substrate and the orthographic projection of the data signal line VD on the base substrate.
  • the potential in the data signal line is pulsating during the light-emitting process, and disturbances caused by electric field coupling may occur, causing the potential of the driving gate of the driving transistor to change. In this way, the display effect is affected.
  • the first active layer 201 by arranging the first active layer 201 on the side of the second active layer 202 away from the data signal line VD, the first active layer connected to the driving gate G1 is enlarged. 201.
  • the distance between the third active layer 203 connected to the data signal line VD alleviates the influence of the data signal line VD on the driving gate G1 of the driving transistor and improves the display effect of the display panel.
  • the orthographic projection of the channel region 202 c of the second active layer 202 on the base substrate is located in the first active layer between the orthographic projection of the channel region 201c of the 201 on the base substrate and the orthographic projection of the data signal line VD on the base substrate, thereby further ensuring that the first active layer 201 connected to the driving gate G1 is connected to the data signal.
  • the distance between the third active layers 203 connected by the line VD is relatively far, which further weakens the influence of the data signal line VD on the driving gate G1 of the driving transistor, and ensures that the display panel has a better display effect.
  • the above-mentioned display panel provided by the embodiment of the present disclosure may further include:
  • the third conductive layer 23 is located on the base substrate;
  • FIG. 16 is a schematic top view of the third conductive layer 23 corresponding to a plurality of sub-pixels
  • FIG. 17 is an enlarged schematic view of the third conductive layer 23 corresponding to one sub-pixel in FIG. 16 .
  • the third conductive layer 23 includes: an initialization signal line VINIT extending along the second direction F2; the second direction F2 is a direction crossing the first direction F1;
  • the initialization signal line VINIT is electrically connected to the first conductive region 202a of the second active layer 202;
  • the first conductive region 202 a of the second active layer 202 is located at one end of the second active layer 202 away from the first active layer 201 .
  • the first conductive region 202a connected to the initialization signal line VINIT at the end of the second active layer 202 away from the first active layer 201, more space can be reserved for the first active layer 201, thereby The distance between the pattern of the first active layer 201 and the first conductive region 203a of the third active layer 203 is farther, so as to prevent the signal of the data signal line VD from passing through the third active layer 203 and the second active layer 202, and affects the potential of the driving gate of the driving transistor, ensuring that the display panel has a better display effect.
  • the display panel may further include: a shielding structure 231 located on the base substrate;
  • the shielding structure 231 By disposing the shielding structure 231 between the first conductive region 201a of the first active layer 201 and the first conductive region 203a of the third active layer 203, the third active layer 203 and the first active layer can be shielded
  • the signal interference between the layers 201 further prevents the signal of the data signal line VD from being disturbed. good display.
  • the above-mentioned display panel provided by the embodiment of the present disclosure may further include: a fourth conductive layer 24 located on the side of the semiconductor layer 20 away from the base substrate;
  • FIG. 18 is a schematic top view of the structure of the fourth conductive layer 24 corresponding to a plurality of sub-pixels
  • FIG. 19 is an enlarged schematic view of the fourth conductive layer 24 corresponding to one sub-pixel in FIG.
  • the layer 24 includes: a fixed potential signal line VDD extending along the first direction F1;
  • the shielding structure 231 is electrically connected to the fixed potential signal line VDD.
  • the fixed potential signal line VDD has a stable power supply signal.
  • a high-level power supply signal can be applied to the fixed potential signal line VDD, or a low-level power supply signal can also be applied to the fixed potential signal line VDD.
  • the magnitude of the power supply signal applied to the fixed potential signal line VDD is not limited here.
  • the shielding structure 231 is set to be electrically connected to the fixed potential signal line VDD, and during the light-emitting process, the shielding structure 231 has a stable power supply signal, so as to play a better shielding effect, and further reduce the connection between the third active layer 203 and the third active layer 203. Signal interference between the first active layers 201 prevents the signal jump of the data signal line VD from affecting the driving gate G1 of the driving transistor.
  • the shielding structure 231 and the initialization signal line VINIT are arranged on the same layer.
  • the shielding structure 231 and the initialization signal line VINIT can be fabricated by the same patterning process.
  • the shielding structure 231 and the initialization signal line VINIT can be obtained at the same time. graphics, thereby reducing one-step manufacturing process and saving manufacturing costs.
  • the third conductive layer 23 may further include: a conductive connection structure 232 connected to the shielding structure 231 ;
  • the fixed potential signal line VDD is electrically connected to the shielding structure 231 through the conductive connection structure 232 .
  • the orthographic projection of the fixed potential signal line VDD on the base substrate has a certain distance from the orthographic projection of the shielding structure 231 on the base substrate.
  • the conductive connection structure 232 in the third conductive layer 23
  • the electrical connection between the fixed potential signal line VDD and the shielding structure 231 can be realized.
  • an insulating layer is provided between the third conductive layer 23 and the fourth conductive layer 24, and the conductive connection structure 232 can be connected to the shielding structure 231 through the via hole in the insulating layer.
  • the fixed potential signal line VDD is connected, and the conductive connection structure 232 is connected to the shielding structure 231 in the same layer.
  • the conductive connection structure 232 and the shielding structure 231 can be made into the same pattern, so as to avoid setting the connection separately
  • the structure and the manufacturing process are relatively simple.
  • the first conductive layer 21 can be disposed on the side of the semiconductor layer 20 away from the base substrate 10
  • the second conductive layer 22 can be disposed on the first conductive layer 21 and the semiconductor layer 20
  • the third conductive layer 23 is arranged between the first conductive layer 21 and the second conductive layer 22
  • the fourth conductive layer 24 is arranged between the first conductive layer 21 and the third conductive layer 23.
  • a fifth conductive layer 25 is further provided on the side of the first conductive layer 21 away from the base substrate 10 , and the fifth conductive layer 25 includes a plurality of anodes 251 .
  • a first gate insulating layer GI1 may be provided between the semiconductor layer 20 and the second conductive layer 22 , and a first gate insulating layer GI1 may be provided between the second conductive layer 22 and the third conductive layer 23 .
  • the second gate insulating layer GI2 is provided, the interlayer insulating layer ILD is provided between the third conductive layer 23 and the fourth conductive layer 24, the first flat layer PLN1 is provided between the first conductive layer 21 and the fourth conductive layer 24, A second flat layer PLN2 is disposed between a conductive layer 21 and the fifth conductive layer 25 .
  • the fourth conductive layer 24 may further include: a first conductive connection part LB1 , a second conductive connection part LB2 and a third conductive connection part LB2 which are insulated from each other. connection part LB3;
  • the driving gate G1 is electrically connected to the first conductive region 201a of the first active layer 201 through the first conductive connection portion LB1.
  • the upper end is connected to the first conductive region 201a of the first active layer 201 through at least one via penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1, and the other One end (ie, the lower end in FIG. 19 ) is connected to the driving gate G1 through at least one via hole penetrating the interlayer insulating layer ILD and the second gate insulating layer GI2 .
  • the data signal line VD is electrically connected to the first conductive region 203a of the third active layer 203 through the second conductive connection portion LB2.
  • one end of the second conductive connection portion LB2 passes through At least one via penetrating through the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1 is connected to the first conductive region 203a of the third active layer 203, and the other end (ie, FIG. 19 The lower end in the middle) is connected to the data signal line VD through at least one via hole penetrating the first flat layer PLN1.
  • the initialization signal line VINIT is electrically connected to the first conductive region 202a of the second active layer 202 through the third conductive connection portion LB3.
  • the third conductive connection portion LB3 ie, the upper end in FIG. 19
  • the other end ie, the lower end in FIG. 19
  • the interlayer insulating layer ILD passes through the interlayer insulating layer ILD, the second gate insulating layer GI2 and the first gate insulating layer.
  • At least one via hole of the layer GI1 is connected to the first conductive region 202 a of the second active layer 202 .
  • the fourth conductive layer 24 may further include: a fourth conductive connection part LB4, one end (the right end in FIG. 19 ) of the fourth conductive connection part LB4 passes through the interlayer insulating layer ILD and the second gate insulating layer GI2 and at least one via hole of the first gate insulating layer GI1 are connected to the first conductive region 206a of the sixth active layer 206 of the second light-emitting control transistor, and the other end (the left end in FIG.
  • a fourth conductive connection part LB4 one end (the right end in FIG. 19 ) of the fourth conductive connection part LB4 passes through the interlayer insulating layer ILD and the second gate insulating layer GI2 and at least one via hole of the first gate insulating layer GI1 are connected to the first conductive region 206a of the sixth active layer 206 of the second light-emitting control transistor, and the other end (the left end in FIG.
  • the first active layer 201 includes: a first bending part LZ1, and a second bending part LZ2;
  • One end of the first bending portion LZ1 is the first conductive region 201a of the first active layer 201, and the other end is connected to the second bending portion LZ2, and is bent toward the side away from the data signal line VD;
  • the second bending portion LZ2 is “n” shaped, one end of the second bending portion LZ2 is connected to the first bending portion LZ1 , and the other end is connected to the second active layer 202 .
  • the above-mentioned second conductive layer 22 may further include: a reset line RST, and the gate of the initialization transistor is the part where the reset line RST overlaps with the first active layer 201 . It can be seen from FIG. 7 that the first has The source layer 201 has two parts overlapping with the reset line RST. Therefore, the initialization transistor is a double-gate structure, and the second bent portion LZ2 is set to an "n" shape, which is easier to form a double-gate structure with the reset line RST.
  • the first bending portion LZ1 is set as: one end is the first conductive region 201a of the first active layer 201, and the other end is bent toward the side away from the data signal line VD, which can be the second bending portion LZ2 More space is left, so that the distances between the first bent portion LZ1 and the second bent portion LZ2 and the first conductive region 203 a of the third active layer 203 are both farther.
  • the distance between the first conductive region 201a of the first active layer 201 and the first conductive region 203a of the third active layer 203 in the second direction F2 is d1
  • the distance between any point at the edge of the folded portion LZ1 and the first conductive region 203a of the third active layer 203 in the second direction F2 is d2. It can be clearly seen from the figure that d2 is greater than d1, that is, the first bending The distance between the portion LZ1 and the first conductive region 203a of the third active layer 203 is relatively large.
  • the second active layer 202 includes: a first branch portion FZ1, and a second branch portion FZ2;
  • One end of the first branch portion FZ1 is the first conductive region 202a of the second active layer 202, and the other end is connected to the second branch portion FZ2;
  • the first branch portion FZ1 extends along the second direction F2, and the second branch portion FZ2 extends along the first direction F1.
  • Disposing the first conductive region 202a of the second active layer 202 on the side of the first branch portion FZ1 away from the first active layer 201 is more beneficial to connect the first conductive region 202a of the second active layer 202 with the first conductive region 202a of the second active layer 202.
  • the initialization signal line VINIT is connected, and the first branch portion FZ1 is arranged on the side of the second branch portion FZ2 away from the first active layer 201 , which can leave more space for the first active layer 201 .
  • the second branch portion FZ2 is arranged to extend along the first direction F1 to facilitate connection with the sixth active layer 206 .
  • the third active layer 203 includes: a conductive protrusion TQ, and a conductive extension YS extending along the first direction F1;
  • One end of the conductive raised portion TQ is the first conductive region 203 a of the third active layer 203 , and the other end is connected to the conductive extension portion YS.
  • the second conductive layer 22 may further include: a scan line GA extending along the second direction F2, and the gate of the data writing transistor is the portion where the scan line GA and the third active layer 203 overlap.
  • the conductive extension portion YS is arranged to extend along the first direction F1, so that the third active layer 203 can have an overlapping portion with the scan line GA.
  • the conductive bumps TQ By arranging the conductive bumps TQ, it is convenient for the first conductive region 203a to be electrically connected to the data signal line VD, and the conductive bumps TQ can be arranged on the side of the conductive extension YS close to the first active layer 201, and also It can be disposed on the side of the conductive extension YS away from the first active layer 201, which is not limited here.
  • the above-mentioned semiconductor layer 20 may further include: a fourth active layer 204 of the driving transistor T4 , a fifth active layer 205 of the first light emission control transistor, and a sixth active layer of the second light emission control transistor layer 206, and the seventh active layer 207 of the threshold compensation transistor, each active layer in the semiconductor layer 20 may include a first conductive region, a second conductive region and a channel region, and the channel region may be located in the first conductive region Between the conductive region and the second conductive region, optionally, the first conductive region is used as the source of the transistor, and the second conductive region is used as the drain of the transistor; or the first conductive region is used as the drain of the transistor, and the first conductive region is used as the drain of the transistor.
  • the biconductive region serves as the source of the transistor, which is not limited here.
  • each active layer in the semiconductor layer 20 may be integrally provided.
  • the connected active layers may share a conductive region.
  • the first active layer 201 and the second active layer 202 share a conductive region b1, as shown in the third active layer.
  • the layer 203 , the fourth active layer 204 , and the fifth active layer 205 share the conductive region b2 .
  • other active layers may also share the conductive region, which will not be repeated here.
  • the semiconductor layer 20 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned first conductive region and second conductive region may be regions doped with n-type impurities or p-type impurities.
  • the second conductive layer 22 may include the second electrode c2 of the storage capacitor CST, the scan line GA, the reset line RST, the light emission control line EM, the drive gate G1 of the drive transistor, The gate of the data writing transistor, the gate of the threshold compensation transistor, the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the initialization transistor and the gate of the reset transistor, wherein the driving transistor
  • the gate G1 may be the second pole c2 that stores the CST.
  • the gate of the data writing transistor may be the portion where the scan line GA and the third active layer overlap
  • the gate of the first light-emitting control transistor may be the light-emitting control line EM and the third active layer.
  • the gate of the second light-emitting control transistor can be the part where the light-emitting control line EM and the sixth active layer 206 overlap
  • the gate of the initialization transistor is the reset line RST and the first active layer
  • the gate of the reset transistor is the part where the reset line RST overlaps with the second active layer 202
  • the threshold compensation transistor can be a thin film transistor with a double gate structure
  • the first gate of the threshold compensation transistor can be a scan
  • the second gate of the threshold compensation transistor may be the portion where the protrusion protruding from the scan line GA overlaps the seventh active layer 207 .
  • the scan lines GA, the reset lines RST and the light emission control lines EM are arranged along the first direction F1. And the scan line GA, the reset line RST and the light emission control line EM extend substantially along the second direction F2. Exemplarily, the scan line GA is located between the reset line RST and the light emission control line EM.
  • the second pole c2 of the storage capacitor CST is located between the scan line GA and the light emission control line EM.
  • the protrusion protruding from the scanning line GA is located on the side of the scanning line GA away from the light emission control line EM.
  • the third conductive layer 13 may include the first electrode c1 of the storage capacitor CST, the initialization signal line VINIT, the shielding structure 231 and the conductive connection structure 232, wherein the first electrode of the storage capacitor CST The pole c1 at least partially overlaps with the second pole c2 of the storage capacitor CST to form the storage capacitor CST.
  • FIG. 20 is a schematic top view of the structure of the fifth conductive layer in the embodiment of the disclosure.
  • the plurality of anodes in the fifth conductive layer can be divided into a first anode 251a, a second anode 251b, a third anode 251c and a
  • the fourth anode 251d correspondingly, the plurality of sub-pixels in the display panel may be divided into a plurality of repeating units, and each repeating unit may include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, wherein , the first sub-pixel may include a first anode 251a, the second sub-pixel may include a second anode 251b, the third sub-pixel may include a third anode 251c, and the fourth sub-pixel may include a fourth anode 251d.
  • the number of sub-pixels in the repeating structure may also be other values, which are not limited here.
  • a plurality of sub-pixels spx in the display panel are arranged in an array in the first direction F1 and the second direction F2;
  • the display panel includes a plurality of data signal lines, and the data signal lines are divided into a first data signal line VD1 and a second data signal line VD2;
  • each column of sub-pixels spx the sub-pixels spx in odd-numbered rows share a first data signal line VD1, and the sub-pixels spx in even-numbered rows share a second data signal line VD2, for example, in FIG.
  • the first, third and fifth sub-pixels spx are all connected to the first data signal line VD1
  • the second, fourth and sixth sub-pixels spx are all connected to the second data signal line VD2.
  • each row of sub-pixels for example, a row of sub-pixels arranged along the second direction F2 in FIG. 1
  • each column of sub-pixels spx It is set as follows: the sub-pixels spx of odd-numbered rows share a first data signal line VD1, and the sub-pixels spx of even-numbered rows share a second data signal line VD2.
  • the sub-pixels of odd-numbered rows and the sub-pixels of even-numbered rows can be respectively adjusted to It is driven to solve the problem of insufficient writing time for each row of sub-pixel data during high frame rate display.
  • the second direction F2 is used as the row direction
  • the first direction F1 is used as the column direction for illustration.
  • the direction F2 is used as the column direction, which is not limited here.
  • the display panel may include sub-pixels spx of multiple colors, for example, may include sub-pixels spx of three colors of red, green, and blue, or may include sub-pixels spx of four colors, or more
  • the sub-pixels of the color are not limited here.
  • the plurality of sub-pixels spx in the display panel may be arranged neatly as shown in FIG. 1 , or may be set so that adjacent sub-pixel rows are staggered by a certain distance, and the arrangement of the sub-pixels is not limited here.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel, the display device can be applied to any mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. functional product or component. Since the principle of solving the problem of the display device is similar to that of the above-mentioned display panel, the implementation of the display device can refer to the implementation of the above-mentioned display panel, and the repetition will not be repeated.
  • the first active layer connected to the driving gate is enlarged, and the first active layer is connected to the data signal line.
  • the distance between the third active layers connected by the signal lines alleviates the influence of the data signal lines on the driving gates of the driving transistors and improves the display effect of the display panel.

Abstract

本公开实施例提供了一种显示面板及显示装置，显示面板包括：衬底基板，以及位于衬底基板之上的多个子像素；子像素，包括：半导体层，位于衬底基板之上；半导体层包括：初始化晶体管的第一有源层，复位晶体管的第二有源层，数据写入晶体管的第三有源层；第一导电层，位于半导体层背离衬底基板的一侧；第一导电层包括：沿第一方向延伸的数据信号线；第二导电层，位于衬底基板之上；第二导电层包括：驱动晶体管的驱动栅极；驱动栅极与第一有源层的第一导电化区域电连接；数据信号线与第三有源层的第一导电化区域电连接；第二有源层在衬底基板上的正投影，位于第一有源层在衬底基板上的正投影与数据信号线在衬底基板上的正投影之间。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤指一种显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。
随着显示技术的不断发展，人们对显示效果的要求也越来越高，近年来高刷新频率显示产品越来越受到关注，然而，对于高刷新频率的显示面板，数据信号的跳变会对驱动晶体管的栅极产生影响，从而影响显示效果。
发明内容
本公开实施提供的显示面板，其中，所述显示面板包括：衬底基板，以及位于所述衬底基板之上的多个子像素；
所述子像素，包括：
半导体层，位于所述衬底基板之上；所述半导体层包括：初始化晶体管的第一有源层，复位晶体管的第二有源层，数据写入晶体管的第三有源层；
第一导电层，位于所述半导体层背离所述衬底基板的一侧；所述第一导电层包括：沿第一方向延伸的数据信号线；
第二导电层，位于所述衬底基板之上；所述第二导电层包括：驱动晶体管的驱动栅极；
所述驱动栅极与所述第一有源层的第一导电化区域电连接；
所述数据信号线与所述第三有源层的第一导电化区域电连接；
所述第二有源层在所述衬底基板上的正投影，位于所述第一有源层在所述衬底基板上的正投影与所述数据信号线在所述衬底基板上的正投影之间。
可选地，在本公开实施例中，所述第二有源层的沟道区在所述衬底基板上的正投影，位于所述第一有源层的沟道区在所述衬底基板上的正投影与所述数据信号线在所述衬底基板上的正投影之间。
可选地，在本公开实施例中，还包括：
第三导电层，位于所述衬底基板之上；所述第三导电层包括：沿第二方向延伸的初始化信号线；所述第二方向为与所述第一方向交叉的方向；
所述初始化信号线与所述第二有源层的第一导电化区域电连接；
所述第二有源层的第一导电化区域位于所述第二有源层背离所述第一有源层的一端。
可选地，在本公开实施例中，还包括：位于所述衬底基板之上的屏蔽结构；
所述屏蔽结构在所述衬底基板上的正投影，位于所述第一有源层的第一导电化区域在所述衬底基板上的正投影与所述三有源层的第一导电化区域在所述衬底基板上的正投影之间。
可选地，在本公开实施例中，还包括：位于所述半导体层背离所述衬底基板的一侧的第四导电层；
所述第四导电层包括：沿所述第一方向延伸的固定电位信号线；
所述屏蔽结构与所述固定电位信号线电连接。
可选地，在本公开实施例中，所述屏蔽结构与所述初始化信号线同层设置。
可选地，在本公开实施例中，所述第三导电层，还包括：与所述屏蔽结构相连的导电连接结构；
所述固定电位信号线通过所述导电连接结构与所述屏蔽结构电连接。
可选地，在本公开实施例中，所述第四导电层，还包括：相互绝缘的第一导电连接部、第二导电连接部及第三导电连接部；
所述驱动栅极通过所述第一导电连接部与所述第一有源层的第一导电化区域电连接；
所述数据信号线通过所述第二导电连接部与所述第三有源层的第一导电化区域电连接；
所述初始化信号线通过所述第三导电连接部与所述第二有源层的第一导电化区域电连接。
可选地，在本公开实施例中，所述第一有源层包括：第一弯折部，以及第二弯折部；
所述第一弯折部的一端为所述第一有源层的第一导电化区域，另一端与所述第二弯折部相连，并朝向背离所述数据信号线的一侧弯折；
所述第二弯折部为“n”字型，所述第二弯折部的一端与所述第一弯折部相连，另一端与所述第二有源层相连。
可选地，在本公开实施例中，所述第二有源层包括：第一分支部，以及第二分支部；
所述第一分支部的一端为所述第二有源层的第一导电化区域，另一端与所述第二分支部相连；
所述第一分支部沿所述第二方向延伸，所述第二分支部沿所述第一方向延伸。
可选地，在本公开实施例中，所述第三有源层包括：导电凸起部，以及沿所述第一方向延伸的导电延伸部；
所述导电凸起部的一端为所述第三有源层的第一导电化区域，另一端与所述导电延伸部连接。
可选地，在本公开实施例中，所述显示面板中的多个子像素在所述第一方向和所述第二方向呈阵列排布；
所述显示面板包括多条所述数据信号线，且所述数据信号线分为第一数据信号线与第二数据信号线；
每一列所述子像素中，奇数行的所述子像素共用一条所述第一数据信号线，偶数行的所述子像素共用一条所述第二数据信号线。
相应地，本公开实施例还提供了一种显示装置，包括：上述显示面板。
附图说明
图1为本公开实施例提供的显示面板的俯视结构示意图；
图2为本公开实施例中一种像素驱动电路的结构示意图；
图3为图2所示的像素驱动电路对应的信号时序图；
图4为本公开实施例提供的显示面板中多个子像素的布局结构示意图；
图5为图4中虚线A1-A2处的截面示意图；
图6为本公开实施例提供的显示面板中一个子像素的布局结构示意图；
图7至图9为本公开实施例提供的显示面板中多个膜层的俯视结构示意图；
图10为多个子像素对应的半导体层的俯视结构示意图；
图11为图10中一个子像素对应的半导体层的放大示意图；
图12为多个子像素对应的第一导电层的俯视结构示意图；
图13为图12中一个子像素对应的第一导电层的放大示意图；
图14为多个子像素对应的第二导电层的俯视结构示意图；
图15为图14中一个子像素对应的第二导电层的放大示意图；
图16为多个子像素对应的第三导电层的俯视结构示意图；
图17为图16中一个子像素对应的第三导电层的放大示意图；
图18为多个子像素对应的第四导电层的俯视结构示意图；
图19为图18中一个子像素对应的第四导电层的放大示意图；
图20为多个子像素对应的第五导电层的俯视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
图1为本公开实施例提供的显示面板的俯视结构示意图，如图1所示，本公开实施例提供的显示面板可以包括：衬底基板10，以及位于衬底基板10之上的多个子像素spx，多个子像素spx在第一方向F1和第二方向F2呈阵列排布。
示例性地，图2为本公开实施例中一种像素驱动电路的结构示意图，结合图1与图2所示，多个子像素spx中的至少一个子像素spx可以包括：像素驱动电路121和发光器件120，其中，像素驱动电路121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光器件120的阳极中，并且对发光器件120的阴极加载相应的电压，可以驱动发光器件120发光。
结合图2所示，像素驱动电路121可以包括：驱动控制电路122、第一发光控制电路123、第二发光控制电路124、数据写入电路125、存储电路126、阈值补偿电路127和复位电路128。
驱动控制电路122可以包括控制端、第一端和第二端。且驱动控制电路122被配置为向发光器件120提供驱动电流，以驱动发光器件120发光。例如，第一发光控制电路123与驱动控制电路122的第一端和第一电压端VDD连接，且第一发光控制电路123被配置为实现驱动控制电路122和第一电压端VDD 之间的连接导通或断开。
第二发光控制电路124与驱动控制电路122的第二端和发光器件120的阳极电连接，且第二发光控制电路124被配置为实现驱动控制电路122和发光器件120之间的连接导通或断开。
数据写入电路125与驱动控制电路122的第一端电连接。且第二发光控制电路124被配置为将数据信号线VD上的信号写入存储电路126。
存储电路126与驱动控制电路122的控制端和第一电压端VDD电连接。且存储电路126被配置为存储数据信号。
阈值补偿电路127分别与驱动控制电路122的控制端和第二端电连接。且阈值补偿电路127被配置为对驱动控制电路122进行阈值补偿。
复位电路128分别与驱动控制电路122的控制端和发光器件120的阳极电连接。且复位电路128被配置为对发光器件120的阳极进行复位，以及对驱动控制电路122的控制端进行复位。
其中，发光器件120可以设置为电致发光二极管，例如OLED和QLED中的至少一种。其中，发光器件120可以包括层叠设置的阳极、发光功能层、阴极。进一步地，发光功能层可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光器件120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2所示，驱动控制电路122可以包括：驱动晶体管T4，驱动控制电路122的控制端包括驱动晶体管T4的驱动栅极，驱动控制电路122的第一端包括驱动晶体管T4的第一极，驱动控制电路122的第二端包括驱动晶体管T4的第二极。
示例性地，结合图2所示，数据写入电路125可以包括数据写入晶体管T3。存储电路126可以包括存储电容CST。阈值补偿电路127包括阈值补偿晶体管T7。第一发光控制电路123可以包括第一发光控制晶体管T5。第二发光控制电路124可以包括第二发光控制晶体管T6。复位电路128可以包括初始化晶体管T1和复位晶体管T2。
具体地，数据写入晶体管T3的第一极与驱动晶体管T4的第一极电连接，数据写入晶体管T3的第二极被配置为与数据信号线VD电连接，以接收数据信号，数据写入晶体管T3的栅极被配置为与扫描线GA电连接以接收信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T4的驱动栅极电连接。
阈值补偿晶体管T7的第一极与驱动晶体管T4的第二极电连接，阈值补偿晶体管T7的第二极与驱动晶体管T4的栅极电连接，阈值补偿晶体管T7的栅极被配置为与扫描线GA电连接以接收信号。
初始化晶体管T1的第一极被配置为与初始化信号线VINIT电连接，以接收复位信号，初始化晶体管T1的第二极与驱动晶体管T4的驱动栅极电连接，初始化晶体管T1的栅极被配置为与复位线RST电连接，以接收信号。
复位晶体管T2的第一极被配置为与初始化信号线VINIT电连接，以接收复位信号，复位晶体管T2的第二极与发光器件120的阳极电连接，复位晶体管T2的栅极被配置为与复位线RST电连接，以接收信号。
第一发光控制晶体管T5的第一极与第一电源端VDD电连接，第一发光控制晶体管T5的第二极与驱动晶体管T4的第一极电连接，第一发光控制晶体管T5的栅极被配置为与发光控制线EM电连接，以接收发光控制信号。
第二发光控制晶体管T6的第一极与驱动晶体管T4的第二极电连接，第二发光控制晶体管T6的第二极与发光器件120的阳极电连接，第二发光控制晶体管T6的栅极被配置为与发光控制线EM电连接，以接收发光控制信号。
发光器件120的阴极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
图3为图2所示的像素驱动电路对应的信号时序图，如图3所示，一帧显示时间中，像素驱动电路的工作过程可以具有三个阶段：T10阶段、T20阶段、T30阶段。其中，rst代表复位线RST上传输的信号，ga代表扫描线GA上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号rst控制初始化晶体管T1导通，从而可以将初始化信号线VINIT上传输的信号提供给驱动晶体管T4的栅极，以对驱动晶体管T4的驱动栅极进行复位。信号rst控制复位晶体管T2导通，以将初始化信号线VINIT上传输的信号提供给发光器件120的阳极，以对发光器件120的阳极进行复位。并且，此阶段中，信号ga控制数据写入晶体管T3和阈值补偿晶体管T7均截止。信号em控制第一发光控制晶体管T5和第二发光控制晶体管T6均截止。
在T20阶段，信号ga控制数据写入晶体管T3和阈值补偿晶体管T7导通，导通的数据写入晶体管T3使数据信号线VD上传输的数据信号对驱动晶体管T4的驱动栅极进行充电，以使驱动晶体管T4的驱动栅极的电压变为：Vdata+|Vth|，其中，Vth代表驱动晶体管T4的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号rst控制初始化晶体管T1和复位晶体管T2均截止。信号em控制第一发光控制晶体管T5和第二发光控制晶体管T6均截止。
在T30阶段，信号em控制第一发光控制晶体管T5和第二发光控制晶体管T6均导通。导通的第一发光控制晶体管T5将第一电源端VDD的电压Vdd提供给驱动晶体管T4的第一极，以使驱动晶体管T4的第一极的电压为Vdd。驱动晶体管T4根据其驱动栅极的电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流，该驱动电流通过导通的第二发光控制晶体管T6提供给发光器件120，驱动发光器件120发光。并且，此阶段中，信号rst控制初始化晶体管T1和复位晶体管T2截止。信号ga控制数据写入晶体管T3和阈值补偿晶体管T7截止。
需要说明的是，在本公开实施例中，除了图2所示的像素驱动电路外， 本公开实施例中的子像素也可以包括其他结构的像素驱动电路，即还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
本公开实施例提供的显示面板中，如图1所示，显示面板可以包括：衬底基板10，以及位于衬底基板10之上的多个子像素spx，图1中以有限数量的子像素spx的一种排布方式进行示意，并不对子像素spx的数量和排布方式进行限定。
图4为本公开实施例提供的显示面板中多个子像素的布局结构示意图，图5为图4中虚线A1-A2处的截面示意图，图6为本公开实施例提供的显示面板中一个子像素的布局结构示意图，为了更清楚的示意各膜层的结构，图7至图9中示出了图6中部分膜层的俯视结构示意图，如图4至图9所示，本公开实施例中，上述子像素，可以包括：
半导体层20，位于衬底基板之上；图10为多个子像素对应的半导体层20的俯视结构示意图，图11为图10中一个子像素对应的半导体层20的放大示意图，结合图10和图11所示，半导体层20包括：初始化晶体管的第一有源层201，复位晶体管的第二有源层202，数据写入晶体管的第三有源层203；
具体地，半导体层20可以采用半导体材料图案化形成，且半导体层20中的各有源层可以包括第一导电化区域、第二导电化区域及沟道区，沟道区可以位于第一导电化区域与第二导电化区域之间，其中，第一导电化区域和第二导电化区域可以为半导体层20导体化得到，例如，可以采用向半导体层20中掺入n型杂质和p型杂质，使半导体层20导体化得到第一导电化区域和第二导电化区域。可选地，第一导电化区域作为晶体管的源极，第二导电化区域作为晶体管的漏极；或者，第一导电化区域作为晶体管的漏极，第二导电化区域作为晶体管的源极，此处不做限定。
第一导电层21，位于半导体层20背离衬底基板的一侧；图12为多个子像素对应的第一导电层21的俯视结构示意图，图13为图12中一个子像素对应的第一导电层21的放大示意图，结合图12和图13所示，第一导电层21包括：沿第一方向F延伸的数据信号线VD；
第二导电层22，位于衬底基板之上；图14为多个子像素对应的第二导电层22的俯视结构示意图，图15为图14中一个子像素对应的第二导电层的放大示意图，结合图14和图15所示，第二导电层22包括：驱动晶体管的驱动栅极G1；
驱动栅极G1与第一有源层201的第一导电化区域201a电连接；
数据信号线VD与第三有源层203的第一导电化区域203a电连接；
第二有源层202在衬底基板上的正投影，位于第一有源层201在衬底基板上的正投影与数据信号线VD在衬底基板上的正投影之间。
在实际应用中，由于显示面板的刷新频率较高，在发光过程中，数据信号线中的电位是跳动的，可能会出现电场耦合产生的扰动，引起驱动晶体管的驱动栅极的电位发生变化，从而影响显示效果，本公开实施例中，通过将第一有源层201设置在第二有源层202背离数据信号线VD的一侧，从而增大驱动栅极G1连接的第一有源层201，与数据信号线VD连接的第三有源层203之间的距离，缓解数据信号线VD对驱动晶体管的驱动栅极G1的影响，提高显示面板的显示效果。
具体地，本公开实施例提供的上述显示面板中，结合图6、图11和图13，第二有源层202的沟道区202c在衬底基板上的正投影，位于第一有源层201的沟道区201c在衬底基板上的正投影与数据信号线VD在衬底基板上的正投影之间，从而，进一步保证驱动栅极G1连接的第一有源层201，与数据信号线VD连接的第三有源层203之间的距离较远，进一步减弱数据信号线VD对驱动晶体管的驱动栅极G1的影响，保证显示面板具有较好的显示效果。
进一步地，本公开实施例提供的上述显示面板中，如图7至图9所示，还可以包括：
第三导电层23，位于衬底基板之上；图16为多个子像素对应的第三导电层23的俯视结构示意图，图17为图16中一个子像素对应的第三导电层23的放大示意图，结合图16和图17所示，第三导电层23包括：沿第二方向F2延伸的初始化信号线VINIT；第二方向F2为与第一方向F1交叉的方向；
初始化信号线VINIT与第二有源层202的第一导电化区域202a电连接；
第二有源层202的第一导电化区域202a位于第二有源层202背离第一有源层201的一端。
通过将与初始化信号线VINIT连接的第一导电化区域202a，设置在第二有源层202背离第一有源层201的一端，可以为第一有源层201留出更多的空间，从而使第一有源层201的图形与第三有源层203的第一导电化区域203a之间的距离较远，避免数据信号线VD的信号通过第三有源层203、第二有源层202，而影响驱动晶体管的驱动栅极的电位，保证显示面板具有较好的显示效果。
更进一步地，本公开实施例提供的显示面板中，参照图7，还可以包括：位于衬底基板之上的屏蔽结构231；
屏蔽结构231在衬底基板上的正投影，位于第一有源层201的第一导电化区域201a在衬底基板上的正投影与三有源层203的第一导电化区域203a在衬底基板上的正投影之间。
通过在第一有源层201的第一导电化区域201a与第三有源层203的第一导电化区域203a之间，设置屏蔽结构231，可以屏蔽第三有源层203与第一有源层201之间的信号干扰，进一步避免数据信号线VD的信号产生扰动，通过第三有源层203、第一有源层201，影响驱动晶体管的驱动栅极G1的电位，保证显示面板具有较好的显示效果。
在具体实施时，本公开实施例提供的上述显示面板中，还可以包括：位于半导体层20背离衬底基板的一侧的第四导电层24；
图18为多个子像素对应的第四导电层24的俯视结构示意图，图19为图18中一个子像素对应的第四导电层24的放大示意图，结合图18和图19所示，第四导电层24包括：沿第一方向F1延伸的固定电位信号线VDD；
屏蔽结构231与固定电位信号线VDD电连接。
在发光过程中，固定电位信号线VDD中具有稳定的电源信号，例如可以向固定电位信号线VDD施加高电平的电源信号，或者也可以向固定电位信号 线VDD施加低电平的电源信号，此处不对向固定电位信号线VDD中施加的电源信号的大小进行限定。将屏蔽结构231设置为与固定电位信号线VDD电连接，在发光过程中，使屏蔽结构231中具有稳定的电源信号，从而起到更好的屏蔽作用，进一步减小第三有源层203与第一有源层201之间的信号干扰，从而避免数据信号线VD的信号跳动，对驱动晶体管的驱动栅极G1产生影响。
在具体实施时，本公开实施例提供的上述显示面板中，参照图16和图17，屏蔽结构231与初始化信号线VINIT同层设置。这样，在工艺过程中，可以将屏蔽结构231与初始化信号线VINIT采用同一构图工艺制作，具体地，可以在对第三导电层23进行图形化的时候，同时得到屏蔽结构231与初始化信号线VINIT的图形，从而减少一步制作工艺，节约制作成本。
具体地，本公开实施例提供的上述显示面板中，参照图17，第三导电层23，还可以包括：与屏蔽结构231相连的导电连接结构232；
固定电位信号线VDD通过导电连接结构232与屏蔽结构231电连接。
同时参照图8，固定电位信号线VDD在衬底基板上的正投影，与屏蔽结构231在衬底基板上的正投影具有一定的距离，通过在第三导电层23中设置导电连接结构232，可以实现固定电位信号线VDD与屏蔽结构231之间的电连接，具体地，第三导电层23与第四导电层24之间具有绝缘层，导电连接结构232可以通过绝缘层中的过孔与固定电位信号线VDD连接，并且，导电连接结构232与同一层中的屏蔽结构231连接，在制作工艺过程中，可以将导电连接结构232与屏蔽结构231制作为同一块图形，从而避免单独设置连接结构，制作工艺较简单。
在具体实施时，如图5所示，可以将第一导电层21设置于半导体层20背离衬底基板10的一侧，可以将第二导电层22设置于第一导电层21与半导体层20之间，将第三导电层23设置于第一导电层21与第二导电层22之间，将第四导电层24设置于第一导电层21与第三导电层23之间，此外，在第一导电层21背离衬底基板10的一侧还设有第五导电层25，第五导电层25包括 多个阳极251。为了避免相邻导电层之间的导电部件短接，可以在半导体层20与第二导电层22之间设置第一栅极绝缘层GI1，在第二导电层22与第三导电层23之间设置第二栅极绝缘层GI2，第三导电层23与第四导电层24之间设置层间绝缘层ILD，第一导电层21与第四导电层24之间设置第一平坦层PLN1，第一导电层21与第五导电层25之间设置第二平坦层PLN2。
在实际应用中，本公开实施例提供的上述显示面板中，参照图19，第四导电层24，还可以包括：相互绝缘的第一导电连接部LB1、第二导电连接部LB2及第三导电连接部LB3；
同时参照图5，驱动栅极G1通过第一导电连接部LB1与第一有源层201的第一导电化区域201a电连接，具体地，第一导电连接部LB1的一端(即图19中靠上的一端)通过贯穿层间绝缘层ILD、第二栅极绝缘层GI2、第一栅极绝缘层GI1的至少一个过孔，与第一有源层201的第一导电化区域201a连接，另一端(即图19中靠下的一端)通过贯穿层间绝缘层ILD、第二栅极绝缘层GI2的至少一个过孔与驱动栅极G1连接。
数据信号线VD通过第二导电连接部LB2与第三有源层203的第一导电化区域203a电连接，具体地，第二导电连接部LB2的一端(即图19中靠上的一端)通过贯穿层间绝缘层ILD、第二栅极绝缘层GI2、第一栅极绝缘层GI1的至少一个过孔，与第三有源层203的第一导电化区域203a连接，另一端(即图19中靠下的一端)通过贯穿第一平坦层PLN1的至少一个过孔与数据信号线VD连接。
初始化信号线VINIT通过第三导电连接部LB3与第二有源层202的第一导电化区域202a电连接，具体地，第三导电连接部LB3的(即图19中靠上的一端)通过贯穿层间绝缘层ILD的至少一个过孔与初始化信号线VINIT连接，另一端(即图19中靠下的一端)通过贯穿层间绝缘层ILD、第二栅极绝缘层GI2、第一栅极绝缘层GI1的至少一个过孔，与第二有源层202的第一导电化区域202a连接。
此外，第四导电层24还可以包括：第四导电连接部LB4，第四导电连接 部LB4的一端(如图19中靠右的一端)通过贯穿层间绝缘层ILD、第二栅极绝缘层GI2、第一栅极绝缘层GI1的至少一个过孔，与第二发光控制晶体管的第六有源层206的第一导电化区域206a连接，另一端(如图19中靠左的一端)通过贯穿第一平坦层PLN1的至少一个过孔，与位于第一导电层21中的阳极转接部YZ连接，阳极转接部YZ通过贯穿第二平坦层PLN2的至少一个过孔与阳极251连接，从而实现第二发光控制晶体管与发光器件120的阳极之间的电连接。
具体地，本公开实施例提供的上述显示面板中，如图11所示，第一有源层201包括：第一弯折部LZ1，以及第二弯折部LZ2；
第一弯折部LZ1的一端为第一有源层201的第一导电化区域201a，另一端与第二弯折部LZ2相连，并朝向背离数据信号线VD的一侧弯折；
第二弯折部LZ2为“n”字型，第二弯折部LZ2的一端与第一弯折部LZ1相连，另一端与第二有源层202相连。
同时参照图14和图15，上述第二导电层22还可以包括：复位线RST，初始化晶体管的栅极为复位线RST与第一有源层201交叠的部分，结合图7可知，第一有源层201具有与复位线RST交叠的两个部分，因而，初始化晶体管为双栅结构，将第二弯折部LZ2设置为“n”字型，更容易与复位线RST构成双栅结构。并且，将第一弯折部LZ1设置为：一端为第一有源层201的第一导电化区域201a，另一端朝向背离数据信号线VD的一侧弯折，可以为第二弯折部LZ2留出更多的空间，以使第一弯折部LZ1和第二弯折部LZ2与第三有源层203的第一导电化区域203a的距离都较远。
具体地，如图11所示，第一有源层201的第一导电化区域201a与第三有源层203的第一导电化区域203a在第二方向F2上的距离为d1，第一弯折部LZ1边缘处任意一点与第三有源层203的第一导电化区域203a在第二方向F2上的距离为d2，从图中可以明显看出，d2大于d1，即，第一弯折部LZ1与第三有源层203的第一导电化区域203a之间的距离较远。
可选地，本公开实施例提供的上述显示面板中，如图11所示，第二有源 层202包括：第一分支部FZ1，以及第二分支部FZ2；
第一分支部FZ1的一端为第二有源层202的第一导电化区域202a，另一端与第二分支部FZ2相连；
第一分支部FZ1沿第二方向F2延伸，第二分支部FZ2沿第一方向F1延伸。
将第二有源层202的第一导电化区域202a设置在第一分支部FZ1远离第一有源层201的一侧，更有利于将第二有源层202的第一导电化区域202a与初始化信号线VINIT连接，并且，将第一分支部FZ1设置在第二分支部FZ2远离第一有源层201的一侧，可以为第一有源层201留出更多的空间。将第二分支部FZ2设置为沿第一方向F1延伸，便于与第六有源层206连接。
在具体实施时，本公开实施例提供的上述显示面板中，如图11所示，第三有源层203包括：导电凸起部TQ，以及沿第一方向F1延伸的导电延伸部YS；
导电凸起部TQ的一端为第三有源层203的第一导电化区域203a，另一端与导电延伸部YS连接。
如图14和图15所示，第二导电层22还可以包括：沿第二方向F2延伸的扫描线GA，数据写入晶体管的栅极为扫描线GA与第三有源层203交叠的部分，导电延伸部YS设置为沿第一方向F1延伸，使第三有源层203能够与扫描线GA具有交叠的部分。通过设置导电凸起部TQ，便于第一导电化区域203a与数据信号线VD实现电连接，并且，导电凸起部TQ可以设置在导电延伸部YS靠近第一有源层201的一侧，也可以设置在导电延伸部YS远离第一有源层201的一侧，此处不做限定。
此外，如图11所示，上述半导体层20还可以包括：驱动晶体管T4的第四有源层204、第一发光控制晶体管的第五有源层205、第二发光控制晶体管的第六有源层206，以及阈值补偿晶体管的第七有源层207，半导体层20中的各有源层可包括第一导电化区域、第二导电化区域及沟道区，沟道区可以位于第一导电化区域与第二导电化区域之间，可选地，第一导电化区域作为 晶体管的源极，第二导电化区域作为晶体管的漏极；或者第一导电化区域作为晶体管的漏极，第二导电化区域作为晶体管的源极，此处不做限定。此外，半导体层20中的各有源层可以一体设置。
在具体实施时，相连接的有源层可以共用导电化区域，例如，如图11所示，第一有源层201与第二有源层202共用导电化区域b1，又如第三有源层203、第四有源层204、第五有源层205共用导电化区域b2，此外，其他有源层也可以共用导电化区域，此处不再一一赘述。
具体地，半导体层20可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的第一导电化区域和第二导电化区域可为掺杂有n型杂质或p型杂质的区域。
示例性地，如图14和图15所示，第二导电层22可以包括存储电容CST的第二极c2、扫描线GA、复位线RST、发光控制线EM、驱动晶体管的驱动栅极G1、数据写入晶体管的栅极、阈值补偿晶体管的栅极、第一发光控制晶体管的栅极、第二发光控制晶体管的栅极、初始化晶体管的栅极及复位晶体管的栅极，其中驱动晶体管的驱动栅极G1可以为存储CST的第二极c2。
例如，结合图7和图11所示，数据写入晶体管的栅极可以为扫描线GA与第三有源层交叠的部分，第一发光控制晶体管的栅极可以为发光控制线EM与第五有源层205交叠的部分，第二发光控制晶体管的栅极可以为发光控制线EM与第六有源层206交叠的部分，初始化晶体管的栅极为复位线RST与第一有源层201交叠的部分，复位晶体管的栅极为复位线RST与第二有源层202交叠的部分，阈值补偿晶体管可为双栅结构的薄膜晶体管，阈值补偿晶体管的第一个栅极可为扫描线GA与第七有源层207交叠的部分，阈值补偿晶体管的第二个栅极可为从扫描线GA突出的突出部与第七有源层207交叠的部分。
示例性地，如图15所示，扫描线GA、复位线RST和发光控制线EM沿第一方向F1排布。且扫描线GA、复位线RST和发光控制线EM大致沿第二方向F2延伸。示例性地，扫描线GA位于复位线RST和发光控制线EM之间。
示例性地，在第一方向F1上，存储电容CST的第二极c2位于扫描线GA和发光控制线EM之间。并且，从扫描线GA突出的突出部位于扫描线GA远离发光控制线EM的一侧。
示例性地，参照图16和图17，上述第三导电层13可以包括存储电容CST的第一极c1、初始化信号线VINIT、屏蔽结构231及导电连接结构232，其中，存储电容CST的第一极c1与存储电容CST的第二极c2至少部分交叠，以形成存储电容CST。
图20为本公开实施例中第五导电层的俯视结构示意图，如图20所示，第五导电层中的多个阳极可以分为第一阳极251a、第二阳极251b、第三阳极251c及第四阳极251d，相应地，显示面板中的多个子像素可以分为多个重复单元，每一个重复单元可以包括第一子像素、第二子像素、第三子像素及第四子像素，其中，第一子像素可以包括第一阳极251a，第二子像素可以包括第二阳极251b，第三子像素可以包括第三阳极251c，第四子像素可以包括第四阳极251d，在具体实施时，重复结构中的子像素数量也可以为其他数值，此处不做限定。
在实际应用中，本公开实施例提供的上述显示面板中，如图1所示，显示面板中的多个子像素spx在第一方向F1和第二方向F2呈阵列排布；
同时参照图12，显示面板包括多条数据信号线，且数据信号线分为第一数据信号线VD1与第二数据信号线VD2；
每一列子像素spx中，奇数行的子像素spx共用一条第一数据信号线VD1，偶数行的子像素spx共用一条第二数据信号线VD2，例如图1中，第一列子像素spx中，第一个、第三个、第五个子像素spx均与第一数据信号线VD1连接，第二个、第四个、第六个子像素spx均与第二数据信号线VD2连接。
对于高刷新频率的显示面板来说，刷新频率的增大会压缩每行子像素(例如图1中沿第二方向F2排列的一排子像素)的数据信号写入时间，将每一列子像素spx设置为：奇数行的子像素spx共用一条第一数据信号线VD1，偶数行的子像素spx共用一条第二数据信号线VD2，在驱动过程中，可以分别 对奇数行子像素和偶数行子像素进行驱动，从而解决高帧频显示时，每行子像素数据写入时间不足的问题。应该说明的是，本公开实施例中，以第二方向F2为行方向，第一方向F1为列方向为例进行说明，在具体实施时，也可以将第一方向F1作为行方向，第二方向F2作为列方向，此处不做限定。
在具体实施时，显示面板可以包括多种颜色的子像素spx，例如可以包括红、绿、蓝三种颜色的子像素spx，或者，也可以包括四种颜色的子像素spx，或更多种颜色的子像素，此处不做限定。显示面板中的多个子像素spx可以如图1所示的整齐排列，也可以设置为相邻子像素行错开一定距离，此处不做子像素的排布方式进行限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括上述显示面板，该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与上述显示面板相似，因此该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
本公开实施例提供的显示面板及显示装置，通过将第一有源层设置在第二有源层背离数据信号线的一侧，从而增大驱动栅极连接的第一有源层，与数据信号线连接的第三有源层之间的距离，缓解数据信号线对驱动晶体管的驱动栅极的影响，提高显示面板的显示效果。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种显示面板，其中，所述显示面板包括：衬底基板，以及位于所述衬底基板之上的多个子像素；
    所述子像素，包括：
    半导体层，位于所述衬底基板之上；所述半导体层包括：初始化晶体管的第一有源层，复位晶体管的第二有源层，数据写入晶体管的第三有源层；
    第一导电层，位于所述半导体层背离所述衬底基板的一侧；所述第一导电层包括：沿第一方向延伸的数据信号线；
    第二导电层，位于所述衬底基板之上；所述第二导电层包括：驱动晶体管的驱动栅极；
    所述驱动栅极与所述第一有源层的第一导电化区域电连接；
    所述数据信号线与所述第三有源层的第一导电化区域电连接；
    所述第二有源层在所述衬底基板上的正投影，位于所述第一有源层在所述衬底基板上的正投影与所述数据信号线在所述衬底基板上的正投影之间。
  2. 如权利要求1所述的显示面板，其中，所述第二有源层的沟道区在所述衬底基板上的正投影，位于所述第一有源层的沟道区在所述衬底基板上的正投影与所述数据信号线在所述衬底基板上的正投影之间。
  3. 如权利要求1所述的显示面板，其中，还包括：
    第三导电层，位于所述衬底基板之上；所述第三导电层包括：沿第二方向延伸的初始化信号线；所述第二方向为与所述第一方向交叉的方向；
    所述初始化信号线与所述第二有源层的第一导电化区域电连接；
    所述第二有源层的第一导电化区域位于所述第二有源层背离所述第一有源层的一端。
  4. 如权利要求3所述的显示面板，其中，还包括：位于所述衬底基板之上的屏蔽结构；
    所述屏蔽结构在所述衬底基板上的正投影，位于所述第一有源层的第一 导电化区域在所述衬底基板上的正投影与所述三有源层的第一导电化区域在所述衬底基板上的正投影之间。
  5. 如权利要求4所述的显示面板，其中，还包括：位于所述半导体层背离所述衬底基板的一侧的第四导电层；
    所述第四导电层包括：沿所述第一方向延伸的固定电位信号线；
    所述屏蔽结构与所述固定电位信号线电连接。
  6. 如权利要求4所述的显示面板，其中，所述屏蔽结构与所述初始化信号线同层设置。
  7. 如权利要求6所述的显示面板，其中，所述第三导电层，还包括：与所述屏蔽结构相连的导电连接结构；
    所述固定电位信号线通过所述导电连接结构与所述屏蔽结构电连接。
  8. 如权利要求5所述的显示面板，其中，所述第四导电层，还包括：相互绝缘的第一导电连接部、第二导电连接部及第三导电连接部；
    所述驱动栅极通过所述第一导电连接部与所述第一有源层的第一导电化区域电连接；
    所述数据信号线通过所述第二导电连接部与所述第三有源层的第一导电化区域电连接；
    所述初始化信号线通过所述第三导电连接部与所述第二有源层的第一导电化区域电连接。
  9. 如权利要求1所述的显示面板，其中，所述第一有源层包括：第一弯折部，以及第二弯折部；
    所述第一弯折部的一端为所述第一有源层的第一导电化区域，另一端与所述第二弯折部相连，并朝向背离所述数据信号线的一侧弯折；
    所述第二弯折部为“n”字型，所述第二弯折部的一端与所述第一弯折部相连，另一端与所述第二有源层相连。
  10. 如权利要求3所述的显示面板，其中，所述第二有源层包括：第一分支部，以及第二分支部；
    所述第一分支部的一端为所述第二有源层的第一导电化区域，另一端与所述第二分支部相连；
    所述第一分支部沿所述第二方向延伸，所述第二分支部沿所述第一方向延伸。
  11. 如权利要求1所述的显示面板，其中，所述第三有源层包括：导电凸起部，以及沿所述第一方向延伸的导电延伸部；
    所述导电凸起部的一端为所述第三有源层的第一导电化区域，另一端与所述导电延伸部连接。
  12. 如权利要求1所述的显示面板，其中，所述显示面板中的多个子像素在所述第一方向和所述第二方向呈阵列排布；
    所述显示面板包括多条所述数据信号线，且所述数据信号线分为第一数据信号线与第二数据信号线；
    每一列所述子像素中，奇数行的所述子像素共用一条所述第一数据信号线，偶数行的所述子像素共用一条所述第二数据信号线。
  13. 一种显示装置，包括：如权利要求1～12任一项所述的显示面板。
PCT/CN2020/112646 2020-08-31 2020-08-31 显示面板及显示装置 WO2022041227A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202080001755.7A CN115485847A (zh) 2020-08-31 2020-08-31 显示面板及显示装置
US17/418,519 US11751450B2 (en) 2020-08-31 2020-08-31 Display panel and display device
PCT/CN2020/112646 WO2022041227A1 (zh) 2020-08-31 2020-08-31 显示面板及显示装置
US18/358,419 US20230371333A1 (en) 2020-08-31 2023-07-25 Display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/112646 WO2022041227A1 (zh) 2020-08-31 2020-08-31 显示面板及显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/418,519 A-371-Of-International US11751450B2 (en) 2020-08-31 2020-08-31 Display panel and display device
US18/358,419 Continuation US20230371333A1 (en) 2020-08-31 2023-07-25 Display panel and display device

Publications (1)

Publication Number Publication Date
WO2022041227A1 true WO2022041227A1 (zh) 2022-03-03

Family

ID=80354310

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/112646 WO2022041227A1 (zh) 2020-08-31 2020-08-31 显示面板及显示装置

Country Status (3)

Country Link
US (2) US11751450B2 (zh)
CN (1) CN115485847A (zh)
WO (1) WO2022041227A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890387A (zh) * 2019-11-26 2020-03-17 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN115909944A (zh) * 2022-12-27 2023-04-04 武汉天马微电子有限公司 显示面板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275368A (zh) * 2016-04-04 2017-10-20 三星显示有限公司 像素及包括像素的有机发光显示设备
CN111128080A (zh) * 2020-03-30 2020-05-08 京东方科技集团股份有限公司 显示基板及显示装置
CN111508977A (zh) * 2020-05-09 2020-08-07 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103971640B (zh) 2014-05-07 2016-08-24 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法和显示装置
CN104409047B (zh) 2014-12-18 2017-01-18 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN108461504B (zh) 2017-02-22 2021-02-19 昆山国显光电有限公司 晶体管的版图结构、像素驱动电路、阵列基板和显示装置
JP6892576B2 (ja) 2017-04-28 2021-06-23 天馬微電子有限公司 表示装置
CN106952940B (zh) 2017-05-26 2020-04-17 上海天马有机发光显示技术有限公司 一种有机发光显示面板和有机发光显示装置
CN109272930B (zh) 2018-11-23 2020-04-24 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN109785797B (zh) 2019-03-14 2020-11-17 电子科技大学 一种amoled像素电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275368A (zh) * 2016-04-04 2017-10-20 三星显示有限公司 像素及包括像素的有机发光显示设备
CN111128080A (zh) * 2020-03-30 2020-05-08 京东方科技集团股份有限公司 显示基板及显示装置
CN111508977A (zh) * 2020-05-09 2020-08-07 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Also Published As

Publication number Publication date
US20230371333A1 (en) 2023-11-16
US20220310751A1 (en) 2022-09-29
CN115485847A (zh) 2022-12-16
US11751450B2 (en) 2023-09-05

Similar Documents

Publication Publication Date Title
JP2021524926A (ja) 表示パネルおよび表示装置
US11961471B2 (en) Display substrate and display device
US11882737B2 (en) Array substrate including switch element that includes control portion and semiconductor portion, and display panel and display device including the same
US20220199734A1 (en) Display panel and display device
CN113870767B (zh) 像素电路、显示基板、显示面板和显示装置
CN114830216B (zh) 像素电路、显示面板及显示装置
US11790847B2 (en) Display substrate and display device
US20230371333A1 (en) Display panel and display device
WO2021232411A1 (zh) 显示基板、显示面板以及显示装置
US20220320213A1 (en) Display substrate and display apparatus
CN111724743A (zh) 像素驱动电路及其驱动方法、显示装置
US20220310023A1 (en) Display substrate, method for manufacturing the same, and display device
US20220310753A1 (en) Display panel and display device
CN114223026B (zh) 阵列基板及其显示面板和显示装置
CN112740317B (zh) 显示装置及其制备方法
US11943983B2 (en) Display substrate, method for manufacturing the same, and display device
US20220336540A1 (en) Display substrate, method for manufacturing the same, and display device
US20220336562A1 (en) Display substrate, method for manufacturing the same, and display device
WO2024000273A1 (zh) 显示面板及显示装置
WO2023159602A9 (zh) 显示面板、显示装置
WO2023225889A1 (zh) 显示基板及显示装置
WO2023230885A9 (zh) 显示面板及显示装置
WO2023109232A1 (zh) 显示面板和显示装置
WO2024011635A9 (zh) 显示面板及显示装置
WO2023230919A1 (zh) 显示基板以及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20950896

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20950896

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.10.2023).