WO2024020750A1 - 显示基板及显示装置 - Google Patents
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- WO2024020750A1 WO2024020750A1 PCT/CN2022/107710 CN2022107710W WO2024020750A1 WO 2024020750 A1 WO2024020750 A1 WO 2024020750A1 CN 2022107710 W CN2022107710 W CN 2022107710W WO 2024020750 A1 WO2024020750 A1 WO 2024020750A1
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- voltage signal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
- OLED organic light-emitting diode
- a display substrate including a display area and a peripheral area surrounding the display area.
- the display substrate includes a substrate, a first voltage signal transmission structure and a light-emitting device layer arranged in sequence.
- the light-emitting device layer includes an anode layer and a cathode layer, and the anode layer is closer to the substrate than the cathode layer.
- the first voltage signal transmission structure is configured to transmit a first voltage signal to the cathode layer in the light-emitting device layer; wherein the first voltage signal transmission structure includes a first part located in the display area and a second part located in the peripheral area, the first voltage signal The first part of the signal transmission structure is electrically connected to the second part of the first voltage signal transmission structure, and the first part of the first voltage signal transmission structure is arranged in the display area.
- the first part of the first voltage signal transmission structure includes a pattern in a mesh structure; and/or the first part of the first voltage signal transmission structure includes a plurality of first voltage signal lines.
- the boundary of the display area of the display substrate includes a plurality of boundary lines
- the second part of the first voltage signal transmission structure includes a first bus line and a second bus line.
- One of the plurality of boundary lines included in the boundary of the display area is a selected boundary line
- the first bus extends along an extension direction of the selected boundary line and is configured to access a first voltage signal provided by an external chip.
- other boundary lines except the selected boundary line are set, and the orthographic projection of the second bus on the substrate is the same as the orthographic projection of the first bus on the substrate. Orthographic projection has no overlap.
- the first part of the first voltage signal transmission structure is connected to the second bus included in the second part of the first voltage signal transmission structure.
- the first voltage signal transmission structure further includes a plurality of connection lines. The first voltage The first part of the signal transmission structure and the first bus included in the second part of the first voltage signal transmission structure are connected through the aforementioned plurality of connection lines.
- the display substrate further includes a first source-drain conductive layer disposed on a side of the substrate and a second source-drain conductive layer disposed on a side of the first source-drain conductive layer away from the substrate.
- the first voltage signal transmission structure is located between the second source-drain conductive layer and the anode layer.
- the anode layer includes a plurality of anodes located in the display area and an overlapping anode located in the peripheral area, and the overlapping anode is electrically insulated from the multiple anodes in the display area.
- the second part of the first voltage signal transmission structure is electrically connected to the cathode layer in the light emitting device layer through the overlapping anode in the peripheral region.
- the display area of the display substrate includes a first display area and a second display area, and the first display area surrounds the second display area.
- the plurality of anodes in the display area include: a plurality of first anodes located in the first display area, and a plurality of second anodes located in the second display area.
- the display substrate also includes a plurality of pixel circuits disposed on one side of the substrate and at least one transparent conductive layer disposed on the side of the second source-drain conductive layer away from the substrate.
- the plurality of pixel circuits are located in the first display area and not in the second display area.
- Each transparent conductive layer includes: a plurality of first transfer electrodes located in the first display area, a plurality of second transfer electrodes located in the second display area, and at least a plurality of first transfer electrodes located in the first display area. The first pattern in the area outside the connected electrode.
- Each first transfer electrode is electrically connected to a first anode, and each second transfer electrode is electrically connected to a second anode.
- the first pattern includes a plurality of meshes. At least one of the at least one transparent conductive layer is a selected transparent conductive layer, a first pattern of the selected transparent conductive layer is configured to transmit a first voltage signal, and the first voltage signal transmission structure includes the selected transparent conductive layer The first pattern of the layer.
- each of the at least one transparent conductive layer is a selected transparent conductive layer
- the first pattern of the selected transparent conductive layer is also located in the peripheral area
- the first pattern of each transparent conductive layer serves as a third A voltage signal transmission structure.
- the portions of each transparent conductive layer in the at least one transparent conductive layer located in the peripheral area are electrically connected, and the portion of the first pattern of the transparent conductive layer farthest from the substrate in the at least one transparent conductive layer located in the peripheral area is overlapping with Anode connection.
- one side surface of the substrate provided with at least one transparent conductive layer includes a plurality of sides, and the display substrate further includes at least one planarization layer.
- At least one transparent conductive layer includes a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer arranged in sequence from the substrate.
- At least one planarization layer includes: located between the first transparent conductive layer and the second transparent conductive layer. a first planarization layer between the layers, a second planarization layer between the second transparent conductive layer and the third transparent conductive layer, and a third planarization layer on a side of the third transparent conductive layer away from the substrate.
- the distance between the boundary of the orthogonal projection of the third planarization layer on the substrate and the side of the substrate close to the boundary is greater than the distance between the boundary of the orthographic projection of the second planarization layer on the substrate and the boundary close to it.
- the distance between the sides of the substrate, and the distance between the boundary of the orthographic projection of the second planarization layer on the substrate and the side of the substrate close to the boundary is greater than the distance between the first planarization layer and the side of the substrate.
- the distance between the front projection of the at least one transparent conductive layer on the substrate and the side of the substrate is smaller than the distance between the front projection of the first planarization layer on the substrate and the side of the display substrate.
- the first pattern as the first voltage signal transmission structure is located in a portion of the peripheral area and is connected to the overlapping anode.
- At least one transparent conductive layer includes a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer arranged in sequence from the substrate.
- the first pattern of the second transparent conductive layer serves as the first voltage signal transmission structure.
- the first pattern of the second transparent conductive layer is also located in the peripheral area.
- the first pattern of the second transparent conductive layer is located in the peripheral area and is in contact with the anode layer. Included lap anode connection.
- the first pattern of the first transparent conductive layer and the first pattern of the third transparent conductive layer are configured to transmit the second voltage signal to the plurality of pixel circuits within the first display area.
- the display substrate further includes an additional metal layer located on the same layer as the selected transparent conductive layer.
- the additional metal layer includes a second pattern, the second pattern is located at least in a part of the first display area except for the plurality of first transfer electrodes, the second pattern of the additional metal layer is configured to transmit the first voltage signal, the first
- the voltage signal transmission structure includes a second pattern of additional metal layers.
- the display substrate further includes an additional metal layer disposed on a side of the selected transparent conductive layer away from the substrate.
- the additional metal layer includes a second pattern, the second pattern of the additional metal layer is disposed on one side of the first pattern of the selected transparent conductive layer, and the second pattern of the additional metal layer is electrically connected to the first pattern of the selected transparent conductive layer.
- the first voltage signal transmission structure also includes a second pattern of additional metal layers.
- a plurality of pixel circuit arrays arranged in an array on one side of the substrate include a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of dummy pixel circuits.
- Each first pixel circuit is electrically connected to a first anode
- each second pixel circuit is electrically connected to a second anode
- the plurality of dummy pixel circuits are electrically insulated from the anode layer.
- a plurality of pixel circuits are arranged into a plurality of pixel circuit columns, at least one pixel circuit column is a normal pixel circuit column, and at least one pixel circuit column is a virtual pixel circuit column.
- the normal pixel circuit column includes a plurality of first pixel circuits and/or a plurality of
- the second pixel circuit and the virtual pixel circuit column include a plurality of virtual pixel circuits.
- the second source-drain conductive layer includes a plurality of voltage signal lines, and each voltage signal line is electrically connected to a pixel circuit column.
- the plurality of voltage signal lines include: a plurality of first voltage signal lines and a plurality of second voltage signal lines.
- the second voltage signal lines are electrically connected to the normal pixel circuit columns, and the first voltage signal lines are electrically connected to the virtual pixel circuit columns.
- Each second voltage signal line is configured to transmit a second voltage signal to each pixel circuit in the pixel circuit column.
- the plurality of first voltage signal lines are configured to transmit the first voltage signal.
- the first voltage signal transmission structure further includes a plurality of A first voltage signal line.
- the second source-drain conductive layer includes a plurality of voltage signal lines, and a plurality of first voltage signal lines included in the plurality of voltage signal lines are electrically connected to the first pattern of the selected transparent conductive layer in the peripheral area. connect.
- the display substrate further includes: a plurality of pixel circuits arranged in an array on one side of the substrate, a gate conductive layer disposed on one side of the substrate, and a first first circuit disposed on a side of the gate conductive layer away from the substrate. a source-drain conductive layer and a second source-drain conductive layer disposed on a side of the first source-drain conductive layer away from the substrate.
- a plurality of pixel circuits are arranged into a plurality of pixel circuit columns.
- the second source-drain conductive layer includes a plurality of voltage signal lines extending along a first direction.
- the first direction is the extending direction of a plurality of pixel circuit columns, and each voltage signal line overlaps with one pixel circuit column.
- the plurality of voltage signal lines include a plurality of first voltage signal lines and a plurality of second voltage signal main lines.
- the plurality of first voltage signal lines are configured to transmit the first voltage signal
- the first voltage signal transmission structure further includes a plurality of first voltage signal lines.
- Each second voltage signal main line is electrically connected to one pixel circuit column and is configured to transmit the second voltage signal to each pixel circuit in the pixel circuit column.
- the gate conductive layer includes a plurality of second voltage signal auxiliary lines extending along the second direction, and the plurality of second voltage signal auxiliary lines are electrically connected to the second voltage signal main line.
- the plurality of second voltage signal sub-lines are configured to transmit second voltage signals to the pixel circuits that overlap with the first voltage signal lines.
- At least one first voltage signal line is provided between every two adjacent second voltage signal main lines among the plurality of second voltage signal main lines, and/or, at least one first voltage signal line is provided between every two adjacent second voltage signal main lines. At least one second voltage signal main line is provided between the lines.
- the display substrate further includes at least one transparent conductive layer and at least one planarization layer disposed on the side of the second source-drain conductive layer away from the substrate, and at least one of the at least one transparent conductive layer is transparent
- the conductive layer is a selected transparent conductive layer, and the first pattern of the selected transparent conductive layer is electrically connected to the plurality of first voltage signal lines in the peripheral area.
- the display substrate further includes: a light-shielding layer disposed on one side of the substrate and a plurality of pixel circuits disposed on a side of the light-shielding layer away from the substrate.
- Each of the plurality of pixel circuits includes a drive transistor.
- the light-shielding layer includes a plurality of light-shielding patterns, and the orthographic projection of the driving transistor of each pixel circuit on the substrate is within the orthographic projection of one light-shielding pattern on the substrate. Multiple light-shielding patterns are connected to each other.
- the light shielding layer is configured to transmit the first voltage signal, and the first voltage signal transmission structure includes the light shielding layer.
- the first source-drain conductive layer and the second source-drain conductive layer are arranged sequentially from the substrate, the second part of the first voltage signal transmission structure includes a first voltage signal bus, and the first part includes a plurality of first voltage signal bus lines.
- a voltage signal sub-line, the first voltage signal bus line is located in the first source-drain conductive layer, and/or is located in the second source-drain conductive layer.
- the size of the first voltage signal bus in a direction perpendicular to its extension direction is 5 ⁇ m ⁇ 20 ⁇ m.
- a display device including: the display substrate as described in any of the above embodiments.
- Figure 1 is a structural diagram of a first voltage signal transmission line in a display substrate according to some embodiments
- Figure 2 is a cross-sectional view obtained based on section line AA in Figure 1;
- Figure 3 is a structural diagram of a first voltage signal transmission structure in a display substrate according to some embodiments.
- Figure 4 is an enlarged view of area B in Figure 3;
- Figure 5 is a cross-sectional view of the film structure of the peripheral area of the display substrate according to some embodiments.
- Figure 6 is a plan structural view of a display substrate according to other embodiments.
- Figure 7 is an enlarged view of area C in Figure 6;
- Figure 8 is a cross-sectional structural view of the first display area of the display substrate according to some embodiments.
- Figure 9A is a cross-sectional structural view of the second display area of the display substrate according to some embodiments.
- Figure 9B is a cross-sectional structural view of the second display area of the display substrate according to other embodiments.
- Figure 10 is an enlarged view of the portion of the transparent conductive layer and the anode layer located in the first display area according to some embodiments;
- 11A is a cross-sectional view of a first display area of a display substrate according to some embodiments.
- 11B is a cross-sectional view of the first display area of the display substrate according to other embodiments.
- Figure 12A is a film structure diagram of a peripheral area of a display substrate according to some embodiments.
- Figure 12B is a structural diagram of the overlapped anode of the display substrate in the peripheral area according to some embodiments.
- Figure 12C is a structural diagram of the third planarization layer of the display substrate in the peripheral area according to some embodiments.
- Figure 12D is a structural diagram of the third transparent conductive layer of the display substrate in the peripheral area according to some embodiments.
- Figure 12E is a structural diagram of the second planarization layer of the display substrate in the peripheral area according to some embodiments.
- Figure 12F is a structural diagram of the second transparent conductive layer of the display substrate in the peripheral area according to some embodiments.
- Figure 12G is a structural diagram of the first planarization layer of the display substrate in the peripheral area according to some embodiments.
- Figure 12H is a structural diagram of the first transparent conductive layer of the display substrate in the peripheral area according to some embodiments.
- Figure 13A is a cross-sectional view of the film structure of the peripheral area of the display substrate according to some embodiments.
- Figure 13B is a cross-sectional view of the film structure of the peripheral area of the display substrate according to other embodiments.
- Figure 14A is a cross-sectional view of additional metal layers according to some embodiments.
- Figure 14B is a cross-sectional view of additional metal layers according to other embodiments.
- Figure 15 is an enlarged structural view of the second display area and its surrounding area according to some embodiments.
- Figure 16 is a structural diagram of the second source-drain conductive layer according to some embodiments.
- Figure 17 is a structural diagram of the second source-drain conductive layer according to other embodiments.
- Figure 18 is a structural diagram of the second source-drain conductive layer according to yet some embodiments.
- Figure 19 is a cross-sectional view of the film structure of the peripheral area of the display substrate according to other embodiments.
- Figure 20A is a cross-sectional view of a light shielding layer according to some embodiments.
- Figure 20B is a plan structural view of a light shielding layer according to some embodiments.
- Figure 21 is a structural diagram of a first voltage signal bus according to some embodiments.
- Figure 22 is a structural diagram of a display device according to some embodiments.
- Figure 23 is a structural diagram of a display substrate bound to a circuit board according to some embodiments.
- first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
- parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
- perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
- equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
- Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
- the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
- example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
- the display device includes a display substrate, and there are many types of display substrates, which can be selected and set according to actual needs.
- the display substrate may include an organic light emitting diode (OLED for short) display substrate, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes for short, QLED for short) display substrate, and a micro light emitting diode (Micro Light Emitting Diodes for short). Micro LED) display substrate, etc., this disclosure does not specifically limit this.
- OLED organic light emitting diode
- QLED Quantum Dot Light Emitting Diodes for short
- micro light emitting diode Micro Light Emitting Diodes for short
- the display substrate 30 includes a display area AA and a peripheral area AN surrounding the display area AA.
- the display area AA is provided with a plurality of sub-pixels P, and the plurality of sub-pixels P are arranged in an array, for example.
- Each sub-pixel P includes a light-emitting device 3 a and a pixel circuit 7 disposed on the substrate 1 .
- the pixel circuit 7 includes a plurality of thin film transistors T and capacitors.
- the display substrate 30 includes a substrate 1, a driving circuit layer and a light emitting device layer 3 arranged in sequence.
- the driving circuit layer includes a plurality of pixel circuits 7 .
- the driving circuit layer includes, for example, a semiconductor layer B arranged from bottom to top, a first gate insulating layer G1 , a first gate conductive layer 8 a , a second gate insulating layer G2 , and a second gate insulating layer G2 .
- the thin film transistor T includes an active layer T1, a source electrode T2, a drain electrode T3 and a gate electrode T4.
- the active layer T1 is located on the semiconductor layer B
- the gate electrode T4 is located on the first gate conductive layer 8a
- the source electrode T2 and the drain electrode T3 Located on the first source-drain conductive layer 41 .
- the lower substrate C1 of the capacitor is located on the first gate conductive layer 8a
- the upper substrate C2 of the capacitor is located on the second gate conductive layer 8b.
- the light-emitting device layer 3 includes a plurality of light-emitting devices 3a.
- the light-emitting device layer 3 includes an anode layer 31, a light-emitting functional layer 32, a cathode layer 33, a pixel defining layer 34, a spacer 35 and an encapsulation layer 36.
- the pixel defining layer 34 is disposed on the side of the anode layer 31 away from the substrate 1.
- the anode layer 31 includes a plurality of first anodes 311 and overlapping anodes 313.
- a plurality of opening areas are provided in the pixel defining layer 34, and each opening area is exposed At least a part of an anode 311, and each light emitting device 3a is disposed in an opening area.
- each opening area of the pixel defining layer 34 is within one first anode 311.
- the light-emitting functional layer 32 is disposed on the side of the anode layer 31 away from the substrate 1.
- the light-emitting functional layer 32 includes a plurality of light-emitting parts 321, and each light-emitting part 321 is located in an opening area.
- the spacer 35 is disposed between the pixel defining layer 34 and the light-emitting functional layer 32 .
- the light-emitting functional layer 32 only includes a light-emitting layer.
- the light-emitting functional layer 32 also includes an electron transporting layer (Election Transporting Layer, referred to as ETL), an electron injection layer (Election Injection Layer, referred to as EIL), a hole transporting layer (Hole Transporting layer). Layer (HTL for short) and hole injection layer (Hole Injection Layer (HIL for short)).
- the material of the anode layer 31 is at least one of ITO, IZO, Au, Pt, and Si.
- the first anode 311 of the light-emitting device 3a is electrically connected to the source T2 or the drain T3 of one of the plurality of thin film transistors T included in the pixel circuit 7.
- the first anode 311 and The source T2 of the thin film transistor T is electrically connected for illustration.
- the above-mentioned source electrode T2 and drain electrode T3 are interchangeable, that is, T2 in FIG. 2 represents the drain electrode, and T3 in FIG. 2 represents the source electrode.
- the source electrode T2 or the drain electrode T3 of the thin film transistor is electrically connected to the first anode 311 through a transfer electrode located on the second source-drain conductive layer 42.
- the display substrate 30 further includes a first voltage signal transmission line VSS arranged in the peripheral area AN.
- the first voltage signal transmission line VSS is arranged around the display area AA and is configured to connect to the cathode of the light-emitting device layer 3
- the layer 33 transmits the first voltage signal Vss, so that the cathode layer 33 is connected to the first voltage.
- the display substrate 30 also includes a second voltage signal transmission line VDD.
- the second voltage signal transmission line VDD is configured to transmit the second voltage signal Vdd to the pixel circuit 7 in the sub-pixel P, thereby allowing the anode layer 31 of the light-emitting device layer 3 to access each The driving signal generated by the pixel circuit 7.
- the light-emitting functional layer 32 located between the cathode layer 33 and the anode layer 31 emits light.
- the material of the semiconductor layer B includes amorphous silicon, single crystal silicon, polycrystalline silicon, or metal oxide semiconductor materials; for example, the material of the semiconductor layer B includes indium gallium zinc oxide (Indium gallium zinc oxide). Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), the present disclosure is not limited thereto.
- the semiconductor layer B includes the active layer T1 of each transistor.
- the overlapping portions of the first gate conductive layer 8a and the semiconductor layer B form transistors respectively.
- the material of the first gate conductive layer 8a includes conductive metal; for example, the material of the first gate conductive layer 8a includes at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto.
- the first gate conductive layer 8a includes gate electrodes of each transistor and a plurality of gate scanning lines.
- the first gate insulating layer G1 is provided between the semiconductor layer B and the first gate conductive layer 8a, and is used to electrically insulate the semiconductor layer B and the first gate conductive layer 8a.
- the material of the first gate insulating layer G1 includes any one of the inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide; for example, the material of the first gate insulating layer G1 includes silicon dioxide. This disclosure is not limited to this.
- the second gate insulating layer G2 is provided between the first gate conductive layer 8a and the second gate conductive layer 8b, and is used to electrically insulate the first gate conductive layer 8a and the second gate conductive layer 8b.
- the material of the second gate insulating layer G2 includes any one of the inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide; for example, the material of the second gate insulating layer G2 includes silicon dioxide. This disclosure is not limited to this.
- the interlayer dielectric layer G3 is disposed between the first source-drain conductive layer 41 and the second gate conductive layer 8b, and is used to electrically insulate the first source-drain conductive layer 41 and the second gate conductive layer 8b.
- the material of the interlayer dielectric layer G3 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
- the first source-drain conductive layer 41 includes a plurality of first signal lines (eg, data lines), a plurality of first electrodes, and the like.
- the second source-drain conductive layer 42 includes a plurality of second signal lines (eg, second voltage signal transmission lines), a plurality of second electrodes, and the like.
- the first voltage signal transmission line VSS is located in the second source-drain conductive layer 42. That is to say, the second source-drain conductive layer 42 includes a plurality of second signal lines located in the display area, and a third signal line located in the peripheral area. A voltage signal transmission line VSS.
- the anode layer 31 also includes an overlapping anode 313 disposed in the peripheral area AN.
- the overlapping anode 313 is connected to the first voltage signal transmission line VSS and is connected to the cathode layer 33 , thereby realizing the overlapping anode. 313 transmits the first voltage signal Vss transmitted by the first voltage signal line VSS to the cathode layer 33 .
- the overlapping anode 313 is only a pattern located on the same film layer as multiple anodes and is used to connect the first voltage signal transmission line VSS and the cathode layer. It is not used in the light-emitting device.
- the overlapping anode is electrically connected to any anode. insulation.
- the overlapping anode 313 is a pattern surrounding the display area.
- the width of the first voltage signal transmission line VSS should not be too narrow, but should have a certain size so that the first voltage signal transmission line VSS
- the voltage signal transmission line VSS has a small resistance, so it will occupy a certain area in the peripheral area, causing the peripheral area to be too wide and reducing the screen-to-body ratio of the display substrate.
- the size of the peripheral area AN in the direction perpendicular to the display area AA can be reduced, such as the size e2 shown in Figure 1.
- the frame of the display device is narrowed, thereby achieving the purpose of increasing the area ratio of the display area AA on the display side.
- the peripheral area AN includes a first voltage signal line VSS configured to transmit the first voltage signal Vss to the light emitting device layer 3.
- the distance of the first voltage signal transmission line VSS perpendicular to the boundary of the display area AA to which it is adjacent can be reduced.
- the size in the direction such as the size e1 shown in Figure 1, to achieve the purpose of narrowing the border.
- some embodiments of the present disclosure provide a display substrate that achieves the effect of narrowing the frame by redesigning the structure of the first voltage signal transmission line VSS.
- the display panel and display device provided by the present disclosure are introduced respectively below.
- FIG. 3 and FIG. 6 are planar structural views of the display substrate 10
- FIG. 4 is an enlarged view based on area B in FIG. 3
- FIG. 7 is an enlarged view based on area C in FIG. 6 .
- FIG. 12A is a diagram showing the film layer structure in the peripheral area of the substrate 10 .
- FIG. 5 , FIG. 13A , FIG. 13B , and FIG. 19 are cross-sectional views showing the film layer structure in the peripheral area of the substrate 10 .
- the multiple anodes M and other structures in the display area AA of the display substrate 10 in Figure 12A are removed, and Figures 12B to 12B are obtained.
- the structural diagram of each transparent conductive layer, each planarization layer or the overlapping anode in the peripheral area of the substrate are shown in 12H.
- FIG. 8 , 11A and 11B are cross-sectional structural views of the first display area AA1 of the display substrate 10 .
- FIG. 10 is an enlarged structural view of the transparent conductive layer and the anode layer in the first display area AA1 of the display substrate 10 .
- 9A and 9B are cross-sectional structural views of the second display area AA2 of the display substrate 10
- FIG. 15 is an enlarged view of the second display area and its surrounding area of the display substrate 10 shown in FIG. 6 .
- FIGS. 14A and 14B are cross-sectional views of the additional metal layer of the display substrate 10
- FIGS. 16 to 18 are structural views of the second source-drain conductive layer 42 of the display substrate 10
- FIGS. 20A and 20B are the light-shielding layer of the display substrate 10 21 is a structural diagram showing the first voltage signal bus of the substrate 10 .
- a to B in reference signs indicate that A belongs to B.
- 61 to 6 indicate that the first planarization layer 61 belongs to the planarization layer 6 .
- the planarization layer 6 only includes the first planarization layer 61; in other embodiments, the planarization layer 6 includes the first planarization layer 61 and also includes other film layer structures.
- the second planarization layer 62 and the third planarization layer 63 are examples of the planarization layer 6 63.
- the side surface of the display substrate 10 on which the light-emitting device layer 3 is disposed is taken as the front surface of the display substrate 10.
- the light-emitting device layer 3 is disposed on the first surface 1a side of the substrate 1, then the first surface of the substrate 1
- the 1a side is the front surface (display side) of the display substrate 10
- the second surface 1b side of the substrate 1 is the back surface (display side) of the display substrate 10.
- a display substrate 10 is provided. As shown in FIG. 3 , the display substrate 10 includes a display area AA and a peripheral area AN surrounding the display area AA.
- the display substrate 10 includes: substrate 1, a voltage signal transmission structure 2 and a light emitting device layer 3.
- the light-emitting device layer 3 includes an anode layer 31 and a cathode layer 33.
- the anode layer 31 is close to the substrate 1 relative to the cathode layer 33.
- the first voltage signal transmission structure 2 includes a first part 21 located in the display area AA and a second part 22 located in the peripheral area AN.
- the first part 21 of the first voltage signal transmission structure 2 and the second part 22 of the first voltage signal transmission structure 2 Electrically connected, the first voltage signal transmission structure 2 is configured to transmit the first voltage signal Vss to the cathode layer 33 .
- the first voltage signal transmission structure 2 includes a first part 21 disposed in the display area AA and a second part 22 disposed in the peripheral area AN, and the first part 21 and the second part 22 of the first voltage signal transmission structure 2 are electrically connected. , jointly transmit the first voltage signal Vss to the cathode layer 33 of the light-emitting device layer 3.
- the first voltage signal transmission line VSS is only provided in the peripheral area, because the first voltage signal transmission structure 2 also includes the first voltage signal transmission line VSS located in the display area AA. of the second part 22, the overall area of the first voltage signal transmission structure 2 is increased, and the resistance of the first voltage signal transmission structure 2 can be greatly reduced.
- the size of the first part 21 located in the frame area can be reduced, for example, in Figure 3
- the size e3 shown is appropriately reduced.
- the size e3 in Figure 3 is smaller than the size e1 in Figure 1, thereby reducing the area occupied by the first voltage signal transmission structure 2 in the frame area AN, so that the display can be narrowed.
- the frame of the substrate for example, the size e4 shown in FIG. 3 is reduced.
- the size e4 in FIG. 3 is smaller than the size e2 in FIG. 1 , thereby increasing the area ratio of the display area AA on the display side.
- the first voltage signal transmission structure 2 includes a first part 21 located in the display area AA and a second part 22 located in the peripheral area AN, so that in addition to inputting the cathode layer 33 from the peripheral area AN, the first voltage signal Vss can also be input from the display area AA is input to the cathode layer 33 .
- its resistance is greatly reduced, thereby reducing the voltage drop of the first voltage signal Vss.
- the attenuation of the first voltage signal Vss caused by the voltage drop can be effectively reduced. , reducing the display effect difference between the middle and the edge of the display substrate, and reducing the power consumption of the display substrate 10 .
- the light-emitting device layer 3 is configured to connect the first voltage signal Vss to its cathode layer 33, and when its anode layer 31 connects to the driving signal provided by the pixel circuit 7, according to the connected first voltage signal Vss and the driving signal.
- the cathode layer 33 of the light-emitting device layer 3 is connected to the first voltage signal Vss
- the cathode layer 33 is connected to the first voltage
- the pixel circuit 7 is connected to the second voltage signal Vdd, and is generated according to the second voltage signal Vdd and the data signal. driving signal.
- the stability of the first voltage signal Vss will affect the stability of the first voltage connected to the cathode layer 33.
- the first part 21 and the second part 22 of the first voltage signal transmission structure 2 jointly transmit the first voltage signal Vss for the cathode layer 33. , while effectively reducing the voltage drop of the first voltage signal Vss, it improves the stability of the first voltage, and also reduces the voltage difference between the first voltage and the second voltage in the display substrate, thereby better reducing the Displays the power consumption of the substrate.
- the substrate 1 includes opposing first and second surfaces 1a and 1b, and a plurality of side surfaces 1c connecting the first and second surfaces 1a and 1b.
- the shape of the first surface 1a and the second surface 1b of the substrate 1 is, for example, a rectangle, and the substrate 1 includes four side surfaces 1c.
- the four corners of the substrate 1 are arc-shaped.
- the material of the substrate 1 is, for example, rigid materials such as glass, quartz, and plastic.
- the material of the substrate 1 is, for example, a flexible material such as a flexible FPC (Flexible Printed Circuit Board) or a PI (Polyimide Film) base film.
- a flexible material such as a flexible FPC (Flexible Printed Circuit Board) or a PI (Polyimide Film) base film.
- the first part 21 of the first voltage signal transmission structure 2 includes a pattern in a mesh structure.
- the first part 21 of the first voltage signal transmission structure 2 includes a plurality of meshes K2.
- the first part 21 of the first voltage signal transmission structure 2 is, for example, removing a plurality of redundant portions arranged in an array on an entire film structure, so that a plurality of arrays are formed on the entire film structure.
- Mesh K2 it can be understood that the first part 21 of the first signal transmission structure 2 obtained in this way is a mesh-shaped film layer structure.
- the first part 21 of the first voltage signal transmission structure 2 includes a plurality of first voltage signal lines 421 extending in the same direction.
- the first portion 21 of the first voltage signal transmission structure 2 includes a pattern in a mesh structure, and the first portion 21 of the first voltage signal transmission structure 2 further includes a plurality of first voltage signals extending in the same direction. Line 421.
- the first part 21 of the first voltage signal transmission structure 2 is, for example, a film layer structure with a stacked design. Further, the first part 21 of the first voltage signal transmission structure 2 includes, for example, a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are electrically connected.
- the first conductive layer includes a plurality of first voltage signal lines 421 extending along the first direction X.
- the second conductive layer includes a plurality of first voltage signal lines 421 extending along the second direction Y.
- the first direction Direction Y, the plurality of first voltage signal lines 421 extending in the first direction X and the plurality of first voltage signal lines extending in the second direction Y form a criss-crossing mesh structure.
- the first conductive layer is, for example, the first source-drain conductive layer 41
- the second conductive layer for example, is the second source-drain conductive layer 42.
- the first part 21 of the first voltage signal transmission structure 2 is arranged in the display area AA and is configured to transmit the first voltage signal Vss to the cathode layer 33 of the light-emitting device layer 3.
- the first part 21 of the first voltage signal transmission structure 2 no matter Using a mesh structure or using multiple first voltage signal lines 421 extending in the same direction, compared with that shown in Figure 1 , only the first voltage signal transmission line 2' is provided in the peripheral area AN for transmitting the first voltage.
- the signal Vss increases the area of the trace used to transmit the first voltage signal Vss. It can be understood that the resistance of the trace used to transmit the first voltage signal Vss decreases, thereby causing the voltage drop of the first voltage signal Vss.
- the reduction can effectively reduce the attenuation of the first voltage signal Vss caused by the voltage drop, and reduce the difference in display effects between the middle and the edge of the display substrate. Furthermore, adopting such a design can make the transmission of the first voltage signal Vss more stable, thereby ensuring that the voltage difference between the first voltage and the second voltage applied to the light-emitting device layer 3 is small, thereby reducing the cost of the display substrate. power consumption.
- the boundary of the display area AA of the display substrate 10 includes multiple boundary lines J, one of which is the selected boundary line J1
- the second boundary line of the first voltage signal transmission structure 2 Part 22 includes a first bus 221 and a second bus 222 .
- the first bus 221 extends along the extension direction of the selected boundary line J1 and is configured to access the first voltage signal Vss provided by the external chip.
- the second bus 222 is arranged around other boundary lines J among the plurality of boundary lines J except the selected boundary line J1, and the orthographic projection of the second bus 222 on the substrate 1 is the same as the orthographic projection of the first bus 221 on the substrate 1. Orthographic projection has no overlap.
- the first bus 221 is disposed close to the selected boundary line J1 of the display area AA.
- the side surface close to the selected boundary line J1 of the display area AA is the selected side surface 1 cc.
- the selected boundary line J1 of the display area AA extends along the first direction X. It can be understood that the first bus 221 extends along the first direction X. Two adjacent side surfaces 1 c of the substrate 1 form a corner. The following is an example where the shape of the substrate 1 is a rectangle. In this case, the substrate 1 includes four corners.
- the orthographic projection of the second bus 222 on the substrate 1 does not overlap with the orthographic projection of the first bus 221 on the substrate 1. It can be understood that the selected side 1cc of the substrate 1 and its two adjacent side surfaces 1c The two formed corners, at close positions, do not include the first bus 221 and the second bus 222 . That is, at the two corner positions of the substrate 1, no connection traces for transmitting the first voltage signal Vss are provided. Therefore, the peripheral area AN is located in the portion of the area close to the two corners of the substrate 1 in the vertical direction. The size in the direction of the boundary J of the display area AA that it is close to is reduced, effectively reducing the frame width of the display substrate 10 at the aforementioned two corner positions.
- the first portion 21 of the first voltage signal transmission structure 2 is connected to the second bus 222 .
- the first voltage signal transmission structure 2 also includes a plurality of connection lines 23 , and the first part 21 of the first voltage signal transmission structure 2 is connected to the first bus 221 through the plurality of connection lines 23 .
- a gap area K1 is formed between two adjacent connection lines 23 and the first part 21 of the first voltage signal transmission structure 2 and the first bus 221 .
- a connection structure between the first part 21 of the voltage signal transmission structure 2 and the first bus 221 uses a plurality of connection lines 23 as the connection structure.
- the gap area K1 formed can be used as a breathable hole, so that the film layer exposed by the gap area K1 can Better heat dissipation effectively alleviates the problem of rapid temperature rise caused by poor heat dissipation between film layer structures, thereby causing increased energy consumption of the display substrate 10 .
- the display substrate 10 further includes a source-drain conductive layer 4 .
- the source-drain conductive layer 4 includes a first source-drain conductive layer 41 disposed on one side of the substrate 1 , and a first source-drain conductive layer 41 disposed on one side of the substrate 1 .
- the source-drain conductive layer 41 is away from the second source-drain conductive layer 42 on one side of the substrate 1 .
- the first voltage signal transmission structure 2 is located between the second source-drain conductive layer 42 and the anode layer 31 .
- the anode layer 31 includes a plurality of anodes M located in the display area AA and an overlapping anode 313 located in the peripheral area AN, and the overlapping anode 313 is electrically insulated from the plurality of anodes M.
- the second portion 22 of the first voltage signal transmission structure 2 is electrically connected to the cathode layer 33 through the overlapping anode 313 .
- the first voltage signal transmission structure 2 is located in the second part 22 of the peripheral area and is electrically connected to the overlapping anode 313 located in the peripheral area AN.
- the overlapping anode 313 is electrically connected to the cathode layer 33, thereby realizing the first voltage signal transmission structure 2
- the transmitted first voltage signal Vss is transmitted to the cathode layer 33 .
- the display substrate 10 further includes a transparent conductive film layer located between the second source-drain conductive layer 42 and the anode layer 31 .
- the transparent conductive film layer is an ITO layer.
- the first voltage signal transmission structure 2 is formed in the transparent conductive film layer and distributed in the display area AA and the peripheral area AN.
- the first portion 21 of the first voltage signal transmission structure 2 is made of transparent conductive material.
- the first voltage signal transmission structure 2 uses, for example, ITO (indium tin oxide), PEDOT (EDOT, a polymer of 3,4-ethylenedioxythiophene monomer).
- the second part 22 of the first voltage signal transmission structure 2 is also made of transparent conductive material.
- the display device may also include electrical components such as sensors, for example, optical sensors.
- the display device includes optical sensors such as a front camera, a proximity light sensor, and a 3D sensing module. These optical components need to receive light from the display side of the display device to implement corresponding functions.
- the optical sensor is usually installed on the non-display surface side of the display substrate, with the photosensitive surface side of the optical sensor facing the display substrate.
- Full Display Cell uses under-screen camera technology to hide the camera and other sensors directly below the screen to achieve full-screen display. This disclosure is based on the full-screen display and introduces several specific implementation methods of the first voltage signal transmission structure 2 distributed in the display area AA.
- the display area AA includes a first display area AA1 and a second display area AA2.
- the first display area AA1 surrounds the second display area AA2.
- the second display area AA2 is, for example, a circular area or a square area.
- the first display area AA1 is a normal display area, that is, the first display area AA1 is distributed with sub-pixels P arranged in an array, and each sub-pixel P includes a pixel circuit 7 and a light-emitting device 3a.
- the second display area AA2 is a transparent display area, which can also be displayed, but has a higher light transmittance.
- the side of the substrate 1 away from the driving circuit layer is provided with sensors, such as cameras, proximity light sensors, 3D sensing modules and other optical sensors. , and the projection of the sensor on the substrate 1 is located in the second display area AA2.
- the photosensitive surface of the optical sensor faces the display surface side of the display device and is used to receive ambient light from the display surface side of the display device.
- sub-pixels P arranged in an array are distributed in the second display area AA2.
- each sub-pixel P in Figure 7 is reduced to a black dot.
- Each sub-pixel P only includes a light-emitting device, and each light-emitting device
- the pixel circuit 7 corresponding to the device is distributed in the first display area AA1. Since the transistors included in the pixel circuit 7 are all made of opaque metal materials, the pixel circuit 7 in the sub-pixel P of the second display area AA2 is set In the first display area AA1, the film layer material of the second display area AA2 is made of a material with a higher light transmittance, thereby improving the light transmittance of the second display area AA2.
- the display substrate 10 includes a plurality of pixel circuits 7 disposed on one side of the substrate 1 and located in the first display area AA1.
- the multiple pixel circuits 7 include: controlling sub-pixels located in the first display area AA1.
- the plurality of pixel circuits 7 are located in the first display area AA1 and are not located in the second display area AA2.
- the plurality of second pixel circuits 72 are distributed in the gap space between the plurality of first pixel circuits 71 .
- the plurality of anodes M include a plurality of first anodes 311 located in the first display area AA1, and a plurality of second anodes 312 located in the second display area AA2.
- Each first pixel circuit 71 is electrically connected to a first anode 311 for controlling the light emitting device 3a connected to the first anode 311 to emit light
- each second pixel circuit 72 is electrically connected to a second anode 312 for controlling the light emitting device 3a connected to the first anode 311.
- the light-emitting device 3a connected to the second anode 312 emits light.
- a connecting wire is required to connect the two.
- a transparent conductive film layer is added between the second source-drain conductive layer 42 and the anode layer 31 for arranging the connecting traces 5d.
- the display substrate 10 further includes at least one transparent conductive layer 5 disposed on the side of the second source-drain conductive layer 42 away from the substrate 1 .
- the transparent conductive layer 5 uses a transparent conductive material. Further, the transparent conductive layer 5 uses, for example, ITO (indium tin oxide), PEDOT (EDOT, a polymer of 3,4-ethylenedioxythiophene monomer).
- ITO indium tin oxide
- PEDOT EDOT, a polymer of 3,4-ethylenedioxythiophene monomer
- the transparent conductive layer 5 includes: a plurality of first transfer electrodes 5a located in the first display area AA1, and a plurality of second transfer electrodes 5a located in the second display area AA2.
- the transfer electrode 5b and the plurality of connection traces 5d spanning the first display area AA1 and the second display area AA2.
- Each first transfer electrode 5a is electrically connected to a first anode 311 in the anode layer 31, and each second transfer electrode 5b is electrically connected to a second anode 312 in the anode layer 31, as shown in Figure 10.
- the first transfer electrode 5a is connected to the anode M located on the upper layer thereof and simultaneously connected to the pixel circuit located on the lower layer thereof, for example, connected to the source or drain of the transistor in the pixel circuit.
- the second transfer electrode 5b is connected to the anode M located on the upper layer thereof, and is connected to the corresponding pixel circuit through the connecting wire 5d.
- One end of each connection line 5d is connected to a second transfer electrode 5b, and the other end is connected to the source or drain of the transistor in the pixel circuit.
- a connecting trace 5d corresponding to a second anode 312 can be located in any layer of the three transparent conductive layers 5.
- a camera and other devices are provided in the second display area AA2, and the transparent conductive layer 5 is used instead of the metal layer as the layout connection trace 5d to input control signals to the second display area AA2. Since the transparent conductive layer 5 It has good light transmittance, so that the transparent conductive layer 5 can play a signal transmission role without blocking the camera and other devices provided in the second display area AA2, thereby ensuring the normal operation of the display substrate 10.
- the transparent conductive layer in the full-screen display that is, arranging transfer electrodes and connecting traces in the transparent conductive layer to realize the control of the second anode of the second display area by the second pixel circuit.
- the transparent conductive layer in the full-screen display, that is, arranging transfer electrodes and connecting traces in the transparent conductive layer to realize the control of the second anode of the second display area by the second pixel circuit.
- the first part of the first voltage signal transmission structure includes a pattern in a mesh structure.
- FIG. 10 is a schematic diagram of the pattern of the transparent conductive layer 5 and the anode layer 31 in a partial area of the first display area AA1 .
- the transparent conductive layer 5 further includes a first pattern 5c located at least in a region of the first display area AA1 except for the plurality of first transfer electrodes 5a.
- the portion of the transparent conductive layer 5 located in the first display area AA1 only includes a plurality of first transfer electrodes 5a.
- the connecting electrode 5a it also includes a first pattern 5c, and the first pattern 5c has no contact with the plurality of first connecting electrodes 5a.
- the first pattern 5c includes a plurality of meshes K2.
- At least one of the at least one transparent conductive layer 5 is a selected transparent conductive layer.
- the first pattern of the selected transparent conductive layer is configured to transmit the first voltage signal Vss.
- the first voltage signal transmission structure 2 includes the selected transparent conductive layer. The first pattern of the transparent conductive layer is determined.
- the transparent conductive layer 5 is the selected transparent conductive layer; when the display substrate includes multiple transparent conductive layers 5, one of the multiple transparent conductive layers 5 is selected. One layer, multiple layers, or all of the transparent conductive layers 5 are selected transparent conductive layers.
- each transparent conductive layer 5 The structure of each transparent conductive layer 5 is the same.
- the first pattern 5c of the transparent conductive layer 5 includes a plurality of meshes K2. It can be understood that the first pattern 5c of the selected transparent conductive layer configured to transmit the first voltage signal Vss The pattern also includes multiple meshes K2. At this time, the selected portion of the transparent conductive layer that transmits the first voltage signal line Vss has a mesh structure.
- the plurality of meshes K2 included in the first pattern 5c can be used as ventilation holes, so that the film layer exposed by the plurality of meshes K2 can better dissipate heat, effectively alleviating the problem of each film. Poor heat dissipation between the layer structures leads to rapid temperature rise, which leads to the problem of increased energy consumption of the display substrate 10 .
- the first pattern 5c is disposed in the second display area AA2.
- the first pattern 5c is provided in a display area AA1 for transmitting the first voltage signal Vss, multiplexing the transparent conductive layer 5, and improving the utilization rate of the transparent conductive layer 5. In this way, there is no need to provide a new film layer used as the first voltage signal transmission structure 2, which saves film materials, simplifies the preparation process, and does not increase the thickness of the display substrate.
- the first network structure of the selected transparent conductive layer in the first display area AA1 is The pattern is configured to transmit the first voltage signal Vss, increasing the overall area of the signal line transmitting the first voltage signal Vss, thereby reducing the resistance of the signal line transmitting the first voltage signal Vss.
- the first voltage signal can be transmitted
- the size of the part of the Vss signal line located in the frame area is appropriately reduced, thereby reducing the area occupied by the signal line transmitting the first voltage signal Vss in the frame area AN, thus narrowing the frame of the display substrate, thereby achieving The purpose is to increase the area ratio of the display area AA on the display side.
- the above-mentioned signal line that transmits the first voltage signal Vss refers to the first voltage signal transmission line VSS in some embodiments as shown in Figure 1. In other embodiments as shown in Figure 3 , refers to the first pattern of the selected transparent conductive layer configured to transmit the first voltage signal Vss.
- the first pattern 5c is arranged inside to transmit the first voltage signal Vss, which increases the utilization rate of the transparent conductive layer. At the same time, it increases the total area of the signal line for transmitting the first voltage signal Vss, thereby improving the stability of the transmission of the first voltage signal Vss. sex.
- each of the at least one layer of transparent conductive layer 5 is a selected transparent conductive layer, and the first pattern of the selected transparent conductive layer is also located in the peripheral area AN, and each layer of transparent conductive layer 5 is a selected transparent conductive layer.
- the first patterns of layers each serve as first voltage signal transmission structures 2 .
- the parts of each transparent conductive layer in the at least one transparent conductive layer 5 located in the peripheral area AN are electrically connected, as shown in FIG. 13A and FIG. 13B .
- the first pattern is located in the part of the peripheral area AN and is connected to the overlapping anode 313.
- the first pattern as the first voltage signal transmission structure 2 is an entire film layer structure covering the display area AA.
- the first pattern as the first voltage signal transmission structure 2 can Covering the pixel circuit, such as the driving transistor, between the first pattern and the substrate 1 can shield the influence of the pixel circuit on the coupling capacitance of the anode.
- the aforementioned covering means that the orthographic projection of the driving transistor included in the pixel circuit on the substrate 1 is surrounded by the orthographic projection of the first pattern as the first voltage signal transmission structure 2 on the substrate 1 .
- the display substrate 10 includes three transparent conductive layers 5 .
- the three transparent conductive layers 5 include a first transparent conductive layer 51 , a second transparent conductive layer 52 and a third transparent conductive layer 52 which are sequentially arranged from the substrate 1 .
- Three transparent conductive layers 53, the first transparent conductive layer 51, the second transparent conductive layer 52 and the third transparent conductive layer 53 are electrically connected to the parts located in the peripheral area AN, and the parts of the third transparent conductive layer 53 located in the peripheral area AN are electrically connected to each other. Connect to the anode 313 connection.
- the display substrate 10 further includes at least one planarization layer 6 .
- At least one layer of transparent conductive layer 5 includes a first transparent conductive layer 51 , a second transparent conductive layer 52 , and a third transparent conductive layer 53 arranged in sequence from the substrate 1 . At least one layer is planarized.
- Layer 6 includes a first planarization layer 61 between the first transparent conductive layer 51 and the second transparent conductive layer 52 , and a second planarization layer 62 between the second transparent conductive layer 52 and the third transparent conductive layer 53 and a third planarization layer 63 located on a side of the third transparent conductive layer 53 away from the substrate 1 .
- the size of the portion of the planarization layer 6 located in the first display area AA1 perpendicular to the substrate 1 is less than or equal to the size of the portion of the planarization layer 6 located in the second display area AA2 perpendicular to the substrate 1 . size of.
- the size of the portion of the planarization layer 6 located in the first display area AA1 perpendicular to the substrate 1 is the same as the size of the portion of the planarization layer 6 located in the second display area AA2 perpendicular to the substrate 1 same.
- the size of the portion of the planarization layer 6 located in the first display area AA1 perpendicular to the substrate 1 is 0.5 dimensional in size perpendicular to the substrate 1 and the size of the portion of the planarization layer 6 located in the second display area AA2 perpendicular to the substrate 1 . One-half the size.
- the portion of the planarization layer 6 located in the first display area AA1 has a dimension perpendicular to the substrate 1 of zero
- the portion of the planarization layer 6 located in the second display area AA2 has a dimension perpendicular to the substrate. The dimensions on 1 are not zero.
- the display substrate 10 includes a substrate 1 , a semiconductor layer B, a first gate insulating layer G1 , a first gate conductive layer 8 a , and a second gate insulating layer G2 arranged in sequence.
- the second gate conductive layer 8b the interlayer insulating layer G3, the first source-drain conductive layer 41, the first insulating layer N1 and the second source-drain conductive layer 42, the second insulating layer N2, the first transparent conductive layer 51, the A planarization layer 61 , a second transparent conductive layer 52 , a second planarization layer 62 , a third transparent conductive layer 53 and a third planarization layer 63 .
- the overlapping anode 313 is a full-surface membrane structure.
- the overlapping anode 313 includes a plurality of fourth openings Q4. With reference to FIG. 13A, it can be understood that the plurality of fourth openings Q4 expose a part of the planarization layer 6.
- the aforementioned planarization layer 6 is, for example, the third Three planarization layers 63 and/or the second planarization layer 62 and the first planarization layer 61 .
- the plurality of fourth openings Q4 are, for example, used as ventilation holes for the third planarization layer 63 and/or the second planarization layer 62 and the first planarization layer 61 to facilitate the third planarization layer 63 and/or the second planarization layer 62 , heat dissipation of the first planarization layer 61 . Since the planarization layer 6 is an insulating material, it will not affect the electrical connection between the overlapping anode 313 and the cathode layer 33 .
- FIGS. 12A and 12C show enlarged structural views of the third planarization layer 63 in the peripheral area AN.
- the edge portion of the third transparent conductive layer 53 in the peripheral area AN also includes a plurality of third openings Q3.
- the plurality of third openings Q3 expose a part of the planarization layer 6.
- the aforementioned planarization layer 6 is, for example, the second planarization layer 62 and/or the first planarization layer 61 .
- the plurality of third openings Q3 serve, for example, as ventilation holes for the second planarization layer 62 and/or the first planarization layer 61 to facilitate heat dissipation of the second planarization layer 62 and/or the first planarization layer 61 .
- 12A and 12E show enlarged structural views of the second planarization layer 62 in the peripheral area AN.
- the edge portion of the second transparent conductive layer 52 in the peripheral area AN also includes a plurality of second openings Q2.
- the plurality of second openings Q2 expose a part of the planarization layer 6.
- the aforementioned planarization layer 6 is, for example, the second planarization layer 62 and/or the first planarization layer 61 .
- the plurality of third openings Q3 serve, for example, as ventilation holes for the second planarization layer 62 and/or the first planarization layer 61 to facilitate heat dissipation of the second planarization layer 62 and/or the first planarization layer 61 .
- FIG. 12G shows an enlarged structural view of the first planarization layer 61 in the peripheral area AN.
- FIG. 12H shows an enlarged structural view of the first transparent conductive layer 51 in the peripheral area AN.
- the edge portion of the first transparent conductive layer 51 in the peripheral area AN also includes a plurality of first openings Q1.
- the plurality of first openings Q1 expose a part of the planarization layer 6
- the aforementioned planarization layer 6 is, for example, the first planarization layer 61 .
- the plurality of first openings Q1 serve, for example, as ventilation holes of the first planarization layer 61 to facilitate heat dissipation of the first planarization layer 61 .
- the planarization layer 6 is an insulating material
- the third opening Q3 on the third transparent conductive layer 53 can be used as a ventilation hole of the planarization layer 6, such as the first planarization layer 61, the second planarization layer 62, and the third planarization layer 63, and will not cause
- the multiple transparent conductive layers 5 are connected to each other through openings in the transparent conductive layers.
- the distance d3 between the boundary of the third planarization layer 63 and the side surface 1 c of the substrate 1 is greater than the distance d2 between the boundary of the second planarization layer 62 and the side surface 1 c of the substrate 1
- the distance d2 between the boundary of the second planarization layer 62 and the side surface 1 c of the substrate 1 is greater than the distance d1 between the first planarization layer 61 and the side surface 1 c of the substrate 1 .
- the display substrate 10 when the display substrate 10 includes a plurality of transparent electrode layers 5 and a plurality of planarization layers 6 , the boundary between the plurality of transparent electrode layers 5 and the plurality of planarization layers 6 and the side surface 1 c of the substrate 1 The distances are all different, and it can be clearly seen from the cross-sectional view of the display substrate 10 that the cross-sections of the boundaries between the plurality of transparent electrode layers 5 and the plurality of planarization layers 6 are stepped.
- the thickness of the display substrate 10 changes gradually in the direction perpendicular to the first surface 1a, avoiding step differences caused by different thicknesses of the film layer structures. Furthermore, it avoids the possibility that the step differences may lead to Displays problems with the normal operation of the substrate 10 .
- FIG. 13A in order to clearly show the distance relationship between the boundary between the transparent conductive layer 5 and the planarization layer 6 and the side surface 1 c of the substrate 1 close to the boundary, FIG.
- the cross-section of each planarization layer 6 at the boundary position of its adjacent transparent conductive layer 5 is step-shaped, but in actual production, the D shown in Figure 13A
- the area is a continuous gradual slope. This design can effectively avoid the breakage problem of the cathode layer 33 caused by too large a step difference in this area.
- At least one transparent conductive layer 5 includes a first transparent conductive layer 51 , a second transparent conductive layer 52 , and a third transparent conductive layer 53
- at least one planarization layer 6 includes a first planarization layer 61 , a second planarization layer 61 , and a third transparent conductive layer 53
- the layer 62 and the third planarization layer 63 are taken as an example for description.
- the side surface of the overlapping anode 313 away from the substrate 1 is flush or substantially flush with the side surface of the third planarization layer 63 away from the substrate 1 .
- the side surface of the overlapping anode 313 away from the substrate 1 is flush or substantially flush with the side surface of the second planarization layer 62 away from the substrate 1 .
- the aforementioned flush or substantially flush means that the distance between the surface of the overlapping anode 313 away from the substrate 1 and the substrate 1 is the same as the distance between the third planarization layer 63 or the second planarization layer 62 away from the substrate 1 .
- the distance between the side surface and the substrate 1 is the same or approximately the same.
- the overlapping anode 313 is electrically insulated from the rest of the anode layer 31, the overlapping anode 313 and the plurality of anodes M included in the anode layer 31 are called a conductive pattern of the anode layer 31. Then, the overlapping anode 313 and the plurality of anodes M and the like are independently separated conductive patterns. Therefore, when preparing the display substrate 10:
- the conductive pattern included in the anode layer 31 is formed in one process, and the size of the conductive pattern included in the anode layer 31 in a direction perpendicular to the substrate 1 is consistent. It can be understood that at this time, the dimensions of the overlapping anode 313 and other conductive patterns in the anode layer 31 in the direction perpendicular to the substrate 1 are consistent.
- the conductive patterns included in the anode layer 31 are formed separately, for example, in two processes, wherein the aforementioned two processes form the overlapping anode 313 and other conductive patterns in the anode layer 31 respectively.
- the size of the overlapping anode 313 may be inconsistent with the size of other conductive patterns in the anode layer 31 in the direction perpendicular to the substrate 1 . Therefore, as shown in FIG. 13B , the side surface of the overlapping anode 313 away from the substrate 1 is, for example, flush with the side surface of the third planarization layer 63 away from the substrate 1 .
- the size in the direction of the substrate 1 is such that there is no step difference in the D' region shown in FIG. 13B, and the distance between the cathode layer 33 and the substrate 1 at each position of the portion in the peripheral area AN is approximately Maintain consistency, thereby effectively avoiding the risk of fracture of the cathode layer 33 in this area due to the presence of step differences.
- the side surface of the overlapping anode 313 away from the substrate 1 is, for example, flush with the side surface of the third planarization layer 63 away from the substrate 1 .
- the overlapping anode 313 will be transparent.
- the step difference existing at the edge position of the conductive layer 5 is compensated. Therefore, the distance between the boundaries of the first transparent conductive layer 51 , the second transparent conductive layer 52 and the third transparent conductive layer 53 and the side surface 1 c of the substrate 1 may be the same. , that is, d1, d2 and d3 can be the same.
- the cross-sections of the boundary portions of all film structures included in the display substrate 10 adopt a stepped design.
- the step-like design adopted in the cross-section of the boundary portion of the film structure described here refers to any film structure in the display substrate 10, such as the transparent conductive layer 5.
- the side of the transparent conductive layer 5 close to the substrate 1, for example, is connected to the third
- the two insulating layers N2 are connected, and the side of the transparent conductive layer 5 away from the substrate 1 is connected to the planarization layer 6. It can be understood that from the side of the substrate 1, the second insulating layer N2, the transparent conductive layer 5, and the planarization layer 6 are connected.
- the flattening layers 6 are arranged in sequence and connected in sequence.
- the distances between the boundaries of the second insulating layer N2, the transparent conductive layer 5 and the planarization layer 6 and the side surface 1c of the substrate 1 are all different, and the distances closest to the substrate 1 are
- the distance between the film layer and the side 1c of the substrate 1 is the smallest, that is, the distance between the boundary of the second insulating layer N2 and the side 1c of the substrate 1 is smaller than the distance between the boundary of the transparent conductive layer 5 and the side 1c of the substrate 1 and the distance between the boundary of the transparent conductive layer 5 and the side surface 1 c of the substrate 1 is smaller than the distance between the boundary of the planarization layer 6 and the side surface 1 c of the substrate 1 .
- the second insulating layer N2, the transparent conductive layer 5, and the planarization layer 6 are regarded as a whole, and the cross-sectional shape at the boundary position of the whole is stepped.
- the distance between the at least one transparent conductive layer 5 and the side of the substrate 1 is smaller than the distance between the first planarization layer 6 and the side 1 c of the display substrate 10 .
- the distance between the boundary of the first transparent conductive layer 51 and the side surface 1 c of the substrate 1 is d4, and the distance between the boundary of the second transparent conductive layer 52 and the side surface 1 c of the substrate 1 is d4. is d5, and the distance between the boundary of the third transparent conductive layer 53 and the side surface 1c of the substrate 1 is d6.
- d4, d5, and d6 are all less than d1, and d4, d5, and d6 are all less than d2, and d4, d5, and d6 are all less than d3.
- At least one of the first transparent conductive layer 51, the second transparent conductive layer 52, and the third transparent conductive layer 53 is a selected transparent conductive layer, and the first pattern of the selected transparent conductive layer is transmitted as the first voltage signal.
- Structure 2 The first pattern as the first voltage signal transmission structure 2 is located in the portion of the peripheral area AN and is connected to the overlapping anode 313 .
- the first transparent conductive layer 51 , the second transparent conductive layer 52 , and the third transparent conductive layer 53 are all selected transparent conductive layers.
- the layer 52 and the first pattern of the third transparent conductive layer 53 are connected in the peripheral area AN, and the portion of the first pattern 53c of the third transparent conductive layer 53 located in the peripheral area AN is connected to the overlapping anode 313 .
- the display substrate 10 includes three transparent conductive layers 5 .
- the three transparent conductive layers 5 include a first transparent conductive layer 51 , a second transparent conductive layer 52 and a third transparent conductive layer 52 which are sequentially arranged from the substrate 1 .
- Three transparent conductive layers 53, the first transfer electrode 51a of the first transparent conductive layer 51, the first transfer electrode 52a of the second transparent conductive layer 52, and the first transfer electrode 53a of the third transparent conductive layer 53 are connected in sequence. , as a whole as a first transfer electrode 5a.
- the first transfer electrode 5a is connected to the second signal line 4a in the source-drain conductive layer 4.
- the first transfer electrode 5a is connected to the source electrode T2 or the drain electrode T3 of the thin film transistor T through the second signal line 4a.
- the display substrate 10 includes two layers of transparent conductive layers 5 .
- the two layers of transparent conductive layers 5 include a first transparent conductive layer 51 and a second transparent conductive layer 52 arranged in sequence from the substrate 1 .
- the first transparent conductive layer 51 The first transfer electrode 51a is connected to the first transfer electrode 52a of the second transparent conductive layer 52, and the whole is formed as a first transfer electrode 5a.
- the first transfer electrode 5a is connected to the second signal line 4a in the source-drain conductive layer 4. In some examples, the first transfer electrode 5a is connected to the source electrode T2 or the drain electrode T3 of the thin film transistor T through the second signal line 4a.
- the display substrate 10 includes a transparent conductive layer 5 , and the first transfer electrode 5 a of the transparent conductive layer 5 is connected to the second signal line 4 a in the source-drain conductive layer 4 .
- the first transfer electrode 5a is connected to the source electrode T2 or the drain electrode T3 of the thin film transistor T through the second signal line 4a.
- At least one transparent conductive layer 5 includes a first transparent conductive layer 51 , a second transparent conductive layer 52 , and The third transparent conductive layer 53.
- the first pattern 52c of the second transparent conductive layer 52 serves as the first voltage signal transmission structure 2 and is configured to transmit the first voltage signal Vss to the plurality of pixel circuits 7.
- the first pattern 52c of the second transparent conductive layer 52 is also located in the periphery. In the area AN, the first pattern 52c of the second transparent conductive layer 52 is located in the peripheral area AN and is connected to the overlapping anode 313.
- the first pattern 51 c of the first transparent conductive layer 51 and the first pattern 53 c of the third transparent conductive layer 53 are configured to transmit the second voltage signal Vdd to the plurality of pixel circuits 7 .
- the second voltage signal Vdd is a constant voltage signal and is more stable than the first voltage signal Vss.
- the second transparent conductive layer 52 is located between the first transparent conductive layer 51 and the third transparent conductive layer 53 so that the first voltage signal Vss The transmission is more stable and not easily affected.
- the display substrate 10 further includes an additional metal layer 43 disposed on a side of the selected transparent conductive layer away from the substrate 1 , and the additional metal layer 43 includes a second pattern 43c.
- the second pattern 43c of the additional metal layer 43 is disposed on one side of the first pattern 5'c of the selected transparent conductive layer 5', and the second pattern 43c of the additional metal layer 43 is in contact with the first pattern of the selected transparent conductive layer 5'. 5'c is electrically connected, and the first voltage signal transmission structure 2 also includes a second pattern 43c of additional metal layer 43.
- the second pattern 43c of the additional metal layer 43 is in direct contact with the first pattern 5'c of the selected transparent conductive layer 5', and the second pattern 43c of the additional metal layer 43 is located on the selected transparent conductive layer 5'.
- the first pattern 5'c is away from one side of the substrate 1 and overlaps the two.
- the second pattern 43c of the additional metal layer 43 and the first pattern 5 of the selected transparent conductive layer 5' 'c achieves electrical connection through the connecting portion.
- the remaining film structures between the additional metal layer 43 and the selected transparent conductive layer 5' include at least one film structure, and the at least one film structure is electrically connected to the additional metal layer 43 and the selected transparent conductive layer 5' respectively.
- the at least one film layer structure includes a connection via connecting the second pattern 43c of the additional metal layer 43 and the first pattern 5'c of the selected transparent conductive layer 5', and the connection
- the via holes are filled with conductive material, and the second pattern 43c of the additional metal layer 43 and the first pattern 5'c of the selected transparent conductive layer 5' are electrically connected through the connection via holes and the conductive material in the connection via holes.
- the aforementioned conductive material includes metallic materials, such as at least one of aluminum, copper or molybdenum.
- the transparent conductive layer 5 is made of a transparent conductive material. Further, the transparent conductive layer 5 uses, for example, ITO (indium tin oxide), PEDOT (EDOT, a polymer of 3,4-ethylenedioxythiophene monomer).
- the additional metal layer 43 is, for example, at least one of aluminum, copper or molybdenum.
- the transparent conductive layer 5' is selected to be at least one of the at least one transparent conductive layer 5. Compared with metal materials, it has better light transmittance and greater resistance, thereby making its transmission
- the first voltage signal Vss produces a voltage drop.
- at least one transparent conductive layer 5 includes a first transparent conductive layer 51 and a second transparent conductive layer 52. Then, the selected transparent conductive layer 5' includes the first transparent conductive layer 51 and the second transparent conductive layer. At least one of 52.
- at least one transparent conductive layer 5 includes a first transparent conductive layer 51, a second transparent conductive layer 52 and a third transparent conductive layer 53. Then, the selected transparent conductive layer 5' includes the first transparent conductive layer 5'. At least one of the layer 51 , the second transparent conductive layer 52 and the third transparent conductive layer 53 .
- the power consumption can be effectively reduced.
- the resistance of the first pattern 5'c that transmits the first voltage signal Vss is used to achieve voltage drop optimization.
- the second pattern 43c has the same shape as the first pattern 5'c of the selected transparent conductive layer 5', and the orthographic projection of the second pattern 43c on the substrate 1 is the same as the first pattern of the selected transparent conductive layer 5'.
- the orthographic projections of 5'c on substrate 1 overlap or approximately overlap.
- the second pattern 43c of the additional metal layer 43 has the same shape as the first pattern 5'c of the selected transparent conductive layer 5', during the preparation process of the display substrate 10, the same mask can be used respectively. Preparing the first pattern 5'c of the selected transparent conductive layer 5' and the second pattern 43c of the additional metal layer 43 requires only process changes and no additional mask is required. While optimizing the voltage drop, no additional increase is required. The preparation cost of the substrate 10 is shown.
- the display substrate 10 further includes an additional metal layer 43, which is located on the same layer as the selected transparent conductive layer 5'.
- the additional metal layer 43 includes a second pattern 43c located at least in a part of the first display area AA1 except for the plurality of first transfer electrodes 5a.
- the second pattern 43c of the additional metal layer 43 is configured to transmit the first voltage signal Vss.
- the first voltage signal transmission structure 2 includes a second pattern 43c of additional metal layer 43.
- the second pattern 43c of the additional metal layer 43 is used to transmit the first voltage signal Vss. Since the resistance of the metal structure is smaller, it is more conducive to optimizing the voltage drop of the first voltage signal Vss.
- the following describes an embodiment in which the first part 21 of the first voltage signal transmission structure 2 includes a plurality of first voltage signal lines.
- FIGS. 15 to 18 only illustrate the positional correspondence between the pixel circuit and the signal line, and do not indicate the upper and lower layer relationships of each structure.
- the plurality of anodes M in the anode layer 31 include a plurality of first anodes 311 located in the first display area AA1 and a plurality of anodes M located in the second display area AA1 .
- the plurality of second anodes 312 in the area AA2 and the plurality of pixel circuits 7 arranged in an array on one side of the substrate 1 include a plurality of first pixel circuits 71 , a plurality of second pixel circuits 72 and a plurality of dummy pixel circuits 73 .
- the first pixel circuit 71 and/or the second pixel circuit 72 includes a plurality of first pixel circuits 71 and a plurality of second pixel circuits 72.
- Each first pixel circuit 71 is electrically connected to a first anode 311, and each second pixel circuit 71 is electrically connected to a first anode 311.
- the pixel circuit 72 is electrically connected to a second anode 312 , and the plurality of dummy pixel circuits 73 are electrically insulated from the anode layer 31 .
- the plurality of pixel circuits 7 are arranged into a plurality of pixel circuit columns, at least one pixel circuit column is a normal pixel circuit column 7a, and at least one pixel circuit column is a dummy pixel circuit column 7b.
- a plurality of pixel circuits 7 are arranged in an array.
- first direction X at least two pixel circuits 7 are arranged in a row, which is called a pixel circuit column.
- the second direction Y at least two pixel circuits 7 are arranged in a row. into a row, called a pixel circuit row.
- the normal pixel circuit column 7a includes a plurality of first pixel circuits 71 and/or a plurality of second pixel circuits 72 arranged along the first direction X
- the virtual pixel circuit column 7b includes a plurality of virtual pixel circuits 73 arranged along the first direction X. .
- the second source-drain conductive layer 42 includes a plurality of voltage signal lines, and each voltage signal line is electrically connected to a pixel circuit column. Among them, a voltage signal line passes through a pixel circuit column, and a voltage signal line overlaps and is electrically connected to each pixel circuit in a pixel circuit column.
- the plurality of voltage signal lines include: a plurality of first voltage signal lines 421 and a plurality of second voltage signal lines 422.
- the second voltage signal lines 422 are electrically connected to the normal pixel circuit columns 7a, and the first voltage signal lines 421 are connected to the virtual pixel circuits. Column 7b is electrically connected.
- Each second voltage signal line 422 is configured to transmit the second voltage signal Vdd to each pixel circuit 7 in the pixel circuit column, and the plurality of first voltage signal lines 421 is configured to transmit the first voltage signal Vss.
- the transmission structure 2 also includes a plurality of first voltage signal lines 421 .
- the plurality of sub-pixels in the display area AA include a first sub-pixel located in the first display area AA1 and a second sub-pixel located in the second display area AA2.
- the first pixel circuit 71 electrically connected to the first anode 311 is used to To control the first sub-pixel
- the second pixel circuit 72 electrically connected to the second anode 312 is used to control the second sub-pixel.
- the plurality of dummy pixel circuits 73 are redundant pixel circuits and do not control the sub-pixels.
- a plurality of pixel circuits 7 are located in the first display area AA1.
- the transparent conductive layer 5 also includes a plurality of connecting wires 5d.
- Each connecting wire 5d is used to connect a pixel circuit 7 and a second anode M.
- each first pixel circuit 71 is connected to a first anode 311 through a connecting wire 5d
- each second pixel circuit 72 is connected to a second anode 312 through a connecting wire 5d.
- the second pixel circuit 72 that controls the second sub-pixel in the second display area AA2 is interspersed with the first pixel circuit 71 that controls the first sub-pixel in the first display area AA1.
- the normal pixel circuit column 7 a includes a plurality of first pixel circuits 71 and/or a plurality of second pixel circuits 72 .
- the dummy pixel circuit column 7b includes a plurality of dummy pixel circuits 73.
- Each pixel circuit 7 needs to be connected to the second voltage signal Vdd.
- the plurality of first voltage signal lines 421 and the plurality of second voltage signal lines 422 serve as second voltage signal transmission lines VDD and are configured to transmit the second voltage signal Vdd.
- the first pixel circuit 71 and/or the second pixel circuit 72 and the dummy pixel circuit 73 are all connected to the second voltage signal Vdd.
- the plurality of dummy pixel circuits 73 are redundant pixel circuits and do not control sub-pixels, they do not It is electrically connected to the anode M, so whether the dummy pixel circuit 73 is connected to the second voltage signal Vdd does not affect the normal display of the display substrate 10 .
- the normal pixel circuit columns 7a and the dummy pixel circuit columns 7b are alternately arranged along the second direction Y.
- a virtual pixel circuit column 7b is included between two adjacent normal pixel circuit columns 7a.
- a row of normal pixel circuit rows 7a and a row of dummy pixel circuit rows 7b are arranged alternately in sequence.
- two adjacent columns of normal pixel circuit columns 7 a include two columns of virtual pixel circuit columns 7 b.
- one column of normal pixel circuit columns 7a and two columns of dummy pixel circuit columns 7b are arranged alternately in sequence.
- two adjacent columns of virtual pixel circuit columns 7 b include two columns of normal pixel circuit columns 7 a.
- two columns of normal pixel circuit columns 7a and one column of dummy pixel circuit columns 7b are arranged alternately in sequence.
- a plurality of first voltage signal lines 421 are configured to transmit the first voltage signal Vss
- the first voltage signal transmission structure 2 also includes a plurality of first voltage signal lines 421
- the plurality of second voltage signal lines 422 are configured to transmit the second voltage signal Vdd as the second voltage signal transmission line VDD.
- the second voltage signal line 422 (originally used to transmit the second voltage signal Vdd) connected to the dummy pixel circuit 73 is used to transmit the first voltage signal Vss, so that the multiple second voltage signal lines 422 are connected without affecting the display effect.
- the plurality of second voltage signal lines 422 transmit the first voltage signal Vss, so that the plurality of second voltage signal lines 422 serve as a part of the first voltage signal transmission structure 2, realizing the distribution of the first voltage signal transmission structure 2 In the display area AA, the effect of reducing the first voltage drop is achieved, thereby reducing the size of the second part 22 of the first voltage signal transmission structure 2 located in the peripheral area AN, such as the size e3 shown in FIG. 3, Reduce the frame size of the display substrate 10, such as size e4 shown in Figure 3.
- the plurality of first voltage signal lines 421 are electrically connected to the first pattern of the selected transparent conductive layer in the peripheral area AN.
- the plurality of second voltage signal lines 422 receive the first voltage signal transmitted from the transparent conductive layer, and the two are connected in the peripheral area, without changing the original structure of each film layer in the display area, and will not affect the display area.
- the pattern distribution of each film layer structure is not limited to:
- the plurality of first voltage signal lines 421 and the first pattern of the selected transparent conductive layer are both configured to transmit the first voltage signal Vss. Since the first pattern of the selected transparent conductive layer is arranged in the display area AA, the selected transparent conductive layer The first pattern of the layer can be connected to the light emitting device layer 3 in the display area AA. Therefore, the size (vertical) of the portion of the plurality of first voltage signal lines 421 and the selected first pattern of the transparent conductive layer located in the peripheral area The size in the direction of the boundary of the display area AA to which it is adjacent) only needs to satisfy the effective connection with the plurality of first voltage signal lines 421.
- connection wiring such as the plurality of first voltage signal lines 421) 421 and the first pattern of the selected transparent conductive layer located in the peripheral area AN is reduced in size. It can be understood that the proportion of the display area AA of the display substrate 10 is correspondingly increased. Further, the display device is realized The borders are narrowed.
- the display substrate 10 further includes: a plurality of pixel circuits 7 arranged in an array on one side of the substrate 1 , a gate gate arranged on one side of the substrate 1
- the conductive layer 8 the first source-drain conductive layer 41 disposed on the side of the gate conductive layer 8 away from the substrate 1
- the second source-drain conductive layer 42 disposed on the side of the first source-drain conductive layer 41 away from the substrate 1 .
- the plurality of pixel circuits 7 are arranged into a plurality of pixel circuit columns.
- the second source-drain conductive layer 42 includes a plurality of voltage signal lines extending along a first direction X.
- the first direction X is the extending direction of a plurality of pixel circuit columns. Each voltage signal line overlaps with a pixel circuit column.
- the aforementioned gate conductive layer 8 includes, for example, a first gate conductive layer 8 a and a second gate conductive layer 8 b.
- the first gate conductive layer 8 a is closer to the substrate 1 than the second gate conductive layer 8 b.
- the plurality of voltage signal lines include a plurality of first voltage signal lines 421 and a plurality of second voltage signal main lines 423 .
- the plurality of first voltage signal lines 421 are configured to transmit the first voltage signal Vss.
- the first voltage signal transmission structure 2 also includes a plurality of first voltage signal lines 421 .
- Each second voltage signal main line 423 is electrically connected to a pixel circuit column and is configured to transmit the second voltage signal Vdd to each pixel circuit in the pixel circuit column.
- the gate conductive layer 8 includes a plurality of second voltage signal auxiliary lines 81 extending along the second direction Y, and the plurality of second voltage signal auxiliary lines 81 are electrically connected to the second voltage signal main line 423 .
- the plurality of second voltage signal secondary lines 81 are configured to transmit the second voltage signal Vdd to the pixel circuit 7 overlapping with the first voltage signal line 421 .
- the first direction X intersects the second direction Y. Further, the first direction X is perpendicular to the second direction Y.
- a plurality of second voltage signal main lines 423 and a plurality of second voltage signal auxiliary lines 81 are located in the display area AA to form a mesh structure.
- the plurality of second voltage signal main lines 423 and the plurality of second voltage signal auxiliary lines 81 are located in the display area AA and are connected to the pixel circuit 7 as VDD signal lines to transmit the second voltage signal Vdd.
- the plurality of second voltage signal main lines 423 It is connected to the portion of the plurality of second voltage signal sub-lines 81 located in the peripheral area AN.
- the plurality of second voltage signal main lines 423 and the plurality of second voltage signal auxiliary lines 81 serve as VDD signal lines to transmit the second voltage signal Vdd.
- the second voltage signal main line 423 is used as a VDD signal line to transmit the second voltage signal Vdd
- the first voltage signal line 421 between two adjacent second voltage signal main lines 423 is used as a VSS signal line. Used to transmit the first voltage signal Vss.
- the second voltage signal Vdd required by the pixel circuit 7 that overlaps with the second voltage signal main line 423 is provided through a plurality of second voltage signal secondary lines 81 in the gate conductive layer 8 .
- At least one first voltage signal line 421 is provided between every two adjacent second voltage signal main lines 423 among the plurality of second voltage signal main lines 423, and /Or, at least one second voltage signal main line 423 is provided between every two adjacent first voltage signal lines 421 .
- the display substrate 10 also includes at least one transparent conductive layer 5 and at least one planarization layer 6 disposed on the side of the second source-drain conductive layer 42 away from the substrate 1 .
- At least one layer At least one transparent conductive layer in the transparent conductive layer 5 is a selected transparent conductive layer, and the first pattern of the selected transparent conductive layer is electrically connected to the plurality of first voltage signal lines 421 in the peripheral area AN.
- the transparent conductive layer 5 includes a first transparent conductive layer 51 , a second transparent conductive layer 52 and a third transparent conductive layer 53 .
- the first transparent conductive layer 51 and the third transparent conductive layer 53 include a plurality of second voltage signal main lines 423 extending along the first direction
- the second voltage signal main line 423 serves as the VDD signal line and is configured to transmit the second voltage signal Vdd
- the second transparent conductive layer 52 includes a plurality of first voltage signal lines 421 extending along the first direction X.
- the plurality of first voltage signal lines 421 included in 52 serve as VSS signal lines and are configured to transmit the first voltage signal Vss.
- the second voltage signal Vdd is transmitted through the plurality of second voltage signal main lines 423 in the first transparent conductive layer 51 and the third transparent conductive layer 53, and the plurality of first voltage signal lines 421 included in the second transparent conductive layer 52 transmits the first voltage signal Vdd.
- Voltage signal Vss The first transparent conductive layer 51 and the third transparent conductive layer 53 surround the second transparent conductive layer 52. Since the second voltage signal Vdd is more stable than the first voltage signal Vss, this will make the second transparent conductive layer 52
- the first voltage signal Vss transmitted within is more stable, thereby ensuring stable transmission of signals required for the operation of the display substrate 10, thereby avoiding the problem of increased power consumption of the display device due to unstable transmission of the first voltage signal Vss.
- the display substrate 10 further includes a light-shielding layer 9 disposed on one side of the substrate 1 and a plurality of pixel circuits 7 disposed on the side of the light-shielding layer 9 away from the substrate 1 .
- Each of the plurality of pixel circuits 7 includes a drive transistor T.
- the light-shielding layer 9 includes a plurality of light-shielding patterns 91 , and the orthographic projection of the driving transistor T of each pixel circuit 7 on the substrate 1 is within the orthographic projection of one light-shielding pattern 91 on the substrate 1 .
- the plurality of light shielding patterns 91 are connected to each other.
- the light shielding layer 9 is configured to transmit the first voltage signal Vss, and the first voltage signal transmission structure 2 includes the light shielding layer 9 .
- the light-shielding layer 9 serves as an isolation layer and is disposed between the driving transistor T and the substrate 1.
- Each light-shielding layer 9 corresponds to at least one driving transistor T to prevent the driving transistor T from contacting the second surface 1b of the substrate 1. Ion transmission occurs between the conductive structures on one side, and when the substrate 1 is a transparent material such as glass, light is emitted from the second surface 1b side of the substrate 1 to the driving transistor T on the first surface 1a side, causing driving The transistor T is abnormal, thereby ensuring the normal operation of the display substrate 10.
- Each light-shielding pattern 91 covers a driving transistor T, and multiple light-shielding patterns 91 are connected to each other through connection lines 92. It can be understood that the multiple light-shielding patterns 91 are an integral structure.
- the display substrate 10 further includes a source-drain conductive layer 4.
- the source-drain conductive layer 4 includes a first source-drain conductive layer 41 and a second source-drain conductive layer 42 sequentially provided from the substrate 1.
- the second part 22 of the first voltage signal transmission structure 2 includes a first voltage signal bus, the first part 21 includes a plurality of first voltage signal sub-lines 211, the first voltage signal bus is located in the first source-drain conductive layer 41, and/ Or the first voltage signal bus is located on the second source-drain conductive layer 42 .
- the size of the first voltage signal bus in a direction perpendicular to its extension direction is 5 ⁇ m ⁇ 20 ⁇ m.
- the first voltage signal bus includes a first bus 221 and a second bus 222 .
- the size d7 of the first bus line 221 in the direction perpendicular to the extending direction is 5 ⁇ m to 20 ⁇ m
- the size d8 of the second bus line 222 in the direction perpendicular to the extending direction is 5 ⁇ m to 20 ⁇ m.
- the size d7 of the first bus line 221 in the direction perpendicular to its extending direction is, for example, 5 ⁇ m, 15 ⁇ m, or 20 ⁇ m.
- the size d8 of the second bus line 222 in the direction perpendicular to its extending direction is, for example, 5 ⁇ m, 15 ⁇ m, or 20 ⁇ m.
- connection traces used to transmit VSS signals such as the first bus 221 and the second bus 222 as shown in Figure 21, have a small width in the portion located in the peripheral area AN. It can be understood that, accordingly, when the display substrate 10 is applied When used in a display device, an ultra-narrow frame of the display device can be achieved.
- Some embodiments of the present disclosure also provide a display device 100, as shown in FIG. 22, including the display substrate 10 as described in any of the above embodiments.
- the display device 100 may be any device that displays images, whether moving (eg, video), stationary (eg, still images), text, or images. More specifically, it is contemplated that the embodiments may be implemented in or in association with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer display, etc.), navigator, cockpit controller and/or display, camera view display (e.g. display of a rear view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging and aesthetic structure (e.g., for a display of an image of a piece of jewelry), etc.
- PDAs personal data assistants
- handheld or portable computers GPS receivers/navigators
- MP4 video players cam
- the above-mentioned display device 100 may also include a frame, a flexible circuit board 20 , and other electronic accessories.
- the display substrate 10 may be disposed within the frame, for example.
- the display substrate 10 further includes a binding lead extending along the second direction Y.
- One end of the binding lead is connected to the first bus 221 , and the other end of the binding lead is used for binding to the flexible circuit board 20 .
- the portion of the fixed lead located outside the peripheral area AN (the portion beyond the substrate 1 ) is bent together with the flexible circuit board 20 to the back of the display substrate 10 .
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Abstract
Description
Claims (18)
- 一种显示基板,包括显示区和环绕所述显示区的周边区,所述显示基板包括:衬底;发光器件层,设置于所述衬底一侧,所述发光器件层包括阳极层和阴极层,所述阳极层相对于所述阴极层靠近所述衬底;第一电压信号传输结构,设置于所述发光器件层与所述衬底之间,被配置为向所述阴极层传输第一电压信号;其中,所述第一电压信号传输结构包括位于所述显示区的第一部分和位于所述周边区的第二部分,所述第一部分和所述第二部分电连接,且所述第一部分布设于所述显示区内。
- 根据权利要求1所述的显示基板,其中,所述第一部分包括呈网状结构的图案;和/或,所述第一部分包括多条第一电压信号线。
- 根据权利要求1或2所述的显示基板,其中,所述显示区的边界包括多个边界线,其中一个边界线为选定边界线;所述第一电压信号传输结构的第二部分包括第一总线和第二总线;所述第一总线沿所述选定边界线的延伸方向延伸,被配置为接入外部芯片提供的第一电压信号;所述第二总线环绕所述多个边界线中除所述选定边界线之外的其他边界线设置,且所述第二总线在所述衬底上的正投影与所述第一总线在所述衬底上的正投影无交叠。
- 根据权利要求3所述的显示基板,其中,所述第一电压信号传输结构的第一部分与所述第二总线连接;所述第一电压信号传输结构还包括多条连接线,所述第一电压信号传输结构的第一部分与所述第一总线通过所述多条连接线连接。
- 根据权利要求1~4中任一项所述的显示基板,还包括:设置于所述衬底一侧的第一源漏导电层;设置于所述第一源漏导电层远离所述衬底一侧的第二源漏导电层;所述第一电压信号传输结构位于所述第二源漏导电层与所述阳极层之间;所述阳极层包括:位于所述显示区内的多个阳极和位于所述周边区的搭接阳极;其中,所述搭接阳极与所述多个阳极电绝缘;所述第一电压信号传输结构的第二部分通过所述搭接阳极,与所述阴极层电连接。
- 根据权利要求5所述的显示基板,其中,所述显示区包括第一显示区和第二显示区,所述第一显示区包围所述第二显示区;所述多个阳极包括:位于所述第一显示区内的多个第一阳极,和位于所述第二显示区内的多个第二阳极;所述显示基板还包括设置于所述衬底一侧的多个像素电路,所述多个像素电路位于所述第一显示区且不位于所述第二显示区;所述显示基板还包括设置于所述第二源漏导电层远离所述衬底一侧的至少一层透明导电层;每层所述透明导电层包括:多个第一转接电极,位于所述第一显示区内,每个第一转接电极与所述阳极层中的一个第一阳极电连接;多个第二转接电极,位于所述第二显示区内,每个第二转接电极与所述阳极层中的一个第二阳极电连接;第一图案,至少位于所述第一显示区中除所述多个第一转接电极之外的部分区域;所述第一图案包括多个网孔;所述至少一层透明导电层中的至少一层透明导电层为选定透明导电层,所述选定透明导电层的第一图案被配置为传输所述第一电压信号,所述第一电压信号传输结构的第一部分包括所述选定透明导电层的第一图案位于显示区内的部分。
- 根据权利要求6所述的显示基板,其中,所述至少一层透明导电层中的每层均为选定透明导电层;所述选定透明导电层的第一图案还位于所述周边区,所述第一电压信号传输结构的第二部分包括所述选定透明导电层的第一图案位于周边区内的部分;每层透明导电层的第一图案均作为所述第一电压信号传输结构;所述至少一层透明导电层中的各层透明导电层位于所述周边区内的部分电连接;所述至少一层透明导电层中最远离所述衬底的透明导电层的第一图案位于周边区的部分,与所述搭接阳极连接。
- 根据权利要求7所述的显示基板,其中,所述衬底设置所述至少一层透明导电层的一侧表面包括多个侧边;所述至少一层透明导电层包括自所述衬底依次设置的第一透明导电层、第二透明导电层、第三透明导电层;所述显示基板还包括至少一层平坦化层,所述至少一层平坦化层包括:第一平坦化层,位于所述第一透明导电层与所述第二透明导电层之间;第二平坦化层,位于所述第二透明导电层和所述第三透明导电层之间;第三平坦化层,位于所述第三透明导电层远离所述衬底的一侧;所述第三平坦化层在所述衬底上的正投影的边界与该边界所靠近的所述衬底的侧面之间的距离,大于所述第二平坦化层在所述衬底上的正投影的边界与所述衬底的侧面之间的距离,且所述第二平坦化层在所述衬底上的正投影的边界与所述衬底的侧面之间的距离,大于所述第一平坦化层在所述衬底上的正投影与所述衬底的侧面之间的距离;所述至少一层透明导电层在所述衬底上的正投影的边界与该边界所靠近的所述衬底的侧面之间的距离,小于所述第一平坦化层在所述衬底上的正投影的边界与该边界所靠近的所述衬底的侧面之间的距离;作为所述第一电压信号传输结构的所述第一图案位于所述周边区的部分,与所述搭接阳极连接。
- 根据权利要求6所述的显示基板,其中,所述至少一层透明导电层包括自所述衬底依次设置的第一透明导电层、第二透明导电层、第三透明导电层;所述第二透明导电层的第一图案作为所述第一电压信号传输结构,第二透明导电层的第一图案还位于所述周边区;所述第二透明导电层的第一图案位于周边区的部分,与所述搭接阳极连接;所述第一透明导电层的第一图案和所述第三透明导电层的第一图案被配置为向所述多个像素电路传输第二电压信号。
- 根据权利要求6~9中任一项所述的显示基板,其中,所述显示基板还包括附加金属层,所述附加金属层包括第二图案;所述附加金属层与所述选定透明导电层位于同层;所述附加金属层的第二图案至少位于所述第一显示区中除所述多个第一转接电极之外的部分区域;所述附加金属层的第二图案被配置为传输所述第一电压信号,所述第一电压信号传输结构包括所述附加金属层的第二图案;或者,所述附加金属层设置于所述选定透明导电层远离所述衬底的一侧;所述附加金属层的第二图案设置于所述选定透明导电层的第一图案的一侧,且所述附加金属层的第二图案与所述选定透明导电层的第一图案电连接,所述第一电压信号传输结构还包括附加金属层的第二图案。
- 根据权利要求6~10中任一项所述的显示基板,其中,所述多个像素电路阵列布置,包括多个第一像素电路、多个第二像素电路 和多个虚拟像素电路,每个第一像素电路与一个所述第一阳极电连接,每个第二像素电路与一个所述第二阳极电连接;所述多个虚拟像素电路与所述阳极层电绝缘;所述多个像素电路排列成多个像素电路列,至少一个像素电路列为正常像素电路列,至少一个像素电路列为虚拟像素电路列;所述正常像素电路列包括多个所述第一像素电路和/或多个所述第二像素电路,所述虚拟像素电路列包括多个所述虚拟像素电路;所述第二源漏导电层包括多条电压信号线,每条电压信号线与一个像素电路列电连接;所述多条电压信号线包括:多条第一电压信号线和多条第二电压信号线,所述第二电压信号线与所述正常像素电路列电连接;所述第一电压信号线与所述虚拟像素电路列电连接;每条第二电压信号线被配置为向所述像素电路列中的各像素电路传输第二电压信号;所述多条第一电压信号线被配置为传输所述第一电压信号;所述第一电压信号传输结构还包括所述多条第一电压信号线。
- 根据权利要求11所述的显示基板,其中,所述多条第一电压信号线与所述选定透明导电层的第一图案在所述周边区电连接。
- 根据权利要求1~12中任一项所述的显示基板,还包括:设置于所述衬底的一侧的多个像素电路,所述多个像素电路阵列布置,所述多个像素电路排列成多个像素电路列;所述显示基板还包括:设置于所述衬底一侧栅导电层;设置于所述栅导电层远离所述衬底一侧的第一源漏导电层;设置于所述第一源漏导电层远离所述衬底一侧的第二源漏导电层;所述第二源漏导电层包括沿第一方向延伸的多条电压信号线,每条电压信号线与一个像素电路列有重叠;所述多条电压信号线包括多条第一电压信号线和多条第二电压信号主线,每条第二电压信号主线与一个所述像素电路列电连接,被配置为向所述像素电路列中的各像素电路传输第二电压信号;所述第一方向为所述多个像素电路列的延伸方向;所述栅导电层包括沿第二方向延伸的多条第二电压信号副线,所述多条第二电压信号副线与所述第二电压信号主线电连接;所述多条第二电压信号副线被配置为,为与所述第一电压信号线有重叠的像素电路传输第二电压信号;其中,所述多条第一电压信号线被配置为传输所述第一电压信号;所述第一电压信号传输结构还包括所述多条第一电压信号线。
- 根据权利要求13所述的显示基板,其中,所述多条第二电压信号主线中的每相邻两个第二电压信号主线之间设置有至少一条第一电压信号线,和/或,每相邻两个第一电压信号线之间设置有至少一条第二电压信号主线。
- 根据权利要求13或14所述的显示基板,其中,所述显示基板还包括设置于所述第二源漏导电层远离所述衬底一侧的至少一层透明导电层和至少一层平坦化层,至少一层透明导电层中的至少一层透明导电层为选定透明导电层,所述选定透明导电层的第一图案与所述多条第一电压信号线在所述周边区电连接。
- 根据权利要求1~15中任一项所述的显示基板,其中,还包括:设置于所述衬底一侧的遮光层;设置于所述遮光层远离所述衬底一侧的多个像素电路,所述多个像素电路中的每个像素电路包括驱动晶体管;其中,所述遮光层包括多个遮光图案,每个像素电路的驱动晶体管在所述衬底上的正投影在一个遮光图案在所述衬底上的正投影内;所述多个遮光图案彼此连接;所述遮光层被配置为传输第一电压信号,所述第一电压信号传输结构还包括所述遮光层。
- 根据权利要求1所述的显示基板,其中,包括自所述衬底依次设置的第一源漏导电层和第二源漏导电层;所述第一电压信号传输结构的第二部分包括第一电压信号总线,所述第一部分包括多条第一电压信号子线;所述第一电压信号总线位于所述第一源漏导电层内,和/或位于所述第二源漏导电层;所述第一电压信号总线在垂直于其延伸方向的方向上的尺寸为5μm~20μm。
- 一种显示装置,其中,包括如权利要求1~16所述的显示基板。
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