WO2022266980A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022266980A1
WO2022266980A1 PCT/CN2021/102252 CN2021102252W WO2022266980A1 WO 2022266980 A1 WO2022266980 A1 WO 2022266980A1 CN 2021102252 W CN2021102252 W CN 2021102252W WO 2022266980 A1 WO2022266980 A1 WO 2022266980A1
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WIPO (PCT)
Prior art keywords
signal line
layer
transmission
substrate
orthographic projection
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PCT/CN2021/102252
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English (en)
French (fr)
Inventor
易宏
张跳梅
青海刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001608.4A priority Critical patent/CN115769703A/zh
Priority to US17/782,979 priority patent/US20240179967A1/en
Priority to PCT/CN2021/102252 priority patent/WO2022266980A1/zh
Publication of WO2022266980A1 publication Critical patent/WO2022266980A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • the purpose of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a display area and a peripheral area surrounding the display area; the display substrate further includes:
  • the first signal line is located in the peripheral area, and the first signal line includes a portion extending along a first direction;
  • a second signal line is located in the peripheral area, the second signal line includes a portion extending along the first direction, at least part of the first signal line is located in the display area and the Between the second signal lines, there is a first space between the orthographic projection of the first signal line on the base of the display substrate and the orthographic projection of the second signal line on the base;
  • a first planar layer comprising a first planar portion located in the peripheral region
  • the second flat layer, the second flat layer includes a first via hole, and the orthographic projection of the first via hole on the substrate has a first overlapping area with the first spacer region; the first flat layer The orthographic projection of the portion on the substrate has a second overlap region with the first overlap region.
  • the first overlapping region is located inside the orthographic projection of the first flat portion on the base.
  • an orthographic projection of the first flat portion on the substrate at least partially overlaps an orthographic projection of the first signal line on the substrate;
  • the width d of the second spacer region perpendicular to the first direction satisfies: 8 ⁇ m ⁇ d ⁇ 12 ⁇ m.
  • the display substrate further includes:
  • a cathode layer at least partially located in the display area
  • the conductive connection layer extends from the display area to the peripheral area, and the conductive connection layer is respectively coupled with the cathode layer and the second signal line; the conductive connection layer is in the The orthographic projection on the substrate at least partially overlaps the second overlapping region.
  • the second planar layer further includes a plurality of second via holes distributed in an array, and the conductive connection layer is coupled to the second signal line through the plurality of second via holes.
  • the display substrate further includes an anode layer, and the conductive connection layer and the anode layer are provided in the same layer and the same material.
  • the display substrate further includes an encapsulation layer, at least part of the encapsulation layer is located on a side of the cathode layer facing away from the substrate, and the encapsulation layer covers the second overlapping region.
  • the display substrate further includes:
  • a plurality of fan-out lines, the plurality of fan-out lines are located in the peripheral area, at least part of the orthographic projections of the fan-out lines on the base overlap with the second overlapping area.
  • the first signal line includes a first transmission part and a second transmission part coupled, the first transmission part extends along the first direction, and at least part of the second transmission part extends along the first direction. extending in two directions, the second direction intersecting the first direction;
  • the second signal line includes a third transmission part and a fourth transmission part coupled, the third transmission part extends along the first direction, at least part of the fourth transmission part along the second direction Extending, the fourth transmission part and the second transmission part are arranged along the first direction, the orthographic projection of the first transmission part on the base and the projection of the third transmission part on the base There is the first spacer between the orthographic projections.
  • the first transmission part includes a coupled first transmission pattern and a second transmission pattern, the first transmission pattern is located between the base and the second transmission pattern;
  • the third transmission part includes a third transmission pattern and a fourth transmission pattern coupled, the third transmission pattern is located between the substrate and the fourth transmission pattern, and the second transmission pattern is between the substrate and the fourth transmission pattern. There is the first spacer between the orthographic projection on the substrate and the orthographic projection of the fourth transmission pattern on the substrate.
  • the display substrate further includes a first source-drain metal layer and a second source-drain metal layer, the first source-drain metal layer is located between the substrate and the second source-drain metal layer;
  • the first transfer pattern and the third transfer pattern are set on the same layer and the same material as the first source-drain metal layer; the second transfer pattern and the fourth transfer pattern are set on the same layer as the second source-drain metal layer Same layer same material setting.
  • the second transmission part includes a fifth transmission pattern and a sixth transmission pattern stacked, the fifth transmission pattern and the first transmission pattern form an integral structure, the sixth transmission pattern and the There is a fourth spacer between the second transmission pattern, the orthographic projection of the fourth spacer on the substrate, and the first boundary of the first flat part towards the third transmission part are on the substrate
  • the orthographic projections on are at least partially overlapping.
  • the display substrate further includes:
  • a third signal line, the third signal line is located in the peripheral area;
  • the third signal line includes a fifth transmission part and a sixth transmission part coupled, and the fifth transmission part is along the first direction Extending, at least part of the sixth transmission part extends along the second direction; the sixth transmission part and the second transmission part are arranged along the first direction;
  • the orthographic projection of the first flat portion on the substrate towards the first boundary of the third transmission part is respectively the same as the orthographic projection of the second transmission part on the substrate and the sixth transmission part in The orthographic projections on the base overlap.
  • the sixth transmission part includes a seventh transmission pattern, and the seventh transmission pattern is arranged in a different layer from the second transmission pattern.
  • the sixth transmission part includes an eighth transmission pattern, the eighth transmission pattern is coupled to the seventh transmission pattern, and the eighth transmission pattern and the first transmission pattern are set in the same layer and the same material .
  • the first signal line includes a positive power line
  • the second signal line includes a negative power line
  • the third signal line includes an initialization signal line
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • a third aspect of the present disclosure provides a method for manufacturing a display substrate, the display substrate including: a display area and a peripheral area surrounding the display area; the manufacturing method includes:
  • the first signal line is located in the peripheral area, and the first signal line includes a portion extending along a first direction;
  • the second signal line is located in the peripheral area, the second signal line includes a portion extending along the first direction, at least part of the first signal line is located in the display area and Between the second signal lines, there is a first space between the orthographic projection of the first signal line on the base of the display substrate and the orthographic projection of the second signal line on the base;
  • first planar layer comprising a first planar portion located at said peripheral region
  • the second planar layer includes a first via hole, and the orthographic projection of the first via hole on the substrate has a first overlapping area with the first spacer region; the first via hole The orthographic projection of the flat portion on the substrate has a second overlap area with the first overlap area.
  • FIG. 1 is a partial structural schematic diagram of a lower frame of a display substrate provided by an embodiment of the present disclosure
  • Fig. 2 is the enlarged schematic diagram of part X1 in Fig. 1;
  • Fig. 3 is the first enlarged schematic diagram of part X3 in Fig. 2;
  • Fig. 4 is the second enlarged schematic diagram of part X3 in Fig. 2;
  • Fig. 5 is the enlarged schematic diagram of part X4 in Fig. 3;
  • Fig. 6 is an enlarged schematic diagram of part X5 in Fig. 3;
  • Fig. 7 is a schematic cross-sectional view along the A1A2 direction in Fig. 6;
  • Fig. 8 is a schematic cross-sectional view along the C1C2 direction in Fig. 6;
  • Fig. 9 is the first enlarged schematic diagram of part of the film layer included in part X2 in Fig. 1;
  • Fig. 10 is the second enlarged schematic diagram of part of the film layer included in part X2 in Fig. 1;
  • Fig. 11 is the 3rd enlarged schematic view of part of the film layer included in X2 part in Fig. 1;
  • Fig. 12 is a schematic cross-sectional view along the F1F2 direction in Fig. 6;
  • FIG. 13 is a schematic diagram of the layout of the first fan-out line in FIG. 6;
  • FIG. 14 is a schematic diagram of the layout of the second fan-out line in FIG. 6;
  • FIG. 15 is a schematic layout diagram of the first source-drain metal layer in FIG. 6;
  • Fig. 16 is a schematic layout diagram of the first flat part in Fig. 6;
  • FIG. 17 is a schematic layout diagram of the second source-drain metal layer in FIG. 6;
  • FIG. 18 is a schematic layout diagram of the second flat layer in FIG. 6;
  • FIG. 19 is a schematic layout diagram of adding a conductive connection layer in FIG. 6;
  • FIG. 20 is a schematic layout diagram of the first source-drain metal layer and the first flat part in FIG. 6;
  • FIG. 21 is a schematic layout diagram of the first source-drain metal layer and the second flat layer in FIG. 6;
  • FIG. 22 is a schematic layout diagram of adding a conductive connection layer in FIG. 20 .
  • the present disclosure provides a display substrate, including: a display area and a peripheral area surrounding the display area; the display substrate further includes: a first signal line and a second signal line both located in the peripheral area, the first There is a first space between the orthographic projection of the signal line on the base of the display substrate and the orthographic projection of the second signal line on the base.
  • the display substrate further includes a first flat layer and a second flat layer, where the first spacer is located, the first flat layer and the second flat layer are both excavated.
  • both the first flat layer and the second flat layer are excavated at the position where the first spacing region is located, resulting in A deep groove will be formed at the position, so that other functional film layers formed later, such as the encapsulation layer 80, etc., will easily break due to the excessive step difference at the groove when they cross the groove, thus causing water vapor and Oxygen can invade the inside of the display substrate from the fractured position, affecting the service life of the display substrate and reducing the yield of the display substrate.
  • an embodiment of the present disclosure provides a display substrate, including: a display area 10 and a peripheral area 20 surrounding the display area 10; the display substrate also include:
  • a first signal line 21, the first signal line 21 is located in the peripheral area 20, and the first signal line 21 includes a portion extending along a first direction;
  • the second signal line 22, the second signal line 22 is located in the peripheral region 20, the second signal line 22 includes a portion extending along the first direction, at least part of the first signal line 21 is located in the Between the display area 10 and the second signal line 22, the orthographic projection of the first signal line 21 (including the first transmission part 210) on the base 90 of the display substrate and the second signal line 22 (including the third transmission part 220) having a first spacer 30 between the orthographic projections on the substrate 90;
  • a first planar layer comprising a first planar portion 40 located in the peripheral region 20;
  • the second planar layer 50, the second planar layer 50 includes a first via hole 51, and the orthographic projection of the first via hole 51 on the substrate 90 has a first overlapping area with the first spacer region 30 ;
  • the orthographic projection of the first flat portion 40 on the substrate 90 has a second overlapping area with the first overlapping area.
  • the display substrate includes the display area 10 and the peripheral area 20, and the display area 10 includes a rectangle or other heterogeneous structures.
  • the peripheral area 20 includes a portion close to the first side of the display area 10, a portion close to the second side of the display area 10, a portion close to the third side of the display area 10 and a portion close to the display area 10. part of the fourth side.
  • the first side and the second side are opposed in the first direction, and the third side and the fourth side are opposed in a second direction.
  • the first side includes the lower side of the display area 10
  • the peripheral area 20 is provided with a driver chip in an area close to the first side
  • the second side includes the lower side of the display area 10.
  • the upper side; the third side includes the left side of the display area 10, the fourth side includes the right side of the display area 10, the peripheral area 20 is close to the third side and close to the A gate driving circuit is arranged in the area of the fourth side.
  • the first signal line 21 is located in the peripheral area 20 .
  • the first signal line 21 includes a portion close to the first side of the display area 10 and a portion close to the second side of the display area 10 .
  • the second signal line 22 is located in the peripheral area 20 .
  • the second signal line 22 includes a portion close to the first side of the display area 10 and a portion close to the second side of the display area 10 .
  • At least part of the first signal line 21 is located between the display area 10 and the second signal line 22 .
  • at least part of the first signal line 21 is located between the display area 10 and the second signal line 22 .
  • the orthographic projection of the first signal line 21 on the base 90 of the display substrate is different from that of the second signal line 22 on the base 90.
  • the orthographic projection of the first signal line 21 on the base 90 of the display substrate is different from that of the second signal line 22 on the base 90.
  • the display substrate further includes the first flat layer, the first flat layer includes a first flat portion 40 located in the peripheral area 20 , and the first flat portion 40 is close to the display area 10 the first side of the .
  • the first flat portion 40 extends from a position close to the display area 10 to a position away from the display area 10 .
  • the first flat layer further includes a second flat portion, at least part of the second flat portion is located in the display area 10 .
  • the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate metal layer that are sequentially stacked along a direction away from the substrate 90 , an interlayer insulating layer, a first source-drain metal layer, a first planar layer, a second source-drain metal layer, a second planar layer 50 , an anode layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer 80 .
  • the display substrate further includes a first passivation layer, and the first passivation layer is located between the first source-drain metal layer and the first flat layer.
  • the display substrate further includes a second passivation layer, and the second passivation layer is located between the second source-drain metal layer and the second flat layer 50.
  • the second planar layer 50 includes the first via hole 51, and the first via hole 51 is used to release water vapor during the process of the display substrate.
  • the orthographic projection of the first via hole 51 on the substrate 90 extends along the first direction.
  • At least part of the orthographic projection of the first via hole 51 on the substrate 90 is located inside the first spacer region 30 .
  • the orthographic projection of the first via hole 51 on the substrate 90 has a first overlapping area with the first spacing region 30 ; the orthographic projection of the first flat portion 40 on the substrate 90 The projection and the first overlapping area have a second overlapping area; both the first overlapping area and the second overlapping area extend along the first direction.
  • the orthographic projection of the first signal line 21 on the base 90 of the display substrate is different from that of the second signal line 22 on the base.
  • the second planar layer 50 includes a first via hole 51, and the orthographic projection of the first via hole 51 on the substrate 90 is different from the first spacer Region 30 has a first overlapping region;
  • the orthographic projection of said first planar portion 40 on said substrate 90 has a second overlapping region with said first overlapping region.
  • the display substrate is arranged in such a structure that the first planar layer can be filled in the second overlapping region, reducing the level difference of the second overlapping region, thereby helping to reduce the subsequent formation of other functions.
  • the risk of breakage of the film layer when crossing the second overlapping area effectively prevents the intrusion of water vapor and oxygen in the environment into the interior of the display substrate in the second overlapping area, thereby improving the service life and display performance of the display substrate.
  • Substrate yield is arranged in such a structure that the first planar layer can be filled in the second overlapping region, reducing the level difference of the second overlapping region, thereby helping to reduce the subsequent formation of other functions.
  • the first overlapping region is set to be located inside the orthographic projection of the first flat portion 40 on the substrate 90 .
  • the above setting method further reduces the risk of the other functional film layers breaking when crossing the second overlapping area, effectively avoiding the intrusion of water vapor and oxygen in the environment into the interior of the display substrate in the first overlapping area , improving the service life of the display substrate.
  • the orthographic projection of the first flat portion 40 on the substrate 90 at least partially overlaps the orthographic projection of the first signal line 21 on the substrate 90 ;
  • a plurality of third via holes Via3 are provided on the first flat portion 40, and the first signal line 21 includes 40 and the substrate 90, and the second transmission pattern 2102 located on the side of the first flat part 40 facing away from the substrate 90, the first transmission pattern 2101 is in the The orthographic projection on the substrate 90 and the orthographic projection of the first flat portion 40 on the substrate 90 at least partly overlap, and the orthographic projection of the second transmission pattern 2102 on the substrate 90 overlaps with the first flat portion 40 Orthographic projections of the portion 40 on the substrate 90 are at least partially overlapped, and the first transmission pattern 2101 and the second transmission pattern 2102 can be coupled through the plurality of third via holes Via3.
  • the plurality of third via holes Via3 are distributed in an array.
  • the orthographic projection of the first flat portion 40 on the substrate 90 does not overlap with the orthographic projection of the second signal line 22 on the substrate 90 .
  • the above setting has a second space between the orthographic projection of the first flat portion 40 on the substrate 90 and the orthographic projection of the second signal line 22 on the substrate 90, so that the first flat portion
  • the orthographic projection of the boundary of 40 on the base 90 does not overlap with the orthographic projection of the second signal line 22 on the base 90, so that the first signal line 21 does not need to climb the first flat portion 40 steps formed.
  • the second signal line 22 includes a third transmission pattern 2201 and a fourth transmission pattern 2202
  • the third transmission pattern 2201 is located between the first flat layer and Between the substrates 90 , the fourth transmission pattern 2202 is located on the side of the first flat layer facing away from the substrate 90 .
  • the fourth transmission pattern 2202 needs The level difference generated across the boundary of the first flat portion 40, so that in the same patterning process, the fourth transmission pattern 2202 and other conductive patterns (also across the level difference, and with the fourth transmission pattern 2202 to transmit different signals, such as the seventh transmission pattern 2310), the conductive material used to make the fourth transmission pattern 2202 and other conductive patterns is likely to remain at the boundary of the first flat portion 40 (such as the X6 portion) , so that a short circuit between the fourth transmission pattern 2202 and the other conductive patterns may easily occur.
  • via holes Via1 and Via2 formed on the first planar layer are schematically shown in FIG. 9 .
  • the first signal line 21 does not need to climb up the level difference formed by the first flat portion 40, thus avoiding the contact between the first signal line 21 and the other conductive patterns. A short circuit occurs between them.
  • the width d of the second spacer region perpendicular to the first direction is set to satisfy: 8 ⁇ m ⁇ d ⁇ 12 ⁇ m.
  • the above arrangement avoids the short circuit between the first signal line 21 and the other conductive patterns, and also reduces the risk of breakage of the other functional film layers when crossing the second overlapping region.
  • the display substrate further includes:
  • a cathode layer at least part of which is located in the display area 10;
  • a conductive connection layer 60 extends from the display area 10 to the peripheral area 20, the conductive connection layer 60 is respectively coupled to the cathode layer and the second signal line 22; the The orthographic projection of the conductive connection layer 60 on the substrate 90 at least partially overlaps with the second overlapping region.
  • the cathode layer can extend from the display area 10 to the peripheral area 20 .
  • the conductive connection layer 60 is located on a side of the second planar layer 50 facing away from the base 90 .
  • the orthographic projection of the conductive connection layer 60 on the substrate 90 at least partially overlaps the orthographic projection of the cathode layer on the substrate 90, and the conductive connection layer 60 is on the substrate 90
  • the orthographic projection of is at least partially overlapped with the orthographic projection of the second signal line 22 on the substrate 90 .
  • the conductive connection layer 60 includes a first conductive connection pattern 601 , a second conductive connection pattern 602 and a plurality of third conductive connection patterns 603 .
  • the plurality of third conductive connection patterns 603 are arranged along the first direction, and each of the third conductive connection patterns 603 is respectively coupled to the first conductive connection pattern 601 and the second conductive connection pattern 602 .
  • the first conductive connection pattern 601 , the second conductive connection pattern 602 and the plurality of third conductive connection patterns 603 form an integral structure.
  • the orthographic projection of the first conductive connection pattern 601 on the substrate 90 at least partially overlaps the orthographic projection of the cathode layer on the substrate 90, and the first conductive connection pattern 601 overlaps at least partially.
  • the stack is coupled to the cathode layer.
  • the orthographic projection of the second conductive connection pattern 602 on the substrate 90 at least partially overlaps the orthographic projection of the second signal line 22 on the substrate 90, and the second conductive connection pattern 602 overlaps is coupled to the second signal line 22 .
  • the orthographic projection of the third conductive connection pattern 603 on the substrate 90 at least partially overlaps with the second overlapping region.
  • the conductive connection layer 60 is not easy to be broken when crossing the second overlapping region, effectively avoiding the environment The water vapor and oxygen in the gas intrude into the inside of the display substrate in the second overlapping region, thereby improving the service life of the display substrate.
  • the second planar layer 50 further includes a plurality of second via holes 52 distributed in an array, and the conductive connection layer 60 passes through the plurality of second via holes. 52 is coupled to the second signal line 22 .
  • the orthographic projection of the plurality of second via holes 52 on the substrate 90 is located inside the orthographic projection of the second signal line 22 on the substrate 90 .
  • the display substrate further includes an anode layer, and the conductive connection layer 60 and the anode layer are provided in the same layer and material.
  • the conductive connection layer 60 and the anode layer are arranged in the same layer and the same material, so that the conductive connection layer 60 and the anode layer can be formed simultaneously in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate. , reducing the manufacturing cost of the display substrate.
  • the display substrate further includes an encapsulation layer 80, at least part of the encapsulation layer 80 is located on the side of the cathode layer facing away from the substrate 90, the encapsulation layer 80 covers the second intersection overlapping area.
  • the encapsulation layer 80 is not easy to be broken when crossing the second overlapping region, effectively avoiding the The water vapor and oxygen intrude into the display substrate in the second overlapping region, thereby improving the service life of the display substrate.
  • the display substrate further includes:
  • a plurality of fan-out lines 70 are located in the peripheral region 20 , and at least part of the orthographic projections of the fan-out lines 70 on the substrate 90 overlap with the second overlapping region.
  • the display substrate further includes a plurality of data lines, and the fan-out lines 70 are respectively coupled to the corresponding data lines and the driving chip.
  • the multiple fan-out lines 70 include multiple first fan-out lines 701 and multiple second fan-out lines 702 .
  • the first fan-out lines 701 are made of a first gate metal layer
  • the plurality of second fan-out lines 702 are made of a second gate metal layer.
  • the unevenness caused by the fan-out line 70 is flattened, so as to avoid cracks in the upper film layer caused by the unevenness caused by the fan-out line 70 .
  • the first signal line 21 includes a coupled first transmission part 210 and a second transmission part 211, and the first transmission part 210 is connected along the first transmission part 211. Extending in one direction, at least part of the second transmission part 211 extends along a second direction, and the second direction intersects the first direction;
  • the second signal line 22 includes a third transmission part 220 and a fourth transmission part 221 coupled to each other, the third transmission part 220 extends along the first direction, and at least part of the fourth transmission part 221 extends along the The second direction extends, the fourth transmission part 221 and the second transmission part 211 are arranged along the first direction, and the orthographic projection of the first transmission part 210 on the substrate 90 is the same as the first transmission part 210
  • the three transmission parts 220 have the first spacer 30 between the orthographic projections on the substrate 90 .
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction
  • the first signal line 21 includes the first transmission part 210 and the second transmission part 211, and the second transmission part 211 is respectively coupled to the first transmission part 210 and the driver chip.
  • the second signal line 22 includes the third transmission part 220 and the fourth transmission part 221 , and the fourth transmission part 221 is coupled to the third transmission part 220 and the driver chip respectively.
  • the orthographic projection of the first transmission part 210 on the substrate 90 is located between the orthographic projection of the third transmission part 220 on the substrate 90 and the display area 10 , and the first There is the first spacer 30 between the orthographic projection of a transmission part 210 on the substrate 90 and the orthographic projection of the third transmission part 220 on the substrate 90 .
  • the orthographic projection of the fourth transmission part 221 on the substrate 90 and the orthographic projection of the second transmission part 211 on the substrate 90 are arranged at intervals along the first direction.
  • the first transmission part 210 includes a coupled first transmission pattern 2101 and a second transmission pattern 2102, and the first transmission pattern 2101 is located at between the substrate 90 and the second transfer pattern 2102;
  • the third transmission part 220 includes a third transmission pattern 2201 and a fourth transmission pattern 2202 coupled, the third transmission pattern 2201 is located between the substrate 90 and the fourth transmission pattern 2202, the first There is the first space 30 between the orthographic projection of the second transmission pattern 2102 on the substrate 90 and the orthographic projection of the fourth transmission pattern 2202 on the substrate 90 .
  • both the first transmission pattern 2101 and the second transmission pattern 2102 extend along the first direction.
  • Both the third transmission pattern 2201 and the fourth transmission pattern 2202 extend along the first direction.
  • the first flat portion 40 between the first transmission pattern 2101 and the second transmission pattern 2102 .
  • the width of the third spacer is larger than the width of the first spacer 30 .
  • the display substrate further includes a first source-drain metal layer and a second source-drain metal layer, the first source-drain metal layer is located between the base 90 and the second source-drain metal layer ;
  • the first transmission pattern 2101 and the third transmission pattern 2201 are set on the same layer and the same material as the first source-drain metal layer; the second transmission pattern 2102 and the fourth transmission pattern 2202 are the same as the second The source and drain metal layers are set in the same layer and the same material.
  • the above arrangement enables the first transfer pattern 2101 and the third transfer pattern 2201 to be formed in the same patterning process as the first source-drain metal layer, so that the second transfer pattern 2102 and the fourth transfer pattern
  • the transmission pattern 2202 can be formed in the same patterning process as the second source-drain metal layer, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.
  • the second transmission part 211 is set to include a fifth transmission pattern and a sixth transmission pattern 2110 arranged in layers, the fifth transmission pattern and the first transmission pattern 2101 form an integral structure, the The sixth transmission pattern 2110 and the second transmission pattern 2102 form an integral structure.
  • the fifth transmission pattern and the sixth transmission pattern 2110 are coupled.
  • At least part of the fifth transmission pattern extends along the second direction
  • at least part of the sixth transmission pattern 2110 extends along the second direction
  • the above arrangement is beneficial to improve the reliability of the first signal line 21 .
  • the second transmission part 211 includes a fifth transmission pattern and a sixth transmission pattern 2110 stacked, the fifth transmission pattern and the first transmission pattern
  • the pattern 2101 is formed as an integral structure, there is a fourth spacer 34 between the sixth transmission pattern 2110 and the second transmission pattern 2102, and the orthographic projection of the fourth spacer 34 on the substrate 90 is consistent with the Orthographic projections of the first flat portion 40 towards the first boundary B1 of the third transmission portion 220 on the base 90 overlap at least partially.
  • the sixth transmission pattern 2110 and the second transmission pattern 2102 can be electrically connected through the fifth transmission pattern and the first transmission pattern 2101 .
  • the above setting method is not only beneficial to improve the reliability of the first signal line 21, but also can prevent the sixth transmission pattern 2110 and the second transmission pattern 2102 from crossing the first boundary B1, thereby avoiding the second The problem of short-circuit burn occurs between the signal line 22 and the third signal line 23 due to the remaining manufacturing material on the first boundary B1.
  • the fourth transmission part 221 includes a ninth transmission pattern and a tenth transmission pattern stacked, and the ninth transmission pattern is located between the tenth transmission pattern and the substrate 90 .
  • the ninth transmission pattern and the third transmission pattern 2201 form an integral structure
  • the tenth transmission pattern and the fourth transmission pattern 2202 form an integral structure
  • the above arrangement is beneficial to improve the reliability of the second signal line 22 .
  • the display substrate further includes:
  • the third signal line 23, the third signal line 23 is located in the peripheral area 20; the third signal line 23 includes a fifth transmission part 230 and a sixth transmission part 231 coupled, the fifth transmission part 230 extends along the first direction, at least part of the sixth transmission part 231 extends along the second direction; the sixth transmission part 231 and the second transmission part 211 are arranged along the first direction;
  • the orthographic projection of the first flat portion 40 on the substrate 90 towards the first boundary B1 of the third transmission part 220 is respectively the same as the orthographic projection of the second transmission part 211 on the substrate 90 and the orthographic projection of the second transmission part 211 on the substrate 90 Orthographic projections of the sixth transmission part 231 on the substrate 90 overlap.
  • the third signal line 23 includes two fifth transmission parts 230 and a plurality of sixth transmission parts 231, one of the two fifth transmission parts 230 is located close to the first side of the display area 10 The other one of the two fifth transmission parts 230 is located close to the second side of the display area 10 .
  • the plurality of sixth transmission parts 231 are respectively coupled to the fifth transmission part 230 close to the first side.
  • the sixth transmission part 231 is also coupled to the driver chip.
  • the display substrate further includes an initialization signal layer, at least part of the initialization signal layer is located in the display area 10 , and the initialization signal layer is respectively coupled to the two fifth transmission parts 230 .
  • the fifth transmission part 230 , the first transmission part 210 and the third transmission part 220 are arranged at intervals along the direction away from the display area 10 .
  • the sixth transmission part 231 , the second transmission part 211 and the fourth transmission part 221 are arranged at intervals along the first direction.
  • the orthographic projection of the first flat portion 40 towards the first boundary B1 of the third transmission part 220 on the substrate 90 is the same as the orthographic projection of the third transmission part 220 on the substrate 90 projections, and the orthographic projections of the fourth transmission part 221 on the substrate 90 do not overlap.
  • the third transmission portion 220 is aligned with the third transmission portion 220
  • the orthographic projections on the substrate 90 and the orthographic projections of the fourth transmission part 221 on the substrate 90 do not overlap;
  • the orthographic projection of the boundary B1 on the substrate 90 overlaps with the orthographic projection of the second transmission part 211 on the substrate 90 and the orthographic projection of the sixth transmission part 231 on the substrate 90 respectively;
  • the second transmission part 211 and the second signal line 22 are arranged on the same layer, and both of them climb up the step difference generated by the first boundary B1 to avoid a short circuit, avoiding the sixth transmission part 231
  • a short-circuit occurs at the part of the center and the second signal line 22 that are arranged on the same layer and climb up the level difference generated by the first boundary B1.
  • the sixth transmission part 231 includes a seventh transmission pattern 2310 , and the seventh transmission pattern 2310 and the second transmission pattern 2102 are arranged in different layers.
  • the above arrangement of the seventh transfer pattern 2310 and the second transfer pattern 2102 in different layers avoids that the seventh transfer pattern 2310 and the second transfer pattern 2102 are produced in the same patterning process, so that even the The second transmission pattern 2102 and the seventh transmission pattern 2310 both climb the level difference generated by the first boundary B1, and there will be no short circuit between the second transmission pattern 2102 and the seventh transmission pattern 2310, avoiding Shows a burn problem in the substrate due to a short circuit between different signal lines.
  • the sixth transmission part 231 includes an eighth transmission pattern, the eighth transmission pattern is coupled to the seventh transmission pattern 2310, and the eighth transmission pattern is connected to the first transmission pattern 2101 Same layer same material setting.
  • the eighth transmission pattern is located between the seventh transmission pattern 2310 and the substrate 90, and the orthographic projection of the eighth transmission pattern on the substrate 90 is in the same position as the seventh transmission pattern 2310.
  • the orthographic projections on the substrate 90 are at least partially overlapping.
  • the eighth transmission pattern and the first transmission pattern 2101 are arranged on the same layer and material, so that the eighth transmission pattern and the first transmission pattern 2101 can be formed simultaneously in the same patterning process, thereby effectively simplifying the The manufacturing process flow of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.
  • the first signal line 21 includes a positive power line
  • the second signal line 22 includes a negative power line
  • the third signal line 23 includes an initialization signal line
  • a single-layer source-drain metal layer and a single-layer anode layer may also be used.
  • a double-layer source-drain metal layer and a double-layer anode layer can be used.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display substrate provided in the above embodiment, there is a first The spacer 30; the second flat layer 50 includes a first via hole 51, and the orthographic projection of the first via hole 51 on the substrate 90 has a first overlapping area with the first spacer 30; The orthographic projection of the first flat portion 40 on the substrate 90 has a second overlapping area with the first overlapping area.
  • the above-mentioned display substrate is arranged in such a structure that the first planar layer can be filled in the second overlapping region, and the level difference of the second overlapping region is reduced, thereby helping to reduce the level difference of other functional films formed subsequently.
  • the risk of layer breakage when crossing the second overlapping region effectively prevents the intrusion of water vapor and oxygen in the environment into the interior of the display substrate in the second overlapping region, improving the service life of the display substrate and the display substrate yield rate.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device can be any product or component with display function such as TV, monitor, digital photo frame, mobile phone, tablet computer, etc.
  • the display device also includes flexible circuit boards, printed circuit boards and backplanes, etc. .
  • Embodiments of the present disclosure also provide a manufacturing method of a display substrate, the manufacturing method is used to manufacture the display substrate provided in the above embodiments, the display substrate includes: a display area 10 and a peripheral area 20 surrounding the display area 10 ;
  • the preparation method comprises:
  • the first signal line 21 is located in the peripheral region 20, and the first signal line 21 includes a portion extending along a first direction;
  • the second signal line 22 is located in the peripheral region 20, the second signal line 22 includes a portion extending along the first direction, at least part of the first signal line 21 is located in Between the display area 10 and the second signal line 22, the orthographic projection of the first signal line 21 on the base 90 of the display substrate and the projection of the second signal line 22 on the base 90 There is a first spacer 30 between the orthographic projections;
  • first planar layer comprising a first planar portion 40 located in said peripheral region 20;
  • the second planar layer 50 includes a first via hole 51, and the orthographic projection of the first via hole 51 on the substrate 90 has a first overlap with the first spacer region 30 area; the orthographic projection of the first flat portion 40 on the substrate 90 has a second overlapping area with the first overlapping area.
  • the orthographic projection of the first signal line 21 on the base 90 of the display substrate is different from the orthographic projection of the second signal line 22 on the base 90
  • An overlapping area; the orthographic projection of the first flat portion 40 on the substrate 90 has a second overlapping area with the first overlapping area.
  • the above-mentioned display substrate is made into such a structure, so that the first flat layer can be filled in the second overlapping area, and the level difference of the second overlapping area is reduced, thereby helping to reduce the number of other functional films formed subsequently.
  • the risk of layer breakage when crossing the second overlapping region effectively prevents the intrusion of water vapor and oxygen in the environment into the interior of the display substrate in the second overlapping region, improving the service life of the display substrate and the display substrate yield rate.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

本公开提供一种显示基板及其制作方法、显示装置。所述显示基板包括：显示区域和周边区域；所述显示基板还包括：第一信号线，第二信号线，第一平坦层和第二平坦层，第一信号线位于周边区域，第一信号线包括沿第一方向延伸的部分；第二信号线位于周边区域，第二信号线包括沿第一方向延伸的部分，第一信号线的至少部分位于显示区域和第二信号线之间，第一信号线在显示基板的基底上的正投影与第二信号线在基底上的正投影之间具有第一间隔区；第一平坦部分包括位于周边区域的第一平坦部分；第二平坦层包括第一过孔，第一过孔在基底上的正投影与第一间隔区具有第一交叠区；第一平坦部分在基底上的正投影与第一交叠区具有第二交叠区。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(英文：Organic Light Emitting Diode，简称：OLED)显示器成为当今平板显示器研究领域的热点之一。越来越多的有源矩阵有机发光二极管(英文：Active Matrix Organic Light Emitting Diode，简称：AMOLED)显示面板进入市场。相对于传统的薄膜晶体管液晶显示面板(英文：Thin Film Transistor Liquid Crystal Display，简称：TFT LCD)，AMOLED显示器具有更快的反应速度，更高的对比度以及更广大的视角。而且随着显示技术的发展，越来越多的电子设备中开始使用轻薄且抗冲击特性表现良好的柔性可弯折OLED显示屏。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：显示区域和包围所述显示区域的周边区域；所述显示基板还包括：
第一信号线，所述第一信号线位于所述周边区域，所述第一信号线包括沿第一方向延伸的部分；
第二信号线，所述第二信号线位于所述周边区域，所述第二信号线包括沿所述第一方向延伸的部分，所述第一信号线的至少部分位于所述显示区域和所述第二信号线之间，所述第一信号线在所述显示基板的基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第一间隔区；
第一平坦层，所述第一平坦层包括位于所述周边区域的第一平坦部分；
第二平坦层，所述第二平坦层包括第一过孔，所述第一过孔在所述基底 上的正投影与所述第一间隔区具有第一交叠区；所述第一平坦部分在所述基底上的正投影与所述第一交叠区具有第二交叠区。
可选的，所述第一交叠区位于所述第一平坦部分在所述基底上的正投影的内部。
可选的，所述第一平坦部分在所述基底上的正投影与所述第一信号线在所述基底上的正投影至少部分交叠；
所述第一平坦部分在所述基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第二间隔区。
可选的，所述第二间隔区在垂直于所述第一方向上的宽度d满足：8μm≤d≤12μm。
可选的，所述显示基板还包括：
阴极层，所述阴极层的至少部分位于所述显示区域；
导电连接层，所述导电连接层从所述显示区域延伸至所述周边区域，所述导电连接层分别与所述阴极层和所述第二信号线耦接；所述导电连接层在所述基底上的正投影与所述第二交叠区至少部分交叠。
可选的，所述第二平坦层还包括阵列分布的多个第二过孔，所述导电连接层通过所述多个第二过孔与所述第二信号线耦接。
可选的，所述显示基板还包括阳极层，所述导电连接层与所述阳极层同层同材料设置。
可选的，所述显示基板还包括封装层，所述封装层的至少部分位于所述阴极层背向所述基底的一侧，所述封装层覆盖所述第二交叠区。
可选的，所述显示基板还包括：
多条扇出线，所述多条扇出线位于所述周边区域，至少部分所述扇出线在所述基底上的正投影与所述第二交叠区交叠。
可选的，所述第一信号线包括相耦接的第一传输部和第二传输部，所述第一传输部沿所述第一方向延伸，所述第二传输部的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
所述第二信号线包括相耦接的第三传输部和第四传输部，所述第三传输部沿所述第一方向延伸，所述第四传输部的至少部分沿所述第二方向延伸， 所述第四传输部与所述第二传输部沿所述第一方向排列，所述第一传输部在所述基底上的正投影与所述第三传输部在所述基底上的正投影之间具有所述第一间隔区。
可选的，所述第一传输部包括相耦接的第一传输图形和第二传输图形，所述第一传输图形位于所述基底和所述第二传输图形之间；
所述第三传输部包括相耦接的第三传输图形和第四传输图形，所述第三传输图形位于所述基底与所述第四传输图形之间，所述第二传输图形在所述基底上的正投影与所述第四传输图形在所述基底上的正投影之间具有所述第一间隔区。
可选的，所述显示基板还包括第一源漏金属层和第二源漏金属层，所述第一源漏金属层位于所述基底与所述第二源漏金属层之间；
所述第一传输图形和所述第三传输图形与所述第一源漏金属层同层同材料设置；所述第二传输图形和所述第四传输图形与所述第二源漏金属层同层同材料设置。
可选的，所述第二传输部包括层叠设置的第五传输图形和第六传输图形，所述第五传输图形与所述第一传输图形形成为一体结构，所述第六传输图形与所述第二传输图形之间具有第四间隔区，所述第四间隔区在所述基底上的正投影，与所述第一平坦部分朝向所述第三传输部的第一边界在所述基底上的正投影至少部分交叠。
可选的，所述显示基板还包括：
第三信号线，所述第三信号线位于所述周边区域；所述第三信号线包括相耦接的第五传输部和第六传输部，所述第五传输部沿所述第一方向延伸，所述第六传输部的至少部分沿所述第二方向延伸；所述第六传输部与所述第二传输部沿所述第一方向排列；
所述第一平坦部分朝向所述第三传输部的第一边界在所述基底上的正投影，分别与所述第二传输部在所述基底上的正投影和所述第六传输部在所述基底上的正投影交叠。
可选的，所述第六传输部包括第七传输图形，所述第七传输图形与所述第二传输图形异层设置。
可选的，所述第六传输部包括第八传输图形，所述第八传输图形与所述第七传输图形耦接，所述第八传输图形与所述第一传输图形同层同材料设置。
可选的，所述第一信号线包括正电源线，所述第二信号线包括负电源线，所述第三信号线包括初始化信号线。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的制作方法，所述显示基板包括：显示区域和包围所述显示区域的周边区域；所述制作方法包括：
制作第一信号线，所述第一信号线位于所述周边区域，所述第一信号线包括沿第一方向延伸的部分；
制作第二信号线，所述第二信号线位于所述周边区域，所述第二信号线包括沿所述第一方向延伸的部分，所述第一信号线的至少部分位于所述显示区域和所述第二信号线之间，所述第一信号线在所述显示基板的基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第一间隔区；
制作第一平坦层，所述第一平坦层包括位于所述周边区域的第一平坦部分；
制作第二平坦层，所述第二平坦层包括第一过孔，所述第一过孔在所述基底上的正投影与所述第一间隔区具有第一交叠区；所述第一平坦部分在所述基底上的正投影与所述第一交叠区具有第二交叠区。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板下边框的部分结构示意图；
图2为图1中X1部分的放大示意图；
图3为图2中X3部分的第一放大示意图；
图4为图2中X3部分的第二放大示意图；
图5为图3中X4部分的放大示意图；
图6为图3中X5部分的放大示意图；
图7为图6中沿A1A2方向的一种截面示意图；
图8为图6中沿C1C2方向的一种截面示意图；
图9为图1中X2部分包括的部分膜层的第一放大示意图；
图10为图1中X2部分包括的部分膜层的第二放大示意图；
图11为图1中X2部分包括的部分膜层的第三放大示意图；
图12为图6中沿F1F2方向的一种截面示意图；
图13为图6中第一扇出线的布局示意图；
图14为图6中第二扇出线的布局示意图；
图15为图6中第一源漏金属层的布局示意图；
图16为图6中第一平坦部分的布局示意图；
图17为图6中第二源漏金属层的布局示意图；
图18为图6中第二平坦层的布局示意图；
图19为在图6中增加导电连接层的布局示意图；
图20为图6中第一源漏金属层和第一平坦部分的布局示意图；
图21为图6中第一源漏金属层和第二平坦层的布局示意图；
图22为在图20中增加导电连接层的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
本公开提供一种显示基板，包括：显示区域和包围所述显示区域的周边区域；所述显示基板还包括：均位于所述周边区域的第一信号线和第二信号线，所述第一信号线在所述显示基板的基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第一间隔区。所述显示基板还包括第一平坦层和第二平坦层，在所述第一间隔区所在的位置，所述第一平坦层和所述第二平坦层均被挖除。
如图7和图8所示，上述显示基板中，在所述第一间隔区所在的位置， 将所述第一平坦层和所述第二平坦层均挖除，导致第一间隔区域所在的位置会形成较深的凹槽，这样后续形成的其他功能膜层，如封装层80等，在跨过凹槽时，由于凹槽处段差过大，容易产生断裂，从而导致环境中的水汽和氧气能够从断裂的位置入侵显示基板内部，影响显示基板的使用寿命，降低显示基板的良率。
请参阅图1至图6，图10，图11和图12，本公开实施例提供了一种显示基板，包括：显示区域10和包围所述显示区域10的周边区域20；所述显示基板还包括：
第一信号线21，所述第一信号线21位于所述周边区域20，所述第一信号线21包括沿第一方向延伸的部分；
第二信号线22，所述第二信号线22位于所述周边区域20，所述第二信号线22包括沿所述第一方向延伸的部分，所述第一信号线21的至少部分位于所述显示区域10和所述第二信号线22之间，所述第一信号线21(包括第一传输部210)在所述显示基板的基底90上的正投影与所述第二信号线22(包括第三传输部220)在所述基底90上的正投影之间具有第一间隔区30；
第一平坦层，所述第一平坦层包括位于所述周边区域20的第一平坦部分40；
第二平坦层50，所述第二平坦层50包括第一过孔51，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区。
示例性的，所述显示基板包括所述显示区域10和所述周边区域20，所述显示区域10包括矩形或其他异性结构。
以所述显示区域10包括矩形为例。所述周边区域20包括靠近所述显示区域10的第一侧的部分，靠近所述显示区域10第二侧的部分，靠近所述显示区域10的第三侧的部分和靠近所述显示区域10的第四侧的部分。所述第一侧和所述第二侧沿所述第一方向相对，所述第三侧和所述第四侧沿第二方向相对。示例性的，所述第一侧包括所述显示区域10的下侧，所述周边区域20靠近所述第一侧的区域内设置有驱动芯片；所述第二侧包括所述显示区域10的上侧；所述第三侧包括所述显示区域10的左侧，所述第四侧包括所述 显示区域10的右侧，所述周边区域20靠近所述第三侧的区域和靠近所述第四侧的区域内设置有栅极驱动电路。
示例性的，所述第一信号线21位于所述周边区域20。示例性的，所述第一信号线21包括靠近所述显示区域10的第一侧的部分，以及靠近所述显示区域10的第二侧的部分。
示例性的，所述第二信号线22位于所述周边区域20。示例性的，所述第二信号线22包括靠近所述显示区域10的第一侧的部分，以及靠近所述显示区域10的第二侧的部分。
示例性的，在靠近所述显示区域10的第一侧，所述第一信号线21的至少部分位于所述显示区域10和所述第二信号线22之间。示例性的，在靠近所述显示区域10的第二侧，所述第一信号线21的至少部分位于所述显示区域10和所述第二信号线22之间。
示例性的，在靠近所述显示区域10的第一侧，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第一间隔区30。示例性的，在靠近所述显示区域10的第二侧，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第一间隔区30。
示例性的，所述显示基板还包括所述第一平坦层，所述第一平坦层包括位于所述周边区域20的第一平坦部分40，所述第一平坦部分40靠近所述显示区域10的第一侧。所述第一平坦部分40从靠近所述显示区域10的位置向远离所述显示区域10的位置延伸。
示例性的，所述第一平坦层还包括第二平坦部分，所述第二平坦部分的至少部分位于所述显示区域10内。
示例性的，所述显示基板包括沿远离所述基底90的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层，第一源漏金属层，第一平坦层，第二源漏金属层，第二平坦层50，阳极层，发光功能层，阴极层，封装层80。示例性的，所述显示基板还包括第一钝化层，所述第一钝化层位于所述第一源漏金属层与所述第一平坦层之间。示例性的，所述显示基板还包括第二钝化层，所述第二钝化层位于 所述第二源漏金属层与所述第二平坦层50之间。
示例性的，所述第二平坦层50包括所述第一过孔51，所述第一过孔51用于放出所述显示基板工艺过程中的水汽。
示例性的，所述第一过孔51在所述基底90上的正投影沿所述第一方向延伸。
示例性的，所述第一过孔51在所述基底90上的正投影的至少部分位于所述第一间隔区30内部。
示例性的，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区；所述第一交叠区和所述第二交叠区均沿所述第一方向延伸。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第一间隔区30；所述第二平坦层50包括第一过孔51，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区。将所述显示基板设置为这种结构，使得所述第一平坦层能够填充在所述第二交叠区，减小所述第二交叠区的段差，从而有利于降低后续形成的其他功能膜层在跨过所述第二交叠区时发生断裂的风险，有效避免了环境中的水汽和氧气在所述第二交叠区入侵到显示基板内部，提升了显示基板的使用寿命和显示基板的良率。
在一些实施例中，设置所述第一交叠区位于所述第一平坦部分40在所述基底90上的正投影的内部。
上述设置方式进一步降低了所述其他功能膜层在跨过所述第二交叠区时发生断裂的风险，有效避免了环境中的水汽和氧气在所述第一交叠区入侵到显示基板内部，提升了显示基板的使用寿命。
如图10所示，在一些实施例中，所述第一平坦部分40在所述基底90上的正投影与所述第一信号线21在所述基底90上的正投影至少部分交叠；
所述第一平坦部分40在所述基底90上的正投影与所述第二信号线22在 所述基底90上的正投影之间具有第二间隔区(如图10中宽度为d的区域)。
如图16，图20和图22所示，示例性的，所述第一平坦部分40上设置有多个第三过孔Via3，在所述第一信号线21包括位于所述第一平坦部分40与所述基底90之间的第一传输图形2101，以及位于所述第一平坦部分40背向所述基底90的一侧的第二传输图形2102时，所述第一传输图形2101在所述基底90上的正投与所述第一平坦部分40在所述基底90上的正投影至少部分交叠，所述第二传输图形2102在所述基底90上的正投影与所述第一平坦部分40在所述基底90上的正投影至少部分交叠，所述第一传输图形2101和所述第二传输图形2102能够通过所述多个第三过孔Via3耦接。示例性的，所述多个第三过孔Via3呈阵列分布。
示例性的，所述第一平坦部分40在所述基底90上的正投影与所述第二信号线22在所述基底90上的正投影不交叠。
上述设置所述第一平坦部分40在所述基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第二间隔区，使得所述第一平坦部分40的边界在所述基底90上的正投影与所述第二信号线22在所述基底90上的正投影不交叠，这样所述第一信号线21不需要爬升所述第一平坦部分40形成的段差。
如图9所示，更详细地说，在所述第二信号线22包括第三传输图形2201和第四传输图形2202的情况下，所述第三传输图形2201位于所述第一平坦层与所述基底90之间，所述第四传输图形2202位于所述第一平坦层背向所述基底90的一侧。如果设置所述第一平坦部分40的边界B0在所述基底90上的正投影与所述第四传输图形2202在所述基底90上的正投影交叠，则所述第四传输图形2202需要跨越所述第一平坦部分40的边界产生的段差，这样在同一次构图工艺中，同时形成所述第四传输图形2202和其他导电图形(也跨越所述段差，且与所述第四传输图形2202传输不同的信号，如第七传输图形2310)时，在所述第一平坦部分40的边界处(如X6部分)容易残留用于制作所述第四传输图形2202和其他导电图形的导电材料，从而容易出现所述第四传输图形2202与所述其他导电图形之间短路的情况。
需要说明，图9中示意了在第一平坦层上形成的过孔Via1和Via2.
而上述实施例提供的显示基板中，所述第一信号线21不需要爬升所述第一平坦部分40形成的段差，从而很好的避免了所述第一信号线21与所述其他导电图形之间发生短路。
如图10所示，在一些实施例中，设置所述第二间隔区在垂直于所述第一方向上的宽度d满足：8μm≤d≤12μm。
上述设置方式在避免所述第一信号线21与所述其他导电图形之间发生短路的同时，还降低了所述其他功能膜层在跨过所述第二交叠区时发生断裂的风险。
如图5，图6，图12，图19，图21和图22所示，在一些实施例中，所述显示基板还包括：
阴极层，所述阴极层的至少部分位于所述显示区域10；
导电连接层60，所述导电连接层60从所述显示区域10延伸至所述周边区域20，所述导电连接层60分别与所述阴极层和所述第二信号线22耦接；所述导电连接层60在所述基底90上的正投影与所述第二交叠区至少部分交叠。
示例性的，所述阴极层能够从所述显示区域10延伸至所述周边区域20。
示例性的，所述导电连接层60位于所述第二平坦层50背向所述基底90的一侧。
示例性的，所述导电连接层60在所述基底90上的正投影与所述阴极层在所述基底90上的正投影至少部分交叠，所述导电连接层60在所述基底90上的正投影与所述第二信号线22在所述基底90上的正投影至少部分交叠。
示例性的，所述导电连接层60包括第一导电连接图形601，第二导电连接图形602和多个第三导电连接图形603。所述多个第三导电连接图形603沿所述第一方向排列，每个所述第三导电连接图形603分别与所述第一导电连接图形601和所述第二导电连接图形602耦接。示例性的，所述第一导电连接图形601，所述第二导电连接图形602和所述多个第三导电连接图形603形成为一体结构。
示例性的，所述第一导电连接图形601在所述基底90上的正投影与所述阴极层在所述基底90上的正投影至少部分交叠，所述第一导电连接图形601 在交叠处与所述阴极层耦接。所述第二导电连接图形602在所述基底90上的正投影与所述第二信号线22在所述基底90上的正投影至少部分交叠，所述第二导电连接图形602在交叠处与所述第二信号线22耦接。所述第三导电连接图形603在所述基底90上的正投影与所述第二交叠区至少部分交叠。
上述实施例提供的显示基板中，由于所述第二交叠区的段差被有效减小，使得所述导电连接层60在跨越所述第二交叠区时不容易发生断裂，有效避免了环境中的水汽和氧气在所述第二交叠区入侵到显示基板内部，提升了显示基板的使用寿命。
如图6和图18所示，在一些实施例中，所述第二平坦层50还包括阵列分布的多个第二过孔52，所述导电连接层60通过所述多个第二过孔52与所述第二信号线22耦接。
示例性的，所述多个第二过孔52在所述基底90上的正投影位于所述第二信号线22在所述基底90上的正投影的内部。
在一些实施例中，设置所述显示基板还包括阳极层，所述导电连接层60与所述阳极层同层同材料设置。
上述将所述导电连接层60与所述阳极层同层同材料设置，使得所述导电连接层60与所述阳极层能够在同一次构图工艺中同时形成，从而有效简化了显示基板的制作流程，降低了显示基板的制作成本。
在一些实施例中，所述显示基板还包括封装层80，所述封装层80的至少部分位于所述阴极层背向所述基底90的一侧，所述封装层80覆盖所述第二交叠区。
上述实施例提供的显示基板中，由于所述第二交叠区的段差被有效减小，使得所述封装层80在跨越所述第二交叠区时不容易发生断裂，有效避免了环境中的水汽和氧气在所述第二交叠区入侵到显示基板内部，提升了显示基板的使用寿命。
如图4所示，在一些实施例中，所述显示基板还包括：
多条扇出线70，所述多条扇出线70位于所述周边区域20，至少部分所述扇出线70在所述基底90上的正投影与所述第二交叠区交叠。
示例性的，所述显示基板还包括多条数据线，所述扇出线70分别与对应 的数据线和驱动芯片耦接。
如图13和图14所示，示例性的，所述多条扇出线70包括多条第一扇出线701和多条第二扇出线702。所述第一扇出线701采用第一栅金属层制作，所述多条第二扇出线702采用第二栅金属层制作。
上述设置至少部分所述扇出线70在所述基底90上的正投影与所述第二交叠区交叠，使得位于所述第二交叠区的第一平坦部分40能够将由所述扇出线70引起的凹凸不平平坦化，避免由所述扇出线70引起的凹凸不平导致上层膜层产生裂痕。
如图3至图6所示，在一些实施例中，所述第一信号线21包括相耦接的第一传输部210和第二传输部211，所述第一传输部210沿所述第一方向延伸，所述第二传输部211的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
所述第二信号线22包括相耦接的第三传输部220和第四传输部221，所述第三传输部220沿所述第一方向延伸，所述第四传输部221的至少部分沿所述第二方向延伸，所述第四传输部221与所述第二传输部211沿所述第一方向排列，所述第一传输部210在所述基底90上的正投影与所述第三传输部220在所述基底90上的正投影之间具有所述第一间隔区30。
示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
示例性的，所述第一信号线21包括所述第一传输部210和所述第二传输部211，所述第二传输部211分别与所述第一传输部210和驱动芯片耦接。
示例性的，所述第二信号线22包括所述第三传输部220和所述第四传输部221，所述第四传输部221分别与所述第三传输部220和驱动芯片耦接。
示例性的，所述第一传输部210在所述基底90上的正投影，位于所述第三传输部220在所述基底90上的正投影与所述显示区域10之间，所述第一传输部210在所述基底90上的正投影与所述第三传输部220在所述基底90上的正投影之间具有所述第一间隔区30。
示例性的，所述第四传输部221在所述基底90上的正投影与所述第二传输部211在所述基底90上的正投影沿所述第一方向间隔排列。
如图6，图15和图17所示，在一些实施例中，所述第一传输部210包 括相耦接的第一传输图形2101和第二传输图形2102，所述第一传输图形2101位于所述基底90和所述第二传输图形2102之间；
所述第三传输部220包括相耦接的第三传输图形2201和第四传输图形2202，所述第三传输图形2201位于所述基底90与所述第四传输图形2202之间，所述第二传输图形2102在所述基底90上的正投影与所述第四传输图形2202在所述基底90上的正投影之间具有所述第一间隔区30。
示例性的，所述第一传输图形2101和所述第二传输图形2102均沿所述第一方向延伸。所述第三传输图形2201和所述第四传输图形2202均沿所述第一方向延伸。
示例性的，所述第一传输图形2101与所述第二传输图形2102之间具有所述第一平坦部分40。所述第三传输图形2201与所述第四传输图形2202之间没有绝缘层，所述第三传输图形2201与所述第四传输图形2202能够整面搭接在一起。
示例性的，所述第二传输图形2102在所述基底90上的正投影与所述第四传输图形2202在所述基底90上的正投影之间具有所述第一间隔区30，所述第一传输图形2101在所述基底90上的正投影与所述第三传输图形2201在所述基底90上的正投影之间具有所述第三间隔区，在垂直于所述第一方向的方向上，所述第三间隔区的宽度大于所述第一间隔区30的宽度。
在一些实施例中，所述显示基板还包括第一源漏金属层和第二源漏金属层，所述第一源漏金属层位于所述基底90与所述第二源漏金属层之间；
所述第一传输图形2101和所述第三传输图形2201与所述第一源漏金属层同层同材料设置；所述第二传输图形2102和所述第四传输图形2202与所述第二源漏金属层同层同材料设置。
上述设置方式使得所述第一传输图形2101和所述第三传输图形2201能够与所述第一源漏金属层在同一次构图工艺中形成，使得所述第二传输图形2102和所述第四传输图形2202能够与所述第二源漏金属层在同一次构图工艺中形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
在一些实施例中，设置所述第二传输部211包括层叠设置的第五传输图 形和第六传输图形2110，所述第五传输图形与所述第一传输图形2101形成为一体结构，所述第六传输图形2110与所述第二传输图形2102形成为一体结构。
示例性的，所述第五传输图形和所述第六传输图形2110耦接。
示例性的，所述第五传输图形的至少部分沿所述第二方向延伸，所述第六传输图形2110的至少部分沿所述第二方向延伸。
上述设置方式有利于提升所述第一信号线21的信赖性。
如图11和图15所示，在一些实施例中，设置所述第二传输部211包括层叠设置的第五传输图形和第六传输图形2110，所述第五传输图形与所述第一传输图形2101形成为一体结构，所述第六传输图形2110与所述第二传输图形2102之间具有第四间隔区34，所述第四间隔区34在所述基底90上的正投影，与所述第一平坦部分40朝向所述第三传输部220的第一边界B1在所述基底90上的正投影至少部分交叠。
示例性的，所述第六传输图形2110与所述第二传输图形2102能够通过所述第五传输图形和所述第一传输图形2101实现电连接。
上述设置方式不仅有利于提升所述第一信号线21的信赖性，而且能够避免所述第六传输图形2110与所述第二传输图形2102跨越所述第一边界B1，从而避免所述第二信号线22与第三信号线23之间由于制作材料在第一边界B1残留而发生短路灼伤问题。
在一些实施例中，所述第四传输部221包括层叠设置的第九传输图形和第十传输图形，所述第九传输图形位于所述第十传输图形与所述基底90之间。
示例性的，所述第九传输图形与所述第三传输图形2201形成为一体结构，所述第十传输图形与所述第四传输图形2202形成为一体结构。
上述设置方式有利于提升所述第二信号线22的信赖性。
如图4，图10,和图11所示，在一些实施例中，所述显示基板还包括：
第三信号线23，所述第三信号线23位于所述周边区域20；所述第三信号线23包括相耦接的第五传输部230和第六传输部231，所述第五传输部230沿所述第一方向延伸，所述第六传输部231的至少部分沿所述第二方向延伸； 所述第六传输部231与所述第二传输部211沿所述第一方向排列；
所述第一平坦部分40朝向所述第三传输部220的第一边界B1在所述基底90上的正投影，分别与所述第二传输部211在所述基底90上的正投影和所述第六传输部231在所述基底90上的正投影交叠。
示例性的，所述第三信号线23包括两个第五传输部230和多个第六传输部231，所述两个第五传输部230中的一个位于靠近所述显示区域10第一侧的位置，所述两个第五传输部230中的另一个位于靠近所述显示区域10第二侧的位置。所述多个第六传输部231分别与靠近所述第一侧的第五传输部230耦接。所述第六传输部231还与驱动芯片耦接。
示例性的，所述显示基板还包括初始化信号层，所述初始化信号层的至少部分位于所述显示区域10，所述初始化信号层分别与所述两个第五传输部230耦接。
示例性的，在靠近所述显示区域10的同一侧，所述第五传输部230，所述第一传输部210和所述第三传输部220沿远离所述显示区域10的方向依次间隔排列。
示例性的，所述第六传输部231，所述第二传输部211和所述第四传输部221沿所述第一方向间隔排列。
示例性的，所述第一平坦部分40朝向所述第三传输部220的第一边界B1在所述基底90上的正投影，与所述第三传输部220在所述基底90上的正投影，以及所述第四传输部221在所述基底90上的正投影均不交叠。
上述实施例提供的显示基板中，通过设置所述第一平坦部分40朝向所述第三传输部220的第一边界B1在所述基底90上的正投影，与所述第三传输部220在所述基底90上的正投影，以及所述第四传输部221在所述基底90上的正投影均不交叠；设置所述第一平坦部分40朝向所述第三传输部220的第一边界B1在所述基底90上的正投影，分别与所述第二传输部211在所述基底90上的正投影和所述第六传输部231在所述基底90上的正投影交叠；避免了所述第二传输部211分中和所述第二信号线22中同层设置，且均爬升所述第一边界B1产生的段差的部分发生短路，避免了所述第六传输部231分中和所述第二信号线22中同层设置，且均爬升所述第一边界B1产生的段 差的部分发生短路。
在一些实施例中，所述第六传输部231包括第七传输图形2310，所述第七传输图形2310与所述第二传输图形2102异层设置。
上述将所述第七传输图形2310与所述第二传输图形2102异层设置，避免了所述第七传输图形2310与所述第二传输图形2102在同一次构图工艺中制作，这样即使所述第二传输图形2102和所述第七传输图形2310均爬升所述第一边界B1产生的段差，所述第二传输图形2102与所述第七传输图形2310之间也不会发生短路，避免了显示基板中出现由于不同信号线之间的短路而引发的灼伤问题。
在一些实施例中，所述第六传输部231包括第八传输图形，所述第八传输图形与所述第七传输图形2310耦接，所述第八传输图形与所述第一传输图形2101同层同材料设置。
示例性的，所述第八传输图形位于所述第七传输图形2310与所述基底90之间，所述第八传输图形在所述基底90上的正投影与所述第七传输图形2310在所述基底90上的正投影至少部分交叠。
上述将所述第八传输图形与所述第一传输图形2101同层同材料设置，使得所述第八传输图形与所述第一传输图形2101能够在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
在一些实施例中，所述第一信号线21包括正电源线，所述第二信号线22包括负电源线，所述第三信号线23包括初始化信号线。
需要说明，上述实施例提供的显示基板中，在布局空间和像素尺寸满足需求时，也可以采用单层的源漏金属层和单层的阳极层。无法满足需求时可以采用双层的源漏金属层和双层的阳极层。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第一间隔区30；所述第二平坦层50包括第一过孔51，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部 分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区。将上述显示基板设置为这种结构，使得所述第一平坦层能够填充在所述第二交叠区，减小所述第二交叠区的段差，从而有利于降低后续形成的其他功能膜层在跨过所述第二交叠区时发生断裂的风险，有效避免了环境中的水汽和氧气在所述第二交叠区入侵到显示基板内部，提升了显示基板的使用寿命和显示基板的良率。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，所述显示装置还包括柔性电路板、印刷电路板和背板等。
本公开实施例还提供了一种显示基板的制作方法，所述制作方法用于制作上述实施例提供的显示基板，所述显示基板包括：显示区域10和包围所述显示区域10的周边区域20；所述制作方法包括：
制作第一信号线21，所述第一信号线21位于所述周边区域20，所述第一信号线21包括沿第一方向延伸的部分；
制作第二信号线22，所述第二信号线22位于所述周边区域20，所述第二信号线22包括沿所述第一方向延伸的部分，所述第一信号线21的至少部分位于所述显示区域10和所述第二信号线22之间，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90上的正投影之间具有第一间隔区30；
制作第一平坦层，所述第一平坦层包括位于所述周边区域20的第一平坦部分40；
制作第二平坦层50，所述第二平坦层50包括第一过孔51，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区。
采用本公开实施例提供的制作方法制作的显示基板中，所述第一信号线21在所述显示基板的基底90上的正投影与所述第二信号线22在所述基底90 上的正投影之间具有第一间隔区30；所述第二平坦层50包括第一过孔51，所述第一过孔51在所述基底90上的正投影与所述第一间隔区30具有第一交叠区；所述第一平坦部分40在所述基底90上的正投影与所述第一交叠区具有第二交叠区。将上述显示基板制作成这种结构，使得所述第一平坦层能够填充在所述第二交叠区，减小所述第二交叠区的段差，从而有利于降低后续形成的其他功能膜层在跨过所述第二交叠区时发生断裂的风险，有效避免了环境中的水汽和氧气在所述第二交叠区入侵到显示基板内部，提升了显示基板的使用寿命和显示基板的良率。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝 对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示基板，包括：显示区域和包围所述显示区域的周边区域；所述显示基板还包括：
    第一信号线，所述第一信号线位于所述周边区域，所述第一信号线包括沿第一方向延伸的部分；
    第二信号线，所述第二信号线位于所述周边区域，所述第二信号线包括沿所述第一方向延伸的部分，所述第一信号线的至少部分位于所述显示区域和所述第二信号线之间，所述第一信号线在所述显示基板的基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第一间隔区；
    第一平坦层，所述第一平坦层包括位于所述周边区域的第一平坦部分；
    第二平坦层，所述第二平坦层包括第一过孔，所述第一过孔在所述基底上的正投影与所述第一间隔区具有第一交叠区；所述第一平坦部分在所述基底上的正投影与所述第一交叠区具有第二交叠区。
  2. 根据权利要求1所述的显示基板，其中，所述第一交叠区位于所述第一平坦部分在所述基底上的正投影的内部。
  3. 根据权利要求1所述的显示基板，其中，所述第一平坦部分在所述基底上的正投影与所述第一信号线在所述基底上的正投影至少部分交叠；
    所述第一平坦部分在所述基底上的正投影与所述第二信号线在所述基底上的正投影之间具有第二间隔区。
  4. 根据权利要求3所述的显示基板，其中，所述第二间隔区在垂直于所述第一方向上的宽度d满足：8μm≤d≤12μm。
  5. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    阴极层，所述阴极层的至少部分位于所述显示区域；
    导电连接层，所述导电连接层从所述显示区域延伸至所述周边区域，所述导电连接层分别与所述阴极层和所述第二信号线耦接；所述导电连接层在所述基底上的正投影与所述第二交叠区至少部分交叠。
  6. 根据权利要求5所述的显示基板，其中，所述第二平坦层还包括阵列分布的多个第二过孔，所述导电连接层通过所述多个第二过孔与所述第二信 号线耦接。
  7. 根据权利要求5所述的显示基板，其中，所述显示基板还包括阳极层，所述导电连接层与所述阳极层同层同材料设置。
  8. 根据权利要求5所述的显示基板，其中，所述显示基板还包括封装层，所述封装层的至少部分位于所述阴极层背向所述基底的一侧，所述封装层覆盖所述第二交叠区。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    多条扇出线，所述多条扇出线位于所述周边区域，至少部分所述扇出线在所述基底上的正投影与所述第二交叠区交叠。
  10. 根据权利要求1所述的显示基板，其中，所述第一信号线包括相耦接的第一传输部和第二传输部，所述第一传输部沿所述第一方向延伸，所述第二传输部的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    所述第二信号线包括相耦接的第三传输部和第四传输部，所述第三传输部沿所述第一方向延伸，所述第四传输部的至少部分沿所述第二方向延伸，所述第四传输部与所述第二传输部沿所述第一方向排列，所述第一传输部在所述基底上的正投影与所述第三传输部在所述基底上的正投影之间具有所述第一间隔区。
  11. 根据权利要求10所述的显示基板，其中，所述第一传输部包括相耦接的第一传输图形和第二传输图形，所述第一传输图形位于所述基底和所述第二传输图形之间；
    所述第三传输部包括相耦接的第三传输图形和第四传输图形，所述第三传输图形位于所述基底与所述第四传输图形之间，所述第二传输图形在所述基底上的正投影与所述第四传输图形在所述基底上的正投影之间具有所述第一间隔区。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括第一源漏金属层和第二源漏金属层，所述第一源漏金属层位于所述基底与所述第二源漏金属层之间；
    所述第一传输图形和所述第三传输图形与所述第一源漏金属层同层同材料设置；所述第二传输图形和所述第四传输图形与所述第二源漏金属层同层 同材料设置。
  13. 根据权利要求12所述的显示基板，其中，所述第二传输部包括层叠设置的第五传输图形和第六传输图形，所述第五传输图形与所述第一传输图形形成为一体结构，所述第六传输图形与所述第二传输图形之间具有第四间隔区，所述第四间隔区在所述基底上的正投影，与所述第一平坦部分朝向所述第三传输部的第一边界在所述基底上的正投影至少部分交叠。
  14. 根据权利要求12所述的显示基板，其中，所述显示基板还包括：
    第三信号线，所述第三信号线位于所述周边区域；所述第三信号线包括相耦接的第五传输部和第六传输部，所述第五传输部沿所述第一方向延伸，所述第六传输部的至少部分沿所述第二方向延伸；所述第六传输部与所述第二传输部沿所述第一方向排列；
    所述第一平坦部分朝向所述第三传输部的第一边界在所述基底上的正投影，分别与所述第二传输部在所述基底上的正投影和所述第六传输部在所述基底上的正投影交叠。
  15. 根据权利要求14所述的显示基板，其中，所述第六传输部包括第七传输图形，所述第七传输图形与所述第二传输图形异层设置。
  16. 根据权利要求15所述的显示基板，其中，所述第六传输部包括第八传输图形，所述第八传输图形与所述第七传输图形耦接，所述第八传输图形与所述第一传输图形同层同材料设置。
  17. 根据权利要求14所述的显示基板，其中，所述第一信号线包括正电源线，所述第二信号线包括负电源线，所述第三信号线包括初始化信号线。
  18. 一种显示装置，包括如权利要求1～17中任一项所述的显示基板。
  19. 一种显示基板的制作方法，所述显示基板包括：显示区域和包围所述显示区域的周边区域；所述制作方法包括：
    制作第一信号线，所述第一信号线位于所述周边区域，所述第一信号线包括沿第一方向延伸的部分；
    制作第二信号线，所述第二信号线位于所述周边区域，所述第二信号线包括沿所述第一方向延伸的部分，所述第一信号线的至少部分位于所述显示区域和所述第二信号线之间，所述第一信号线在所述显示基板的基底上的正 投影与所述第二信号线在所述基底上的正投影之间具有第一间隔区；
    制作第一平坦层，所述第一平坦层包括位于所述周边区域的第一平坦部分；
    制作第二平坦层，所述第二平坦层包括第一过孔，所述第一过孔在所述基底上的正投影与所述第一间隔区具有第一交叠区；所述第一平坦部分在所述基底上的正投影与所述第一交叠区具有第二交叠区。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111430421A (zh) * 2020-04-02 2020-07-17 京东方科技集团股份有限公司 显示装置及其制造方法
JP2020177933A (ja) * 2020-08-06 2020-10-29 セイコーエプソン株式会社 発光装置、および電子機器
CN111880344A (zh) * 2020-07-30 2020-11-03 厦门天马微电子有限公司 一种显示面板及其制备方法、显示装置
US20210135153A1 (en) * 2019-03-11 2021-05-06 Boe Technology Group Co., Ltd. Display substrate, display apparatus, method of fabricating display substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210135153A1 (en) * 2019-03-11 2021-05-06 Boe Technology Group Co., Ltd. Display substrate, display apparatus, method of fabricating display substrate
CN111430421A (zh) * 2020-04-02 2020-07-17 京东方科技集团股份有限公司 显示装置及其制造方法
CN111880344A (zh) * 2020-07-30 2020-11-03 厦门天马微电子有限公司 一种显示面板及其制备方法、显示装置
JP2020177933A (ja) * 2020-08-06 2020-10-29 セイコーエプソン株式会社 発光装置、および電子機器

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