WO2023040360A1 - 显示面板 - Google Patents
显示面板 Download PDFInfo
- Publication number
- WO2023040360A1 WO2023040360A1 PCT/CN2022/096679 CN2022096679W WO2023040360A1 WO 2023040360 A1 WO2023040360 A1 WO 2023040360A1 CN 2022096679 W CN2022096679 W CN 2022096679W WO 2023040360 A1 WO2023040360 A1 WO 2023040360A1
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- WIPO (PCT)
- Prior art keywords
- layer
- crack
- area
- display panel
- protection layer
- Prior art date
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Classifications
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Definitions
- the present disclosure relates to the technical field of display devices, in particular to a display panel.
- a display panel comprising:
- the opening area is provided with openings
- a first crack prevention zone at least partially surrounding the opening zone
- the display panel further includes in the first anti-crack area: a base substrate, an encapsulation layer on the base substrate, at least one ring of anti-crack protection layer on the encapsulation layer; and
- the display area includes at least one touch electrode layer
- the anti-crack protection layer and at least one layer of the at least one touch electrode layer are provided in the same layer and the same material.
- the anti-crack protection layer includes at least one layer of metal
- the touch electrode layer includes a touch metal layer.
- the base substrate and the encapsulation layer extend to the display area; the touch metal layer is located on a side of the encapsulation layer away from the base substrate.
- the at least one touch electrode layer includes a first touch metal layer closer to the encapsulation layer, a second touch metal layer and An insulating layer between the touch control metal layers, the anti-crack protection layer and the first touch control metal layer are set in the same layer and the same material;
- the anti-crack protection layer and the second touch metal layer are provided in the same layer and the same material.
- the first touch metal layer is an electrode pattern layer
- the second touch metal layer is a bridging layer
- the bridging layer communicates with at least part of the electrodes through a via hole penetrating through the touch medium layer.
- the pattern layer realizes electrical connection.
- the anti-crack protection layer includes a first anti-crack protection layer and a second anti-crack protection layer that are laminated, and the first anti-crack protection layer is arranged between the second anti-crack protection layer and the liner. between the base substrates; and
- the first anti-crack protection layer and the first touch metal layer are set on the same layer and the same material
- the second anti-crack protection layer and the second touch metal layer are provided in the same layer and the same material.
- the anti-crack protection layer includes a single-layer or laminated structure of metal or metal oxide.
- the metal includes at least one of the following: copper, molybdenum, titanium-aluminum-titanium; the metal oxide includes: indium tin oxide.
- At least one first anti-crack dam is arranged between the base substrate and the packaging layer; the first anti-crack dam and the anti-crack protective layer are distributed on both sides of the packaging layer .
- the first anti-crack dam and the anti-crack protection layer are stacked on both sides of the encapsulation layer, and the orthographic projection of the anti-crack protection layer on the base substrate at least partially covers the Orthographic projection of the first anti-crack dam on the base substrate.
- the first anti-crack dam and the anti-crack protection layer are disposed on both sides of the encapsulation layer in dislocation, and the orthographic projection of the anti-crack protection layer on the base substrate is located at two adjacent Between the orthographic projections of the first anti-crack dam on the base substrate.
- the display panel further includes: a flow stop area surrounding the first anti-crack area;
- the base substrate and the encapsulation layer extend to the flow-stopping area, and a flow-stop dam is further arranged between the encapsulation layer and the base substrate in the flow-stopping area.
- the display panel further includes: a second anti-crack area surrounding the flow-stopping area; the display panel further includes in the second anti-crack area: a base substrate located between the base substrate A second anti-crack dam is provided between the encapsulation layer on the top, the encapsulation layer located in the second anti-crack area, and the base substrate.
- the anti-crack protection layer there is at least a partial overlap region between the anti-crack protection layer and the orthographic projection of the first anti-crack dam and/or the second anti-crack dam on the base substrate.
- the area where the encapsulation layer contacts the at least one circle of the first anti-crack dam and/or the area of at least one circle of the second anti-crack dam includes at least one concave structure, and the anti-crack protection layer covers at least the sunken structure.
- At least one opening is provided on the display panel
- the shape of the opening includes one of the following: circle, strip and racetrack.
- another display panel comprising:
- the opening area is provided with openings
- a first crack prevention zone at least partially surrounding the opening zone
- the display panel further includes: a base substrate, an encapsulation layer on the base substrate, at least one circle of anti-crack protection layer on the encapsulation layer, and an anti-crack protection layer on the At least one circle of anti-crack dams under the encapsulation layer; the area where the encapsulation layer contacts the at least one circle of anti-crack dams includes at least one recessed structure, and the anti-crack protection layer at least covers the recessed structure.
- the first anti-crack dam and the anti-crack protection layer are stacked on both sides of the encapsulation layer, and the orthographic projection of the anti-crack protection layer on the base substrate at least partially covers the Orthographic projection of the first anti-crack dam on the base substrate.
- the first anti-crack dam and the anti-crack protection layer are disposed on both sides of the encapsulation layer in dislocation, and the orthographic projection of the anti-crack protection layer on the base substrate is located at two adjacent Between the orthographic projections of the first anti-crack dam on the base substrate.
- the first anti-crack dam includes at least one anti-crack structure, so that the encapsulation layer includes a concave structure, and the concave structure includes at least one step perpendicular to the direction of the substrate, and the anti-crack protection A layer at least partially covers the step.
- the concave structure includes at least two first surfaces and a second surface located between the two first surfaces, and two vertical surfaces connecting the first surfaces and the second surfaces There is a step in the direction of the base substrate, and the anti-crack protection layer completely covers the recessed structure.
- the anti-crack protection layer includes a first anti-crack protection layer and a second anti-crack protection layer that are laminated, and the first anti-crack protection layer is arranged between the second anti-crack protection layer and the liner. between the base substrates; and
- the first anti-crack protection layer at least partially covers the concave structure, and/or, the second anti-crack protection layer at least partially covers the concave structure.
- the display area includes at least one touch electrode layer
- the anti-crack protection layer and at least one layer of the at least one touch electrode layer are provided in the same layer and the same material.
- the at least one touch electrode layer includes a first touch metal layer closer to the base substrate, a second touch metal layer and a layer located between the first touch metal layer and the second
- the touch medium layer between the touch metal layers, the anti-crack protection layer and the first touch metal layer are set in the same layer and the same material;
- the anti-crack protection layer and the second touch metal layer are provided in the same layer and the same material.
- FIG. 1 shows an overall schematic diagram of a display panel provided by an embodiment of the present disclosure
- Fig. 2 shows a schematic cross-sectional view of a base substrate of a display panel provided by an embodiment of the present disclosure
- FIG. 3 shows a schematic cross-sectional view of a display panel in the C-D direction provided by an embodiment of the present disclosure
- FIG. 4 shows an overall schematic diagram of a display panel with strip-shaped openings provided by an embodiment of the present disclosure
- FIG. 5 shows an overall schematic diagram of a display panel with two openings provided by an embodiment of the present disclosure
- Fig. 6 shows a schematic diagram of crack blocking provided by an embodiment of the present disclosure
- FIG. 7 shows a schematic cross-sectional view of a touch electrode layer provided by an embodiment of the present disclosure
- Fig. 8 shows a schematic diagram of the distribution of a first mode of an anti-crack protection layer provided by an embodiment of the present disclosure
- Fig. 9 shows a schematic plan view of the distribution of a first mode of an anti-crack protection layer provided by an embodiment of the present disclosure
- Fig. 10 shows a schematic diagram of the distribution of a second mode of an anti-crack protective layer provided by an embodiment of the present disclosure
- Fig. 11 shows a schematic plan view of the distribution of the second mode of an anti-crack protective layer provided by an embodiment of the present disclosure
- FIG. 12 shows a schematic plan view of a touch electrode wiring provided by an embodiment of the present disclosure
- Fig. 13 shows an overall schematic diagram of a display panel with an integral anti-crack protection layer provided by an embodiment of the present disclosure
- Fig. 14 shows an overall schematic diagram of a display panel provided by an embodiment of the present disclosure with a multi-circle anti-crack protection layer
- Fig. 15 shows a schematic cross-sectional view of a display panel in the A-B direction provided by an embodiment of the present disclosure
- FIG. 16 shows a schematic cross-sectional view of another display panel in the A-B direction provided by an embodiment of the present disclosure
- FIG. 17 shows a schematic cross-sectional view of another display panel in the A-B direction provided by an embodiment of the present disclosure
- FIG. 18 shows a flow chart of the steps of a method for manufacturing a display panel provided by an embodiment of the present disclosure
- Fig. 19 shows a schematic diagram of forming a first anti-crack protective layer provided by an embodiment of the present disclosure
- FIG. 20 shows a schematic diagram of forming a touch insulating layer provided by an embodiment of the present disclosure
- Fig. 21 shows a schematic structural diagram of an encapsulation layer with a recessed structure provided by an embodiment of the present disclosure
- Fig. 22 shows a schematic diagram of a recessed structure in which an anti-crack protection layer covers an encapsulation layer according to an embodiment of the present disclosure
- Fig. 23 shows a schematic diagram of a recessed structure in which the anti-crack protection layer is distributed in the first manner and covers the encapsulation layer provided by an embodiment of the present disclosure
- FIG. 24 shows a schematic plan view of a concave structure in which a crack-proof protective layer is distributed in a first manner and covers the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 25 shows a schematic diagram of a recessed structure in which the anti-crack protection layer is distributed in a second manner and covers the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 26 shows a schematic plan view of a concave structure in which the anti-crack protection layer is distributed in a second manner and covers the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 27 shows a schematic diagram of a recessed structure in which a multi-layer anti-crack protection layer covers an encapsulation layer according to an embodiment of the present disclosure
- Fig. 28 shows a schematic plan view of a recessed structure in which a multi-layer anti-crack protection layer covers the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 29 shows a schematic diagram of another multi-layer anti-crack protection layer covering the recessed structure of the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 30 shows a schematic plan view of another recessed structure in which a multi-layer anti-crack protection layer covers an encapsulation layer according to an embodiment of the present disclosure
- Fig. 31 shows a schematic diagram of another multi-layer anti-crack protection layer covering the recessed structure of the encapsulation layer provided by an embodiment of the present disclosure
- Fig. 32 shows a schematic plan view of another multi-layer anti-crack protection layer covering the recessed structure of the encapsulation layer provided by an embodiment of the present disclosure
- FIG. 33 shows an equivalent circuit diagram of a pixel circuit in a display area of a display panel provided by an embodiment of the present disclosure
- 34-38 show the layout design of each layer of the pixel circuit in the display area of a display panel provided by an embodiment of the present disclosure
- FIG. 39 shows a layout design of a conductive layer of a pixel circuit in a display area of a display panel provided by an embodiment of the present disclosure
- FIG. 40 shows another layout design of the second conductive layer of the pixel circuit in the display area of a display panel provided by an embodiment of the present disclosure
- Fig. 41 shows another layout design of the third conductive layer of the pixel circuit in the display area of a display panel provided by an embodiment of the present disclosure
- FIG. 42 shows another layout design of the fourth conductive layer of the pixel circuit in the display area of a display panel provided by an embodiment of the present disclosure.
- the Flexible Multi-Layer On Cell (FMLOC) technology can make the touch signal layer directly on the display layer and the packaging layer, so as to This is the current development trend of Organic Light-Emitting Diode (OLED) display to obtain a thinner screen backplane thickness and narrower lower frame, and to save the manufacturing cost of the display panel.
- FMLOC Flexible Multi-Layer On Cell
- the display panel proposed in the related technology of the hole-digging screen in the display area although the film layer structure of the hole-digging area in the display area has been optimized, to a certain extent, it weakens the cracking of the inorganic packaging layer at the edge of the opening in the display area.
- the spread of the area so as to prevent the display layer and the touch layer of the display/touch area around the display panel digging hole from cracking, and ensure the display effect and touch effect of the display panel.
- the display panel structure proposed in the related art uses the metal signal lines related to the display layer as the anti-crack device, the effect of anti-cracking in the hole-digging area is limited. That is to say, the current display screen realizes Dig holes in the area, and to a certain extent, realize the anti-cracking of the cutting edge, but the anti-cracking ability of the excavated area still needs to be improved.
- This disclosure considers the preparation and implementation process and structural position of the touch signal layer in the touch display integration technology, and proposes to use the related structure of the touch layer as a crack prevention device for the hole-digging area to improve the cracks at the edge of the hole-digging area of the display panel. blocking ability.
- the present disclosure proposes a display panel, a method for preparing a display panel, and a display device.
- the first anti-crack area around the cutout area in the display area of the display panel is set in contact with the display area.
- the touch anti-cracking layer made of metal in the same layer as the control metal layer conducts and disperses the stress of the cracks on the edge of the opening, which can improve the performance of the display panel with holes in the display area without changing the existing overall manufacturing process.
- the crack resistance of the area around the excavated hole is shown.
- FIG. 1 is an overall schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 1 , the overall structure of the display panel is based on the base substrate 11 , on which the display panel can be roughly divided into a display area 70 , a frame area 80 , and a signal connection area 90 .
- the base substrate 11 may be a flexible substrate or a rigid substrate.
- the display panel can be bent or bent; when the base substrate 11 is a rigid substrate, it can meet the rigidity requirements of the display panel; the performance of the specific base substrate 11 depends on the product to determine actual needs.
- the base substrate may include a single-layer structure or a multi-layer structure.
- the base substrate may include polyimide layers and buffer layers stacked in sequence; in other embodiments, the base substrate may also include a plurality of polyimide layers stacked in sequence. imine layer and buffer layer.
- the buffer layer can be made of materials such as silicon nitride or silicon oxide, so as to achieve the effect of blocking water and oxygen and blocking alkaline ions. It should be noted that the structure of the base substrate is not limited thereto, and may be determined according to actual requirements in specific applications.
- the opening area 20 exists in the display area 70 of the display panel, that is, in the display panel, the display area 70 at least partially surrounds the opening area 20 .
- the opening area 20 may be completely located within the range where the display area 70 is located.
- the surrounding area 20 is surrounded by the display area 70; the opening area 20 may also be partially located within the range where the display area 70 is located.
- the time display area 70 partially surrounds the opening area 20 .
- an anti-crack protective layer 41 is provided around the opening surrounding the opening area 20 .
- FIG. 3 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
- the display panel includes: an opening area 20 , a cutting remaining area 30 , and a first anti-crack area 40 .
- each area may be defined on the base substrate first.
- the display area 70, the frame area 80, the signal connection area 90, the opening area 20, the cutting remaining area 30, and the first anti-crack area 40 can be divided on the base substrate first, that is, the display panel is divided into The display area 70 , the border area 80 , the signal connection area 90 , the opening area 20 , the cutting remaining area 30 and the first anti-crack area 40 .
- the opening area 20 is provided with openings 21 .
- the opening 21 may be a via hole penetrating the encapsulation layer 12 and the base substrate 11 , that is, a through hole; the opening 21 may also be a concave hole not penetrating the display panel.
- the remaining cutting area 30 is a circle area surrounding the opening area 20 .
- the remaining cutting area 30 may be a circle remaining after cutting a circle of cutting areas around the opening area 20 during the process of obtaining the display panel including the opening area 20 .
- the hole area 20 is the hole-digging area in the display area 70 of the display panel, and the hollow space therein can be used for placing cameras and various sensors.
- the first anti-crack area 40 at least partially surrounds the opening area 20 .
- the first anti-crack area 40 is a circle area arranged between the display area 70 and the opening area 20; In the case of a part located in the area where the display area 70 is located, the first anti-crack area 40 is an incomplete area between the opening area 20 and the display area 70 .
- the edge of the opening 21 is the cutting edge of the hole dug in the display area 70 of the display panel. It is also the edge of the cutting residual area 30 .
- the opening area 20 can be a circular hole area
- the remaining cutting area 30 can be a ring area surrounding the opening area 20
- the first anti-crack area 40 can be a circle surrounding the remaining cutting area 30. A ring area around the ring.
- the opening area 20 may also be a strip-shaped opening area.
- the remaining cutting area 30 and the first anti-crack area are sequentially surrounding the opening area.
- 20 a circle of strip-shaped area;
- the strip-shaped hole is a closed-shaped hole surrounded by two groups of connected straight line parts and arc parts; in an optional embodiment, the shape of the opening 21 can also be a runway shape.
- two openings 21 can also be provided in the opening area 20 , and the area between the display area 70 and the two openings 21 is the first anti-crack area. 40; In other implementation manners, more openings 21 may be provided in the opening area 20.
- the display panel further includes in the first anti-crack area 40: a base substrate 11, an encapsulation layer 12 located on the base substrate 11, at least one circle of anti-cracking layer located on the encapsulation layer 12. Crack protection layer 41.
- the outer surface of the concave hole may be flush with the surface of the packaging layer 12 facing away from the base substrate 11 , or may be flush with the surface of the base substrate 11 facing away from the packaging layer 12 .
- the encapsulation layer 12 may include a first inorganic encapsulation film layer, an organic encapsulation film layer and a second inorganic encapsulation film layer stacked in sequence, and the first inorganic encapsulation film layer and the second inorganic encapsulation film layer may be formed twice respectively. It can be obtained by chemical vapor deposition, and can also be formed by physical vapor deposition process.
- the material of the first inorganic packaging film layer and the second inorganic packaging film layer can be inorganic materials such as silicon nitride and silicon oxide;
- the organic packaging film layer adopts inkjet printing process It can also be formed by a spraying process, and the material of the organic encapsulation film layer can be acrylic-based polymer, silicon-based polymer and other materials;
- the encapsulation layer 12 of the first anti-crack area 40 can be a part of the encapsulation layer of the entire display panel,
- the encapsulation layer 12 here can extend to the opening area 20 to the cutting remaining area 30, and can also extend to the display area 70 of the display panel, so as to package the circuit components of the entire display panel on the entire base substrate 11, and protect Circuit components are not corroded by water vapor and oxygen, and form structural protection for the entire display panel.
- the base substrate 11 located in the first anti-crack area 40 may also be a part of the base substrate of the entire display panel, and the base substrate 11 there may extend toward the opening area 20.
- the direction extends to the remaining cutting area 30, and may also extend to the display area 70 of the display panel.
- the anti-crack protection layer 41 is used to block the cracks generated by the cutting of the opening area 20, and prevent the cracks of the encapsulation layer 12 caused by cutting when digging holes from spreading to the display area of the display panel, touch The encapsulation layer 12 in the region, thereby avoiding damage to the internal light-emitting layer and touch electrode layer protected by the encapsulation layer 12 .
- the anti-crack protection layer 41 is provided on the same layer as the touch electrode layer 71 corresponding to the display area, and the material can be consistent, and can also be formed synchronously in preparation. Therefore, in the embodiment of the present disclosure, the anti-crack protection layer 41 may be made of a metal material consistent with the touch electrode layer, so as to meet the requirement of material ductility for crack prevention at the edge of the hole.
- the display panel further It includes a display area 70; the display area 70 includes at least one touch electrode layer 71, the touch electrode layer 71 includes a touch metal layer, and the anti-crack protection layer 41 includes at least one layer of metal.
- the touch electrode layer 71 is used to realize the touch function of the display area 70 of the display panel, and the display area 70 overlaps or partially overlaps with the touch area of the display panel.
- the anti-crack protection layer 41 and at least one layer of the touch electrode layer 71 are provided in the same layer and the same material in the display panel. .
- the setting of the same layer and the same material may be that the anti-crack protection layer 41 and at least one layer of the touch electrode layer 71 are located in the same layer in the hierarchical structure of the display panel and made of the same material, further At least one layer of the anti-crack protection layer 41 and the touch electrode layer 71 can be formed by the same step process during preparation, and there is no limit to the requirement that at least one layer of the anti-crack protection layer 41 and the touch electrode layer 71 be on the opposite lining.
- the vertical direction of the plane of the base substrate 11 is in the same plane, that is, in the direction perpendicular to the plane of the base substrate 11, the distance between the anti-crack protection layer 41 and the base substrate 11 is the same as the distance between at least one layer of the touch electrode layer 71 and the substrate.
- the size of the base substrate 11 may vary.
- the anti-crack protection layer 41 can be the corresponding layer of the touch electrode layer 71 prepared based on the touch display integration technology, that is, formed on the same layer.
- the metal layer of the integrated touch pattern is used to prepare the anti-crack structure around the hole.
- this can also be beneficial to further realize the separation of the display area 70 and the non-display area of the display panel through the functional setting of the anti-crack protection layer 41. Unification of touch functions.
- FIG. 6 is a schematic diagram of crack blocking provided by an embodiment of the present disclosure.
- the display panel proposed by the embodiment of the present disclosure is provided with at least one ring of anti-crack protection layer 41 in the first anti-crack area 40 surrounding the cutting area of the opening area 20.
- the anti-crack protection layer 41 is ring-shaped around the hole.
- the present disclosure further provides a display panel, in which the base substrate 11 and the encapsulation layer 12 extend to the display area 70 .
- the touch electrode layer 71 is located on a side of the encapsulation layer 12 away from the base substrate 11 .
- the touch metal layer of the touch electrode layer 71 of the display area 70 may be located above the encapsulation layer 12 in the position area of the display area 70, and may be in contact with the surface of the encapsulation layer 12 away from the base substrate 11;
- the crack protection layer 41 may also be correspondingly located above the encapsulation layer 12 in the position area of the first crack prevention area 40 , and correspondingly be in contact with the surface of the encapsulation layer 12 facing away from the base substrate 11 .
- FIG. 7 is a schematic cross-sectional view of a touch metal layer provided by an embodiment of the present disclosure. As shown in FIG. 7 , in an optional implementation manner, the present disclosure also provides a display panel, in which the at least one touch electrode layer 71 includes stacked first touch electrodes.
- the anti-crack protection layer 41 can be provided in the same layer and material as the first touch metal layer 701 , or the anti-crack protection layer 41 can also be provided in the same layer and material as the second touch metal layer 703 . That is, when preparing the display panel, the anti-crack protection layer 41 can be formed in the same step process as the first touch metal layer 701, and the anti-crack protection layer 41 can also be formed in the same step process as the second touch metal layer 703. .
- the touch electrode layer 71 can be used as a signal line of the touch pattern on the surface of the display panel to transmit the touch signal to respond to an external touch action on the display device where the display panel is located, thereby realizing Display the touch function of the panel.
- the first touch metal layer 701 can be a bridging layer, that is, as a part of the wiring bridging the touch electrodes
- the second touch crack prevention layer 703 can be an electrode pattern layer, that is, a wiring of the touch electrodes a part of.
- first touch metal layer 701 and the second touch crack prevention layer 703 there is an element used to connect the first touch metal layer 701 and the touch control layer 702 in the touch medium layer 702.
- the through hole of the second touch metal layer 703 is described above.
- a touch base layer 704 is also provided for isolating and protecting the first touch metal layer 701;
- a touch protection layer 705 is further provided for isolating and protecting the second touch metal layer 703 .
- the through hole in the touch control medium layer 702 can be used to form a metal structure integrated with the second touch metal layer 703 in the through hole when forming the second touch metal layer 703 ,
- the metal structure can be connected with the first touch metal layer 701 to realize electrical connection, and then the first touch metal layer 701 and the second touch metal layer 703 cooperate to realize the touch function.
- the touch medium layer 702 can be made of inorganic materials, such as SiO 2 or SiNx; the touch medium layer 702 can also be made of organic materials, such as resin or UV glue, which is not specifically limited in this embodiment of the present disclosure.
- the touch medium layer 702 may not be disposed between the first touch metal layer 701 and the second touch metal layer 703 .
- FIG. 8 is a schematic diagram of distribution of a first mode of a double-layer anti-crack protection layer provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic diagram of distribution in a second mode of a double-layer anti-crack protection layer provided by an embodiment of the present disclosure.
- the present disclosure also provides a display panel, in which , the anti-crack protection layer 41 includes a first anti-crack protection layer 401 and a second anti-crack protection layer 403 that are stacked.
- the first anti-crack protection layer 401 is arranged between the second anti-crack protection layer 403 and the base substrate 11, and the first anti-crack protection layer 401 is arranged on the second anti-crack protection layer 403. layer 403 and the base substrate 11 .
- a touch insulating layer 402 is disposed between the first anti-crack protection layer 401 and the second anti-crack protection layer 403, and the touch insulation layer 402 can cover the first anti-crack protection layer 401 , the touch insulation layer 402 can electrically insulate and separate the first anti-crack protection layer 401 and the second anti-crack protection layer 403, so that the first anti-crack protection layer 401 and the second anti-crack protection layer
- the protection layer 403 respectively performs corresponding electrical functions.
- the first anti-crack protection layer 401 and the first touch metal layer 701 are correspondingly provided on the same layer and the same material
- the touch insulating layer 402 and the touch control medium layer 702 are correspondingly provided on the same layer and the same material
- the The second anti-crack protection layer 403 and the second touch metal layer 703 are correspondingly provided in the same layer and the same material.
- each ring of anti-crack protective layer 41 may be 0.8 ⁇ m to 1.2 ⁇ m, such as 0.8 ⁇ m, 0.9 ⁇ m, 1 ⁇ m, 1.1 ⁇ m, 1.2 ⁇ m, etc.
- the anti-crack protection layer 41 including the first anti-crack protection layer 401 and the second anti-crack protection layer 403 can block the cracks at the edge of the opening with double effects, and prevent edge cracks more effectively.
- the display area/touch area spreading to the surrounding area of the digging hole ensures the display effect and touch effect of the display area.
- FIG. 12 is a schematic plan view of touch electrode traces of a crack-proof protective layer provided by an embodiment of the present disclosure.
- the above-mentioned embodiment proposes a display panel in which a touch anti-crack layer 41 is provided in the first anti-crack area 40, which can improve the anti-crack capability of the area around the opening area 20 of the display screen, and the touch anti-crack layer
- the split layer 41 can also be used to realize the touch function of the display panel in the area around the hole, without relying on additional touch function components.
- each circle of the touch crack prevention layer 41 can be connected to peripheral electrodes or ground electrodes through the traces of the touch electrodes in the frame area 80 . It should be noted that the content provided in FIG. 12 is only for a simple illustration of the connection wiring between the touch-control anti-crack layer 41 and the electrodes, and does not limit the internal arrangement of the wiring.
- the present disclosure also provides a display panel, in which the first anti-crack protection layer 401 is a part of the traces of the touch electrodes, so The second anti-crack protection layer 403 is a part of the wires bridging the touch electrodes.
- the traces of the touch electrodes and the traces bridging the touch electrodes are connected to the touch chip 91 , and the touch chip 91 is used for processing and responding to the touch signals provided by the traces.
- the anti-crack protective layer 41 can also be a part of the touch signal lines of the touch electrodes.
- the touch signal lines corresponding to the display area 70 of the display panel can The touch behavior responds, thereby completing the user's control of the corresponding terminal of the display panel, so that the display panel does not need to add additional touch function components, such as: no need to provide a touch function sensor film or an outer glass touch layer, and it can also be used on the display panel
- the touch function is provided around the digging hole to ensure the realization of the touch function.
- the thickness of each ring of the anti-crack protection layer 41 in at least one circle of anti-crack protection layer 41 can be the same as that of the display area of the display panel.
- the touch signal lines corresponding to 70 have the same thickness.
- the thickness of each ring of the anti-crack protection layer 41 may be 0.4 ⁇ m-0.6 ⁇ m.
- FIG. 12 simply shows the planar traces of the touch electrodes connecting the first anti-crack protection layer 701 and the second anti-crack protection layer 703.
- the traces of the touch electrodes bridged by the second anti-crack protection layer can also be connected with
- the traces of the touch electrodes of the first anti-crack protection layer may be located at different layers in the vertical direction of the display panel.
- the first anti-crack protection layer 401 and the second anti-crack protection layer 403 can also be used to cooperate to realize the touch function of the display panel in the black border (Black Mask, BM) area around the opening area 20 .
- Black Mask, BM black border
- At least one circle of the touch insulation layer 402 may also have a first circle that penetrates the circle.
- the openings of the first anti-crack protection layer 401 and the second anti-crack protection layer 403, the metal wires for connecting the wiring of the first anti-crack protection layer 401 and the second anti-crack protection layer 403 are arranged in the openings so that the first anti-crack protection layer 401 and the second anti-crack protection layer 403 cooperate to realize the touch function of the first anti-crack area 40 .
- the anti-crack protection layer 41 can use the double-layered structure of the anti-crack protection layer 41 to realize the touch function of the surrounding area of the hole.
- the first anti-crack protection layer 401 and the first touch metal layer 701 are formed in the same layer and the same material, and the touch insulating layer 402 and the touch control medium layer 702 are correspondingly formed in the same layer and the same material Forming, the second anti-crack protection layer 403 and the second touch metal layer 703 are formed in the same layer and the same material, so the materials and thicknesses of the structures formed in the same layer can be the same.
- the material of the first anti-crack protection layer 401 and the first touch metal layer 701 may be the same, the material of the touch insulation layer 402 and the touch medium layer 702 may be the same, and the second The material of the anti-crack protection layer 403 and the second touch metal layer 703 may be the same.
- the material of the touch insulation layer 402 may be the same as that of the encapsulation layer 12 .
- the touch insulating layer 402 may also be a material that is easier to achieve high-precision preparation, and/or a material with better electrical insulation performance than that of the encapsulation layer 12 .
- the present disclosure also provides a display panel, in which the first anti-crack protection layer 401 and the second anti-crack protection layer 41 of the anti-crack protection layer 41
- the protective layer 403 is not connected to the outside of the display panel and is used as a PCD line, that is, the first anti-crack protective layer 401 and the second anti-crack protective layer 403 are not connected to the traces of the touch electrodes in the frame area 80; and, in this implementation In this manner, the anti-crack protection layer 41 is provided as an integral structure.
- the first anti-crack area 40 is a circle area around the opening area 20, and the first anti-crack area 40 has a certain width in the plane direction of the display panel (that is, the first anti-crack area 40 is close to the opening The distance between one side of the area 20 and the side of the first anti-crack area 40 close to the display area 70), within this width, the anti-crack protective layer 41 needs to at least partially cover the encapsulation layer 12 in the first anti-crack area , so the display panel may include at least one ring of anti-crack protection layer 41 around the opening area.
- FIG. 13 shows a schematic plan view of a display panel.
- the anti-crack protection layer 41 may have an integral structure.
- the width of the anti-crack protection layer 41 in the plane direction of the display panel may be the same as the width of the first anti-crack region 40 in the plane direction of the display panel, so that the anti-crack protection layer 41 can
- the encapsulation layer 12 in the area of the anti-crack area 40 is completely covered, thereby preventing the edge cracks of the digging hole caused by the cutting of the opening area 20 from spreading to the display area and the touch area of the display panel, effectively improving the anti-corrosion protection of the display area and the touch area of the display panel. Crack ability to ensure the display effect and touch function of the display panel.
- FIG. 14 shows a schematic plan view of another display panel.
- the anti-crack protection layer 41 includes a multi-turn structure
- each ring of anti-crack protection layer 41 is independently disposed on the encapsulation layer 12 .
- the anti-crack protection layer 41 includes a plurality of ring-shaped parts arranged in the first anti-crack area 40 with the same center and concentric circles at intervals.
- the anti-crack protection layer 41 comprises four ring structures, so in the first anti-crack area 40, the anti-crack protection layer 41 is shown as four ring parts distributed concentrically with the same center, and the second The encapsulation layer 12 in the anti-crack area 40 is partially covered, and the multi-circle anti-crack protective layer 41 can further prevent the cracks in the opening area 20 from spreading to the display area of the display panel.
- the touch signal layer is directly fabricated on the display layer and the packaging layer 12. Considering various factors such as manufacturing accuracy, electrical conductivity, material ductility, cost, and process maturity, titanium-aluminum-titanium is usually used. (Ti-Al-Ti) as a touch functional material.
- titanium-aluminum-titanium is a three-layer metal laminated film, including an upper titanium base layer composed of titanium or mainly titanium, a middle aluminum metal layer composed of aluminum or mainly aluminum, and a lower layer made of Titanium or a titanium-based metal layer mainly composed of titanium.
- the titanium film can prevent the oxidation of the aluminum layer
- the aluminum film is used as a conductive material for the transmission of electrical signals.
- the anti-crack protective layer 41 can also be a metal material that comprehensively considers the manufacturing accuracy and ductility, and is not limited to titanium-aluminum-titanium.
- the present disclosure realizes the preparation and formation of the touch electrode layer 71 of the display area 70 to realize the layered structure of the anti-crack protection layer around the digging hole, and further prevents cracks at the edge of the digging hole. Therefore, in an optional implementation manner, corresponding to the hierarchical structure of the anti-crack protection layer 71, the anti-crack protection layer includes a single-layer or laminated structure of metal or metal oxide.
- the metal includes at least one of the following: copper, molybdenum, titanium-aluminum-titanium;
- the metal oxide includes: indium tin oxide.
- the present disclosure also provides a display panel, in which the first anti-crack protective layer 401
- the material of 402 of the second anti-crack protection layer is different from each other. That is, the materials of the first anti-crack protection layer 401 and the second anti-crack protection layer 403 of the same circle can be different from each other.
- the materials of the first anti-crack protection layer 401 and the second anti-crack protection layer 402 may be two materials with different electrical properties.
- the first anti-crack protection layer 401 may be made of indium tin oxide
- the second anti-crack protection layer 403 may be made of titanium-aluminum-titanium.
- first anti-crack protection layer 401 and the second anti-crack protection layer 403 have an upper-lower layer relationship on the insulating layer of the first anti-crack area 40, and their roles in blocking cracks can be different. Therefore, the first The materials of the anti-crack protection layer 401 and the second anti-crack protection layer 403 may also be two materials with different ductility.
- the first anti-crack protection layer 401 may be made of molybdenum
- the second anti-crack protection layer 403 may be made of indium tin oxide.
- the first anti-crack area 40 is a part of the BM area, since there is no need to provide a display function, In the first anti-crack area 40, only the base substrate 11 and the encapsulation layer 12 take up more space, and the first anti-crack area 40 of the display panel has a lot of "vacant" space.
- the present disclosure also provides a display panel, in the first anti-crack area 40 of the display panel, the base substrate 11 and the encapsulation layer 12 are arranged There is at least one turn of the first anti-crack dam 42 .
- the first anti-crack dam 42 can be made of metal material, so that the first anti-crack area 40 can further block the propagation of cracks at the edge of the opening to the direction of the display area 70 .
- the first anti-crack dam 42 and the anti-crack protection layer 41 are distributed on both sides of the encapsulation layer 12 according to the first manner and/or the second manner.
- the at least one ring of anti-crack protection layer 41 may be disposed on the encapsulation layer 12 at a position area corresponding to the plurality of rings of first anti-crack dams 42 .
- the position area corresponding to the multi-circle first anti-crack dam 42 may be the upper position where the first anti-crack dam 42 is away from the base substrate 11, or the first anti-crack dam 42 may point to the opening area 20 direction or a side orientation pointing to the display area 70 direction.
- the number of turns of the anti-crack protective layer 41 may be the same as that of the first anti-crack dam 42, so as to reduce the difficulty of manufacturing and improve the effect of preventing cracks.
- the number of turns of the anti-crack protection layer 41 can also be different from that of the first anti-crack dam 42, so as to realize the wiring of a specific touch pattern and realize the corresponding touch function in the surrounding area of the hole.
- the anti-crack protective layer 41 and the first anti-crack dam 42 on both sides of the encapsulation layer 12, it can be combined with the first anti-crack dam 42 to improve the protection of the display panel.
- the cracks in the openings 21 are prevented from propagating toward the display area 70 , which helps to improve the crack blocking effect.
- the present disclosure also provides a display panel, in which the first crack prevention dam 42 and the anti-crack protection layer 41 are distributed on both sides of the encapsulation layer 12 according to the first method, the first method is: the first anti-crack dam 42 and the anti-crack protection layer 41 are stacked on the On both sides of the encapsulation layer 12 , the orthographic projection of the first anti-crack dam 42 on the substrate 11 at least partially covers the orthographic projection of the anti-crack protection layer 41 on the substrate 11 .
- the orthographic projection of the first anti-crack dam 42 on the substrate 11 can completely cover the orthographic projection of the anti-crack protective layer 41 on the substrate 11 , and, the center position of the orthographic projection of the first anti-crack dam 42 on the base substrate 11 may coincide with the center position of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 .
- each circle of the anti-crack protective layer 41 can be disposed on a first area on the encapsulation layer 12, wherein the first area is directly opposite to the first anti-crack The position area directly above the dam 42 , so that the anti-crack protective layer 41 and the first anti-crack dam 42 are symmetrically arranged on the upper and lower sides of the encapsulation layer 12 .
- the directly above refers to a direction away from the base substrate 11 in a direction perpendicular to the horizontal plane with the surface of the base substrate 11 as a horizontal plane.
- a circle of anti-crack protection layer 41 and the first anti-crack protection layer 42 are arranged in a projected coincident relationship, so that each circle of anti-crack protection layer 41 can be regularly aligned with the circle of anti-crack protection layer 41.
- the first anti-crack dam 42 constitutes at least one set of first anti-crack combination units, such first anti-crack combination units form "multiple high walls" that block the crack propagation in the opening 21 mainly in the encapsulation layer 12, and can The ability to block cracks mainly caused by the encapsulation layer 12 is enhanced, and the anti-crack effect of the display panel is improved.
- the present disclosure also provides a display panel, in which the first anti-crack dam 42 and the anti-crack protection The layer 41 is distributed on both sides of the encapsulation layer 12 according to the second method; the second method is: the first anti-crack dam 42 and the anti-crack protection layer 41 are dislocated on both sides of the encapsulation layer 12 On the side, the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 is located between the orthographic projections of two adjacent first anti-crack dams 42 on the base substrate 11 .
- the central position of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 can be in the gap formed by two adjacent first anti-crack dams 42 .
- the center positions of the orthographic projections on the base substrate 11 coincide.
- each ring of anti-crack protection layer 41 may be provided on a second area on the encapsulation layer 12, wherein the second area is the same as two adjacent rings of the first anti-crack layer.
- the anti-crack protective layer 41 and the first anti-crack dam 42 are alternately arranged on both sides of the encapsulation layer 12 .
- the region corresponding to the gap formed by two adjacent turns of the first anti-crack dam 42 refers to the gap formed between the encapsulation layer 12 between two adjacent turns of the first anti-crack dam 42 .
- the anti-crack protection layer 41 is set to coincide with the projection of the interval area of the first anti-crack dam 42, so that each circle of anti-crack protection layer 41 can be regularly adjacent to the left and right two circles of the first anti-crack dam 42 Constitute a "sandwich type" second anti-crack combination unit, such a second anti-crack unit forms a "thick wall" that blocks the crack propagation in the opening 21 mainly in the encapsulation layer 12, and can enhance the ability to block cracks , improve the anti-cracking effect of the display panel.
- the present disclosure also provides a display panel, in which In the display panel, the first anti-crack dam 42 and the anti-crack protection layer 41 are distributed on both sides of the encapsulation layer 12 in the first manner and the second manner; The crack dam 42 and the anti-crack protection layer 41 are distributed on both sides of the encapsulation layer 12 according to the first method, and the remaining turns of the first anti-crack dam 42 and the anti-crack protection layer 41 are distributed according to the second method. distributed on both sides of the encapsulation layer 12 .
- the target anti-crack protection layer 41 in the at least one circle of anti-crack protection layer 41 is disposed on the first area on the encapsulation layer 12 .
- the target anti-crack protective layer 41 is the anti-crack protective layer with a partial number of turns.
- the first area is the position area directly above the first anti-crack dam 42; wherein, the target anti-crack protection layer 41 is part of the at least one circle of anti-crack protection layer 41.
- the anti-crack layer 41 is touched.
- the remaining anti-crack protection layer 41 in the at least one circle of anti-crack protection layer 41 except the target anti-crack protection layer 41 is arranged on the second area on the encapsulation layer 12, wherein the second area is On the area corresponding to the gap formed by two adjacent circles of the first anti-crack dam 42, so that each circle of anti-crack protective layer 41 and the first anti-crack dam 42 of the remaining number are alternately arranged on the Both sides of the encapsulation layer 12 .
- the first anti-crack dam 41 is distributed on both sides of the encapsulation layer 12 according to the first method and the second method at the same time, and the target anti-crack protection layer 41 of which part of the number of turns is distributed according to the first method, Compared with the remaining anti-crack protection layer 41, it can be kept at a position farther away from the base substrate 11, and based on this positional relationship, the wiring requirements and/or crack blocking requirements of the specific touch pattern in the peripheral area of the opening area 20 can be met.
- the anti-crack protective layer 41 and the first anti-crack dam 42 distributed according to two distribution methods form a combination of upper and lower positional relationships and a staggered combination, which can also enhance the ability to block cracks and improve the anti-crack effect of the display panel.
- the present disclosure also provides A display panel is provided.
- the base substrate 11 and the encapsulation layer 12 extend to the remaining cutting area 30; the display panel also includes a concave-convex structure 31 , the concave-convex structure 31 is located between the encapsulation layer 12 and the base substrate 11 in the remaining cutting area 30 .
- the concave-convex structure 31 can be at least one circle, and at least one circle of the concave-convex structure 31 can be distributed around the opening area 20 in sequence.
- the concave-convex structure 31 includes a first concave-convex structure, the minimum distance between the first concave-convex structure and the opening 21 is 0 ⁇ m-30 ⁇ m, at least one of the concave-convex structures 31 has a surface away from the base substrate 11, and The side surfaces connected by the surfaces, wherein at least one of the surface and the side surfaces is concave-convex, and the first concave-convex structure is the concave-convex structure 31 with the smallest distance from the center of the opening area 20 .
- a display panel is provided, the display panel is provided with a concave-convex structure 31 in the remaining cutting area 30 closer to the opening 21 than the first anti-crack area 40, which can better cope with extreme conditions
- the cracking of the lower opening 21 may cause damage to the anti-crack protection layer 41, enhance the ability of the display panel to prevent cracking at the edge of the hole, and can also be used in the anti-crack protection layer 41 to realize the touch function in the area around the opening area 20 In the case of , the touch function of the display panel in the peripheral area of the opening area 20 is ensured.
- the present disclosure further provides a display panel, and the display panel further includes: a flow stop area 50 surrounding the first anti-crack area 40 .
- the base substrate 11 and the encapsulation layer 12 extend to the flow-stopping area 50, and a flow-stopping layer is also arranged between the encapsulation layer 12 and the base substrate 11 in the flow-stopping area 50. Dam 51.
- the flow stop dam 51 may be multi-turn, and the multi-turn stop dam 51 may be distributed around the first anti-crack zone 40 in sequence.
- a display panel is provided.
- the display panel is provided with a multi-circle stop dam 51 in the direction from the first anti-crack area 40 to the display area 70, which can prevent the ink of the display panel from overflowing and avoid damage to the display panel.
- the appearance and function of the anti-crack protection layer 41 can also avoid affecting the realization of the touch function of the anti-crack protection layer 41 when the touch control crack prevention layer is used to realize the touch control function of the peripheral area of the opening area 20 .
- the display panel further includes in the second anti-crack area 60: a base substrate 11, an encapsulation layer located on the base substrate 11 12.
- a second anti-crack dam 61 is further provided between the encapsulation layer 12 and the base substrate 11 in the second anti-crack area 60 .
- the second anti-crack dam 61 can be multi-circle, and the multi-circle second anti-crack dam 61 can be distributed around the flow-stopping area 50 in sequence. Moreover, there is at least a partial overlap area between the anti-crack protection layer 41 and the orthographic projection of the first anti-crack dam 42 and/or the second anti-crack dam 61 on the base substrate 11 .
- a display panel is provided.
- the display panel is provided with multiple rings of second anti-crack dams 61 nearer to the display area 70, which can not only cooperate with the cracking of the opening 21 by the anti-crack protective layer 41 Further provide the blocking effect to the spread of the display area 70, and can also deal with the situation that the display panel is broken from the display area 70, and prevent the crack from spreading further to the position of the opening area 20 where the anti-crack protection layer 41 is located, preventing the crack protection from being damaged.
- the damage caused by the layer 41 can ensure the touch function around the opening area 20 of the display panel when the anti-crack protection layer 41 is used to realize the touch function in the area around the opening area 20 .
- the present disclosure also provides a display panel.
- the display panel further includes in the first anti-crack area 40: At least one metal layer between the base substrates.
- the at least one metal layer includes a first metal layer 101 and a second metal layer 102, wherein the first metal layer 101 is located on the second Between the metal layer 102 and the base substrate 11 , the first metal layer 101 serves as an electrode layer, and the second metal layer 102 serves as a bridging layer. Moreover, the orthographic projections of the first metal layer 101 and the second metal layer 102 on the base substrate 11 at least partly overlap with the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 .
- a display panel is provided, and the display panel is provided with a first metal layer 101 and a second metal layer 102 between the encapsulation layer 12 and the base substrate 11 of the first anti-crack area 40.
- the first metal layer 101 and the second metal layer 102 are more conducive to realizing the touch function in the peripheral area of the opening area 20 by using the anti-crack protection layer 41 .
- the present disclosure also provides a display panel.
- the display panel further includes in the display area 70 : Between the driving circuit layer 12 and the light emitting layer 32 .
- the part of the driving circuit layer located in the display area 70 may include a thin film transistor and a capacitor structure.
- the thin film transistor can be a top gate type, and this thin film transistor can include an active layer 220, a first gate insulating layer 113, a gate 224, a second gate insulating layer 114, an interlayer dielectric layer 115, a source 222. Drain 221.
- the active layer 220 can be formed on the buffer layer 112
- the first gate insulating layer 113 covers the buffer layer 112 and the active layer 220
- the gate 224 is formed on the side of the first gate insulating layer 113 away from the active layer 220.
- the second gate insulating layer 114 covers the gate 224 and the first gate insulating layer 113
- the interlayer dielectric layer 115 covers the second gate insulating layer 114
- the source electrode 222 and the drain electrode 221 are formed on the interlayer dielectric layer 115 away from the base substrate 11 and are respectively located on opposite sides of the gate 224
- the source 222 and the drain 221 can respectively contact the opposite sides of the active layer 220 through via holes (for example: metal via holes).
- via holes for example: metal via holes.
- the thin film transistor can also be of bottom gate type.
- the capacitor structure may include a first pole plate 225 and a second pole plate 226.
- the first pole plate 225 and the gate electrode 224 are arranged on the same layer, and the second pole plate 226 is located between the second gate insulating layer 114 and the layer. between the interlayers 115 and opposite to the first plate 225 .
- the materials of the grid 224 , the first pole plate 225 and the second pole plate 226 may include metal materials or alloy materials, such as molybdenum, aluminum and titanium.
- the source electrode 222 and the drain electrode 221 may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed by molybdenum, aluminum, titanium, etc.
- the multi-layer structure is a multi-metal layer stack, such as titanium, aluminum, Titanium three-layer metal stack (Al/Ti/Al), etc.
- the light emitting layer 32 includes a first pixel electrode 321 and a pixel defining portion 117 sequentially formed on the interlayer dielectric layer. It should be understood that the display device may also include a light emitting portion 322 and a second pixel electrode 323. .
- the planarization layer 116 can also be fabricated before manufacturing the display device, and the planarization layer can be a single-layer structure or a multi-layer structure; the planarization layer It is usually made of organic materials, such as: photoresist, acrylic-based polymers, silicon-based polymers and other materials; portion is formed between the interlayer dielectric layer 115 and the first pixel electrode 321 .
- the first pixel electrode 321 can be electrically connected to the drain electrode 221 through a metal via hole, and the first pixel electrode 321 can be an anode, and the anode can be ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO) and other materials; the pixel defining portion 117 can cover the planarized portion, and the pixel defining portion 117 can be made of organic materials, such as organic materials such as photoresist, and the pixel defining portion 117 is located in the display area
- the part of 70 may have a pixel opening exposing the first pixel electrode 321; the light emitting part 322 is located in the pixel opening and formed on the first pixel electrode 321, the light emitting part 322 may include a small molecular organic material or a polymer molecular organic material, and may It is a fluorescent light-emitting material or a phosphorescent light-emitting material, which can emit red light, green light, blue light, or white light, etc.
- the second pixel electrode 323 covers the light emitting part 322, and the polarity of the second pixel electrode 323 is opposite to that of the first pixel electrode 321;
- the pixel electrode 323 can be a cathode, and the cathode can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
- the first pixel electrode 321 , the light emitting portion 322 and the second pixel electrode 323 may constitute a light emitting sub-pixel.
- the part of the display device located in the display area 70 may include a plurality of light-emitting sub-pixels arranged in an array.
- the first pixel electrodes 321 of each light-emitting sub-pixel are independent from each other, and the second pixel electrodes 323 of each light-emitting sub-pixel are connected on the entire surface; that is, the second pixel electrode 323 is arranged on the entire surface of the display panel.
- the structure is a common electrode for multiple display devices.
- a support portion 118 can also be provided on the side of the pixel defining portion 117 away from the interlayer dielectric layer 115, and the support portion 118 can support the protective film layer (not shown in the figure). shown) to avoid the situation that the protective film layer is in contact with the first pixel electrode 321 or other wirings and the first pixel electrode 321 or other wirings are easily damaged.
- this protective film layer mainly appears during the transfer of the semi-finished product to avoid damage to the semi-finished product during the transfer process, specifically: during the transfer of the substrate on which the support portion 118 has been fabricated to the evaporation production line , a protective film layer can be covered, and the protective film layer can be removed when the luminescent material needs to be evaporated.
- the material of the supporting portion 118 can be the same as that of the pixel defining portion 117, and the supporting portion 118 and the pixel defining portion 117 can be formed by the same patterning process, but not limited thereto, the material of the supporting portion 118 can also be the same as that of the pixel
- the materials of the defining portion 117 are different, and the supporting portion 118 and the pixel defining portion 117 can also be formed by different patterning processes.
- the first pixel electrode 321 can also be electrically connected to the drain electrode 221 through the first transfer electrode 227 .
- the planarization part can be a double-layer structure, specifically, it can include the first planarization film (PLN1) layer 181 and the second The second planarization film (PLN2) layer 182, in addition, the first passivation film (PVX) layer 190 can also be formed between the first planarization film layer 181 and the interlayer dielectric layer 115, and this passivation film layer 190 can be formed by oxidation Silicon, silicon nitride or silicon oxynitride and other materials; the first passivation film layer 190 covers the source electrode 222 and the drain electrode 221.
- a passivation film layer can also be formed between the dielectric layers 115; and the first via electrode 227 is formed between the first planarization film layer 181 and the second planarization film layer 182, and passes through the first planarization film layer 181 in turn.
- the via hole (such as a metal via hole) on the first passivation film layer 190 is electrically connected to the drain electrode 221; and the first pixel electrode 321 can pass through the via hole (such as a metal via hole) on the second planarization film layer 182 ) is electrically connected to the first via electrode 227, as shown in FIG. 16 .
- the first via electrode 227 may also be formed between the first planarization film layer 181 and the first passivation film layer 190 .
- the driving circuit layer further includes a second transfer electrode 228, and the first pixel electrode 321 can be connected to the drain through the second transfer electrode 228 and the first transfer electrode 227. 221 is electrically connected.
- the planarization part includes the sequentially formed first planarization film layer 181
- a third planarization film layer 183 is also included, and the third planarization film layer 183 is formed on the side of the second planarization film layer 182 away from the first planarization film layer 181.
- a second passivation film layer (not shown in the figure) may also be formed between the third planarization film layer 183 and the second planarization film layer 182; the second via electrode 228 is formed on the third planarization film layer 183 and the second planarization film layer 182, and is electrically connected to the first transfer electrode 227 through the via hole on the second planarization film layer 182; and the first transfer electrode passes through the first planarization film layer 181 and the via holes (such as metal via holes) on the first passivation film layer 190 are electrically connected to the drain electrode 221; and the first pixel electrode 321 can pass through the third planarization film layer 183 and the second passivation film layer
- the via hole is electrically connected to the second via electrode 228; the second via electrode 228 may also be formed between the second planarization film layer 182 and the second passivation film layer.
- FIG. 18 is a flowchart of steps of a method for manufacturing a display panel provided by an embodiment of the present disclosure. As shown in FIG. 18 , an embodiment of the present disclosure also provides a method for manufacturing a display panel, the method comprising:
- the preparation method of the encapsulation layer 12 is an existing technology, and the electronic components and film layers between the substrate 11 of the display area and the touch area and the encapsulation layer 12, including the light-emitting layer, etc., can be It is prepared by the prior art and will not be repeated here.
- the structure obtained in the preceding steps can be aligned and grasped by using charge-coupled device (CCD) visual inspection technology, and then the surface of the encapsulation layer 12 of the structure can be inspected by using the preset processing area image. mark.
- the preset image of the processing area includes at least the preset image of the first anti-crack area 40, the preset image of the cutting area and the preset image of the opening area.
- the cutting area at least includes the remaining cutting area 30 after cutting and perforating.
- the center position of the hole area corresponds to the center position of the hole area 20 obtained after cutting and perforating.
- the preparation of the anti-crack protection layer 41 can utilize the existing FMLOC technology, and the specific method will not be repeated here.
- the punching and cutting method of the display panel is also a prior art, for example, the punching can be cut by laser, so the specific method will not be repeated here.
- the present disclosure also provides a method for preparing at least one double-layer anti-crack protection layer 41, comprising:
- FIG. 19 is a schematic diagram of forming a first crack protection layer provided by an embodiment of the present disclosure.
- the position area directly above the multi-circle first anti-crack dam 42 of the first anti-crack area 40 and/or adjacent two On the area corresponding to the gap formed by the circle of the first anti-crack dam 42, at least one circle of the first anti-crack protection layer 401 is prepared.
- FIG. 20 is a schematic diagram of forming a touch insulating layer provided by an embodiment of the present disclosure.
- the aforementioned step is to prepare the first anti-crack protection layer 401 in the position area directly above the multi-circle first anti-crack dam 42 of the first anti-crack area 40 on the encapsulation layer 12, then The touch insulating layer 402 also corresponds to the position area directly above the first anti-crack dam 42 on the first anti-crack protection layer 401.
- the side surface of each circle of the first anti-crack protection layer 401 The touch insulating layer 402 is prepared, so that each circle of the prepared touch insulating layer 402 wraps the circle of the first touch crack prevention layer 401 .
- the anti-crack protection layer 41 can be made of the same or similar material as the encapsulation layer 12 , and the preparation method of the anti-crack protection layer 41 can also be the same as the encapsulation layer 12 by using a vapor deposition masking method.
- the touch insulation layer 402 can also be prepared through a mask, so that at least one circle of the touch insulation layer 402 has an opening through the first anti-crack protection layer 401 and the second anti-crack protection layer 403 of the circle. .
- mask processing can be performed on the preset holes corresponding to the openings penetrating through the first anti-crack protection layer 401 and the second anti-crack protection layer 403 to obtain the
- the specific preparation process for the opening of the anti-crack protection layer 403 can be performed using existing technologies, so details are not repeated here.
- the first anti-crack protection layer 401 , the touch insulation layer 402 , and the second anti-crack protection layer 403 of each circle form the anti-crack protection layer 41 of the circle.
- each layer of the touch metal layer and the medium layer of the display area corresponding to each layer in the anti-crack protection layer 41 can be used to cooperate to realize the touch function of the display panel in the location area, and the anti-crack protection around the opening 21
- the layer 41 can prevent cracks from the opening 21 of the display panel from spreading to the display area 70 , and even the anti-crack protection layer 41 can realize the touch function in the area around the opening 21 .
- a single-layer or double-layer metal anti-crack protection layer 41 is prepared in the first anti-crack area 40 around the cutting area of the display panel opening 21, so as to obtain
- the anti-crack protective layer 41 is used to improve the anti-crack ability of the display area around the opening 21 of the perforated display panel in the display area 70, and without adding additional touch unit components, the touch function of the area around the opening can also be realized .
- an organic light-emitting layer is also arranged between the encapsulation layer 12 and the first anti-crack dam 42, and the first anti-crack dam 42 is usually a titanium-aluminum-titanium (Ti-Al-Ti) film layer , considering that the material of the organic light-emitting layer has better climbing characteristics, usually a part of the aluminum layer in the titanium-aluminum-titanium (Ti-Al-Ti) film layer is etched inward, so that the titanium layer on the top layer and the aluminum layer in the middle The layer forms an internally sunken structure, and the unetched top layer of titanium forms a brim of a certain length, thereby blocking the climbing organic light-emitting layer material.
- the organic luminescent material layer there is a risk of forming water and oxygen intrusion channels.
- At least one recessed structure 200 is formed on the surface away from the first anti-crack dam 42, specifically, the recessed structure 200 is located on both sides of the titanium layer of the top layer, and the position where the recessed structure 200 is located on the encapsulation layer 12 is prone to cracks, cracks The generation of will lead to stress concentration at this place, which will lead to reliability risk at this position.
- an embodiment of the present disclosure provides another display panel, as shown in FIG. 3 , the display panel includes an opening area 20, a display Zone 70 and the first crack protection zone 40.
- the display area 70 at least partially surrounds the opening area 20
- the first anti-crack area 40 is located between the display area 70 and the opening area 20
- the first anti-crack area 40 at least partially surrounds the apertured area 20 .
- the display panel further includes in the first anti-crack area 40: a base substrate 11, an encapsulation layer 12 located on the base substrate 11, an encapsulation layer 12 located on the encapsulation layer 12 At least one circle of anti-crack protection layer 41 on the top and at least one circle of first anti-crack dam 42 under the encapsulation layer 12; the area where the encapsulation layer 12 contacts the at least one circle of first anti-crack dam 42 At least one concave structure 200 is included, and the anti-crack protection layer 41 covers at least the concave structure 200 .
- the first anti-crack dam 42 includes at least one concave-convex structure.
- the surface of the bottom substrate 11 is the top surface, and the concave-convex structure of the first anti-crack dam 42 is shown as a side surface concave toward the inner side of the aluminum layer formed between the titanium layer of the top layer and the aluminum layer of the middle layer.
- the encapsulation layer 12 When the encapsulation layer 12 is deposited, due to Due to the film-forming properties of the encapsulation layer 12 itself, the encapsulation layer 12 will form a recessed structure 200 at the side of the recess, and since the first anti-crack dam has two recessed sides, the encapsulation layer 12 will form two recesses Structure 200.
- the recessed structure 200 includes at least one step perpendicular to the direction of the base substrate 11 , and the anti-crack protection layer 41 at least covers the step. That is, the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 at least partially overlaps the orthographic projection of the step on the base substrate 11 .
- the anti-crack protection layer 41 at least partially covers the recessed structure 200 on the surface of the encapsulation layer 12, on the one hand, it can completely prevent water vapor from invading the display panel through the cracks and the water-oxygen channel formed by the organic light-emitting layer; on the other hand, After the recessed structure 200 of the encapsulation layer 12 is covered by the anti-crack protective layer 41 of metal material, the problem of stress concentration at the crack can be effectively improved due to the strong bonding force between the metal layers.
- the present disclosure further provides a display panel, in which the recessed structure 200 includes at least two first surfaces and is located between the two first surfaces.
- the second surface of the second surface, and two steps perpendicular to the direction of the base substrate connecting the first surface and the second surface, the anti-crack protection layer 41 completely covers the recessed structure 200 .
- the encapsulation layer 12 covers the first anti-crack dam 42
- two planes parallel to the base substrate 11 will be formed, these two planes are the two first surfaces, and the second surface is the two planes.
- the surface between the two first surfaces is inclined relative to the base substrate 11, and the second surface and the two first surfaces are connected by two steps perpendicular to the direction of the base substrate 22, so that the encapsulation layer 12 contacts the first The concave structure 200 formed behind the anti-crack dam 42 .
- the anti-crack protective layer 41 completely covers the recessed structure 200, that is, the anti-crack protective layer 41 completely covers the two first surfaces and the second surface, and as shown in FIG. 23 and FIG. 24, the anti-crack protective layer 41 is on the base substrate 11
- the orthographic projection of completely covers the orthographic projection of the recessed structure 200 on the base substrate 11 .
- the anti-crack protection layer 41 completely covers the concave structure 200 on the surface of the encapsulation layer 12, which can better prevent water vapor from invading the display panel through the cracks and the water-oxygen channel formed by the organic light-emitting layer and improve the generation of the concave structure. stress concentration, thereby increasing the service life of the display panel.
- the side surface of the anti-crack protective layer 41 is inclined relative to the plane direction of the base substrate 11, and the inclination angle between the side surface and the plane direction of the base substrate 11 can be 20°-40°, for example, 20° , 25°, 30°, 40°, etc.
- the present disclosure also provides a display panel, in which the anti-crack protection layer 41 is on the base substrate
- the orthographic projection on 11 covers the orthographic projection of the first anti-crack dam 42 on the base substrate 11;
- the minimum distance between the boundaries of the orthographic projection above is greater than or equal to 0.4 ⁇ m and less than or equal to 0.5 ⁇ m, so as to ensure that the anti-crack protection layer 41 can completely cover the recessed structure 200 on the encapsulation layer 12 .
- the anti-crack protection layer 41 can be set in the same layer and the same material as the first touch metal layer 701 in the touch electrode layer 71, or the anti-crack protection layer 41 can be arranged with the first touch metal layer 701 in the touch electrode layer 71.
- the second touch metal layer 702 is provided with the same layer and the same material. That is, in the process of preparing the display panel, the anti-crack protection layer 41 can be formed synchronously with the first touch metal layer 701, and can also be formed synchronously with the second touch metal layer 702, and the material and thickness of the anti-crack protection layer 41 can be the same as The first touch metal layer 701 and the second touch metal layer 702 are the same.
- the anti-crack protective layer 41 when forming the anti-crack protective layer 41, it is only necessary to change the mask of the first touch metal layer 701 or the second touch metal layer 702 located in the first anti-crack area 40, and strictly control the first anti-crack dam 42 and the first touch metal layer 701 or the second touch metal layer 702; at the same time, it is also necessary to control the frontal projection boundary of the anti-crack protection layer 41 on the base substrate 11 and the first anti-crack dam 42 The minimum distance between orthographic projection boundaries on the base substrate 11.
- the present disclosure also provides a display panel, in which the anti-crack protection layer 41 can be formed synchronously with the first touch metal layer 701, and in the process , determine that the alignment accuracy between the first anti-crack dam 42 and the first touch metal layer 701 is less than or equal to 0.3, determine the boundary of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 and the first anti-crack dam 42
- the minimum distance between orthographic boundaries on the base substrate 11 is 0.5 microns.
- the present disclosure also provides a display panel, in which the anti-crack protection layer 41 can be formed synchronously with the second touch metal layer 703, and in the process, it is determined
- the alignment accuracy between the first anti-crack dam 42 and the second touch metal layer 703 is less than or equal to 0.3, and the boundary of the orthographic projection of the partition layer on the base substrate 11 and the first anti-crack dam 42 on the base substrate 11 are determined.
- the minimum distance between boundaries on the orthographic projection is 0.5 ⁇ m.
- the present disclosure also provides a display panel, in which the anti-crack protection layer 41 can be formed synchronously with the first touch metal layer 701, and in the process, it is determined
- the alignment accuracy between the first anti-crack dam 42 and the first touch metal layer 701 is less than or equal to 0.2, and it is determined that the boundary of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 and the first anti-crack dam 42 on the lining
- the minimum distance between the orthographic boundaries on the base substrate 11 is 0.4 microns.
- the present disclosure also provides a display panel, in which the anti-crack protection layer 41 can be formed synchronously with the second touch metal layer 703, and in the process, it is determined
- the alignment accuracy between the first anti-crack dam 42 and the second touch metal layer 703 is less than or equal to 0.2, and it is determined that the boundary of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 and the first anti-crack dam 42 on the lining
- the minimum distance between the orthographic boundaries on the base substrate 11 is 0.4 microns.
- the present disclosure also provides a display panel, in which the first anti-crack dam 42 and the anti-crack protection Layers 41 are stacked on both sides of the encapsulation layer 12, and the orthographic projection of the first anti-crack dam 42 on the base substrate 11 at least partially covers the anti-crack protection layer 41 on the base substrate 11. Orthographic projection on .
- the orthographic projection of the first anti-crack dam 42 on the substrate 11 can completely cover the orthographic projection of the anti-crack protection layer 41 on the substrate 11 , and, the center position of the orthographic projection of the first anti-crack dam 42 on the base substrate 11 may coincide with the center position of the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 .
- both sides of the anti-crack protection layer 41 extend toward the recessed structure 200 on the encapsulation layer 12, so that the anti-crack protection layer 41 covers the recessed structure 200, so that the anti-crack protection layer 41 can Prevent water vapor from invading the display panel through the cracks and the water-oxygen channel formed by the organic light-emitting layer, and improve the stress concentration at the recessed structure 200 .
- the present disclosure also provides a display panel, in which the first anti-crack dam 42 and the anti-crack protection The layer 41 is dislocated on both sides of the encapsulation layer 12, and the orthographic projection of the anti-crack protection layer 41 on the base substrate 11 is located between two adjacent first crack dams 42 on the base substrate.
- the two sides of the anti-crack protective layer 41 extend toward the recessed structure 200 on the encapsulation layer 12, so that the anti-crack protective layer 41 covers the recessed structure 200, so that the anti-crack protective layer 41 It can prevent water vapor from invading the display panel through the cracks and the water-oxygen channel formed by the organic light-emitting layer, and improve the situation of stress concentration at the recessed structure 200 .
- the central position of the orthographic projection of the anti-crack protective layer 41 on the base substrate 11 can be in the gap formed by two adjacent first anti-crack dams 42 .
- the center positions of the orthographic projections on the base substrate 11 coincide.
- the present disclosure further provides a display panel, in which the anti-crack protection layer 41 includes first anti-crack The crack protection layer 401 and the second crack protection layer 403 and the touch insulating layer 402 located between the first crack protection layer 401 and the second crack protection layer 403 .
- the anti-crack protection layer 41 is a double layer
- the first anti-crack protection layer 401 and/or the second anti-crack protection layer 403 can be selected to cover the concave structure.
- the first anti-crack protection layer 401 when the first anti-crack protection layer 401 is selected to cover the recessed structure, it is only necessary to make the first anti-crack protection layer
- the orthographic projection of 401 on the base substrate 11 covers the orthographic projection of the recessed structure on the base substrate 11; as for the touch insulating layer 402 and the second anti-crack protection layer 403, they are normally formed on the first anti-crack layer. on the crack protection layer 401 , and the orthographic projection of the second crack protection layer 403 on the base substrate 11 does not exceed the orthographic projection of the first crack protection layer 401 on the base substrate 11 .
- the first anti-crack protection layer 401 and the second anti-crack protection layer 403 can also cover the recessed structure at the same time.
- the orthographic projection of the first anti-crack protection layer 401 on the base substrate 11 coincides with the orthographic projection of the second anti-crack protection layer 403 on the base substrate 11, and completely covers the concave structure on the base substrate 11. orthographic projection.
- the anti-crack protection layer 41 including the first anti-crack protection layer 401 and the second anti-crack protection layer 403 is set, and the first anti-crack protection layer 401 or the second anti-crack protection layer 403 covers the The concave structure, while using the double anti-crack protective layer 41 to improve the ability of the first anti-crack area 40 to prevent crack propagation, also realizes the elimination of the risk of water and oxygen intrusion channels formed by the organic light-emitting material layer and the reliability caused by the existence of cracks risk.
- Embodiments of the present disclosure further provide a display device, which includes the display panel described in any one of the above embodiments.
- the display device may include OLED (Organic Light-Emitting Diode, organic light-emitting diode) display screen, mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Select accordingly and will not repeat them here
- OLED Organic Light-Emitting Diode, organic light-emitting diode
- the display region 70 of the above-mentioned display panel and its manufacturing method will be introduced in combination with the pixel circuit and layout of the display region 70 in the display panel.
- FIG. 33 is an equivalent circuit diagram of a pixel circuit in a display area of a display panel provided by at least one embodiment of the present disclosure
- FIGS. 27-31 are individual circuit diagrams of a pixel circuit in a display area of a display panel provided in some embodiments of the present disclosure.
- FIG. 33 is an equivalent circuit diagram of a pixel circuit in a display panel provided by at least one embodiment of the present disclosure
- FIGS. 34-38 are schematic diagrams of layers of a pixel circuit in a display panel provided by some embodiments of the present disclosure.
- the pixel circuit located in the display area in the driving circuit layer includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, connected to a plurality of thin film transistors T1, T2 , T3, T4, T5, T6 and T7 a plurality of signal lines and storage capacitor Cst, a plurality of signal lines include gate line GL (ie scanning signal line), light emission control line EM, initialization line RL, data line DAT and the first Power supply line VDD.
- gate line GL ie scanning signal line
- EM light emission control line
- initialization line RL initialization line RL
- DAT data line
- VDD first Power supply line
- the gate lines GL may include a first gate line GLn and a second gate line GLn-1, for example, the first gate line GLn may be used to transmit a gate scan signal, and the second gate line GLn-1 may be used to transmit a reset signal.
- the light emission control line EM can be used to transmit light emission control signals.
- the pixel circuit is a 7T1C pixel circuit.
- the embodiments of the present disclosure include but are not limited thereto, and the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, etc., which are not limited in the embodiments of the present disclosure.
- the first gate line GLn of the pixel circuit corresponding to each row of light-emitting sub-pixels in the display area 70 located on the left and right sides of the opening area 20 in the display area 70 can be electrically connected to transmit the gate scanning signal through the gate signal line of the inner circle, so as to realize The compensation effect of the gate scan signal.
- the first gate G1 of the first TFT T1 is electrically connected to the third drain D3 of the third TFT T3 and the fourth drain D4 of the fourth TFT T4 .
- the first source S1 of the first TFT T1 is electrically connected to the second drain D2 of the second TFT T2 and the fifth drain D5 of the fifth TFT T5 .
- the first drain D1 of the first TFT T1 is electrically connected to the third source S3 of the third TFT T3 and the sixth source S6 of the sixth TFT T6 .
- the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scanning signal
- the second source S2 of the second thin film transistor T2 is configured to To be electrically connected to the data line DAT to receive data signals
- the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1 .
- the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line S3 of the first thin film transistor T1.
- a drain D1 is electrically connected, and the third drain D3 of the third TFT T3 is electrically connected to the first gate G1 of the first TFT T1.
- the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal
- the fourth source S4 of the fourth thin film transistor T4 is configured to To be electrically connected to the initialization line RL to receive the initialization signal
- the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate G1 of the first thin film transistor T1 .
- the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
- the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
- the first power line VDD is electrically connected to receive the first power signal
- the fifth drain D5 of the fifth TFT T5 is electrically connected to the first source S1 of the first TFT T1 .
- the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film
- the first drain D1 of the transistor T1 is electrically connected
- the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (eg, the first electrode 112 ) of the light-emitting sub-pixel.
- the seventh gate G7 of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, and the seventh source S7 of the seventh thin film transistor T7 is connected to the light emitting
- the first display electrode (such as the first electrode 112 ) of the sub-pixel is electrically connected, and the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization signal.
- the seventh drain D7 of the seventh thin film transistor T7 can be electrically connected to the initialization line RL by being connected to the fourth source S4 of the fourth thin film transistor T4 .
- the storage capacitor Cst includes a first capacitor electrode CE1 (ie, the first plate 130 ) and a second capacitor electrode CE2 (ie, the second plate 131 ).
- the second capacitive electrode CE2 is electrically connected to the first power line VDD
- the first capacitive electrode CE1 is electrically connected to the first gate G1 of the first TFT T1 and the third drain D3 of the third TFT T3.
- the second display electrode (for example, the second electrode 115 ) of the light-emitting sub-pixel 1d is electrically connected to the second power supply line VSS.
- first power line VDD and the second power line VSS are a power line providing a high voltage, and the other is a power line providing a low voltage.
- first power line VDD provides a constant first voltage, which is a positive voltage
- second power line VSS provides a constant second voltage, which can be a negative voltage. wait.
- the second voltage may be a ground voltage.
- transistors can be divided into N-type transistors and P-type transistors.
- the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type TFTs) as an example to elaborate
- the transistor T6 and the seventh thin film transistor T7 can be P-type transistors.
- the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can use N-type transistors (eg, N-type TFTs) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.
- N-type transistors eg, N-type TFTs
- the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
- the source and drain of the transistor may be symmetrical in structure, so there may be no difference in the physical structure of the source and the drain. In the embodiments of the present disclosure, the source and drain of all or part of the transistor may be are interchangeable.
- the pixel circuit includes the above-mentioned thin film transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, connected to a plurality of thin film transistors T1, T2, T3, T4 , the first gate line GLn, the second gate line GLn-1, the light emitting control line EM, the initialization line RL, the data line DAT and the first power line VDD of T5, T6 and T7.
- the structure of the pixel circuit will be described with reference to FIG. 33 and FIGS. 34-38.
- FIG. 34 is a schematic diagram of the stacked positional relationship among the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit.
- FIG. 35 shows semiconductor layers of a pixel circuit.
- the semiconductor layer shown in FIG. 35 includes the active layer 220 shown in FIG. 15 , FIG. 16 and FIG. 17 , and the active layer 220 is, for example, the active layer of the sixth thin film transistor T6 .
- the semiconductor layer can be formed by using a semiconductor material layer through a patterning process. The semiconductor layer can be used to make the above-mentioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6 and seventh thin film transistor T7.
- Source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
- the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
- an insulating layer is formed on the above-mentioned semiconductor layer, and the insulating layer includes the first gate insulating layer 113 shown in FIG. 15 , FIG. 16 and FIG. 17 , and FIGS. 34-38 not shown in
- Fig. 36 shows the first conductive layer of the pixel circuit.
- the first conductive layer of the pixel circuit is provided on the above-mentioned insulating layer so as to be insulated from the semiconductor layer shown in FIG. 35 .
- the first conductive layer may include the first capacitor electrode CE1 (equivalent to the first plate 225) of the storage capacitor Cst, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the first thin film transistor T1 , the gates of the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 (for example, the above-mentioned first gate G1, Second, second grid G2, third grid G3, fourth grid G4, fifth grid G5, sixth grid G6 and seventh grid G7).
- the first capacitor electrode CE1 equivalent to the first plate 225 of the storage capacitor Cst
- the first gate line GLn the second gate line GLn-1
- the light emission control line EM and the first thin film transistor T1
- the gates of the second thin film transistor T2 the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the
- the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are the first gate line GLn, the second gate line GLn- 1.
- the third thin film transistor T3 can be a thin film transistor with a double gate structure, and one gate of the third thin film transistor T3 can be the overlapped part of the first gate line GLn and the semiconductor layer.
- the other gate of the third thin film transistor T3 may be a protruding part protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first capacitive electrode CE1.
- the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively overlapping portions of the second gate line GLn-1 and the semiconductor layer.
- another insulating layer is formed on the above-mentioned first conductive layer, and the insulating layer includes the second gate insulating layer 114 shown in FIG. 15 , FIG. 16 and FIG. 17 , Not shown in Figures 27-31.
- Figure 37 shows the second conductive layer of the pixel circuit.
- the second conductive layer of the pixel circuit includes the second capacitive electrode CE2 of the storage capacitor Cst (ie, the second plate 226 ) and the initialization line RL.
- the second capacitive electrode CE2 at least partially overlaps with the first capacitive electrode CE1 to form a storage capacitor Cst.
- the second capacitive electrode CE2 shown in FIG. 37 has a notch, and in some embodiments, the second capacitive electrode CE2 may not have the notch.
- the embodiments of the present disclosure do not limit the specific structure of the second capacitive electrode CE2.
- the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792 .
- the orthographic projection of the first light-shielding portion 791 on the base substrate covers the active layer between the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3, and the drain of the fourth thin film transistor T4, thereby preventing External light affects the active layers of the second TFT T2 , the third TFT T3 and the fourth TFT T4 .
- the orthographic projection of the second light-shielding portion 792 on the base substrate covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
- the first light shielding portion 791 can be integrated with the second light shielding portion 792 of the adjacent pixel circuit, and is electrically connected to the first power supply line VDD through a via hole penetrating through the insulating layer.
- another insulating layer is formed on the above-mentioned second conductive layer, and the insulating layer includes the interlayer dielectric layer 115 shown in FIG. 15 , FIG. 16 and FIG. 17 . 34-38 not shown.
- Figure 38 shows the third conductive layer of the pixel circuit.
- the third conductive layer of the pixel circuit includes a data line DAT and a first power line VDD.
- the data line DAT is connected to the second via hole in the semiconductor layer through at least one via hole (for example, via hole VH1 ) in the first gate insulating layer 113 , the second gate insulating layer 114 and the interlayer dielectric layer 115 .
- the source regions of the two thin film transistors T2 are connected.
- the first power line VDD is connected to the source region corresponding to the fifth thin film transistor T5 in the semiconductor layer through at least one via hole (such as via hole VH2 ) in the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer.
- the first power line VDD is connected to the second capacitive electrode CE2 in the second conductive layer through at least one via hole (for example, via hole VH3 ) in the interlayer dielectric layer.
- the third conductive layer further includes a first connection part CP1 , a second connection part CP2 and a third connection part CP3 .
- One end of the first connection part CP1 is connected to the corresponding third thin film transistor T3 in the semiconductor layer through at least one via hole (for example, via hole VH4) in the first gate insulating layer 113, the second gate insulating layer 114, and the interlayer dielectric layer 115.
- the drain region is connected, and the other end of the first connection portion CP1 is connected to the first thin film transistor T1 in the first conductive layer through at least one via hole (such as via hole VH5) in the second gate insulating layer 114 and the interlayer dielectric layer 115. connected to the grid.
- One end of the second connection portion CP2 is connected to the initialization line RL through a via hole (such as the via hole VH6) in the interlayer dielectric layer, and the other end of the second connection portion CP2 passes through the first gate insulating layer 113, the second gate insulating layer 114 and at least one via hole (for example, via hole VH7 ) in the interlayer dielectric layer 115 is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
- a via hole such as the via hole VH6
- the third connection part CP3 is connected to the drain of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (such as the via hole VH8) in the first gate insulating layer 113, the second gate insulating layer 114, and the interlayer dielectric layer 115. Regions are connected.
- the pixel circuits of the display panel may further have a fourth conductive layer.
- FIG. 39 shows a fourth conductive layer of a pixel circuit.
- the fourth conductive layer includes a second power line VDD2 and a third power line VDD3, the second power line VDD2 extends along the vertical direction in the figure, the third power line VDD3 and the second power line VDD2 intersect.
- the second power line VDD2 and the third power line VDD3 are electrically connected to each other or have an integral structure.
- the second power line VDD2 and the third power line VDD3 are respectively electrically connected to the first power line VDD through via holes, thereby forming a mesh power line structure.
- This structure helps to reduce the resistance on the power line to reduce the voltage drop on the power line, and helps to evenly deliver the power supply voltage to each sub-pixel of the display panel.
- the fourth conductive layer further includes a fourth connection portion CP4 insulated from the second power line VDD2 and the third power line VDD3, and the fourth connection electrode is used to connect the sixth transistor T6 to The drain D6 is electrically connected to the light-emitting sub-pixel.
- the fourth connection electrode is implemented as the first transfer electrode 227 in the above embodiment, and is used to electrically connect the first pixel electrode 321 of the light-emitting sub-pixel to the drain 221 of the thin film transistor.
- a protection layer is formed on the above-mentioned fourth conductive layer, and the protection layer includes the planarization portion shown in FIG. 15 , FIG. 16 and FIG. 17 , and in FIGS. 34-38 not shown.
- the above conductive layers may also adopt other layouts.
- FIG. 40 shows another layout design of another second conductive layer pattern.
- the second conductive layer includes the second capacitor electrode CE2 of the storage capacitor Cst (that is, the second plate 226), the reset signal line Init1, the second power signal line VDD2, and the light shielding portion S .
- the second power signal line VDD2 is integrally formed with the second capacitive electrode CE2.
- FIG. 41 shows another layout design of another third conductive layer pattern.
- the third conductive layer includes a data line Vd, a first power signal line VDD1 and a shielding line PB.
- the data line Vd, the first power signal line VDD1 and the shielding line PB all extend along the same direction, such as the vertical direction in the figure.
- the third conductive layer may further include a first connection part CP1 , a second connection part CP2 and a third connection part CP3 for electrically connecting different wires or electrodes.
- FIG. 42 shows another layout design of another fourth conductive layer pattern.
- the fourth conductive layer includes a fourth connection portion CP4 and third power signal lines VDD3 distributed along the vertical and horizontal directions in the figure.
- the third power signal line VDD3 may be connected in parallel with the first power signal line VDD1 to form a mesh power structure, which is beneficial to reduce the resistance of the power signal line.
- references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
- any reference signs placed between parentheses shall not be construed as limiting the claim.
- the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
- the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
- the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
- the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.
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Abstract
显示面板。属于显示器件技术领域。该显示面板包括开孔区(20),设置有开孔;显示区(70),显示区(70)至少部分围绕开孔区(20);第一防裂区(40);显示面板在第一防裂区(40)还包括:至少一圈防裂保护层(41);显示区(70)包括至少一层触控电极层(71);其中,防裂保护层(41)与至少一层触控电极层(71)中的至少一层同层同材料设置。本公开中显示面板的防裂保护层(41),以提高挖孔周边区域的防裂能力。
Description
相关申请的交叉引用
本公开要求在2021年09月16日提交中国专利局、申请号为202111086347.9、名称为“一种显示面板及其制备方法、显示装置”的中国专利申请的优先权,其全部内容通过引用结合在本公开中。
本公开涉及显示器件技术领域,特别是涉及一种显示面板。
移动显示终端的便携性质以及用户的视觉感受,对显示屏幕提出了窄边框和轻薄化的要求。自全面屏概念出现后,为了提高屏幕的屏占比,各式设计的异形屏幕竞相出现,从刘海屏到水滴屏,再到目前主流的挖孔屏。使用挖孔孔径较小的屏幕,能够改善用户的使用体验,带来更好的沉浸感。相关技术已经提出在显示面板的显示区内部打孔并将摄像头、传感器等放置于孔内,以此提高屏占比,增强用户观看显示屏幕的视觉冲击感。
概述
根据本公开的第一方面,提供一种显示面板,包括:
开孔区,所述开孔区设置有开孔;
显示区,所述显示区至少部分围绕所述开孔区;和
第一防裂区,所述第一防裂区至少部分围绕所述开孔区;
所述显示面板在所述第一防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述封装层之上的至少一圈防裂保护层;并且
所述显示区包括至少一层触控电极层;
其中,所述防裂保护层与所述至少一层触控电极层中的至少一层同层同材料设置。
可选地,所述防裂保护层包括至少一层金属,所述触控电极层包括触控金属层。
可选地,所述衬底基板以及所述封装层延伸到所述显示区;所述触控金属层位于所述封装层背离所述衬底基板的一侧。
可选地,所述至少一层触控电极层包括更靠近所述封装层的第一触控金属层,第二触控金属层和位于所述第一触控金属层和所述第二触控金属层之间的绝缘层,所述防裂保护层与所述第一触控金属层同层同材料设置;
和/或者,所述防裂保护层与所述第二触控金属层同层同材料设置。
可选地,所述第一触控金属层为电极图案层,所述第二触控金属层为桥接层,所述桥接层通过贯穿所述触控介质层的过孔与至少部分所述电极图案层实现电连接。
可选地,所述防裂保护层包括层叠设置的第一防裂保护层和第二防裂保护层,所述第一防裂保护层设置于所述第二防裂保护层与所述衬底基板之间;并且
其中,所述第一防裂保护层与第一触控金属层同层同材料设置;
所述第二防裂保护层与所述第二触控金属层同层同材料设置。
可选地,所述防裂保护层包括金属或金属氧化物的单层或叠层结构。
可选地,所述金属包括以下至少一者:铜,钼,钛-铝-钛;所述金属氧化物包括:氧化铟锡。
可选地,所述衬底基板与所述封装层之间设置有至少一圈第一防裂坝;所述第一防裂坝与所述防裂保护层分布在所述封装层的两侧。
可选地,所述第一防裂坝与所述防裂保护层层叠设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影至少部分覆盖所述第一防裂坝在所述衬底基板上的正投影。
可选地,所述第一防裂坝与所述防裂保护层错位设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影位于相邻两所述第一防裂坝在所述衬底基板上的正投影之间。
可选地,所述显示面板还包括:围绕所述第一防裂区的止流区;
其中,所述衬底基板和所述封装层延伸到所述止流区,位于所述止流区的所述封装层与所述衬底基板之间还设置有止流坝。
可选地,所述显示面板还包括:围绕所述止流区的第二防裂区;所述显示面板在所述第二防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述第二防裂区的所述封装层与所述衬底基板之间设置有第二防裂坝。
可选地,所述防裂保护层与所述第一防裂坝和/或所述第二防裂坝在所述衬底基板上的正投影存在至少部分重叠区域。
可选地,所述封装层接触所述至少一圈第一防裂坝的区域和/或至少一圈第二防裂坝的区域至少包括一个凹陷结构,所述防裂保护层至少覆盖所述凹陷结构。
可选地,所述开孔在所述显示面板上设置有至少一个;
所述开孔的形状包括以下之一:圆形、条形和跑道状。
根据本公开的第二方面,提供另一种显示面板,包括:
开孔区,所述开孔区设置有开孔;
显示区,所述显示区至少部分围绕所述开孔区;和
第一防裂区,所述第一防裂区至少部分围绕所述开孔区;
所述显示面板在所述第一防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述封装层之上的至少一圈防裂保护层和位于所述封装层之下的至少一圈防裂坝;所述封装层接触所述至少一圈防裂坝的区域至少包括一个凹陷结构,所述防裂保护层至少覆盖所述凹陷结构。
可选地,所述第一防裂坝与所述防裂保护层层叠设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影至少部分覆盖所述第一防裂坝在所述衬底基板上的正投影。
可选地,所述第一防裂坝与所述防裂保护层错位设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影位于相邻两所述第一防裂坝在所述衬底基板上的正投影之间。
可选地,所述第一防裂坝至少包括一个防裂结构,使得所述封装层包括凹陷结构,所述凹陷结构至少包括一个垂直于所述衬底基板方向的台阶,所述防裂保护层至少部分覆盖住所述台阶。
可选地,所述凹陷结构包括至少两个第一表面和位于两个所述第一表面之间的第二表面,以及连接所述第一表面和所述第二表面的两个垂直于所述衬底基板方向的台阶,所述防裂保护层完全覆盖所述凹陷结构。
可选地,所述防裂保护层包括层叠设置的第一防裂保护层和第二防裂保护层,所述第一防裂保护层设置于所述第二防裂保护层与所述衬底基板之间;并且
所述第一防裂保护层至少部分覆盖所述凹陷结构,和/或,所述第二防裂保护层至少部分覆盖所述凹陷结构。
可选地,所述显示区包括至少一层触控电极层;
其中,所述防裂保护层与所述至少一层触控电极层中的至少一层同层同材料设置。
可选地,所述至少一层触控电极层包括更靠近所述衬底基板的第一触控金属层,第二触控金属层和位于所述第一触控金属层和所述第二触控金属层之间的触控介质层,所述防裂保护层与所述第一触控金属层同层同材料设置;
和/或者,所述防裂保护层与所述第二触控金属层同层同材料设置。
上述说明仅是本公开技术方案的概述,为了能够更清楚了解本公开的技术手段,而可依照说明书的内容予以实施,并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂,以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案,下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1示出了本公开实施例提供的一种显示面板的整体示意图;
图2示出了本公开实施例提供的一种显示面板的衬底基板的截面示意图;
图3示出了本公开实施例提供的一种显示面板在C-D方向的截面示意图;
图4示出了本公开实施例提供的一种具有条形开孔的显示面板的整体示意图;
图5示出了本公开实施例提供的一种具有两个开孔的显示面板的整体示意图;
图6示出了本公开实施例提供的一种裂纹阻挡示意图;
图7示出了本公开实施例提供的一种触控电极层的截面示意图;
图8示出了本公开实施例提供的一种防裂保护层的第一方式分布示意图;
图9示出了本公开实施例提供的一种防裂保护层的第一方式分布的平面示意图;
图10示出了本公开实施例提供的一种防裂保护层的第二方式分布示意图;
图11示出了本公开实施例提供的一种防裂保护层的第二方式分布的平面示意图;
图12示出了本公开实施例提供的一种触控电极走线的平面示意图;
图13示出了本公开实施例提供的一种具有整体防裂保护层的显示面板的整体示意图;
图14示出了本公开实施例提供的一种具有多圈防裂保护层的显示面板的整体示意图;
图15示出了本公开实施例提供的一种显示面板在A-B方向的截面示意图;
图16示出了本公开实施例提供的另一种显示面板在A-B方向的截面示意图;
图17示出了本公开实施例提供的另一种显示面板在A-B方向的截面示意图;
图18示出了本公开实施例提供的一种显示面板的制备方法的步骤流程图;
图19示出了本公开实施例提供的一种形成第一防裂保护层的示意图;
图20示出了本公开实施例提供的一种形成触控绝缘层的示意图;
图21示出了本公开实施例提供的一种具有凹陷结构的封装层的结构示意图;
图22示出了本公开实施例提供的一种防裂保护层覆盖封装层的凹陷结构的示意图;
图23示出了本公开实施例提供的一种防裂保护层按第一方式分布且覆盖封装层的凹陷结构的示意图;
图24示出了本公开实施例提供的一种防裂保护层按第一方式分布且覆盖封装层的凹陷结构的平面示意图;
图25示出了本公开实施例提供的一种防裂保护层按第二方式分布且覆盖封装层的凹陷结构的示意图;
图26示出了本公开实施例提供的一种防裂保护层按第二方式分布且覆盖封装层的凹陷结构的平面示意图;
图27示出了本公开实施例提供的一种多层防裂保护层覆盖封装层的凹陷结构的示意图;
图28示出了本公开实施例提供的一种多层防裂保护层覆盖封装层的凹陷结构的平面示意图;
图29示出了本公开实施例提供的另一种多层防裂保护层覆盖封装层的凹陷结构的示意图;
图30示出了本公开实施例提供的另一种多层防裂保护层覆盖封装层的凹陷结构的平面示意图;
图31示出了本公开实施例提供的另一种多层防裂保护层覆盖封装层的凹陷结构的示意图;
图32示出了本公开实施例提供的另一种多层防裂保护层覆盖封装层的凹陷结构的平面示意图;
图33示出了本公开实施例提供的一种显示面板中显示区的像素电路的等效电路图;
图34-38示出了本公开实施例提供的一种显示面板中显示区的像素电路的各层的版图设计;
图39示出了本公开实施例提供的一种显示面板中显示区的像素电路的一个导电层的版图设计;
图40示出了本公开实施例提供的一种显示面板中显示区的的像素电路的第二导电层的另一版图设计;
图41示出了本公开实施例提供的一种显示面板中显示区的的像素电路的第三导电层的另一版图设计;
图42示出了本公开实施例提供的一种显示面板中显示区的的像素电路的第四导电层的另一版图设计。
详细描述
相关技术中提出在显示模组上集成触控功能,比如,触控显示一体化 (Flexible Multi-Layer On Cell,FMLOC)技术可将触控信号层直接制作在显示层和封装层之上,以此获得更轻薄的屏幕背板厚度以及更窄的下边框,并能够节约显示面板的制造成本,是目前有机发光二极管(Organic Light-Emitting Diode,OLED)显示屏发展的趋势。
在显示区挖孔屏幕的相关技术中提出的显示面板,虽然对显示区内的挖孔区域的膜层结构进行了优化,一定程度上减弱了显示区开孔的边缘的无机封装层开裂向显示区的蔓延,以此防止显示面板挖孔周边的显示/触控区的显示层和触控层开裂,保障了显示面板的显示效果和触控效果。
然而,考虑到相关技术中提出的显示面板结构以显示层相关的金属信号线作为防裂装置,实现的挖孔区域的防裂效果是有限的,也就是说,目前的显示屏幕实现了在显示区内的挖孔,并在一定程度上实现了裁切边缘防裂,但是挖孔区域的防裂能力仍然有待提高。本公开考虑结合触控显示一体化技术中触控信号层的制备实现过程与结构位置,提出将触控层的的相关结构作为挖孔区域的防裂装置,提高显示面板挖孔区域边缘的裂纹阻挡能力。因此,本公开提出了一种显示面板、一种显示面板的制备方法和一种显示装置,通过在显示面板的显示区内的开孔裁切区域周边的第一防裂区设置与显示区触控金属层同层的金属材质的触控防裂层,对开孔边缘裂纹的应力进行传导分散,能够在不改变现有的制备总体工艺流程的前提下,提高显示区打孔的显示面板的挖孔周边显示区域的防裂能力。
为使本公开的上述目的、特征和优点能够更加明显易懂,下面结合附图和具体实施方式对本公开作进一步详细的说明。
参照图1,图1是本公开实施例提供的一种显示面板的整体示意图。如图1所示,显示面板整体结构是基于衬底基板11的,在此之上,显示面板上大致可以划分为显示区70,边框区80,信号连接区90。
具体地,衬底基板11可以为柔性基板或者刚性基板。衬底基板11为柔性基板时,可以使得显示面板具有可弯曲或可弯折等性能;衬底基板11为刚性基板时,则可以满足显示面板的刚性需求;具体衬底基板11的性能根据产品的实际需求进行确定。
另外,衬底基板可以包括单层结构或多层结构。示例性地,如图2所示,该衬底基板可以包括依次层叠设置的聚酰亚胺层和缓冲层;在其他的实施方式中,衬底基板也可以包括多个依次层叠设置的聚酰亚胺层和缓冲层。其中,缓冲层可以选用氮化硅或氧化硅等材料制作而成,以达到阻隔水氧和阻隔碱性离子的效果。需要说明的是,该衬底基板的结构不限于此,在具体应用时,可以根据实际需求进行确定。
该显示面板的显示区70中存在开孔区20,也即是在该显示面板中,显示区70至少部分围绕所述开孔区20。示例性地,开孔区20可以完全位于显示 区70所在的范围内,此时,开孔区20周围均为显示区70;开孔区20也可以部分位于显示区70所在的范围内,此时显示区70部分围绕开孔区20。其中,在环绕开孔区20的开孔的周围区域,设置有防裂保护层41。
参照图3,图3是本公开实施例提供的一种显示面板的截面示意图。如图3所示,所述显示面板包括:开孔区20、切割剩余区30、第一防裂区40。
需要说明的是,为了便于在显示面板的各区域加工所需部件,可以先在衬底基板上定义出各个区域。示例性地,可以先在衬底基板上划分出显示区70、边框区80、信号连接区90、开孔区20、切割剩余区30和第一防裂区40,即在显示面板上划分出显示区70、边框区80、信号连接区90、开孔区20、切割剩余区30和第一防裂区40。
其中,所述开孔区20设置有开孔21。具体地,该开孔21可以是贯穿封装层12和衬底基板11的过孔,即,通孔;该开孔21还可以是不贯穿显示面板的凹孔。
具体地,所述切割剩余区30是围绕所述开孔区20的一圈区域。切割剩余区30可以是加工得到包括开孔区20的显示面板的过程中,对围绕开孔区20的一圈切割区进行切割后剩余的一圈区域。开孔区20,即显示面板的显示区70内的挖孔区域,其内镂空的空间可以用于放置摄像头以及各类传感器。
具体地,所述第一防裂区40至少部分围绕所述开孔区20。示例性地,在开孔区20完全位于显示区70所在的范围的情况下,第一防裂区40为设置在显示区70以及开孔区20之间的一圈区域;在开孔区20部分位于显示区70所在的范围的情况下,第一防裂区40为不完整的设置在开孔区20和显示区70之间的一段区域。
参照图1所示,开孔21的边缘即是在所述显示面板的显示区70内挖孔的裁切边缘。也是切割剩余区30的边缘。示例性地来说,开孔区20可以是圆形孔区,则切割剩余区30可以是环绕开孔区20的一圈圆环区域,第一防裂区40可以是环绕切割剩余区30圆环的一圈圆环区域。
此外,在一种可选的实施方式中,如图4所示,开孔区20内也可以是条形孔区,此时切割剩余区30和第一防裂区则为依次环绕开孔区20的一圈条形区域;条形孔是由两组相连的直线部分和弧线部分围成的封闭形状的孔;在一种可选的实施方式中,开孔21的形状还可以为跑道状。
在一种可选的实施方式中,如图5所示,开孔区20还可以设置两个开孔21,在显示区70与两个开孔21之间的区域即为第一防裂区40;在其他实施方式中,开孔区20内还可以设置更多数量的开孔21。
其中,所述显示面板在所述第一防裂区40还包括:衬底基板11、位于所述衬底基板11之上的封装层12、位于所述封装层12之上的至少一圈防裂保护层41。
进一步地,若开孔21为凹孔,该凹孔的开孔外表面可以与封装层12背离衬底基板11的表面齐平,也可以与衬底基板11背离封装层12的表面齐平。
其中,所述封装层12可以包括依次层叠设置的第一无机封装膜层、有机封装膜层和第二无机封装膜层,第一无机封装膜层和第二无机封装膜层可以由分别两次化学气相沉积获得,也可以采用物理气相沉积工艺形成,第一无机封装膜层和第二无机封装膜层的材料可以选用氮化硅、氧化硅等无机材料;有机封装膜层采用喷墨打印工艺制作,也可以采用喷涂工艺形成,有机封装膜层的材料可以采用丙烯酸基聚合物、硅基聚合物等材料;第一防裂区40的封装层12可以是整个显示面板的封装层的一部分,该处的封装层12可以向开孔区20方向延伸到切割剩余区30,还可以向显示面板的显示区70延伸,以对整个衬底基板11上整个显示面板的电路元器件进行封装,保护电路元器件不受水汽、氧气的侵蚀,以及,对整个显示面板形成结构保护。
因此,与封装层12的延伸相对应的,位于第一防裂区40的衬底基板11也可以是整个显示面板的衬底基板的一部分,该处的衬底基板11可以向开孔区20方向延伸到切割剩余区30,还可以向显示面板的显示区70延伸。
其中,一方面来说,所述防裂保护层41用于对开孔区20裁切产生的裂纹进行阻挡,防止挖孔时切割导致的封装层12裂纹蔓延至显示面板的显示区域、触控区域的封装层12,进而避免造成封装层12所保护的内部的发光层、触控电极层的破坏。另一方面来说,所述防裂保护层41与显示区域对应的触控电极层71同层设置,材质可以一致,制备上也可以同步形成。因此,在本公开实施例中,可以与触控电极层一致的,所述防裂保护层41可以是金属材质,进而满足挖孔边缘防裂对材料延展性的要求。
参照图1所示,为了摆脱整个显示面板对额外的触控功能组件的依赖,在申请实施例中,所述显示面板在所述第一防裂区40远离所述开孔21的一侧还包括显示区70;所述显示区70包括至少一层触控电极层71,所述触控电极层71包括触控金属层,且防裂保护层41包括至少一层金属。
其中,所述触控电极层71用于实现显示面板的显示区70的触控功能,显示区70与显示面板的触控区域重叠或部分重叠。
为了进一步便于实现触控电极层71和防裂保护层41的制备形成,所述防裂保护层41与所述触控电极层71中的至少一层在所述显示面板中同层同材料设置。
其中,所述同层同材料设置可以是所述防裂保护层41与所述触控电极层71中的至少一层在所述显示面板的层次结构中位于同一层且制备材料相同,进一步地,防裂保护层41与触控电极层71中的至少一层可以在制备时由同一步工艺形成,并不限定要求防裂保护层41与触控电极层71中的至少一层在相对衬底基板11平面的垂直方向上处于同一平面,即在垂直于衬底基板11 平面的方向上,防裂保护层41距离衬底基板11的尺寸与触控电极层71中的至少一层距离衬底基板11的尺寸可以不相同。
在本公开实施例中,防裂保护层41可以是基于触控显示一体化技术制备的触控电极层71的对应层,即形成于同一层,因此,本公开可以看作是利用触控显示一体化触控图案的金属层制备挖孔周边的防裂结构,当然,这样做还可以有利于进一步通过对防裂保护层41的功能性设置,实现显示面板的显示区70和非显示区域的触控功能的统一。
参照图6,图6是本公开实施例提供的一种裂纹阻挡示意图。如图6所示,通过上述实施例,本公开实施例提出的显示面板,在围绕开孔区20切割区域的第一防裂区40设置有至少一圈防裂保护层41,防裂保护层41为绕孔环状,当从孔边缘区域产生的封装层12裂纹扩散遇到由金属制作的防裂保护层41,防裂保护层41的金属走线可以对开孔21边缘裂纹的应力起到传导分散的作用,经过至少一圈防裂保护层41的拦阻,裂纹在原方向上的扩散能力会逐步衰减直至消失,使得显示面板基于防裂保护层41金属材质的良好的延展性,能够防止开孔区20切割导致的挖孔边缘裂纹蔓延至显示面板的显示区域、触控区域,有效提升显示面板显示区域、触控区域的防裂能力,保障显示面板的显示效果和触控功能。
在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述衬底基板11以及所述封装层12延伸到所述显示区70。
与防裂保护层41所处层次结构相对应的,所述触控电极层71位于所述封装层12背离所述衬底基板11的一侧。
示例性地,显示区70的触控电极层71的触控金属层可以位于显示区70位置区域的封装层12的上方,可以与封装层12背离衬底基板11的一侧表面接触;则防裂保护层41也可以对应位于第一防裂区40位置区域的封装层12的上方,并对应地与封装层12背离衬底基板11的一侧表面接触。
参照图7,图7是本公开实施例提供的一种触控金属层的截面示意图。如图7所示,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述至少一层触控电极层71包括层叠设置的第一触控金属层701、第二触控金属层703以及位于第一触控金属层701和第二触控金属层之间的触控介质层702;其中,所述第一触控金属层701设置于所述第二触控金属层703与所述衬底基板11之间,即第一触控金属层701更靠近衬底基板11,而第二触控金属层703较第一触控金属层701更接近封装层12。
具体地,防裂保护层41可以与第一触控金属层701同层同材料设置,或者,防裂保护层41也可以与第二触控金属层703同层同材料设置。即,在制备显示面板时,防裂保护层41可以与第一触控金属层701在同一步工艺中形成,防裂保护层41也可以与第二触控金属层703在同一步工艺中形成。
具体地,所述触控电极层71可以用于作为显示面板表面的触控图形的信号线,用于传递触控信号,以对外部针对显示面板所在的显示装置的触摸动作进行响应,进而实现显示面板的触控功能。
其中,第一触控金属层701可以是桥接层,即作为桥接所述触控电极的走线的一部分,第二触控防裂层703可以是电极图案层,即作为触控电极的走线的一部分。
进一步地,为了实现第一触控金属层701和第二触控防裂层703各自所起的作用,所述触控介质层702中存在用于连接所述第一触控金属层701和所述第二触控金属层703的通孔。
进一步地,在所述第一触控金属层701背离所述第二触控金属层703的一侧,还设置有触控基底层704,用于对第一触控金属层701进行隔离保护;在所述第二触控金属层703背离所述第一触控金属层701的一侧,还设置有触控保护层705,用于对第二触控金属层703进行隔离保护。
如图7所示,所述触控介质层702中的通孔,可以用于在形成第二触控金属层703时,在通孔内形成与第二触控金属层703一体的金属结构,该金属结构可以与第一触控金属层701进行连接,实现电性连接,进而使第一触控金属层701和第二触控金属层703配合实现触控功能。
具体地,触控介质层702可以选用无机材料,例如SiO
2或SiNx;触控介质层702也可以选用有机材料,例如树脂或UV胶,在本公开实施例中,对此不做具体限定。
在一种可选的实施方式中,第一触控金属层701和第二触控金属层703之间也可以不设置触控介质层702。
参照图8,图8是本公开实施例提供的一种双层防裂保护层的第一方式分布示意图。或者,参照图10,图10是本公开实施例提供的一种双层防裂保护层的第二方式分布示意图。如图8或图10所示,为了与触控电极层71的形成与层次结构相适应,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述防裂保护层41包括层叠设置的第一防裂保护层401和第二防裂保护层403。
其中,所述第一防裂保护层401设置于所述第二防裂保护层403与所述衬底基板11之间,所述第一防裂保护层401设置于所述第二防裂保护层403与所述衬底基板11之间。
其中,所述第一防裂保护层401和所述第二防裂保护层403之间设置有触控绝缘层402,所述触控绝缘层402可以包覆所述第一防裂保护层401,触控绝缘层402可以对所述第一防裂保护层401和所述第二防裂保护层403进行电学绝缘分离,以使所述第一防裂保护层401和所述第二防裂保护层403分别执行相应的电学功能。
其中,所述第一防裂保护层401与所述第一触控金属层701对应同层同材料设置,触控绝缘层402与所述触控介质层702对应同层同材料设置,所述第二防裂保护层403与所述第二触控金属层703对应同层同材料设置。
具体地,对于包括所述第一防裂保护层401和所述第二防裂保护层403的防裂保护层41来说,与触控电极层71的层次结构相对应的,由于包含了双层叠构金属,每一圈防裂保护层41的厚度可以是0.8μm至1.2μm,例如0.8μm、0.9μm、1μm、1.1μm、1.2μm等等。
通过上述实施例,包括所述第一防裂保护层401和所述第二防裂保护层403的防裂保护层41能够对开孔边缘的裂纹进行双重效果的阻挡,更加有效地防止边缘裂纹蔓延至挖孔周边区域的显示区/触控区,保障显示区域的显示效果和触控效果。
参照图12,图12是本公开实施例提供的一种防裂保护层的触控电极走线的平面示意图。如图12所示,上述实施例提出了在第一防裂区40设置触控防裂层41的显示面板,可以提升显示屏幕的开孔区20周边区域的防裂能力,而该触控防裂层41还可以用于实现显示面板在挖孔周边区域的触控功能,而摆脱对额外的触控功能组件的依赖。
与显示区70的触控金属层71相同或相似的,每一圈触控防裂层41可以通过边框区80的触控电极的走线,连接周边电极或者接地电极。需要注意的是,图12提供的内容,仅用于对触控防裂层41与电极的连接走线进行简单示意,不对走线的内部排布产生限定。
为此,在可选的一种实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂保护层401为触控电极的走线的一部分,所述第二防裂保护层403为桥接所述触控电极的走线的一部分。
其中,触控电极的走线,以及,桥接所述触控电极的走线均连接到触控芯片91上,触控芯片91用于对走线提供的触控信号进行处理和响应。
其中,防裂保护层41也即可以是触控电极的触控信号线的一部分,对于显示面板来说,至少显示面板的显示区70对应的触控信号线能够根据用户对显示面板相应位置的触摸行为进行响应,由此完成用户对显示面板相应终端的控制,使得显示面板无需增加额外的触摸功能组件,比如:无需提供触控功能传感器膜材或者外玻璃触控层,也能在显示面板的挖孔周边提供触控功能,保障触控功能的实现。考虑到防裂保护层41与显示面板的显示区70的触控信号线可以同时制备形成,至少一圈防裂保护层41中每一圈防裂保护层41的厚度可以与显示面板的显示区70对应的触控信号线的厚度一致,具体地,对于单层金属结构的防裂保护层41来说,每一圈防裂保护层41的厚度可以是0.4μm-0.6μm。
图12简单示出了连接第一防裂保护层701和第二防裂保护层703的触控 电极的平面走线,实际上第二防裂保护层桥接的触控电极的走线还可以与第一防裂保护层的触控电极的走线可以位于显示面板垂直方向中的不同层。在此基础上,第一防裂保护层401和第二防裂保护层403还可以用于配合实现显示面板在开孔区20周边黑边(Black Mask,BM)区域的触控功能。为了使第一防裂保护层401和第二防裂保护层403配合实现第一防裂区40的触控功能,至少一圈的所述触控绝缘层402中还可以存在贯通该圈的第一防裂保护层401和第二防裂保护层403的开孔,所述开孔中设置用于连接所述第一防裂保护层401和第二防裂保护层403的走线的金属线,以使第一防裂保护层401和第二防裂保护层403配合实现第一防裂区40的触控功能。
通过上述实施例,沿用了触控电极层71中第一触控金属层701与第二触控金属层703之间的功能关系,与触控金属层71实现显示区域的触控功能相对应的,防裂保护层41可以利用双层叠构的防裂保护层41实现挖孔周边区域的触控功能。
为了便于制备形成,所述第一防裂保护层401与所述第一触控金属层701同层同材料形成,所述触控绝缘层402与所述触控介质层702对应同层同材料形成,所述第二防裂保护层403与所述第二触控金属层703同层同材料形成,则同层形成结构的材质、厚度等均可以相同。
即,所述第一防裂保护层401与所述第一触控金属层701的材质可以相同,所述触控绝缘层402与所述触控介质层702的材质可以相同,所述第二防裂保护层403与所述第二触控金属层703的材质可以相同。为进一步便于制备形成,触控绝缘层402的材质可以与封装层12的材质还可以相同。为了实现触控并提升触控性能,触控绝缘层402还可以是更加容易实现高精度制备的材料材质,和/或者,电学绝缘性能比封装层12的电学绝缘性能更好的材料材质。
在一种可选的实施方式中,如图13所示,本公开还提供一种显示面板,在所述显示面板中,防裂保护层41的第一防裂保护层401和第二防裂保护层403不连接至显示面板的外侧作为PCD线使用,即第一防裂保护层401和第二防裂保护层403不与边框区80的触控电极的走线连接;并且,在该实施方式中,防裂保护层41设置为整体结构。
具体地,由于第一防裂区40是围绕开孔区20的一圈区域,而第一防裂区40在显示面板的平面方向上具有一定的宽度(即第一防裂区40靠近开孔区20的一侧到第一防裂区40靠近显示区70的一侧之间的距离),在这个宽度内,防裂保护层41需要将第一防裂区内的封装层12至少部分覆盖,因此显示面板可以包括围绕开孔区的至少一圈防裂保护层41。
参照图13,图13示出了一种显示面板的平面结构示意图。如图13所示,在防裂保护层41为一圈结构的情况下,防裂保护层41可以为一个整体结构。 示例性地,此时,防裂保护层41在显示面板平面方向上的宽度可以与第一防裂区40在显示面板平面方向的宽度相同,如此,便可以使得防裂保护层41将第一防裂区40区域内的封装层12完全覆盖,从而防止开孔区20切割导致的挖孔边缘裂纹蔓延至显示面板的显示区域、触控区域,有效提升显示面板显示区域、触控区域的防裂能力,保障显示面板的显示效果和触控功能。
参照图14,图14示出了另一种显示面板的平面结构示意图。如图14所示,在防裂保护层41包括多圈结构的情况下,每一圈防裂保护层41独立地设置在封装层12上。此时,防裂保护层41包括以同一圆心呈同心圆状间隔排列在第一防裂区40内的多个圆环形部分。在图7中,防裂保护层41包括四圈结构,因此在第一防裂区40内,防裂保护层41表现为以同一圆心呈同心圆状分布的四个圆环部分,并将第一防裂区40内的封装层12部分覆盖,此时多圈的防裂保护层41可以进一步地阻止开孔区20的裂缝的蔓延至显示面板的显示区域。
目前的FMLOC技术将触控信号层直接制作在显示层和封装层12之上,综合考虑制备精度、电导性能、材料延展性、成本、工艺成熟程度等多种因素,通常采用钛-铝-钛(Ti-Al-Ti)作为触控功能材料。
其中,钛-铝-钛是一种三层的金属层叠膜,包括上层的由钛或者主要由钛构成的钛基层、中间的由铝或主要由铝构成的铝金属层、和作为下层的由钛或者主要由钛所构成的钛基金属层。在钛-铝-钛的三层金属层叠膜中,钛膜能够起到防止铝层氧化的作用,铝膜用于作为导电材料,进行电信号的传输。
考虑到挖孔BM区域的宽度小,防裂保护层41的精度要求较高,且需要防裂保护层41的材料需要具有高延展性,以阻挡封装层12裂纹从挖孔区域蔓延到显示区域和触控区域,因此,防裂保护层41还可以是综合考虑制备精度和延展性的金属材质,并不局限于钛-铝-钛。
上述实施例已经提到,本公开实现了利用显示区70的触控电极层71的制备形成,实现挖孔周边位置的防裂保护层的层次结构,进而实挖孔边缘裂纹阻挡。因此,在一种可选的实施方式中,可以与防裂保护层71的层次结构相对应的,所述防裂保护层包括金属或金属氧化物的单层或叠层结构。
进一步地,在一种可选的实施方式中,所述金属包括以下至少一者:铜,钼,钛-铝-钛;
所述金属氧化物包括:氧化铟锡。
进一步地,考虑到第一防裂保护层401和第二防裂保护层403各自对应的显示区的触控信号线用于实现整个防裂保护层41的触控功能的作用存在差异,为了提高防裂保护层41的触控性能和裂纹阻挡能力,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂保护层401和所述第二防裂保护层的402材质互不相同。即,同一圈的第一 防裂保护层401和第二防裂保护层403的材质可以互不相同。其中,所述第一防裂保护层401和所述第二防裂保护层的402的材质可以是电学性能存在差异的两种材质。
示例性地,第一防裂保护层401可以是氧化铟锡材质,第二防裂保护层403可以是钛-铝-钛质。
更进一步地,第一防裂保护层401和第二防裂保护层403在第一防裂区40的绝缘层上存在上下层关系,在阻挡裂纹时所起的作用可以不同,因此,第一防裂保护层401和第二防裂保护层403的材质还可以是延展性存在差异的两种材质。
示例性地,第一防裂保护层401可以是钼材质,第二防裂保护层403可以是氧化铟锡材质。
考虑到显示面板的显示区70的封装层12与衬底基板11之间存在众多元器件,而在本公开实施例中,第一防裂区40是BM区域的一部分,由于无需提供显示功能,第一防裂区40主要只有衬底基板11、封装层12比较占用空间,显示面板的第一防裂区40“空置”空间较多,为了充分利用“空置”空间,并实现对裂纹的阻挡,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板的第一防裂区40中,所述衬底基板11与所述封装层12之间设置有至少一圈第一防裂坝42。
其中,所述第一防裂坝42可以是金属材质,以用于第一防裂区40进一步阻挡开孔边缘裂纹向显示区70方向的蔓延。
其中,所述第一防裂坝42与所述防裂保护层41按照第一方式和/或第二方式分布在所述封装层12的两侧。
具体地,所述至少一圈防裂保护层41可以设置在所述封装层12上与所述多圈第一防裂坝42相对应的位置区域。进一步的,与所述多圈第一防裂坝42相对应的位置区域,可以是第一防裂坝42背离衬底基板11的上方位,还可以是第一防裂坝42指向开孔区20方向或者指向显示区70方向的侧方位。
具体地,防裂保护层41的圈数可以与第一防裂坝42相同,以降低制备制造的难度,提高阻挡裂纹的效果。防裂保护层41的圈数还可以与第一防裂坝42不相同,以实现特定的触控图形的走线,实现挖孔周边区域相应的触控功能。
在本公开实施例中,通过将至少一圈防裂保护层41与所述第一防裂坝42分布在所述封装层12的两侧,可以与第一防裂坝42组合对显示面板的开孔21的裂纹向显示区70方向的蔓延进行阻挡,有助于提升裂纹阻挡效果。
如图8和图9所示,为了进一步提升裂纹阻挡效果,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂坝42与所述防裂保护层41按照第一方式分布在所述封装层12的两侧,所述 第一方式为:所述第一防裂坝42与所述防裂保护层41层叠设置在所述封装层12的两侧,所述第一防裂坝42在所述衬底基板11上的正投影至少部分覆盖所述防裂保护层41在所述衬底基板11上的正投影。
进一步地,参见图8和图9,所述第一防裂坝42在所述衬底基板11上的正投影可以完全覆盖所述防裂保护层41在所述衬底基板11上的正投影,并且,所述第一防裂坝42在所述衬底基板11上的正投影的中心位置可以与所述防裂保护层41在所述衬底基板11上的正投影的中心位置重合。
进一步地,参见图8和图9,每一圈所述防裂保护层41可以设置在所述封装层12上的第一区域,其中,所述第一区域为正对所述第一防裂坝42正上方的位置区域,以使所述防裂保护层41和所述第一防裂坝42对称设置在所述封装层12的上下两侧。
其中,所述正上方是指以衬底基板11的表面为水平面,与该水平面垂直的方向上远离衬底基板11的方向。
通过本公开实施例,将一圈防裂保护层41与第一防裂坝42设置为投影重合的关系,使每一圈防裂保护层41可以规则地与该圈防裂保护层41下方的第一防裂坝42构成至少一组的第一防裂组合单元,这样的第一防裂组合单元形成了阻挡主要在封装层12中的开孔21裂纹蔓延的“多堵高墙”,能够增强对主要由封装层12所引起的裂纹的拦阻能力,提升显示面板防裂效果。
如图10和图11所示,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂坝42与所述防裂保护层41按照第二方式分布在所述封装层12的两侧;所述第二方式为:所述第一防裂坝42与所述防裂保护层41错位设置在所述封装层12的两侧,所述防裂保护层41在所述衬底基板11上的正投影位于相邻两所述第一防裂坝42在所述衬底基板11上的正投影之间。
进一步地,参见图10和图11,所述防裂保护层41在所述衬底基板11上的正投影的中心位置可以与相邻两所述第一防裂坝42构成的间隙在所述衬底基板11上的正投影的中心位置重合。
进一步的,参见图10和图11,每一圈防裂保护层41可以设置在所述封装层12上的第二区域,其中,所述第二区域为与相邻两圈所述第一防裂坝42构成的间隙所对应的区域上,以使所述防裂保护层41和所述第一防裂坝42交错设置在所述封装层12的两侧。
其中,相邻两圈所述第一防裂坝42构成的间隙所对应的区域,是指相邻两圈所述第一防裂坝42之间的封装层12之间形成的间隙。
通过本公开实施例,设置防裂保护层41与第一防裂坝42间隔区域的投影重合,使每一圈防裂保护层41可以规则地与左右相邻的两圈第一防裂坝42构成“夹心式”的第二防裂组合单元,这样的第二防裂单元形成了阻挡主要 在封装层12中的开孔21裂纹蔓延的“一堵厚墙”,能够增强对裂纹的拦阻能力,提升显示面板防裂效果。
更进一步地,为了便于满足防裂保护层41的触控电极的走线需求和/或裂纹阻挡需求,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂坝42与所述防裂保护层41按照第一方式和第二方式分布在所述封装层12的两侧;其中,部分圈数的所述第一防裂坝42与所述防裂保护层41按照第一方式分布在所述封装层12的两侧,剩余圈数的所述第一防裂坝42与所述防裂保护层41按照第二方式分布在所述封装层12的两侧。
具体地,所述至少一圈防裂保护层41中的目标防裂保护层41设置在所述封装层12上的第一区域。其中,目标防裂保护层41,即部分圈数的防裂保护层。其中,所述第一区域为正对所述第一防裂坝42正上方的位置区域;其中,所述目标防裂保护层41为所述至少一圈防裂保护层41中的部分圈的触控防裂层41。以及,所述至少一圈防裂保护层41中除所述目标防裂保护层41外的剩余防裂保护层41设置在所述封装层12上的第二区域,其中所述第二区域为与相邻两圈所述第一防裂坝42构成的间隙所对应的区域上,以使所述剩余部分数量的每一圈防裂保护层41和所述第一防裂坝42交错设置在所述封装层12的两侧。
通过本公开实施例,第一防裂坝41同时按照第一方式和第二方式分布在所述封装层12的两侧,则其中部分圈数的目标防裂保护层41按照第一方式分布,相对于剩余防裂保护层41,可以保持位于更加远离衬底基板11的位置,则可以基于该位置关系满足开孔区20周边区域的特定的触控图形的走线需求和/或裂纹阻挡需求,同时按照两种分布方式分布的防裂保护层41与第一防裂坝42形成进行上下位置关系的组合、交错式的组合,同样能够增强对裂纹的拦阻能力,提升显示面板防裂效果。
显示面板的开孔切割造成边缘碎裂的程度是存在差异的,在一些较为极端的场景下,如果裂纹向内蔓延,显示面板的开孔21位置的封装层12和衬底基板11甚至会出现脱开的情况,而防裂保护层41金属的延展性也是有限的,这种情况下防裂保护层41提供的触控功能容易遭到破坏。为了进一步提高显示面板的防裂效果,并且,也为了防止防裂保护层41遭到破坏而影响开孔区20周边区域的触控功能,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板的第一防裂区40中,所述衬底基板11以及所述封装层12延伸到所述切割剩余区30;所述显示面板还包括凹凸结构31,所述凹凸结构31位于所述切割剩余区30的所述封装层12和所述衬底基板11之间。
其中,所述凹凸结构31可以是至少一圈,至少一圈所述凹凸结构31可 以依次围绕所述开孔区20分布。所述凹凸结构31中包括第一凹凸结构,第一凹凸结构到开孔21的最小间距为0微米-30微米,至少一个所述凹凸结构31具有背离所述衬底基板11的表面,以及与所述表面连接的侧面,其中,所述表面、所述侧面中的至少一者呈凹凸状,所述第一凹凸结构为距离所述开孔区20中心距离最小的所述凹凸结构31。
通过本公开实施例,提供了一种显示面板,该显示面板在相较第一防裂区40来说更靠近开孔21的切割剩余区30设置了凹凸结构31,能够更好地应对极端情况下开孔21碎裂可能对防裂保护层41造成的破坏,增强显示面板挖孔边缘防脱裂的能力,也可以在防裂保护层41用于实现开孔区20周边区域的触控功能的情况下,保障显示面板在开孔区20周边区域的触控功能。
对于防裂保护层41来说,除了要应对可能来自开孔区20方向的碎裂情况,还需要应对来自显示区70方向的油墨外溢的情况,为此,参照图3所示,在一种可选的实施方式中,本公开还提供了一种显示面板,所述显示面板还包括:围绕所述第一防裂区40的止流区50。
其中,所述衬底基板11和所述封装层12延伸到所述止流区50,位于所述止流区50的所述封装层12与所述衬底基板11之间还设置有止流坝51。
具体地,止流坝51可以是多圈,多圈止流坝51可以依次围绕第一防裂区40分布。
通过本公开实施例,提供了一种显示面板,该显示面板在第一防裂区40向显示区70的方向设置了多圈止流坝51,能够防止显示面板的油墨外溢,避免损害显示面板的外观、功能,也可以在触控防裂层用于实现开孔区20周边区域的触控功能的情况下,避免影响防裂保护层41的触控功能的实现。
为了进一步与防裂保护层41匹配实现更强的显示面板防裂能力,参照图3所示,在一种可选的实施方式中,本公开还提供了一种显示面板,所述显示面板还包括:围绕所述止流区50的第二防裂区60;所述显示面板在所述第二防裂区60还包括:衬底基板11、位于所述衬底基板11之上的封装层12、位于第二防裂区60的所述封装层12与所述衬底基板11之间还设置有第二防裂坝61。
其中,第二防裂坝61可以是多圈,多圈第二防裂坝61可以依次围绕止流区50分布。并且,防裂保护层41与第一防裂坝42和/或第二防裂坝61在衬底基板11上的正投影存在至少部分重叠区域。
通过本公开实施例,提供了一种显示面板,该显示面板在更接近显示区70的位置区域设置多圈第二防裂坝61,不仅可以配合防裂保护层41对开孔21的碎裂进一步向显示区70蔓延提供阻挡的效果,还可以应对显示面板从显示区70碎裂的情况,避免裂纹进一步向防裂保护层41所在的开孔区20方向的位置蔓延,防止对防裂保护层41造成破坏,可以在防裂保护层41用于实 现开孔区20周边区域的触控功能的情况下,保障显示面板开孔区20周边的触控功能。
在一种可选的实施方式中,如图8或图10所示,本公开还提供了一种显示面板,所述显示面板在所述第一防裂区40还包括:位于封装层与所述衬底基板之间的至少一层金属层。
具体地,参照图8和图10所示,在图8和图10中,所述至少一层金属层包括第一金属层101和第二金属层102,其中,第一金属层101位于第二金属层102与衬底基板11之间,并且第一金属层101作为电极层,第二金属层102作为桥接层。并且,第一金属层101和第二金属层102在所述衬底基板11上的正投影与防裂保护层41在所述衬底基板11上的正投影至少部分重叠。
通过本公开实施例,提供了一种显示面板,该显示面板在第一防裂区40的封装层12和衬底基板11之间还设置了第一金属层101和第二金属层102,利用第一金属层101和第二金属层102可以更有利于实现利用防裂保护层41在开孔区20周边区域的触控功能。
在一种可选的实施方式中,如图15所示,本公开还提供了一种显示面板,该显示面板在显示区70还包括:依次层叠设置在所述衬底基板11与所述封装层12之间的驱动电路层和发光层32。
具体地,驱动电路层中位于显示区70的部位可包括薄膜晶体管和电容结构。
如图15所示,薄膜晶体管可为顶栅型,此薄膜晶体管可包括有源层220、第一栅绝缘层113、栅极224、第二栅绝缘层114、层间介质层115、源极222、漏极221。具体地,有源层220可形成在缓冲层112上,第一栅绝缘层113覆盖缓冲层112及有源层220,栅极224形成在第一栅绝缘层113背离有源层220的一侧,第二栅绝缘层114覆盖栅极224和第一栅绝缘层113,层间介质层115覆盖第二栅绝缘层114,源极222和漏极221形成在层间介质层115背离衬底基板11的一侧并分别位于栅极224的相对两侧,该源极222和漏极221可分别通过过孔(例如:金属过孔)与有源层220的相对两侧接触。应当理解的是,此薄膜晶体管也可为底栅型。
如图15所示,电容结构可包括第一极板225和第二极板226,此第一极板225与栅极224同层设置,第二极板226位于第二栅绝缘层114与层间介质层115之间,并与第一极板225相对设置。
举例而言,栅极224和第一极板225、第二极板226的材料可以包括金属材料或者合金材料,例如包括钼、铝及钛等。源极222和漏极221可以包括金属材料或者合金材料,例如由钼、铝及钛等形成的金属单层或多层结构,例如,该多层结构为多金属层叠层,例如钛、铝、钛三层金属叠层(Al/Ti/Al)等
如图15所示,发光层32包括依次形成在层间介质层上的第一像素电极321和像素界定部117,应当理解的是,该显示器件还可包括发光部322和第二像素电极323。
具体地,在显示区70的薄膜晶体管为顶栅型时,在制作显示器件之前还可制作平坦化层116,此平坦化层可为单层结构,也可为多层结构;此平坦化层通常采用有机材料制作而成,例如:光刻胶、丙烯酸基聚合物、硅基聚合物等材料;如图13所示,此平坦化层116可包括位于显示区70的平坦化部,平坦化部形成在层间介质层115与第一像素电极321之间。其中,第一像素电极321可通过金属过孔与漏极221电性连接,该第一像素电极321可为阳极,此阳极可为ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等材料制作而成;像素界定部117可覆盖平坦化部,此像素界定部117可为有机材料制作而成,例如:光刻胶等有机材料,且像素界定部117中位于显示区70的部分可具有露出第一像素电极321的像素开口;发光部322位于像素开口内并形成在第一像素电极321上,该发光部322可包括小分子有机材料或聚合物分子有机材料,可以为荧光发光材料或磷光发光材料,可以发红光、绿光、蓝光,或可以发白光等;并且,根据实际不同需要,在不同的示例中,发光部322还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层;第二像素电极323覆盖发光部322,且该第二像素电极323的极性与第一像素电极321的极性相反;此第二像素电极323可为阴极,此阴极可为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料制作而成。
需要说明的是,如图15所示,第一像素电极321、发光部322和第二像素电极323可构成一个发光子像素。其中,显示器件中位于显示区70的部分可包括多个阵列排布的发光子像素。此外,还需说明的是,各发光子像素的第一像素电极321相互独立,各发光子像素的第二像素电极323整面连接;即第二像素电极323为设置在显示面板上的整面结构,为用于多个显示器件的公共电极。
在一种可行的实施方式中,如图15所示,像素界定部117背离层间介质层115的一侧还可设置支撑部118,该支撑部118可起到支撑保护膜层(图中未示出)的作用,以避免保护膜层与第一像素电极321或其他走线接触而导致第一像素电极321或其他走线容易损坏的情况。需要说明的是,此保护膜层主要出现在半成品转移的过程中,以避免转移过程中半成品出现损坏的情况,具体地:在将制作完支撑部118的基板转移到蒸镀产线的过程中,可覆盖一层保护膜层,当需要进行发光材料的蒸镀时,而将保护膜层移除。
举例而言,支撑部118的材料可与像素界定部117的材料相同,且支撑部118与像素界定部117可采用同一次构图工艺形成,但不限于此,支撑部118的材料也可与像素界定部117的材料不同,且支撑部118与像素界定部 117也可采用不同构图工艺形成。
在一种可行的实施方式中,如图16所示,第一像素电极321还可通过第一转接电极227与漏极221电性连接。当第一像素电极321通过第一转接电极227与漏极221电性连接时,该平坦化部可为双层结构,具体可包括依次形成的第一平坦化膜(PLN1)层181及第二平坦化膜(PLN2)层182,此外,在第一平坦化膜层181与层间介质层115之间还可形成第一钝化膜(PVX)层190,该钝化膜层190可由氧化硅、氮化硅或者氮氧化硅等材料形成;该第一钝化膜层190覆盖源极222、漏极221,需要说明的是,在平坦化部为单层时,平坦化部与层间介质层115之间也可形成钝化膜层;而第一转接电极227形成在第一平坦化膜层181与第二平坦化膜层182之间,并依次通过第一平坦化膜层181及第一钝化膜层190上的过孔(例如金属过孔)与漏极221电性连接;而第一像素电极321可通过第二平坦化膜层182上的过孔(例如金属过孔)与第一转接电极227电性连接,如图16所示。但不限于此,第一转接电极227也可形成在第一平坦化膜层181与第一钝化膜层190之间。
在一种可行的实施方式中,如图17所示,驱动电路层还包括第二转接电极228,第一像素电极321可通过第二转接电极228和第一转接电极227与漏极221电性连接。在第一像素电极321通过第二转接电极228和第一转接电极221与漏极221电性连接时,如前文所述,还平坦化部除了包括依次形成的第一平坦化膜层181和第二平坦化膜层182外,还包括有第三平坦化膜层183,第三平坦化膜层183形成在第二平坦化膜层182远离第一平坦化膜层181的一侧,此外,在第三平坦化膜层183与第二平坦化膜层182之间还可形成第二钝化膜层(图中未示出);第二转接电极228形成在第三平坦化膜层183与第二平坦化膜层182之间,并通过第二平坦化膜层182上的过孔与第一转接电极227电性连接;而第一转接电极依次通过第一平坦化膜层181及第一钝化膜层190上的过孔(例如金属过孔)与漏极221电性连接;而第一像素电极321可以通过第三平坦化膜层183及第二钝化膜层上过孔与第二转接电极228电性连接;第二转接电极228也可形成在第二平坦化膜层182与第二钝化膜层之间。
参照图18,图18是本公开实施例提供的一种显示面板的制备方法的步骤流程图。如图18所示,本公开实施例还提供了一种显示面板的制备方法,所述方法包括:
S31,在衬底基板11的封装区域上形成封装层12。
在本公开实施例中,封装层12的制备方法是现有技术,显示区域、触控区域的衬底基板11和封装层12之间的电子元器件及膜层,包括发光层等,均可以由现有技术制备完成,在此不再赘述。
S32,在所述封装层12的表面标记出第一防裂区40,切割区以及预开孔区;其中,所述第一防裂区40围绕所述切割区,所述切割区围绕所述预开孔区。
具体地,可以通过电荷耦合元件(Charge-coupled Device,CCD)视觉检测技术对前述步骤中得到的结构进行对准抓取,再利用预设的加工区域图像对该结构的封装层12的表面进行标记。其中,预设的加工区域图像至少包括预设的第一防裂区40图像,预设的切割区图像以及预设的开孔区图像。
其中,切割区至少包含切割打孔后的留下的切割剩余区30。开孔区的中心位置对应切割打孔后的得到的开孔区20的中心位置。
S33,在所述封装层12的所述第一防裂区40之上形成至少一圈防裂保护层41;其中,所述防裂保护层41是金属材质。
具体地,防裂保护层41的制备可以利用现有的FMLOC技术,在此不再赘述具体做法。
S34,在形成所述至少一圈防裂保护层41后,在所述封装层12的所述切割区对准所述开孔区进行打孔,得到显示面板;其中,所述显示面板中包括进行所述打孔后得到设置有开孔21的开孔区20,以及,围绕所述开孔区20的切割剩余区30。
其中,显示面板的打孔切割方法也是现有技术,比如,其中,打孔可以采用镭射切割,因此不再赘述具体做法。
为了提高制备得到的显示面板的开孔区20周边区域阻挡开孔21裂纹的效果,以及,提高在显示面板制备的开孔切割过程中阻挡开孔21裂纹的效果,在一种可选的实施方式中,本公开还提供了一种制备至少一圈双层防裂保护层41的方法,包括:
S41,在所述封装层12的所述第一防裂区40之上形成至少一圈第一防裂保护层401。
参见图19,图19是本公开实施例提供的一种形成第一防裂保护层的示意图。如图19所示,可以通过掩膜沉积或者刻蚀的方式,在所述封装层12上第一防裂区40的多圈第一防裂坝42正上方的位置区域和/或者相邻两圈第一防裂坝42构成的间隙所对应的区域上,制备至少一圈第一防裂保护层401。
S42,在所述至少一圈第一防裂保护层401的每一圈第一防裂保护层401上,制备触控绝缘层402,得到至少一圈触控绝缘层402。
参见图20,图20是本公开实施例提供的一种形成触控绝缘层的示意图。如图20所示,在前述步骤是在所述封装层12上第一防裂区40的多圈第一防裂坝42正上方的位置区域制备第一防裂保护层401的情况下,则触控绝缘层402也对应在第一防裂保护层401上的第一防裂坝42正上方的位置区域,这种情况下,还可以在每一圈第一防裂保护层401的侧表面进行触控绝缘层402 的制备,以使制备得到的每一圈的所述触控绝缘层402对该圈所述第一触控防裂层401进行包裹。
其中,防裂保护层41的材料可以选用封装层12相同或相似的材料,防裂保护层41的制备方法也可以与封装层12一样选用气相沉积掩膜法。其中,还可以通过掩膜制备触控绝缘层402,使至少一圈的所述触控绝缘层402中存在贯通该圈的第一防裂保护层401和第二防裂保护层403的开孔。该方法可以通过在与贯通第一防裂保护层401和第二防裂保护层403的开孔对应的预设孔位进行掩膜处理,得到贯通所述第一防裂保护层401和第二防裂保护层403的开孔,其具体的制备过程采用现有技术即可,因此不再赘述。
S43,在所述至少一圈触控绝缘层402的每一圈触控绝缘层402之上,制备第二防裂保护层403,得到至少一圈第二防裂保护层403。
参见图8或图10,本公开实施例得到每一圈的第一防裂保护层401、触控绝缘层402、第二防裂保护层403组成该圈的防裂保护层41。
其中,防裂保护层41中各层对应的显示区域的各层触控金属层和介质层可以用于共同配合实现所在位置区域的显示面板的触控功能,而环绕开孔21的防裂保护层41可以阻挡显示面板的开孔21裂纹蔓延至显示区70,甚至防裂保护层41也可以实现开孔21周边区域的触控功能。
通过上述实施例提供的显示面板的制备方法,实现了在显示面板开孔21裁切区域周边的第一防裂区40制备单层或者双层的金属材质的防裂保护层41,以将得到的防裂保护层41用于提高显示区70打孔显示面板的开孔21周边显示区域的防裂纹能力,以及,无需增加额外的触控单元组件,也可以实现开孔周边区域的触控功能。
在制备显示面板的过程中,封装层12与第一防裂坝42之间还设置有有机发光层,而第一防裂坝42通常为钛-铝-钛(Ti-Al-Ti)膜层,考虑到有机发光层材料有较好的爬坡特性,通常将钛-铝-钛(Ti-Al-Ti)膜层中的铝层向内刻蚀一部分,使得顶层的钛层与中间的铝层形成一个内部陷入的结构,未被刻蚀的顶层的钛层形成一定长度的帽檐,从而阻断爬坡的有机发光层材料。但由于有机发光材料层优异的爬坡性能使其存在形成水氧侵入通道的风险。
并且,如图21所示,在沉积封装层12的时候,受限于自身的成膜特性,封装层12材料爬坡后内侧成膜速率小,外侧成膜速率大,最终导致在封装层12远离第一防裂坝42的一侧表面形成至少一个凹陷结构200,具体地,凹陷结构200位于顶层的钛层的两侧,而在封装层12上凹陷结构200所在的位置容易出现裂缝,裂缝的产生会导致该处应力集中,从而导致该位置存在信赖性风险。
为了消除有机发光材料层形成水氧侵入通道的风险和消除裂缝存在引起的信赖性风险,本公开实施例提供另一种显示面板,如图3所示,该显示面 板包括开孔区20、显示区70和第一防裂区40。
具体地,所述显示区70至少部分围绕所述开孔区20,所述第一防裂区40位于所述显示区70与所述开孔区20之间,且所述第一防裂区40至少部分围绕所述开孔区20。
进一步地,参照图22所示,所述显示面板在所述第一防裂区40还包括:衬底基板11、位于所述衬底基板11之上的封装层12、位于所述封装层12之上的至少一圈防裂保护层41和位于所述封装层12之下的至少一圈第一防裂坝42;所述封装层12接触所述至少一圈第一防裂坝42的区域至少包括一个凹陷结构200,所述防裂保护层41至少覆盖所述凹陷结构200。
具体地,所述第一防裂坝42至少包括一个凹凸结构,在第一防裂坝42为钛-铝-钛(Ti-Al-Ti)膜层的情况下,若顶层的钛层远离衬底基板11的面为顶面,第一防裂坝42的凹凸结构则表现为顶层的钛层与中层的铝层之间形成的朝向铝层内侧凹陷的侧面,在沉积封装层12时,由于封装层12自身的成膜特性,封装层12在所述凹陷的侧面的位置会形成一个凹陷结构200,而由于第一防裂坝具有两个凹陷的侧面,因此封装层12会形成两个凹陷结构200。
并且,所述凹陷结构200至少包括一个垂直于所述衬底基板11方向的台阶,所述防裂保护层41至少覆盖住所述台阶。即防裂保护层41在衬底基板11上的正投影与所述台阶在所述衬底基板11上的正投影至少部分重叠。
通过本公开实施例,防裂保护层41将封装层12表面的凹陷结构200至少部分覆盖,一方面可以完整阻挡水汽借由裂缝和有机发光层形成的水氧通道侵入显示面板,另一方面,封装层12的凹陷结构200位置被金属材料的防裂保护层41覆盖后,由于金属层间结合力较强,因此可以有效改善裂缝处产生应力集中的问题。
在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述凹陷结构200包括至少两个第一表面和位于两个所述第一表面之间的第二表面,以及连接所述第一表面和所述第二表面的两个垂直于所述衬底基板方向的台阶,所述防裂保护层41完全覆盖所述凹陷结构200。
具体地,封装层12覆盖到第一防裂坝42上后,会形成两个平行于衬底基板11的平面,这两个平面即所述两个第一表面,而第二表面则为两个第一表面之间的相对于衬底基板11倾斜的表面,连接第二表面和两个第一表面的为两个垂直于衬底基板22方向的台阶,如此组成了封装层12接触第一防裂坝42后形成的凹陷结构200。防裂保护层41完全覆盖凹陷结构200,即防裂保护层41完全覆盖两个第一表面和第二表面,并且如图23和图24所示,防裂保护层41在衬底基板11上的正投影完全覆盖凹陷结构200在衬底基板11上的正投影。
通过本公开实施例,防裂保护层41将封装层12表面的凹陷结构200完 全覆盖,可以更好地阻挡水汽借由裂缝和有机发光层形成的水氧通道侵入显示面板并改善凹陷结构处产生应力集中的情况,从而增加显示面板的使用寿命。
如图22所示,防裂保护层41的侧面相对于衬底基板11的平面方向倾斜设置,该侧面与衬底基板11平面方向之间的倾斜角度可以为20°-40°,例如20°、25°、30°、40°等等。
为了保证防裂保护层41可以完整覆盖凹陷结构200,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,防裂保护层41在衬底基板11上的正投影覆盖第一防裂坝42在衬底基板11上的正投影;且防裂保护层41在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离大于或等于0.4微米,且小于或等于0.5微米,以保证防裂保护层41可以完整覆盖封装层12上的凹陷结构200。
同时,如前文所述,防裂保护层41可以和触控电极层71中的第一触控金属层701同层同材料设置,或者,防裂保护层41可以和触控电极层71中的第二触控金属层702同层同材料设置。即在制备显示面板的过程中,防裂保护层41可以和第一触控金属层701同步成型,也可以和第二触控金属层702同步成型,防裂保护层41的材料和厚度可以与第一触控金属层701或第二触控金属层702相同。
具体地,在形成防裂保护层41时,只需更改位于第一防裂区40的第一触控金属层701或第二触控金属层702的掩模板,并且严格管控第一防裂坝42与第一触控金属层701或第二触控金属层702之间的对位精度;同时,还需要控制防裂保护层41在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离。
例如,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,防裂保护层41可以与第一触控金属层701同步成型,在该过程中,确定第一防裂坝42与第一触控金属层701之间的对位精度小于或等于0.3,确定防裂保护层41在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离为0.5微米。
在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,防裂保护层41可以与第二触控金属层703同步成型,在该过程中,确定第一防裂坝42与第二触控金属层703之间的对位精度小于或等于0.3,确定隔断层在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离为0.5微米。
在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,防裂保护层41可以与第一触控金属层701同步成型,在该过程中,确定第一防裂坝42与第一触控金属层701之间的对位精度小于或等于0.2, 确定防裂保护层41在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离为0.4微米。
在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,防裂保护层41可以与第二触控金属层703同步成型,在该过程中,确定第一防裂坝42与第二触控金属层703之间的对位精度小于或等于0.2,确定防裂保护层41在衬底基板11上的正投影边界与第一防裂坝42在衬底基板11上的正投影边界之间的最小距离为0.4微米。
参照图23和图24所示,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂坝42与所述防裂保护层41层叠设置在所述封装层12的两侧,所述第一防裂坝42在所述衬底基板11上的正投影至少部分覆盖所述防裂保护层41在所述衬底基板11上的正投影。
进一步地,参见图23和图24,所述第一防裂坝42在所述衬底基板11上的正投影可以完全覆盖所述防裂保护层41在所述衬底基板11上的正投影,并且,所述第一防裂坝42在所述衬底基板11上的正投影的中心位置可以与所述防裂保护层41在所述衬底基板11上的正投影的中心位置重合。并且,在本公开实施例中,防裂保护层41的两侧向封装层12上的凹陷结构200进行了延伸,使得防裂保护层41将凹陷结构200覆盖,从而使得防裂保护层41可以阻挡水汽借由裂缝和有机发光层形成的水氧通道侵入显示面板并改善凹陷结构200处产生应力集中的情况。
如图25和图26所示,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述第一防裂坝42与所述防裂保护层41错位设置在所述封装层12的两侧,所述防裂保护层41在所述衬底基板11上的正投影位于相邻两所述第一防裂坝42在所述衬底基板11上的正投影之间,并且,防裂保护层41的两侧向封装层12上的凹陷结构200进行了延伸,使得防裂保护层41将凹陷结构200覆盖,从而使得防裂保护层41可以阻挡水汽借由裂缝和有机发光层形成的水氧通道侵入显示面板并改善凹陷结构200处产生应力集中的情况。
进一步地,参见图25和图26,所述防裂保护层41在所述衬底基板11上的正投影的中心位置可以与相邻两所述第一防裂坝42构成的间隙在所述衬底基板11上的正投影的中心位置重合。
参照图27和图28所示,在一种可选的实施方式中,本公开还提供了一种显示面板,在所述显示面板中,所述防裂保护层41包括层叠设置的第一防裂保护层401和第二防裂保护层403以及位于第一防裂保护层401和第二防裂保护层403之间的触控绝缘层402。在防裂保护层41为双层的情况下,可以选择使第一防裂保护层401和/第二防裂保护层403覆盖所述凹陷结构。
具体地,如图27和图28所示,在选择第一防裂保护层401覆盖所述凹 陷结构时,只需在制备第一防裂保护层401的过程中,使第一防裂保护层401在所述衬底基板11上的正投影覆盖所述凹陷结构在所述衬底基板11上的正投影;至于触控绝缘层402和第二防裂保护层403则正常形成在第一防裂保护层401上,并且第二防裂保护层403在衬底基板11上的正投影不超出第一防裂保护层401在衬底基板11上的正投影。
如图29和图30所示,在选择第二防裂保护层403覆盖所述凹陷结构时,则需要在制备完成第一防裂保护层401和触控绝缘层402后,使第二防裂保护层403的边界延伸,并最终使第二防裂保护层403超出所述第一防裂保护层401的部分将所述凹陷结构覆盖,此时第二防裂保护层403在衬底基板11上的正投影则会超出第一防裂保护层401在衬底基板11上的正投影。
如图31和图32所示,在一种可行的实施方式中,还可以使第一防裂保护层401和第二防裂保护层403同时覆盖凹陷结构。此时,第一防裂保护层401在衬底基板11上的正投影和第二防裂保护层403在衬底基板11上的正投影重合,且完全覆盖凹陷结构在衬底基板11上的正投影。
通过本公开实施例,设置包括第一防裂保护层401和第二防裂保护层403的防裂保护层41,并使第一防裂保护层401或第二防裂保护层403覆盖所述凹陷结构,在利用双重的防裂保护层41提高了第一防裂区40阻止裂纹蔓延能力的同时,也实现了消除有机发光材料层形成水氧侵入通道的风险和消除裂缝存在引起的信赖性风险。
本公开实施例还提供了一种显示装置,所述显示装置包括上述任一项实施例所述的显示面板。
具体地,显示装置可以包括OLED(OrganicLight-Emitting Diode,有机发光二极管)显示屏、手机等移动装置、手表等可穿戴设备、VR装置等等,本领域技术人员可根据该显示设备的具体用途进行相应地选择,在此不再赘述
下面,结合显示面板中显示区70的像素电路以及版图对上述显示面板的显示区70及其制备方法进行介绍。
图33为本公开至少一实施例提供的一种显示面板中显示区的像素电路的等效电路图,图27-31为本公开一些实施例提供的一种显示面板中显示区的像素电路的各层的版图设计。
图33为本公开至少一实施例提供的一种显示面板中的像素电路的等效电路图,图34-38为本公开一些实施例提供的一种显示面板中的像素电路的各层的示意图。
在一些实施例中,如图33所示,驱动电路层中位于显示区的像素电路包括多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多条信号线和存储电容Cst,多条信号线 包括栅线GL(即扫描信号线)、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。栅线GL可包括第一栅线GLn和第二栅线GLn-1,例如第一栅线GLn可用于传输栅极扫描信号,第二栅线GLn-1可用于传输复位信号。发光控制线EM可用于传输发光控制信号。由此,像素电路为7T1C的像素电路。
需要说明的是,本公开实施例包括但并不限于此,像素电路也可采用其他类型的电路结构,例如7T2C结构或者9T2C结构等,本公开实施例对此不作限制。
例如,可以通过内圈栅极信号线将显示区70中位于开孔区20左右两侧的每行发光子像素对应的像素电路的第一栅线GLn电连接以传输栅极扫描信号,从而实现栅极扫描信号的补偿效果。
例如,如图33所示,第一薄膜晶体管T1的第一栅极G1与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如,如图33所示,第二薄膜晶体管T2的第二栅极G2被配置为与第一栅线GLn电连接以接收栅极扫描信号,第二薄膜晶体管T2的第二源极S2被配置为与数据线DAT电连接以接收数据信号,第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如,如图33所示,第三薄膜晶体管T3的第三栅极G3被配置为与第一栅线GLn电连接,第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏极D1电连接,第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极G1电连接。
例如,如图33所示,第四薄膜晶体管T4的第四栅极G4被配置为与第二栅线GLn-1电连接以接收复位信号,第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化信号,第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极G1电连接。
例如,如图33所示,第五薄膜晶体管T5的第五栅极G5被配置为与发光控制线EM电连接以接收发光控制信号,第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号,第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如,如图33所示,第六薄膜晶体管T6的第六栅极G6被配置为与发光控制线EM电连接以接收发光控制信号,第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接,第六薄膜晶体管T6的第六漏极D6与发光子像素的第一显示电极(例如:第一电极112)电连接。
例如,如图33所示,第七薄膜晶体管T7的第七栅极G7被配置为与第二栅线GLn-1电连接以接收复位信号,第七薄膜晶体管T7的第七源极S7与发光子像素的第一显示电极(例如第一电极112)电连接,第七薄膜晶体管T7的第七漏极D7被配置为与初始化线RL电连接以接收初始化信号。例如,第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如,如图33所示,存储电容Cst包括第一电容电极CE1(即:第一极板130)和第二电容电极CE2(即:第二极板131)。第二电容电极CE2与第一电源线VDD电连接,第一电容电极CE1与第一薄膜晶体管T1的第一栅极G1和第三薄膜晶体管T3的第三漏极D3电连接。
例如,如图33所示,发光子像素1d的第二显示电极(例如第二电极115)与第二电源线VSS电连接。
需要说明的是,第一电源线VDD和第二电源线VSS之一为提供高电压的电源线,另一个为提供低电压的电源线。在如图33所示的实施例中,第一电源线VDD提供恒定的第一电压,第一电压为正电压;而第二电源线VSS提供恒定的第二电压,第二电压可以为负电压等。例如,在一些示例中,第二电压可以为接地电压。
需要说明的是,上述的复位信号和上述的初始化信号可为同一信号。
还需要说明的是,按照晶体管的特性,晶体管可以分为N型晶体管和P型晶体管,为了清楚起见,本公开的实施例以晶体管为P型晶体管(例如,P型TFT)为例详细阐述了本公开的技术方案,也就是说,在本公开的描述中,第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管,本领域技术人员还可以根据实际需要利用N型晶体管(例如,N型TFT)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是,本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件,薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的,所以其源极、漏极在物理结构上可以是没有区别的,本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
在一些实施例中,如图34所示,像素电路包括上述的薄膜晶体管T1、T2、T3、T4、T5、T6和T7、存储电容Cst、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。下面,结合图33和图34-38 对像素电路的结构进行说明。
例如,图34为像素电路的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的示意图。
图35示出了像素电路的半导体层。例如,图35所示的该半导体层包括图15、图16和图17中所示的有源层220,该有源层220例如为第六薄膜晶体管T6的有源层。如图35所示,半导体层可采用半导体材料层通过构图工艺形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层,各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如,半导体层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是,上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开一些实施例提供的显示面板中,在上述的半导体层上形成有绝缘层,该绝缘层包括图15、图16和图17中所示的第一栅绝缘层113,图34-38中未示出。
图36示出了像素电路的第一导电层。例如,如图36所示,像素电路的第一导电层设置在上述绝缘层上,从而与图35所示的半导体层绝缘。第一导电层可包括存储电容Cst的第一电容电极CE1(相当于第一极板225)、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极(例如,上述的第一栅极G1、第,二栅极G2、第三栅极G3、第四栅极G4、第五栅极G5、第六栅极G6和第七栅极G7)。如图36所示,第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1、发光控制线EM与半导体层交叠的部分,第三薄膜晶体管T3可为双栅结构的薄膜晶体管,第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分,第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部;第一薄膜晶体管T1的栅极可为第一电容电极CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管,两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
在本公开一些实施例提供的显示面板中,在上述的第一导电层上形成有另一绝缘层,该绝缘层包括图15、图16和图17中所示的第二栅绝缘层114,图27-31中未示出。
图37示出了像素电路的第二导电层。例如,如图37所示,像素电路的第二导电层包括存储电容Cst的第二电容电极CE2(即:第二极板226)和初始化线RL。第二电容电极CE2与第一电容电极CE1至少部分重叠以形成存 储电容Cst。
例如,图37示出的第二电容电极CE2具有缺口,在一些实施例中,第二电容电极CE2也可以不具有该缺口。本公开的实施例对第二电容电极CE2的具体结构不做限定。
在一些实施例中,第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层,从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层,从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素电路的第二遮光部792为一体结构,并通过贯穿绝缘层中的过孔与第一电源线VDD电连接。
在本公开一些实施例提供的显示面板中,在上述的第二导电层上形成有另一绝缘层,该绝缘层包括图15、图16和图17中所示的层间介质层115,图34-38中未示出。
图38示出了像素电路的第三导电层。例如,如图38所示,像素电路的第三导电层包括数据线DAT和第一电源线VDD。结合图34和图38所示,数据线DAT通过第一栅绝缘层113、第二栅绝缘层114和层间介质层115中的至少一个过孔(例如过孔VH1)与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD通过第一栅绝缘层、第二栅绝缘层和层间介质层中的至少一个过孔(例如过孔VH2)与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD通过层间介质层中的至少一个过孔(例如过孔VH3)与第二导电层中的第二电容电极CE2相连。
例如,第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过第一栅绝缘层113、第二栅绝缘层114和层间介质层115中的至少一个过孔(例如过孔VH4)与半导体层中对应第三薄膜晶体管T3的漏极区域相连,第一连接部CP1的另一端通过第二栅绝缘层114和层间介质层115中的至少一个过孔(例如过孔VH5)与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过层间介质层中的一个过孔(例如过孔VH6)与初始化线RL相连,第二连接部CP2的另一端通过第一栅绝缘层113、第二栅绝缘层114和层间介质层115中的至少一个过孔(例如过孔VH7)与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过第一栅绝缘层113、第二栅绝缘层114和层间介质层115中的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。
例如,在一些实施例中,显示面板的像素电路还可以具有第四导电层。 例如,图39示出了像素电路的第四导电层。如图39所示,该第四导电层包括第二电源线VDD2和第三电源线VDD3,该第二电源线VDD2沿图中的竖直方向延伸,第三电源线VDD3与第二电源线VDD2相交。例如,第二电源线VDD2和第三电源线VDD3彼此电连接或为一体的结构。
例如,在一些实施例中,第二电源线VDD2和第三电源线VDD3分别通过过孔与第一电源线VDD电连接,由此从而形成网状的电源线结构。这种结构有助于降低电源线上的电阻从而降低电源线的压降,并有助于将电源电压均匀地输送至显示面板的各个子像素中。
例如,在一些实施例中,该第四导电层还包括与该第二电源线VDD2和第三电源线VDD3相绝缘的第四连接部CP4,该第四连接电极用于将第六晶体管T6的漏极D6与发光子像素电连接。例如,第四连接电极即实现为上述实施例中的第一转接电极227,用于将发光子像素的第一像素电极321与薄膜晶体管的漏极221电连接。
在本公开一些实施例提供的显示面板中,在上述的第四导电层上形成有保护层,该保护层包括图15、图16和图17中所示的平坦化部,图34-38中未示出。
例如,在一些实施例中,上述各导电层也可以采用其他布图。例如,图40示出了另一种第二导电层图的另一版图设计。如图40所示,在该示例中,第二导电层包括存储电容Cst的第二电容电极CE2(即:第二极板226)、复位信号线Init1、第二电源信号线VDD2以及遮光部S。第二电源信号线VDD2与第二电容电极CE2一体形成。
例如,图41示出了另一种第三导电层图的另一版图设计。如图41所示,该第三导电层包括数据线Vd、第一电源信号线VDD1以及屏蔽线PB。上述数据线Vd、第一电源信号线VDD1以及屏蔽线PB均沿相同的方向延伸,例如图中的竖直方向。例如,第三导电层还可以包括第一连接部CP1、第二连接部CP2和第三连接部CP3,以用于将不同的走线或者电极电连接。
例如,图42示出了另一种第四导电层图的另一版图设计。如图42所示,该第四导电层包括第四连接部CP4以及沿图中的竖直方向和水平方向交叉分布的第三电源信号线VDD3。例如,在一些示例中,第三电源信号线VDD3可与第一电源信号线VDD1并联,从而形成网状的电源结构,有利于降低电源信号线的电阻。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着,结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外,请注意,这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中,说明了大量具体细节。然而,能够理解,本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中,并未详细示出公知的方法、结构和技术,以便不模糊对本说明书的理解。
在权利要求中,不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中,这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是:以上实施例仅用以说明本公开的技术方案,而非对其限制;尽管参照前述实施例对本公开进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
Claims (24)
- 一种显示面板,包括:开孔区,所述开孔区设置有开孔;显示区,所述显示区至少部分围绕所述开孔区;和第一防裂区,所述第一防裂区至少部分围绕所述开孔区;所述显示面板在所述第一防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述封装层之上的至少一圈防裂保护层;并且所述显示区包括至少一层触控电极层;其中,所述防裂保护层与所述至少一层触控电极层中的至少一层同层同材料设置。
- 根据权利要求1所述的显示面板,其中,所述防裂保护层包括至少一层金属,所述触控电极层包括触控金属层。
- 根据权利要求2所述的显示面板,其中,所述衬底基板以及所述封装层延伸到所述显示区;并且所述触控金属层位于所述封装层背离所述衬底基板的一侧。
- 根据权利要求3所述的显示面板,其中,所述至少一层触控电极层包括更靠近所述衬底基板的第一触控金属层,第二触控金属层和位于所述第一触控金属层和所述第二触控金属层之间的触控介质层,所述防裂保护层与所述第一触控金属层同层同材料设置;和/或者,所述防裂保护层与所述第二触控金属层同层同材料设置。
- 根据权利要求4所述的显示面板,其中,所述第一触控金属层为桥接层,所述第二触控金属层为电极图案层,所述桥接层通过贯穿所述触控介质层的通孔与至少部分所述电极图案层实现电连接。
- 根据权利要求4所述的显示面板,其中,所述防裂保护层包括层叠设置的第一防裂保护层和第二防裂保护层,所述第一防裂保护层设置于所述第二防裂保护层与所述衬底基板之间;并且其中,所述第一防裂保护层与第一触控金属层同层同材料设置;所述第二防裂保护层与所述第二触控金属层同层同材料设置。
- 根据权利要求1所述的显示面板,其中,所述防裂保护层包括金属或金属氧化物的单层或叠层结构。
- 根据权利要求7所述的显示面板,其中,所述金属包括以下至少一者:铜,钼,钛-铝-钛;所述金属氧化物包括:氧化铟锡。
- 根据权利要求1-8任一项所述的显示面板,其中,所述第一防裂区还包括位于所述封装层之下的至少一圈第一防裂坝;所述第一防裂坝与所述防 裂保护层分布在所述封装层的两侧。
- 根据权利要求9所述的显示面板,其中,所述第一防裂坝与所述防裂保护层层叠设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影至少部分覆盖所述第一防裂坝在所述衬底基板上的正投影。
- 根据权利要求9所述的显示面板,其中,所述第一防裂坝与所述防裂保护层错位设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影位于相邻两所述第一防裂坝在所述衬底基板上的正投影之间。
- 根据权利要求1-11任一项所述的显示面板,其中,所述显示面板还包括:围绕所述第一防裂区的止流区;并且其中,所述衬底基板和所述封装层延伸至所述止流区,位于所述止流区的所述封装层与所述衬底基板之间设置有止流坝。
- 根据权利要求11所述的显示面板,其中,所述显示面板还包括:围绕所述止流区的第二防裂区;所述显示面板在所述第二防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述第二防裂区的所述封装层与所述衬底基板之间设置有第二防裂坝。
- 根据权利要求13所述的显示面板,其中,所述防裂保护层与所述第一防裂坝和/或所述第二防裂坝在所述衬底基板上的正投影存在至少部分重叠区域。
- 根据权利要求1-14任一项所述的显示面板,其中,所述封装层接触所述至少一圈第一防裂坝的区域和/或至少一圈第二防裂坝的区域至少包括一个凹陷结构,所述防裂保护层至少覆盖所述凹陷结构。
- 根据权利要求1-15任一项所述的显示面板,其中,所述开孔在所述显示面板上设置有至少一个;所述开孔的形状包括以下之一:圆形、条形和跑道状。
- 一种显示面板,包括:开孔区,所述开孔区设置有开孔;显示区,所述显示区至少部分围绕所述开孔区;和第一防裂区,所述第一防裂区至少部分围绕所述开孔区;所述显示面板在所述第一防裂区还包括:衬底基板、位于所述衬底基板之上的封装层、位于所述封装层之上的至少一圈防裂保护层和位于所述封装层之下的至少一圈第一防裂坝;所述封装层接触所述至少一圈第一防裂坝的区域至少包括一个凹陷结构,所述防裂保护层至少覆盖所述凹陷结构。
- 根据权利要求17所述的显示面板,其中,所述第一防裂坝与所述防裂保护层层叠设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影至少部分覆盖所述第一防裂坝在所述衬底基板上的正投影。
- 根据权利要求17所述的显示面板,其中,所述第一防裂坝与所述防裂保护层错位设置在所述封装层的两侧,所述防裂保护层在所述衬底基板上的正投影位于相邻两所述第一防裂坝在所述衬底基板上的正投影之间。
- 根据权利要求17所述的显示面板,其中,所述第一防裂坝至少包括一个凹凸结构,使得所述封装层包括凹陷结构,所述凹陷结构至少包括一个垂直于所述衬底基板方向的台阶,所述防裂保护层至少部分覆盖住所述台阶。
- 根据权利要求20所述的显示面板,其中,所述凹陷结构包括至少两个第一表面和位于两个所述第一表面之间的第二表面,以及连接所述第一表面和所述第二表面的两个垂直于所述衬底基板方向的台阶,所述防裂保护层完全覆盖所述凹陷结构。
- 根据权利要求17-21任一项所述的显示面板,其中,所述防裂保护层包括层叠设置的第一防裂保护层和第二防裂保护层,所述第一防裂保护层设置于所述第二防裂保护层与所述衬底基板之间;并且所述第一防裂保护层至少部分覆盖所述凹陷结构,和/或,所述第二防裂保护层至少部分覆盖所述凹陷结构。
- 根据权利要求17-22任一项所述的显示面板,其中,所述显示区包括至少一层触控电极层;其中,所述防裂保护层与所述至少一层触控电极层中的至少一层同层同材料设置。
- 根据权利要求23所述的显示面板,其中,所述至少一层触控电极层包括更靠近所述衬底基板的第一触控金属层,第二触控金属层和位于所述第一触控金属层和所述第二触控金属层之间的触控介质层,所述防裂保护层与所述第一触控金属层同层同材料设置;和/或者,所述防裂保护层与所述第二触控金属层同层同材料设置。
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CN202111086347.9A CN113889517B (zh) | 2020-12-02 | 2021-09-16 | 一种显示面板及其制备方法、显示装置 |
CN202111086347.9 | 2021-09-16 |
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PCT/CN2022/096679 WO2023040360A1 (zh) | 2020-12-02 | 2022-06-01 | 显示面板 |
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US (2) | US20230422588A1 (zh) |
EP (2) | EP4213214A4 (zh) |
JP (1) | JP2023551768A (zh) |
KR (1) | KR20230110493A (zh) |
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WO (2) | WO2022116055A1 (zh) |
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CN211929490U (zh) * | 2020-03-31 | 2020-11-13 | 京东方科技集团股份有限公司 | 显示基板及显示面板 |
KR20230110493A (ko) * | 2020-12-02 | 2023-07-24 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | 표시 패널 및 표시 장치 |
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2020
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- 2020-12-02 CN CN202310317829.3A patent/CN116249406A/zh active Pending
- 2020-12-02 CN CN202080003174.7A patent/CN114846617B/zh active Active
- 2020-12-02 EP EP20963903.8A patent/EP4213214A4/en active Pending
- 2020-12-02 US US18/252,315 patent/US20230422588A1/en active Pending
- 2020-12-02 JP JP2023524649A patent/JP2023551768A/ja active Pending
- 2020-12-02 WO PCT/CN2020/133432 patent/WO2022116055A1/zh active Application Filing
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2021
- 2021-09-16 CN CN202111086347.9A patent/CN113889517B/zh active Active
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2022
- 2022-06-01 EP EP22868737.2A patent/EP4273904A4/en active Pending
- 2022-06-01 US US18/022,435 patent/US20240268189A1/en active Pending
- 2022-06-01 WO PCT/CN2022/096679 patent/WO2023040360A1/zh unknown
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EP4273904A1 (en) | 2023-11-08 |
CN113889517B (zh) | 2023-12-29 |
WO2022116055A1 (zh) | 2022-06-09 |
EP4213214A4 (en) | 2023-11-08 |
US20230422588A1 (en) | 2023-12-28 |
EP4273904A4 (en) | 2024-08-07 |
CN113889517A (zh) | 2022-01-04 |
CN114846617A (zh) | 2022-08-02 |
EP4213214A1 (en) | 2023-07-19 |
CN114846617B (zh) | 2023-11-03 |
KR20230110493A (ko) | 2023-07-24 |
CN116249406A (zh) | 2023-06-09 |
JP2023551768A (ja) | 2023-12-13 |
US20240268189A1 (en) | 2024-08-08 |
CN116137904A (zh) | 2023-05-19 |
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