WO2023103069A1 - 柔性显示面板和柔性阵列基板 - Google Patents

柔性显示面板和柔性阵列基板 Download PDF

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Publication number
WO2023103069A1
WO2023103069A1 PCT/CN2021/139543 CN2021139543W WO2023103069A1 WO 2023103069 A1 WO2023103069 A1 WO 2023103069A1 CN 2021139543 W CN2021139543 W CN 2021139543W WO 2023103069 A1 WO2023103069 A1 WO 2023103069A1
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WIPO (PCT)
Prior art keywords
layer
hole
flexible substrate
flexible
thin film
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PCT/CN2021/139543
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English (en)
French (fr)
Inventor
曹蔚然
林高波
徐源竣
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/623,501 priority Critical patent/US20240049523A1/en
Publication of WO2023103069A1 publication Critical patent/WO2023103069A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, in particular to a flexible display panel and a flexible array substrate.
  • a flexible display panel generally includes a multi-layer laminated inorganic insulating layer. As the requirements for the bendability of flexible display panels are getting higher and higher, the conventional stacked inorganic insulating layer structure has been difficult to meet the requirements of flexible display panels.
  • the present application provides a flexible display panel and a flexible array substrate capable of improving bending performance.
  • the present application provides a flexible display panel, including a display area, and the flexible display panel includes:
  • the thin film transistor layer is disposed on the flexible substrate and located in the display area, the thin film transistor layer includes a plurality of insulating layers stacked, and the surface of the thin film transistor layer away from the flexible substrate is provided with a first a via hole, the first via hole penetrating at least one of the plurality of insulating layers; and
  • An organic flat layer covers the side of the thin film transistor layer away from the flexible substrate, and fills the first through hole.
  • the thin film transistor layer includes a thin film transistor, and the first through hole is disposed adjacent to the thin film transistor.
  • the plurality of insulating layers include a gate insulating layer, an interlayer insulating layer, a source-drain layer, and a passivation layer
  • the thin film transistor layer further includes a semiconductor layer and a gate
  • the semiconductor layer The gate layer is disposed on the flexible substrate, the gate layer is disposed on the side of the semiconductor layer away from or close to the flexible substrate, and the gate insulating layer is disposed between the gate layer and the semiconductor layer.
  • the source and drain layers are arranged on the side of the gate layer and the semiconductor layer away from the flexible substrate, and the interlayer insulating layer is arranged on the source and drain layers and the semiconductor layer
  • the passivation layer is arranged on the side of the source and drain layer away from the flexible substrate, the first through hole penetrates at least a part of the passivation layer, or the first through hole penetrating through at least a part of the interlayer insulating layer.
  • the flexible display panel further includes a buffer layer, the buffer layer is disposed between the plurality of insulating layers and the flexible substrate, and the first through hole penetrates through the buffer layer. at least partly.
  • the flexible display panel includes a barrier layer, and the barrier layer is disposed between the thin film transistor layer and the flexible substrate;
  • the flexible substrate includes a first flexible substrate, a second flexible substrate and a barrier layer, the second flexible substrate is located between the thin film transistor layer and the first flexible substrate, and the barrier layer is set Between the first flexible substrate and the second flexible substrate, a second through hole is opened in the second flexible substrate, and the second through hole penetrates at least In part, the barrier layer fills the second via hole.
  • the orthographic projection of the hole wall of the first through hole on the plane where the first flexible substrate is located is the same as that of the hole wall of the second through hole on the plane where the first flexible substrate is located.
  • the orthographic projections on are at least partially overlapping; or
  • the orthographic projection of the hole wall of the first through hole on the plane where the first flexible substrate is located is within the range of the orthographic projection of the hole wall of the second through hole on the plane where the first flexible substrate is located .
  • the diameter of the second through hole is 4 microns larger than the diameter of the first through hole.
  • the depth of the second through hole is greater than the depth of the first through hole.
  • the flexible substrate further includes an adhesive layer, the adhesive layer is disposed between the barrier layer and the second flexible substrate, and the second through hole penetrates through the second flexible substrate.
  • the substrate exposes the adhesive layer or the barrier layer.
  • the flexible display panel further includes a first electrode, a pixel definition layer, a light emitting layer, and a second electrode, the first electrode is disposed on the thin film transistor layer, and the pixel definition layer is disposed on the The first electrode is away from the side of the thin film transistor layer, an opening is opened in the pixel definition layer, the light emitting layer is arranged in the opening, and the second electrode covers the pixel definition layer and the light emitting layer. layer.
  • the present application also provides a flexible array substrate, including a display area, and the flexible array substrate includes:
  • the thin film transistor layer is disposed on the flexible substrate and located in the display area, the thin film transistor layer includes a plurality of insulating layers stacked, and the surface of the thin film transistor layer away from the flexible substrate is provided with a first a via hole, the first via hole penetrating at least one of the plurality of insulating layers; and
  • An organic flat layer covers the side of the thin film transistor layer away from the flexible substrate, and fills the first through hole.
  • the thin film transistor layer includes a thin film transistor, and the first through hole is disposed adjacent to the thin film transistor.
  • the plurality of insulating layers include a gate insulating layer, an interlayer insulating layer, a source-drain layer, and a passivation layer
  • the thin film transistor layer further includes a semiconductor layer and a gate layer
  • the semiconductor layer is disposed on the flexible substrate
  • the gate layer is disposed on a side of the semiconductor layer away from or close to the flexible substrate
  • the gate insulating layer is disposed on the gate layer
  • the source-drain layer is arranged on the side of the gate layer and the semiconductor layer away from the flexible substrate
  • the interlayer insulating layer is arranged on the source-drain layer
  • the passivation layer is arranged on the side of the source and drain layer away from the flexible substrate, and the first through hole penetrates at least a part of the passivation layer, or, the The first through hole penetrates at least a part of the interlayer insulating layer.
  • the flexible array substrate further includes a buffer layer, the buffer layer is disposed between the plurality of insulating layers and the flexible substrate, and the first through hole penetrates the flexible substrate. at least a portion of the buffer layer.
  • the flexible array substrate includes a barrier layer, and the barrier layer is disposed between the thin film transistor layer and the flexible substrate;
  • the flexible substrate includes a first flexible substrate, a second flexible substrate and a barrier layer, the second flexible substrate is located between the thin film transistor layer and the first flexible substrate, and the barrier layer is set Between the first flexible substrate and the second flexible substrate, a second through hole is opened in the second flexible substrate, and the second through hole penetrates at least In part, the barrier layer fills the second via hole.
  • the orthographic projection of the wall of the first through hole on the plane where the first flexible substrate the orthographic projections on the plane of the substrate overlap at least partially;
  • the orthographic projection of the hole wall of the first through hole on the plane where the first flexible substrate is located is within the range of the orthographic projection of the hole wall of the second through hole on the plane where the first flexible substrate is located .
  • the diameter of the second through hole is 4 microns larger than the diameter of the first through hole .
  • the depth of the second through hole is greater than the depth of the first through hole.
  • the flexible substrate further includes an adhesive layer, the adhesive layer is disposed between the barrier layer and the second flexible substrate, and the second through hole runs through the The second flexible substrate exposes the adhesive layer or the barrier layer.
  • the stress is applied to the first through holes, which can effectively reduce the damage to the flexible display panel due to bending.
  • Improve product bending performance Furthermore, the organic planar layer is filled in the first through hole, and the inorganic material in the insulating layer is replaced by an organic material to further improve the bending resistance, which can greatly improve the physical bendability of the flexible display panel.
  • FIG. 1 is a schematic structural view of a flexible display panel according to a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a flexible display panel according to a second embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a flexible display panel according to a third embodiment of the present application.
  • FIG. 4 is a flowchart of a method for manufacturing a flexible display panel of the present application.
  • 5( a ) to 5 ( d ) are schematic diagrams of the steps of the manufacturing method of the flexible display panel of the present application.
  • a first feature being “on” or “below” a second feature may include the first and second features directly, or may include that the first and second features are not directly connected but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • "Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more features.
  • the present application provides a flexible display panel.
  • the display panel in the embodiment of the present application can be used in mobile phones, tablet computers, e-readers, electronic display screens, notebook computers, mobile phones, augmented reality (augmented reality, AR) ⁇ virtual reality (virtual reality, VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.
  • augmented reality augmented reality, AR
  • virtual reality virtual reality
  • the display panel may be an organic light-emitting diode (Organic Light-emitting Diode, OLED) display panel, a quantum dot light-emitting diode (Quantum Dot Light-emitting Diode, QLED) display panel, Micro Light-emitting Diode (Micro-LED) display panel, submillimeter light-emitting diode (Mini Light-emitting Diode, Mini-LED) display panel or Liquid Crystal (Liquid Crystal) display panel.
  • OLED Organic Light-emitting Diode
  • QLED Quantum Dot Light-emitting Diode
  • Micro-emitting Diode Micro Light-emitting Diode
  • submillimeter light-emitting diode Mini Light-emitting Diode, Mini-LED
  • Liquid Crystal Liquid Crystal
  • the flexible array substrate of the present application will be described by taking a flexible array substrate used for an OLED display panel as an example.
  • the flexible display panel 1 includes a display area AA. It can be understood that the flexible display panel 1 also includes a non-display area (not shown) surrounding the display area AA.
  • display area AA refers to an area on the flexible display panel 1 for disposing light-emitting devices and pixel driving circuits of the light-emitting devices, that is, an area composed of all pixel areas.
  • the area around the display area AA is a non-display area.
  • the flexible display panel 1 includes a flexible array substrate 100.
  • the flexible array substrate 100 includes a flexible substrate 10, a thin film transistor layer 20 disposed on the flexible substrate 10 and located in the display area AA, and a layer covering the thin film transistor layer 20 away from the flexible substrate 10.
  • the thin film transistor layer 20 includes a plurality of insulating layers stacked.
  • the plurality of insulating layers includes a passivation layer PV, an interlayer insulating layer IL, and the like.
  • a first through hole VIA1 is opened on the surface 20 a of the thin film transistor layer 20 away from the flexible substrate 10 .
  • the first via hole VIA1 penetrates at least one of the plurality of insulating layers.
  • the organic planarization layer 30 fills the first via holes VIA1.
  • the organic planarization layer 30 may be an organic photoresist material.
  • the stress is applied to the first through hole VIA1, which can effectively reduce the impact of bending on the flexibility. Damage to the array substrate 100 improves the bending performance of the product.
  • the organic planar layer 30 is filled in the first through hole VIA1 , and the inorganic material in the insulating layer is replaced with an organic material to further improve the bending resistance, which can greatly improve the physical bendability of the flexible array substrate 100 .
  • the thin film transistor layer 20 includes a plurality of thin film transistors.
  • the first via hole VIA1 is disposed adjacent to the thin film transistor.
  • the application does not limit the number and position of the first through holes VIA1.
  • at least one first through hole VIA1 may be provided around each thin film transistor. It is also possible that a plurality of first through holes VIA1 are arranged around one thin film transistor. By arranging the first through hole VIA1 around the thin film transistor, the thin film transistor can be more effectively protected and the reliability of the thin film transistor can be improved.
  • a plurality of thin film transistors are arranged at intervals, and the first through hole VIA1 is arranged between the plurality of thin film transistors. In other words, the first through hole VIA1 and each thin film transistor in the thin film transistor layer 20 are staggered to avoid affecting the thin film transistor during bending.
  • the driving circuit of the OLED display panel may be 2T1C, 3T1C, 5T1C, or 7T1C.
  • the driving circuit in FIG. 1 is a 2T1C pixel driving circuit, therefore, the plurality of thin film transistors include a driving thin film transistor T1 and a switching thin film transistor T2. It can be understood that, according to different types of driving circuits, the thin film transistor layer 20 may also include other thin film transistors. As shown in FIG. 1 , one first through hole VIA1 is arranged adjacent to the driving thin film transistor T1 , and the other first through hole VIA1 is arranged adjacent to the switching thin film transistor T2 .
  • the thin film transistor layer 20 includes a semiconductor layer SL, a gate insulating layer GI, a gate layer GE, an interlayer insulating layer IL, a source and drain layer SD and a passivation layer PV.
  • the semiconductor layer SL is disposed on the flexible substrate 10, the gate layer GE is disposed on a side of the gate layer GE away from or close to the flexible substrate 10, and the gate insulating layer GI is disposed between the gate layer GE and the semiconductor layer SL,
  • the source-drain layer SD is arranged on the side of the gate layer GE and the semiconductor layer SL away from the flexible substrate 10, the interlayer insulating layer IL is arranged between the source-drain layer SD and the semiconductor layer SL, and the passivation layer PV is arranged on the source layer.
  • the first via hole VIA1 penetrates at least a part of the passivation layer PV or, the first via hole VIA1 penetrates at least a part of the interlayer insulating layer IL.
  • the fact that the first through hole VIA1 penetrates at least a part of the passivation layer PV means that the first through hole VIA1 may penetrate a part of the passivation layer PV, or may completely penetrate the passivation layer PV.
  • the first via hole VIA1 penetrates at least a part of the interlayer insulating layer IL, which means that the first via hole VIA1 completely penetrates the passivation layer PV and a part of the interlayer insulating layer IL, and may also completely penetrate the passivation layer PV and the interlayer insulating layer.
  • Layer IL Depending on the depth of the first through hole VIA1 and the film layers it passes through, the first through hole VIA1 can be formed by one photomask etching, or can be formed by two or more photomask etching.
  • the thin film transistor of the present application is a top-gate thin film transistor. Specifically, it is a self-alignment thin film transistor.
  • the semiconductor layer SL is disposed on a side of the gate layer GE close to the flexible substrate 10 , and the first through hole VIA1 completely penetrates the passivation layer PV and the interlayer insulating layer IL.
  • the flexible array substrate 100 further includes a buffer layer BL, and the buffer layer BL is disposed between the thin film transistor layer 20 and the flexible substrate 10 . Further, the buffer layer BL is disposed between the plurality of insulating layers and the flexible substrate 10 .
  • the first via hole VIA1 penetrates at least a portion of the buffer layer BL.
  • a barrier layer BA is further disposed between the buffer layer BL and the flexible substrate 10 .
  • the first through hole VIA1 does not penetrate through the barrier layer BA.
  • the first via hole VIA1 completely penetrates the passivation layer PV and penetrates a portion of the interlayer insulating layer IL.
  • the first via hole VIA1 completely penetrates the passivation layer PV.
  • the gate layer GE includes a first gate GE1 and a second gate GE2 arranged at intervals.
  • the gate insulating layer GI includes a first gate insulating layer GI1 and a second gate insulating layer GI2 arranged at intervals.
  • the semiconductor layer SL includes a first semiconductor layer SL1 and a second semiconductor layer SL2 arranged at intervals.
  • the source-drain layer SD includes a first source S1 , a first drain D1 , a second source S2 , and a second drain D2 arranged at intervals.
  • the first semiconductor layer SL1 is disposed on the flexible substrate 10, the first gate insulating layer GI1 is disposed on the surface of the first semiconductor layer SL1 away from the flexible substrate 10, and the first gate GE1 is disposed on the surface of the first gate insulating layer GI1 away from the flexible substrate 10.
  • the first source S1 and the first drain D1 are arranged on the side of the first gate GE1 far away from the first semiconductor layer SL1, and the first source S1 and the first drain D1 are set on the
  • the contact holes in the insulating interlayer IL are respectively connected to both ends of the first semiconductor layer SL1.
  • the first semiconductor layer SL1 may include a channel of semiconductor and conductor parts on both sides of the channel.
  • the first source S1 and the first drain D1 are respectively connected to two conductor portions of the first semiconductor layer SL1 .
  • the driving transistor T1 includes a first semiconductor layer SL1, a first gate insulating layer GI1, a first gate GE1, a first source S1, and a first drain D1.
  • the second semiconductor layer SL2 is disposed on the flexible substrate 10, the second gate insulating layer GI2 is disposed on the surface of the second semiconductor layer SL2 away from the flexible substrate 10, and the second gate GE2 is disposed on the surface of the second gate insulating layer GI2 away from the flexible substrate 10.
  • the second source S2 and the second drain D2 are arranged on the side of the second gate GE2 away from the second semiconductor layer SL2, and the second source S2 and the second drain D2 are set on the The contact holes in the insulating interlayer IL are respectively connected to both ends of the second semiconductor layer SL2.
  • the second semiconductor layer SL2 may include a semiconductor channel and conductor parts located on both sides of the channel.
  • the second source S2 and the second drain D2 are respectively connected to two conductor portions of the second semiconductor layer SL2 .
  • the switching transistor T2 includes a second semiconductor layer SL2, a second gate insulating layer GI2, a second gate GE2, a second source S2, and a second drain D2.
  • the thin film transistor may also be a bottom gate thin film transistor.
  • the first through hole VIA1 may penetrate through the gate insulating layer GI.
  • the flexible substrate 10 includes a first flexible substrate 11 , a second flexible substrate 12 , a barrier layer 13 and an adhesive layer 14 .
  • the second flexible substrate 12 is located between the thin film transistor layer 20 and the first flexible substrate 11 .
  • the barrier layer 13 is disposed between the first flexible substrate 11 and the second flexible substrate 12 to block water vapor.
  • the adhesive layer 14 is disposed between the barrier layer 13 and the second flexible substrate 12 to increase the adhesion between the second flexible substrate 12 and the barrier layer 13 .
  • the material of the flexible organic layer is selected from polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate One or more of (PC), polyetherimide (PEI) and polyethersulfone (PES).
  • the material of the barrier layer 13 is selected from one or more of inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the adhesion layer 14 may be a
  • a second through hole VIA2 is opened in the second flexible substrate 12 .
  • the second via hole VIA2 penetrates through at least a portion of the first flexible substrate 11 .
  • the second through hole VIA2 penetrates through at least a part of the first flexible substrate 11 means: the second through hole VIA2 penetrates a part of the first flexible substrate 11 , or the second through hole VIA2 completely penetrates the first flexible substrate 11 .
  • the second via hole VIA2 may pass through the second flexible substrate 12 to expose the adhesive layer 14 or the barrier layer 13 .
  • the barrier layer BA fills the second via hole VIA2.
  • the opening of the second through hole VIA2 is designed to release stress when the second flexible substrate 12 is bent.
  • the orthographic projection of the hole wall VIA1a of the first through hole VIA1 on the plane of the first flexible substrate 11 overlaps at least partially the orthographic projection of the hole wall of the second through hole VIA2 on the plane of the first flexible substrate 11, Or the orthographic projection of the hole wall of the first through hole VIA1 on the plane of the first flexible substrate 11 is within the range of the orthographic projection of the hole wall of the second through hole VIA2 on the plane of the first flexible substrate 11 .
  • the first through hole VIA1 and the second through hole VIA2 are arranged correspondingly.
  • first through hole VIA1 By designing the first through hole VIA1 to correspond to the second through hole VIA2 , a deep hole can be formed, which is more conducive to stress release in the deep hole and reduces the impact on the nearby thin film transistors during bending. If the first through hole VIA1 and the second through hole VIA2 are arranged in a staggered manner, on the one hand, the space will be increased, and on the other hand, the thin film transistor may be affected by dislocation due to stress release.
  • the second through hole VIA2 The diameter of the first through hole VIA1 is smaller than the diameter of the second through hole VIA2 .
  • the diameter of the first through hole VIA1 and the diameter of the second through hole VIA2 both refer to the maximum diameter of the through hole.
  • the design that the diameter of the first through hole VIA1 is smaller than that of the second through hole VIA2 is mainly to consider the alignment overlap between the first through hole VIA1 and the second through hole VIA2 .
  • the second through hole VIA2 is allowed to have an alignment of about 2 microns compared with the first through hole VIA1 Error, that is, when both the first through hole VIA1 and the second through hole VIA2 are round holes, the diameter of the second through hole VIA2 is more than 4 microns larger than the diameter of the first through hole VIA1, which can ensure the alignment of the two.
  • the depth H2 of the second through hole VIA2 is greater than the depth H1 of the first through hole VIA1 . The greater the depth of the via, the greater the effect of stress relief.
  • the depth H2 of the second via hole VIA2 By setting the depth H2 of the second via hole VIA2 to be greater than the depth H1 of the first via hole VIA1, the stress is concentrated in the second via hole VIA2 during bending, which can avoid the stress concentration in the first via hole VIA1 and affect the thin film transistor. .
  • the depth H2 of the second through hole VIA2 is 4 microns to 6 microns. It can be understood that the present application does not limit the shapes of the first through hole VIA1 and the second through hole VIA2 , and the first through hole VIA1 and the second through hole VIA2 may be rectangular holes, square holes or circular holes.
  • the display panel 1 also includes a first electrode 200, a pixel definition layer 300, a light emitting layer 400, and a second electrode 500.
  • the first electrode 200 is disposed on the flexible array substrate 100, and the pixel definition layer 300 is disposed on the side of the first electrode 200 away from the flexible array substrate 100, an opening 300a is opened in the pixel definition layer 300, the light emitting layer 400 is disposed in the opening 300a, and the second electrode 500 covers the pixel definition layer 300 and the light emitting layer 400 .
  • the first electrode 200 may be an anode
  • the second electrode 500 may be a cathode; or the first electrode 200 may be a cathode, and the second electrode 500 may be an anode.
  • the present application also provides a method for manufacturing a flexible display panel, which is used for manufacturing the above-mentioned flexible display panel.
  • the manufacturing method of the flexible display panel includes the following steps:
  • the thin film transistor layer includes a plurality of insulating layers stacked.
  • the plurality of insulating layers includes a passivation layer, an interlayer insulating layer, and the like.
  • the thin film transistor layer includes a plurality of thin film transistors.
  • the plurality of thin film transistors include driving thin film transistors and switching thin film transistors.
  • a plurality of thin film transistors are arranged at intervals.
  • step 101 before the step of forming a thin film transistor layer on the flexible substrate, the steps may also include:
  • a buffer layer is formed on the flexible array substrate, and a barrier layer is formed on the buffer layer.
  • step 101 may also include:
  • Step 1011 Opening a second through hole in the second flexible substrate, the second through hole penetrates at least a part of the first flexible substrate, and the barrier layer fills the second through hole.
  • the opening of the second via hole is designed to release stress when the second flexible substrate is bent.
  • a first through hole is formed at a position corresponding to the second through hole.
  • the orthographic projection of the wall on the plane where the first flexible substrate is located is within the range of the orthographic projection of the wall of the second through hole on the plane where the first flexible substrate is located.
  • the first through hole By designing the first through hole to correspond to the second through hole, a deep hole can be formed, which is more conducive to stress release in the deep hole, and reduces the influence on the nearby thin film transistors during bending. If the first through hole and the second through hole are staggered, on the one hand, the space will be increased, and on the other hand, the dislocation may affect the thin film transistor due to stress release.
  • the orthographic projection of the hole wall of the first through hole on the plane where the first flexible substrate is located is within the range of the orthographic projection of the hole wall of the second through hole on the plane where the first flexible substrate is located, the first through hole The diameter of the hole is smaller than that of the second through hole.
  • the design that the diameter of the first through hole is smaller than that of the second through hole is mainly to consider the alignment overlap between the first through hole and the second through hole.
  • the second through hole is allowed to have an alignment error of about 2 microns compared with the first through hole, that is, When both the first through hole VIA1 and the second through hole VIA2 are round holes, the diameter of the second through hole is larger than the diameter of the first through hole by more than 4 microns, which can ensure the alignment of the two.
  • the depth of the second through hole is greater than the depth of the first through hole. The greater the depth of the via, the greater the effect of stress relief.
  • the depth of the second through hole By setting the depth of the second through hole to be greater than the depth of the first through hole, stress is concentrated in the second through hole during bending, which can avoid stress concentration in the first through hole from affecting the thin film transistor.
  • the depth of the second through hole is 4 microns to 6 microns.
  • the depth of the second through hole is 4 microns to 6 microns. It can be understood that the present application does not limit the shapes of the first through hole VIA1 and the second through hole VIA2 , and the first through hole VIA1 and the second through hole VIA2 may be rectangular holes, square holes or circular holes.
  • the first through holes are disposed between the thin film transistors.
  • the first through hole and each thin film transistor in the thin film transistor layer are arranged in a staggered manner.
  • the thin film transistor can be more effectively protected and the reliability of the thin film transistor can be improved.
  • the application does not limit the number and position of the first through holes.
  • at least one first through hole may be provided around each thin film transistor.
  • the first through hole penetrates at least a part of the passivation layer or, the first through hole penetrates at least a part of the interlayer insulating layer. Further, the first through hole penetrates at least a part of the buffer layer. More specifically, the first through hole penetrates a part of the buffer layer. In order to maintain the water and oxygen barrier effect of the barrier layer, the first through hole does not penetrate through the barrier layer.
  • the organic planar layer may be an organic photoresist material.
  • Forming the organic passivation layer on the side of the thin film transistor layer away from the flexible substrate specifically includes steps:
  • An organic photoresist layer is formed on the side of the thin film transistor layer away from the flexible substrate, and an electrode connection hole is opened in the organic photoresist layer.
  • 104 Form a first electrode layer, a pixel definition layer, a light emitting layer, and a second electrode layer on the flexible array substrate to obtain a flexible display panel.
  • Step 201 Please refer to FIG. 5( a ), providing a flexible substrate 10 , which includes a first flexible substrate 11 , a barrier layer 13 , an adhesive layer 14 and a second flexible substrate 12 stacked in sequence.
  • the first flexible substrate 11 and the second flexible substrate 12 are polyimide
  • the barrier layer 13 is silicon oxide
  • the adhesion layer 14 is amorphous silicon.
  • the thickness of the second flexible substrate 12 is 5 microns to 10 microns.
  • a second through hole VIA2 is opened in the second flexible substrate 12 by using photolithography process. The second through hole VIA2 passes through the second flexible substrate 12 to expose the adhesive layer 14 .
  • the depth H2 of the second through hole VIA2 is 4 ⁇ m to 6 ⁇ m.
  • Step 202 Please refer to FIG. 5( a ), deposit a barrier layer BA on the flexible substrate 10 , and form a buffer layer BL on the barrier layer BA.
  • the barrier layer BA includes silicon oxide, silicon nitride and silicon oxide stacked in sequence.
  • the total thickness of the barrier layer BA is 1000 ⁇ to 5000 ⁇ .
  • Step 203 Referring to FIG. 5(b), a semiconductor material layer (not shown) is formed on the buffer layer BL, and the semiconductor material layer includes a first semiconductor material layer and a second semiconductor material layer.
  • the material of the semiconductor material layer can be IGZO, ITZO or IGZTO.
  • the thickness of the semiconductor layer SL is 100 angstroms to 1000 angstroms.
  • Step 204 Deposit a gate insulating material layer on the semiconductor layer SL, the material of the gate insulating material layer is silicon oxide, and the thickness is 1000 angstroms to 3000 angstroms.
  • Step 205 Deposit a gate metal layer on the gate insulating layer GI.
  • the material of the gate metal layer can be a single layer of Mo, Al, Cu, Ti, etc., or Mo/Al/Mo, Al/Mo, Mo/ Cu, MoTi/Cu and other multi-layer metals, with a thickness of 500 angstroms to 10000 angstroms.
  • Step 206 Using a photomask, define the gate layer GE and the gate insulating layer GI.
  • the gate insulating layer GI includes a first gate insulating layer GI1 and a second gate insulating layer GI2.
  • the first gate insulating layer GI1 is on the first semiconductor layer SL1.
  • the second gate insulating layer GI2 is on the second semiconductor layer SL2.
  • the gate layer GE includes a first gate GE1 layer and a second gate GE2 layer.
  • the first gate GE1 layer is located on the first gate insulating layer GI1.
  • the second gate GE2 layer is located on the second gate insulating layer GI2.
  • the gate metal layer is first etched by wet etching, and then the patterned first gate GE1 and second gate GE2 are used for self-alignment, and the gate insulating layer GI is dry etched to obtain the first gate insulating layer.
  • Step 207 conducting a conductorization treatment on the upper semiconductor material layer without the protection of the gate insulating layer GI by using plasma (Plasma) treatment to form an N-doped conductor region as the source region and the drain contacting the source and the drain district.
  • the semiconductor material layer under the gate insulating layer GI is left untreated, and serves as a thin film transistor channel, forming a semiconductor layer SL including a first semiconductor layer SL1 and a second semiconductor layer SL2 .
  • Step 208 Deposit a silicon oxide film as the interlayer insulating layer IL with a thickness of 3000 angstroms to 10000 angstroms, and etch the contact holes of the source, the drain and the semiconductor layer SL in the interlayer insulating layer IL.
  • the buffer hole can also be etched, so as to form the first through hole later.
  • the buffer hole is located between the first semiconductor layer SL1 and the second semiconductor layer SL2.
  • Step 209 Depositing a source-drain metal layer, the material of the source-drain metal layer can be Mo, Al, Cu, Ti, etc., or an alloy of Mo, Al, Cu, Ti, the thickness of the source-drain metal layer is 2000 angstroms to 10000 angstroms, Then, a first source S1 , a first drain D1 , a second source S2 , and a second drain D2 are formed by a photolithography process.
  • the first source S1 and the first drain D1 are respectively connected to two ends of the first semiconductor layer SL1 through via holes opened in the interlayer insulating layer IL.
  • the second source S2 and the second drain D2 are respectively connected to two ends of the second semiconductor layer SL2 through contact holes opened in the interlayer insulating layer IL.
  • Step 210 Deposit a passivation layer PV, which can be a silicon oxide film with a thickness of 1000 angstroms to 5000 angstroms, and etch to form the first through hole VIA1 on the basis of the buffer hole, and simultaneously etch to form the first via hole VIA1 Hole CH1.
  • the first contact hole CH1 penetrates through the passivation layer PV, exposing the first drain D1.
  • Step 211 Please refer to FIG. 5( c ), deposit an organic photoresist material as the organic planar layer 30 .
  • It can be a photoresist layer with different compositions, and the thickness of the organic planar layer 30 is 10000 angstroms to 50000 angstroms, and the organic planar layer 30 fills the first via hole VIA1.
  • the second contact hole CH2 , the second contact hole CH2 and the first contact hole CH1 may be formed on the organic planar layer 30 by photolithography to obtain the flexible array substrate 100 .
  • Step 212 Please refer to FIG. 5(d), deposit the first electrode 200, the first electrode 200 is an anode, and the first electrode 200 includes metal materials with high reflectivity, including but not limited to ITO/Ag/ITO, IZO/ Ag/IZO, ITO/Al/ITO or IZO/Al/IZO, etc., the first electrode 200 is overlapped with the driving thin film transistor T1 through the first overlapping hole CH1 and the second overlapping hole CH2;
  • Step 213 forming a pixel definition layer 300 , the thickness of the pixel definition layer 300 is 10000 angstroms to 20000 angstroms, and an opening 300 a is defined by a photolithography process.
  • Step 214 Form the light emitting layer 400 in the opening 300a.
  • Step 215 Forming the second electrode 500 on the light-emitting layer 400 and the pixel definition layer 300, the second electrode 500 being a cathode, to obtain a completed display panel.

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Abstract

本申请提供柔性显示面板和柔性阵列基板。柔性显示面板包括柔性衬底、设置于柔性衬底的显示区的薄膜晶体管层以及覆盖薄膜晶体管层的有机平坦层。薄膜晶体管层包括多个绝缘层，薄膜晶体管层远离柔性衬底的表面开设有贯穿多个绝缘层中的至少一个的第一通孔。有机平坦层填充第一通孔。

Description

柔性显示面板和柔性阵列基板 技术领域
本申请涉及显示技术领域，尤其涉及一种柔性显示面板和柔性阵列基板。
 背景技术
近年来，柔性显示面板由于能够被弯曲或者卷曲，能够适应各种显示需求，应用越来越广泛。柔性显示面板一般包括多层叠层的无机绝缘层。随着对柔性显示面板弯折性的要求越来越高，常规的叠层无机绝缘层结构已经难以满足柔性显示面板的要求。
 技术问题
有鉴于此，本申请提供一种能够提升弯折性能的柔性显示面板和柔性阵列基板。
 技术解决方案
本申请提供一种柔性显示面板，包括显示区，所述柔性显示面板包括：
柔性衬底；
薄膜晶体管层，设置于所述柔性衬底上且位于所述显示区，所述薄膜晶体管层包括层叠设置的多个绝缘层，所述薄膜晶体管层远离所述柔性衬底的表面开设有第一通孔，所述第一通孔贯穿所述多个绝缘层中的至少一个；以及
有机平坦层，覆盖于所述薄膜晶体管层远离所述柔性衬底的一侧，并填充所述第一通孔。
在一种实施方式中，所述薄膜晶体管层包括薄膜晶体管，所述第一通孔与所述薄膜晶体管相邻设置。
在一种实施方式中，所述多个绝缘层包括栅极绝缘层、层间绝缘层、源漏极层以及钝化层，所述薄膜晶体管层还包括半导体层和栅极，所述半导体层设置于所述柔性衬底上，所述栅极层设置于所述半导体层远离或者靠近所述柔性衬底的一侧，所述栅极绝缘层设置于所述栅极层与所述半导体层之间，所述源漏极层设置于所述栅极层和所述半导体层远离所述柔性衬底的一侧，所述层间绝缘层设置于所述源漏极层与所述半导体层之间，所述钝化层设置于所述源漏极层远离所述柔性衬底的一侧，所述第一通孔贯穿所述钝化层的至少一部分，或者，所述第一通孔贯穿所述层间绝缘层的至少一部分。
在一种实施方式中，所述柔性显示面板还包括缓冲层，所述缓冲层设置于所述多个绝缘层与所述柔性衬底之间，所述第一通孔贯穿所述缓冲层的至少一部分。
在一种实施方式中，所述柔性显示面板包括阻挡层，所述阻挡层设置于所述薄膜晶体管层与所述柔性衬底之间；
所述柔性衬底包括第一柔性衬底、第二柔性衬底以及阻隔层，所述第二柔性衬底位于所述薄膜晶体管层与所述第一柔性衬底之间，所述阻隔层设置于所述第一柔性衬底与所述第二柔性衬底之间，所述第二柔性衬底中开设有第二通孔，所述第二通孔贯穿所述第一柔性衬底的至少一部分，所述阻挡层填充所述第二通孔。
在一种实施方式中，所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影与所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影至少部分重叠；或者
所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影位于所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影的范围内。
在一种实施方式中，所述第一通孔和所述第二通孔均为圆孔时，所述第二通孔的直径比所述第一通孔的直径大4微米。
在一种实施方式中，所述第二通孔的深度大于所述第一通孔的深度。
在一种实施方式中，所述柔性衬底还包括黏附层，所述黏附层设置于所述阻隔层与所述第二柔性衬底之间，所述第二通孔贯穿所述第二柔性衬底暴露出所述黏附层或者所述阻隔层。
在一种实施方式中，所述柔性显示面板还包括第一电极、像素定义层、发光层和第二电极，第一电极设置于所述薄膜晶体管层上，所述像素定义层设置于所述第一电极远离所述薄膜晶体管层的一侧，所述像素定义层中开设有开口，所述发光层设置于所述开口中，所述第二电极覆盖于所述像素定义层和所述发光层上。
本申请还提供一种柔性阵列基板，包括显示区，所述柔性阵列基板包括：
柔性衬底；
薄膜晶体管层，设置于所述柔性衬底上且位于所述显示区，所述薄膜晶体管层包括层叠设置的多个绝缘层，所述薄膜晶体管层远离所述柔性衬底的表面开设有第一通孔，所述第一通孔贯穿所述多个绝缘层中的至少一个；以及
有机平坦层，覆盖于所述薄膜晶体管层远离所述柔性衬底的一侧，并填充所述第一通孔。
在一种实施方式的柔性阵列基板中，所述薄膜晶体管层包括薄膜晶体管，所述第一通孔与所述薄膜晶体管相邻设置。
在一种实施方式的柔性阵列基板中，所述多个绝缘层包括栅极绝缘层、层间绝缘层、源漏极层以及钝化层，所述薄膜晶体管层还包括半导体层和栅极层，所述半导体层设置于所述柔性衬底上，所述栅极层设置于所述半导体层远离或者靠近所述柔性衬底的一侧，所述栅极绝缘层设置于所述栅极层与所述半导体层之间，所述源漏极层设置于所述栅极层和所述半导体层远离所述柔性衬底的一侧，所述层间绝缘层设置于所述源漏极层与所述半导体层之间，所述钝化层设置于所述源漏极层远离所述柔性衬底的一侧，所述第一通孔贯穿所述钝化层的至少一部分，或者，所述第一通孔贯穿所述层间绝缘层的至少一部分。
在一种实施方式的柔性阵列基板中，所述柔性阵列基板还包括缓冲层，所述缓冲层设置于所述多个绝缘层与所述柔性衬底之间，所述第一通孔贯穿所述缓冲层的至少一部分。
在一种实施方式的柔性阵列基板中，所述柔性阵列基板包括阻挡层，所述阻挡层设置于所述薄膜晶体管层与所述柔性衬底之间；
所述柔性衬底包括第一柔性衬底、第二柔性衬底以及阻隔层，所述第二柔性衬底位于所述薄膜晶体管层与所述第一柔性衬底之间，所述阻隔层设置于所述第一柔性衬底与所述第二柔性衬底之间，所述第二柔性衬底中开设有第二通孔，所述第二通孔贯穿所述第一柔性衬底的至少一部分，所述阻挡层填充所述第二通孔。
在一种实施方式的柔性阵列基板中，所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影与所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影至少部分重叠；或者
所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影位于所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影的范围内。
在一种实施方式的柔性阵列基板中，所述第一通孔和所述第二通孔均为圆孔时，所述第二通孔的直径比所述第一通孔的直径大4微米。
在一种实施方式的柔性阵列基板中，所述第二通孔的深度大于所述第一通孔的深度。
在一种实施方式的柔性阵列基板中，所述柔性衬底还包括黏附层，所述黏附层设置于所述阻隔层与所述第二柔性衬底之间，所述第二通孔贯穿所述第二柔性衬底暴露出所述黏附层或者所述阻隔层。
 有益效果
本申请通过在薄膜晶体管层的多个绝缘层中开设第一通孔，当对柔性显示面板施加弯折力时，应力施加在第一通孔里，可有效减少弯折对柔性显示面板的损伤，改善产品弯折性能。进一步，使有机平坦层填充于第一通孔中，以有机材料代替绝缘层中的无机材料，进一步提高抗弯折能力，可以大幅度提升柔性显示面板的物理可弯折性。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请的第一实施方式的柔性显示面板的结构示意图；
图2为本申请的第二实施方式的柔性显示面板的结构示意图；
图3为本申请的第三实施方式的柔性显示面板的结构示意图；
图4为本申请的柔性显示面板的制造方法的流程图；
图5（a）至图5（d）为本申请的柔性显示面板的制造方法的步骤示意图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接，也可以包括第一和第二特征不是直接连接而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。
本申请提供一种柔性显示面板。本申请实施例中的显示面板可以用于手机、平板电脑、电子阅读器、电子展示屏、笔记本电脑、手机、增强现实(augmented reality，AR)\虚拟现实(virtual reality，VR)设备、媒体播放器、可穿戴设备、数码相机、车载导航仪等。
显示面板可以为有机发光二极管（Organic Light-emitting Diode，OLED）显示面板、量子点发光二极管（Quantum Dot Light-emitting Diode，QLED）显示面板、微发光二极管（Micro Light-emitting Diode，Micro-LED）显示面板、次毫米发光二极管（Mini Light-emitting Diode，Mini-LED）显示面板或者液晶（Liquid Crystal）显示面板。
以下，以用于OLED显示面板的柔性阵列基板为例说明本申请的柔性阵列基板。
请参考图1，柔性显示面板1包括显示区AA。可以理解，柔性显示面板1还包括围绕显示区AA的非显示区（未图示）。在本申请中，“显示区AA”是指用于柔性显示面板1上用于设置发光器件以及发光器件的像素驱动电路的区域，即由全部像素区域构成的区域。显示区AA周边的区域为非显示区。柔性显示面板1包括柔性阵列基板100，柔性阵列基板100包括柔性衬底10、设置于柔性衬底10上且位于显示区AA的薄膜晶体管层20以及覆盖于薄膜晶体管层20远离柔性衬底10的一侧的有机平坦层30。薄膜晶体管层20包括层叠设置的多个绝缘层。多个绝缘层包括钝化层PV和层间绝缘层IL等。薄膜晶体管层20远离柔性衬底10的表面20a开设有第一通孔VIA1。第一通孔VIA1贯穿多个绝缘层中的至少一个。有机平坦层30填充第一通孔VIA1。有机平坦层30可以是有机光阻材料。
本申请通过在薄膜晶体管层20的多个绝缘层中开设第一通孔VIA1，当对柔性阵列基板100施加弯折力时，应力施加在第一通孔VIA1里，可有效减少弯折对柔性阵列基板100的损伤，提升产品的弯折性能。进一步，使有机平坦层30填充于第一通孔VIA1中，以有机材料代替绝缘层中的无机材料，进一步提高抗弯折能力，可以大幅度提升柔性阵列基板100的物理可弯折性。
进一步，薄膜晶体管层20包括多个薄膜晶体管。第一通孔VIA1与薄膜晶体管相邻设置。本申请不限定第一通孔VIA1的个数与位置。可选的，可以在每个薄膜晶体管的周围各设置至少一个第一通孔VIA1。也可以是，多个第一通孔VIA1围绕一个薄膜晶体管设置。通过将第一通孔VIA1设置在薄膜晶体管周围，可更有效地保护薄膜晶体管，提高薄膜晶体管可靠性。多个薄膜晶体管相互间隔设置，第一通孔VIA1设置于多个薄膜晶体管之间。换句话说，第一通孔VIA1与薄膜晶体管层20中的每个薄膜晶体管均错开设置，在弯折时，避免影响薄膜晶体管。
具体地，OLED显示面板的驱动电路可以为2T1C、3T1C、5T1C或者7T1C等。图1的驱动电路为2T1C像素驱动电路，因此，多个薄膜晶体管包括驱动薄膜晶体管T1和开关薄膜晶体管T2。可以理解，根据驱动电路的类型不同，薄膜晶体管层20还可以包括其他薄膜晶体管。如图1所示，一个第一通孔VIA1与驱动薄膜晶体管T1相邻设置，另一个第一通孔VIA1与开关薄膜晶体管T2相邻设置。
从垂直于柔性衬底10的方向上看，薄膜晶体管层20包括半导体层SL、栅极绝缘层GI、栅极层GE、层间绝缘层IL、源漏极层SD和钝化层PV。半导体层SL设置于柔性衬底10上，栅极层GE设置于栅极层GE远离或者靠近柔性衬底10的一侧，栅极绝缘层GI设置于栅极层GE与半导体层SL之间，源漏极层SD设置于栅极层GE和半导体层SL远离柔性衬底10的一侧，层间绝缘层IL设置于源漏极层SD与半导体层SL之间，钝化层PV设置于源漏极层SD远离柔性衬底10的一侧，第一通孔VIA1贯穿钝化层PV的至少一部分或者，第一通孔VIA1贯穿层间绝缘层IL的至少一部分。第一通孔VIA1贯穿钝化层PV的至少一部分是指：第一通孔VIA1可以贯穿钝化层PV的一部分，也可以完全贯穿钝化层PV。第一通孔VIA1贯穿层间绝缘层IL的至少一部分是指：第一通孔VIA1完全贯穿钝化层PV并贯穿层间绝缘层IL的一部分，也可以完全贯穿钝化层PV和层间绝缘层IL。根据第一通孔VIA1的深度以及贯穿的膜层不同，第一通孔VIA1可以通过一道光罩刻蚀形成，也可以经过两道和两道以上光罩刻蚀形成。
可选的，如图1所示，本申请的薄膜晶体管为顶栅型薄膜晶体管。具体地，为自对准（self-alignment）型薄膜晶体管。半导体层SL设置于栅极层GE靠近柔性衬底10的一侧，第一通孔VIA1完全贯穿钝化层PV与层间绝缘层IL。进一步，柔性阵列基板100还包括缓冲层BL，缓冲层BL设置于薄膜晶体管层20与柔性衬底10之间。进一步，缓冲层BL设置于多个绝缘层与柔性衬底10之间。第一通孔VIA1贯穿缓冲层BL的至少一部分。进一步，缓冲层BL与柔性衬底10之间还设置有阻挡层BA。为了保持阻挡层BA的水氧阻隔效果，第一通孔VIA1不贯穿阻挡层BA。如图2所示，第一通孔VIA1完全贯穿钝化层PV并贯穿层间绝缘层IL的一部分。如图3所示，第一通孔VIA1完全贯穿钝化层PV。
具体地，栅极层GE包括间隔设置的第一栅极GE1和第二栅极GE2。栅极绝缘层GI包括间隔设置的第一栅极绝缘层GI1和第二栅极绝缘层GI2。半导体层SL包括间隔设置的第一半导体层SL1和第二半导体层SL2。源漏极层SD包括间隔设置的第一源极S1、第一漏极D1和第二源极S2、第二漏极D2。
第一半导体层SL1设置在柔性衬底10上，第一栅极绝缘层GI1设置在第一半导体层SL1远离柔性衬底10的表面，第一栅极GE1设置在第一栅极绝缘层GI1远离第一半导体层SL1的表面，第一源极S1和第一漏极D1设置于第一栅极GE1远离第一半导体层SL1的一侧，第一源极S1和第一漏极D1通过开设于层间绝缘层IL中的接触孔分别与第一半导体层SL1的两端连接。第一半导体层SL1可以包括半导体的沟道和位于沟道两侧的导体部。第一源极S1和第一漏极D1分别连接于第一半导体层SL1的两个导体部。驱动晶体管T1包括第一半导体层SL1、第一栅极绝缘层GI1、第一栅极GE1、第一源极S1和第一漏极D1。
第二半导体层SL2设置在柔性衬底10上，第二栅极绝缘层GI2设置在第二半导体层SL2远离柔性衬底10的表面，第二栅极GE2设置在第二栅极绝缘层GI2远离第二半导体层SL2的表面，第二源极S2和第二漏极D2设置于第二栅极GE2远离第二半导体层SL2的一侧，第二源极S2和第二漏极D2通过开设于层间绝缘层IL中的接触孔分别与第二半导体层SL2的两端连接。第二半导体层SL2可以包括半导体的沟道和位于沟道两侧的导体部。第二源极S2和第二漏极D2分别连接于第二半导体层SL2的两个导体部。开关晶体管T2包括第二半导体层SL2、第二栅极绝缘层GI2、第二栅极GE2、第二源极S2和第二漏极D2。
在本申请其他实施方式中，薄膜晶体管也可以为底栅型薄膜晶体管。根据薄膜晶体管的结构不同，当栅极绝缘层GI整面覆盖柔性衬底10时，第一通孔VIA1可以贯穿栅极绝缘层GI。
柔性衬底10包括第一柔性衬底11、第二柔性衬底12、阻隔层13以及黏附层14。第二柔性衬底12位于薄膜晶体管层20与第一柔性衬底11之间。阻隔层13设置于第一柔性衬底11与第二柔性衬底12之间，以阻隔水汽。黏附层14设置于阻隔层13与第二柔性衬底12之间，以增加第二柔性衬底12与阻隔层13之间的附着性。柔性有机层的材料选自聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚芳酯(PAR)、聚碳酸酯(PC)、聚醚酰亚胺(PEI)和聚醚砜(PES)中的一种或多种。阻隔层13的材料选自氧化硅，氮化硅、氮氧化硅等无机材料中的一种或多种。黏附层14的材料可以是a-si（非晶硅）。
可选的，第二柔性衬底12中开设有第二通孔VIA2。第二通孔VIA2贯穿第一柔性衬底11的至少一部分。第二通孔VIA2贯穿第一柔性衬底11的至少一部分是指：第二通孔VIA2贯穿第一柔性衬底11的一部分，或者第二通孔VIA2完全贯穿第一柔性衬底11。第二通孔VIA2可以贯穿第二柔性衬底12暴露出黏附层14或者阻隔层13。阻挡层BA填充第二通孔VIA2。第二通孔VIA2开孔设计是为了在第二柔性衬底12弯折的时候释放应力。进一步，第一通孔VIA1的孔壁VIA1a在第一柔性衬底11所在平面上的正投影与第二通孔VIA2的孔壁在第一柔性衬底11所在平面上的正投影至少部分重叠，或者第一通孔VIA1的孔壁在第一柔性衬底11所在平面上的正投影位于第二通孔VIA2的孔壁在第一柔性衬底11所在平面上的正投影的范围内。换句话说，第一通孔VIA1与第二通孔VIA2对应设置。通过将第一通孔VIA1与第二通孔VIA2设计成对应，可以形成深孔，更有助于应力释放在深孔里，减小弯折时对附近薄膜晶体管的影响。如果第一通孔VIA1与第二通孔VIA2错开设置，一方面会增加空间，另一方面可能会因为应力释放错位影响薄膜晶体管。当第一通孔VIA1的孔壁在第一柔性衬底11所在平面上的正投影位于第二通孔VIA2的孔壁在第一柔性衬底11所在平面上的正投影的范围内时，第一通孔VIA1的孔径小于第二通孔VIA2的孔径。这里的第一通孔VIA1的孔径和第二通孔VIA2的孔径均是指通孔的最大孔径。设计成第一通孔VIA1的孔径小于第二通孔VIA2主要是考虑第一通孔VIA1与第二通孔VIA2的对位重叠。可选的，为了保证第一通孔VIA1与第二通孔VIA2的对位，考虑到对位精度的问题，第二通孔VIA2相较于第一通孔VIA1允许有2微米左右的对位误差，即，当第一通孔VIA1和第二通孔VIA2均为圆孔时，第二通孔VIA2的直径比第一通孔VIA1的直径大4微米以上，可以保证二者的对位。可选的，第二通孔VIA2的深度H2大于第一通孔VIA1的深度H1。通孔深度越大，则缓解应力的作用越大。通过将第二通孔VIA2的深度H2设为大于第一通孔VIA1的深度H1，弯折时，应力集中在第二通孔VIA2，可以避免应力集中在第一通孔VIA1而影响到薄膜晶体管。具体地，第二通孔VIA2的深度H2为4微米至6微米。可以理解，本申请并不限定第一通孔VIA1和第二通孔VIA2的形状，第一通孔VIA1和第二通孔VIA2可以是矩形孔、方形孔或者圆形孔等。
除上面描述的柔性阵列基板100之外，显示面板1还包括第一电极200、像素定义层300、发光层400和第二电极500，第一电极200设置于柔性阵列基板100上，像素定义层300设置于第一电极200远离柔性阵列基板100的一侧，像素定义层300中开设有开口300a，发光层400设置于开口300a中，第二电极500覆盖于像素定义层300和发光层400上。第一电极200可以是阳极，第二电极500可以是阴极；或者第一电极200是阴极，第二电极500是阳极。
本申请还提供一种柔性显示面板的制造方法，其用于制造上述柔性显示面板。如图4所示，柔性显示面板的制造方法包括以下步骤：
101：在柔性衬底上形成薄膜晶体管层，薄膜晶体管层包括层叠设置的多个绝缘层。
多个绝缘层包括钝化层和层间绝缘层等。薄膜晶体管层包括多个薄膜晶体管。多个薄膜晶体管包括驱动薄膜晶体管和开关薄膜晶体管。多个薄膜晶体管相互间隔设置。
可选的，在步骤101中，在柔性衬底上形成薄膜晶体管层的步骤之前还可以包括步骤：
在柔性阵列基板上形成缓冲层，在缓冲层上形成阻挡层。
可选的，在步骤101中还可以包括：
步骤1011：在第二柔性衬底中开设第二通孔，第二通孔贯穿第一柔性衬底的至少一部分，阻挡层填充第二通孔。第二通孔开孔设计是为了在第二柔性衬底弯折的时候释放应力。
并且，在步骤102中，在对应第二通孔的位置形成第一通孔。第一通孔的孔壁在第一柔性衬底所在平面上的正投影与第二通孔的孔壁在第一柔性衬底所在平面上的正投影至少部分重叠，或者第一通孔的孔壁在第一柔性衬底所在平面上的正投影位于第二通孔的孔壁在第一柔性衬底所在平面上的正投影的范围内。
通过将第一通孔与第二通孔设计成对应，可以形成深孔，更有助于应力释放在深孔里，减小弯折时对附近薄膜晶体管的影响。如果第一通孔与第二通孔错开设置，一方面会增加空间，另一方面可能会因为应力释放错位影响薄膜晶体管。当第一通孔的孔壁在第一柔性衬底所在平面上的正投影位于第二通孔的孔壁在第一柔性衬底所在平面上的正投影的范围内时，第一通孔的孔径小于第二通孔的孔径。设计成第一通孔的孔径小于第二通孔主要是考虑第一通孔与第二通孔的对位重叠。可选的，为了保证第一通孔与第二通孔的对位，考虑到对位精度的问题，第二通孔相较于第一通孔允许有2微米左右的对位误差，即，当第一通孔VIA1和第二通孔VIA2均为圆孔时，第二通孔的直径比第一通孔的直径大4微米以上，可以保证二者的对位。可选的，第二通孔的深度大于第一通孔的深度。通孔深度越大，则缓解应力的作用越大。通过将第二通孔的深度设为大于第一通孔的深度，弯折时，应力集中在第二通孔，可以避免应力集中在第一通孔而影响到薄膜晶体管。具体地，第二通孔的深度为4微米至6微米。具体地，第二通孔的深度为4微米至6微米。可以理解，本申请并不限定第一通孔VIA1和第二通孔VIA2的形状，第一通孔VIA1和第二通孔VIA2可以是矩形孔、方形孔或者圆形孔等。
102：在薄膜晶体管层远离柔性衬底的表面开设第一通孔，第一通孔贯穿多个绝缘层中的至少一个。
第一通孔设置于多个薄膜晶体管之间。换句话说，第一通孔与薄膜晶体管层中的每个薄膜晶体管均错开设置。通过将第一通孔设置在薄膜晶体管周围，可更有效地保护薄膜晶体管，提高薄膜晶体管可靠性。本申请不限定第一通孔的个数与位置。可选的，可以在每个薄膜晶体管的周围各设置至少一个第一通孔。
可选的，第一通孔贯穿钝化层的至少一部分或者，第一通孔贯穿层间绝缘层的至少一部分。进一步，第一通孔贯穿缓冲层的至少一部分。更具体的，第一通孔贯穿一部分的缓冲层。为了保持阻挡层的水氧阻隔效果，第一通孔不贯穿阻挡层。
103：在薄膜晶体管层远离柔性衬底的一侧形成有机钝化层，有机平坦层填充第一通孔，得到柔性阵列基板。
在步骤103中，有机平坦层可以是有机光阻材料。
在薄膜晶体管层远离柔性衬底的一侧形成有机钝化层具体包括步骤：
在薄膜晶体管层远离柔性衬底的一侧形成有机光阻层，在有机光阻层中开设电极连接孔。
104：在柔性阵列基板上形成第一电极层、像素定义层、发光层和第二电极层，得到柔性显示面板。
以下，通过具体的例子说明本申请的实施方式。
本申请的一个实施方式的柔性阵列基板的制造方法包括：
步骤201：请参考图5（a），提供柔性衬底10，柔性衬底10包括依次层叠的第一柔性衬底11、阻隔层13、黏附层14以及第二柔性衬底12。其中，第一柔性衬底11与第二柔性衬底12为聚酰亚胺，阻隔层13为氧化硅，黏附层14为非晶硅。第二柔性衬底12的厚度为5微米至10微米。利用黄光制程在第二柔性衬底12中开设第二通孔VIA2。第二通孔VIA2贯穿第二柔性衬底12暴露出黏附层14。
第二通孔VIA2的深度H2为4微米至6微米。
步骤202：请参考图5（a），在柔性衬底10上沉积阻挡层BA，在阻挡层BA上形成缓冲层BL。阻挡层BA包括依次层叠设置的氧化硅、氮化硅和氧化硅。阻挡层BA的总厚度为1000埃至5000埃。
步骤203：请参考图5（b），在缓冲层BL上形成半导体材料层（未图示），半导体材料层包括第一半导体材料层和第二半导体材料层。半导体材料层的材料可以为IGZO、ITZO或IGZTO。半导体层SL的厚度为100埃至1000埃。
步骤204：在半导体层SL上沉积栅极绝缘材料层，栅极绝缘材料层的材料为氧化硅，厚度1000埃至3000埃。
步骤205：在栅极绝缘层GI上沉积栅极金属层，栅极金属层的材料可以是单层Mo，Al，Cu，Ti等，也可以是Mo/Al/Mo、Al/Mo、Mo/Cu、MoTi/Cu等多层金属，厚度为500埃至10000埃。
步骤206：利用一道光罩，定义出栅极层GE和栅极绝缘层GI。栅极绝缘层GI包括第一栅极绝缘层GI1和第二栅极绝缘层GI2。第一栅极绝缘层GI1位于第一半导体层SL1上。第二栅极绝缘层GI2位于第二半导体层SL2上。栅极层GE包括第一栅极GE1层和第二栅极GE2层。第一栅极GE1层位于第一栅极绝缘层GI1上。第二栅极GE2层位于第二栅极绝缘层GI2上。具体地，采用湿蚀刻先蚀刻栅极金属层，再利用图案化的第一栅极GE1和第二栅极GE2图形为自对准，干法蚀刻栅极绝缘层GI，得到第一栅极绝缘层GI1和第二栅极绝缘层GI2。
步骤207：采用等离子（Plasma）处理对上方没有栅极绝缘层GI保护的半导体材料层进行导体化处理，形成N掺杂的导体区域，作为与源极和漏极接触的源极区和漏极区。栅极绝缘层GI下方的半导体材料层不做处理，作为薄膜晶体管沟道，形成包含第一半导体层SL1和第二半导体层SL2的半导体层SL。
步骤208：沉积氧化硅膜作为层间绝缘层IL，厚度在3000埃至10000埃，并且在层间绝缘层IL中蚀刻出源极、漏极与半导体层SL的接触孔。同时还可以蚀刻出缓冲孔，以便后续形成第一通孔。缓冲孔位于第一半导体层SL1与第二半导体层SL2之间。
步骤209：沉积源漏金属层，源漏金属层材料可以是Mo，Al，Cu，Ti等，或者是Mo，Al，Cu，Ti的合金，源漏金属层的厚度为2000埃至10000埃，然后通过黄光制程形成隔设置的第一源极S1、第一漏极D1和第二源极S2、第二漏极D2。第一源极S1和第一漏极D1通过开设于层间绝缘层IL中的过孔分别与第一半导体层SL1的两端连接。第二源极S2和第二漏极D2通过开设于层间绝缘层IL中的接触孔分别与第二半导体层SL2的两端连接。
步骤210：沉积钝化层PV，钝化层PV可以为氧化硅薄膜，厚度为1000埃至5000埃，并在缓冲孔的基础上蚀刻形成第一通孔VIA1，同时蚀刻形成和第一搭接孔CH1。第一搭接孔CH1贯穿钝化层PV，暴露出第一漏极D1。
步骤211：请参考图5（c），沉积有机光阻材料作为有机平坦层30。可以是不同成分的光阻层，有机平坦层30的厚度为10000埃至50000埃，有机平坦层30填充第一通孔VIA1。另外，在步骤211中，还可以通过黄光制程在有机平坦层30上形成第二搭接孔CH2，第二搭接孔CH2与第一搭接孔CH1，得到柔性阵列基板100。
步骤212：请参考图5（d），沉积第一电极200，第一电极200为阳极，第一电极200包括具有高反射率的金属材料，包括但不局限于ITO/Ag/ITO，IZO/Ag/IZO，ITO/Al/ITO或者IZO/Al/IZO等，第一电极200通过第一搭接孔CH1和第二搭接孔CH2与驱动薄膜晶体管T1搭接；
步骤213：形成像素定义层300，像素定义层300的厚度在10000埃至20000埃，通过黄光制程定义出开口300a。
步骤214：在开口300a中形成发光层400。
步骤215：在发光层400和像素定义层300上形成第二电极500，第二电极500是阴极，得到完成显示面板。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种柔性显示面板，包括显示区，其中，所述柔性显示面板包括：
    柔性衬底；
    薄膜晶体管层，设置于所述柔性衬底上且位于所述显示区，所述薄膜晶体管层包括层叠设置的多个绝缘层，所述薄膜晶体管层远离所述柔性衬底的表面开设有第一通孔，所述第一通孔贯穿所述多个绝缘层中的至少一个；以及
    有机平坦层，覆盖于所述薄膜晶体管层远离所述柔性衬底的一侧，并填充所述第一通孔。
  2. 如权利要求1所述的柔性显示面板，其中，所述薄膜晶体管层包括薄膜晶体管，所述第一通孔与所述薄膜晶体管相邻设置。
  3. 如权利要求1所述的柔性显示面板，其中，所述多个绝缘层包括栅极绝缘层、层间绝缘层、源漏极层以及钝化层，所述薄膜晶体管层还包括半导体层和栅极层，所述半导体层设置于所述柔性衬底上，所述栅极层设置于所述半导体层远离或者靠近所述柔性衬底的一侧，所述栅极绝缘层设置于所述栅极层与所述半导体层之间，所述源漏极层设置于所述栅极层和所述半导体层远离所述柔性衬底的一侧，所述层间绝缘层设置于所述源漏极层与所述半导体层之间，所述钝化层设置于所述源漏极层远离所述柔性衬底的一侧，所述第一通孔贯穿所述钝化层的至少一部分，或者，所述第一通孔贯穿所述层间绝缘层的至少一部分。
  4. 如权利要求3所述的柔性显示面板，其中，所述柔性显示面板还包括缓冲层，所述缓冲层设置于所述多个绝缘层与所述柔性衬底之间，所述第一通孔贯穿所述缓冲层的至少一部分。
  5. 如权利要求1所述的柔性显示面板，其中，所述柔性显示面板包括阻挡层，所述阻挡层设置于所述薄膜晶体管层与所述柔性衬底之间；
    所述柔性衬底包括第一柔性衬底、第二柔性衬底以及阻隔层，所述第二柔性衬底位于所述薄膜晶体管层与所述第一柔性衬底之间，所述阻隔层设置于所述第一柔性衬底与所述第二柔性衬底之间，所述第二柔性衬底中开设有第二通孔，所述第二通孔贯穿所述第一柔性衬底的至少一部分，所述阻挡层填充所述第二通孔。
  6. 如权利要求5所述的柔性显示面板，其中，所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影与所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影至少部分重叠；或者
    所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影位于所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影的范围内。
  7. 如权利要求6所述的柔性显示面板，其中，所述第一通孔和所述第二通孔均为圆孔时，所述第二通孔的直径比所述第一通孔的直径大4微米。
  8. 如权利要求5所述的柔性显示面板，其中，所述第二通孔的深度大于所述第一通孔的深度。
  9. 如权利要求5所述的柔性显示面板，其中，所述柔性衬底还包括黏附层，所述黏附层设置于所述阻隔层与所述第二柔性衬底之间，所述第二通孔贯穿所述第二柔性衬底暴露出所述黏附层或者所述阻隔层。
  10. 如权利要求9所述的柔性显示面板，其中，所述柔性显示面板还包括第一电极、像素定义层、发光层和第二电极，第一电极设置于所述薄膜晶体管层上，所述像素定义层设置于所述第一电极远离所述薄膜晶体管层的一侧，所述像素定义层中开设有开口，所述发光层设置于所述开口中，所述第二电极覆盖于所述像素定义层和所述发光层上。
  11. 一种柔性阵列基板，包括显示区，其中，所述柔性阵列基板包括：
    柔性衬底；
    薄膜晶体管层，设置于所述柔性衬底上且位于所述显示区，所述薄膜晶体管层包括层叠设置的多个绝缘层，所述薄膜晶体管层远离所述柔性衬底的表面开设有第一通孔，所述第一通孔贯穿所述多个绝缘层中的至少一个；以及
    有机平坦层，覆盖于所述薄膜晶体管层远离所述柔性衬底的一侧，并填充所述第一通孔。
  12. 如权利要求11所述的柔性阵列基板，其中，所述薄膜晶体管层包括薄膜晶体管，所述第一通孔与所述薄膜晶体管相邻设置。
  13. 如权利要求11所述的柔性阵列基板，其中，所述多个绝缘层包括栅极绝缘层、层间绝缘层、源漏极层以及钝化层，所述薄膜晶体管层还包括半导体层和栅极层，所述半导体层设置于所述柔性衬底上，所述栅极层设置于所述半导体层远离或者靠近所述柔性衬底的一侧，所述栅极绝缘层设置于所述栅极层与所述半导体层之间，所述源漏极层设置于所述栅极层和所述半导体层远离所述柔性衬底的一侧，所述层间绝缘层设置于所述源漏极层与所述半导体层之间，所述钝化层设置于所述源漏极层远离所述柔性衬底的一侧，所述第一通孔贯穿所述钝化层的至少一部分，或者，所述第一通孔贯穿所述层间绝缘层的至少一部分。
  14. 如权利要求13所述的柔性阵列基板，其中，所述柔性阵列基板还包括缓冲层，所述缓冲层设置于所述多个绝缘层与所述柔性衬底之间，所述第一通孔贯穿所述缓冲层的至少一部分。
  15. 如权利要求11所述的柔性阵列基板，其中，所述柔性阵列基板包括阻挡层，所述阻挡层设置于所述薄膜晶体管层与所述柔性衬底之间；
    所述柔性衬底包括第一柔性衬底、第二柔性衬底以及阻隔层，所述第二柔性衬底位于所述薄膜晶体管层与所述第一柔性衬底之间，所述阻隔层设置于所述第一柔性衬底与所述第二柔性衬底之间，所述第二柔性衬底中开设有第二通孔，所述第二通孔贯穿所述第一柔性衬底的至少一部分，所述阻挡层填充所述第二通孔。
  16. 如权利要求15所述的柔性阵列基板，其中，所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影与所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影至少部分重叠；或者
    所述第一通孔的孔壁在所述第一柔性衬底所在平面上的正投影位于所述第二通孔的孔壁在所述第一柔性衬底所在平面上的正投影的范围内。
  17. 如权利要求16所述的柔性阵列基板，其中，所述第一通孔和所述第二通孔均为圆孔时，所述第二通孔的直径比所述第一通孔的直径大4微米。
  18. 如权利要求15所述的柔性阵列基板，其中，所述第二通孔的深度大于所述第一通孔的深度。
  19. 如权利要求15所述的柔性阵列基板，其中，所述柔性衬底还包括黏附层，所述黏附层设置于所述阻隔层与所述第二柔性衬底之间，所述第二通孔贯穿所述第二柔性衬底暴露出所述黏附层或者所述阻隔层。
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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424957A (zh) * 2017-06-16 2017-12-01 武汉华星光电半导体显示技术有限公司 柔性tft基板的制作方法
CN107658333A (zh) * 2017-10-31 2018-02-02 京东方科技集团股份有限公司 一种柔性显示面板及其制造方法、柔性显示装置
CN109166880A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN109166862A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
US10269830B1 (en) * 2017-11-27 2019-04-23 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Flexible array substrate and manufacturing method thereof
CN110690226A (zh) * 2019-09-03 2020-01-14 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795403B (zh) * 2015-04-16 2016-08-31 京东方科技集团股份有限公司 一种柔性基板及其制作方法、显示装置
CN207409491U (zh) * 2017-10-31 2018-05-25 京东方科技集团股份有限公司 一种柔性显示面板及柔性显示装置
CN108400261B (zh) * 2018-05-02 2020-11-24 京东方科技集团股份有限公司 一种柔性显示器件及其制作方法
CN109192878B (zh) * 2018-08-30 2019-11-26 武汉华星光电半导体显示技术有限公司 柔性oled显示面板
CN110610966B (zh) * 2019-08-26 2022-03-29 武汉华星光电半导体显示技术有限公司 显示装置
KR20210025738A (ko) * 2019-08-27 2021-03-10 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN111244111A (zh) * 2020-01-20 2020-06-05 京东方科技集团股份有限公司 阵列基板及显示装置
CN112490271A (zh) * 2020-11-26 2021-03-12 京东方科技集团股份有限公司 一种显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424957A (zh) * 2017-06-16 2017-12-01 武汉华星光电半导体显示技术有限公司 柔性tft基板的制作方法
CN107658333A (zh) * 2017-10-31 2018-02-02 京东方科技集团股份有限公司 一种柔性显示面板及其制造方法、柔性显示装置
US10269830B1 (en) * 2017-11-27 2019-04-23 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Flexible array substrate and manufacturing method thereof
CN109166880A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN109166862A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN110690226A (zh) * 2019-09-03 2020-01-14 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板

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