WO2021190162A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021190162A1
WO2021190162A1 PCT/CN2021/074947 CN2021074947W WO2021190162A1 WO 2021190162 A1 WO2021190162 A1 WO 2021190162A1 CN 2021074947 W CN2021074947 W CN 2021074947W WO 2021190162 A1 WO2021190162 A1 WO 2021190162A1
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Prior art keywords
insulating layer
display area
layer
display
base substrate
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PCT/CN2021/074947
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English (en)
French (fr)
Inventor
孟秋华
田雪雁
左岳平
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京东方科技集团股份有限公司
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Priority to US17/913,778 priority Critical patent/US20240215393A1/en
Publication of WO2021190162A1 publication Critical patent/WO2021190162A1/zh
Priority to US18/198,951 priority patent/US20230292577A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • This application relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display panel.
  • the present application discloses a display substrate, a preparation method thereof, and a display panel, with the purpose of improving the bending resistance of the flexible display panel and improving the yield rate of flexible display products.
  • a display substrate includes:
  • a base substrate having a display area and a non-display area surrounding the display area
  • the gate layer is located on the base substrate
  • the interlayer insulating layer is located on the side of the gate layer away from the base substrate, and includes a first organic insulating layer and a first inorganic insulating layer; the first organic insulating layer covers the display area and part of the Non-display area
  • the source and drain layer is located on the side of the interlayer insulating layer away from the base substrate;
  • the encapsulation layer covers the display area and part of the non-display area, and the orthographic projection of the boundary of the encapsulation layer on the base substrate surrounds the orthographic projection of the first organic insulating layer on the base substrate.
  • the non-display area includes a fan-shaped wiring area and a binding area located on a first side of the display area, and a gate driving circuit area located on at least one of two opposite sides of the display area, the The opposite sides are adjacent to the first side;
  • the first organic insulating layer covers the gate driving circuit area, and the orthographic projection of the first organic insulating layer on the base substrate does not overlap the bonding area.
  • the first inorganic insulating layer covers at least a part of the non-display area, and the orthographic projection of the first inorganic insulating layer in the non-display area and the first organic insulating layer in the non-display area The orthographic projections of the regions overlap.
  • the first inorganic insulating layer covers the fan-shaped wiring area and the binding area.
  • the orthographic projection of the first inorganic insulating layer on the base substrate is located in the non-display area and surrounds the display area, and the first inorganic insulating layer is located in the first organic insulating layer away from the One side of the gate layer, and the first inorganic insulating layer covers the boundary of the first organic insulating layer.
  • the orthographic projection of the first inorganic insulating layer on the base substrate does not overlap with the gate driving circuit area.
  • the first inorganic insulating layer is located between the gate layer and the first organic insulating layer; the first inorganic insulating layer covers the display area and the non-display area.
  • a portion of the first inorganic insulating layer covering the display area is provided with a hollow portion, and the hollow portion does not overlap with the pattern of the gate layer.
  • the display substrate further includes at least one layer of barrier dams located in the non-display area and sequentially arranged along the direction from the display area to the non-display area;
  • the orthographic projection of the boundary of the first organic insulating layer on the base substrate is located on the side of the last barrier dam facing the display area.
  • the thickness of the first organic insulating layer is 1 ⁇ m-2 ⁇ m; the thickness of the first inorganic insulating layer is 50 nm-150 nm.
  • a display panel includes the display substrate as described in any one of the above.
  • a method for preparing a display substrate includes:
  • the base substrate has a display area and a non-display area surrounding the display area;
  • the interlayer insulating layer includes a first organic insulating layer and a first inorganic insulating layer; the first organic insulating layer covers the display area and part of the non-display area. Area;
  • An encapsulation layer is prepared on the source and drain layer, the encapsulation layer covers the display area and part of the non-display area, and the orthographic projection of the boundary of the encapsulation layer on the base substrate surrounds the first organic The orthographic projection of the insulating layer on the base substrate.
  • preparing an interlayer insulating layer on the gate layer specifically includes:
  • a first inorganic insulating layer is deposited on the first organic insulating layer, and a pattern of the first inorganic insulating layer is formed by a patterning process; the orthographic projection of the pattern of the first inorganic insulating layer on the base substrate is located in the The non-display area surrounds the display area, and the pattern of the first inorganic insulating layer covers the boundary of the first organic insulating layer.
  • preparing an interlayer insulating layer on the gate layer specifically includes:
  • a first organic insulating layer is deposited on the first inorganic insulating layer, and a pattern of the first organic insulating layer is formed through a patterning process.
  • FIG. 1 is a schematic diagram of the front structure of a display substrate provided by an embodiment of the application:
  • FIG. 2 is a schematic diagram of a partial cross-sectional structure of a display substrate along the direction X1-X2 in FIG. 1 according to an embodiment of the application;
  • FIG. 3 is a schematic diagram of a partial cross-sectional structure of a display substrate along the direction X3-X4 in FIG. 1 according to an embodiment of the application;
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a display substrate along the X1-X2 direction in FIG. 1 according to another embodiment of the application;
  • FIG. 5 is a schematic diagram of a partial cross-sectional structure of a display substrate along the X3-X4 direction in FIG. 1 according to another embodiment of the application;
  • FIG. 6 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of a display substrate during the manufacturing process according to an embodiment of the application.
  • FIG. 8 is a schematic diagram of a partial cross-sectional structure of a display substrate during the manufacturing process according to another embodiment of the application.
  • Polysilicon thin film transistors Poly TFTs
  • PI substrates flexible substrates
  • the bending performance can be specifically improved by selecting an organic interlayer insulating layer instead of an inorganic interlayer insulating layer to improve the bending resistance of the backplane.
  • the organic interlayer insulating layer replaces the inorganic layer, it is prone to poor packaging and wiring breakdown and burnout, resulting in poor display substrate failure.
  • the embodiments of the present application disclose a display substrate, a preparation method thereof, and a display panel. Specifically, by improving the structure of the interlayer insulating layer of the thin film transistor in the flexible display panel, the bending resistance of the flexible display substrate is improved, and packaging defects are avoided. Wire breakdown and burn damage, etc., thereby improving the yield of flexible display products.
  • FIGS. 2 and 3 are cross-sectional views of the display substrate in a specific embodiment
  • FIGS. 4 and 5 are the display substrate in another specific embodiment. Sectional view.
  • FIGS. 2 and 4 are schematic cross-sectional views of the substrate shown in FIG. 1 along the X1-X2 direction
  • FIGS. 3 and 5 are schematic cross-sectional views of the substrate shown in FIG. 1 along the X3-X4 direction. It should be noted that, in order to express as clearly as possible the approximate position and shape of each structure in the substrate, the cross-sectional schematic diagrams of FIGS.
  • FIGS. 2 and 4 are not completely consistent with the specific structural conditions shown in the cross-sectional schematic diagrams of FIGS. 3 and 5, for example,
  • the cross-sectional views of FIGS. 2 and 4 show the TFT 3 and the storage capacitor 4 in the pixel circuit in the display area AA, while the display area AA in FIGS. 3 and 5 only roughly shows the position of the pixel circuit 100.
  • the light-emitting structure 200 driven by the pixel circuit 100 is mainly illustrated.
  • FIGS. 3 and 5 illustrate the composite structure of the inorganic layer 51 and the organic layer 52 and the barrier dam 6 structure in the encapsulation layer 5, and FIG. 2 and FIG. 4 is not shown.
  • FIGS. 2 and 4 and the cross-sectional schematic diagrams of FIGS. 3 and 5 respectively only embody a part of the specific structure, those skilled in the art can fully understand the overall structure of the cross-section based on common knowledge. Go into details again.
  • an embodiment of the present application provides a display substrate, including:
  • the base substrate 1 has a display area AA and a non-display area surrounding the display area AA;
  • the gate layer (for example, the gate metal layer) is located on the base substrate 1;
  • the interlayer insulating layer 2 is located on the side of the gate layer away from the base substrate 1 and includes a first organic insulating layer 21 and a first inorganic insulating layer 22; the first organic insulating layer 21 covers the display area AA and part of the non-display area;
  • the source/drain layer (for example, the source/drain metal layer) is located on the side of the interlayer insulating layer 2 away from the base substrate 1;
  • the encapsulation layer 5 covers the display area AA and part of the non-display area, and the orthographic projection of the boundary of the encapsulation layer 5 on the base substrate 1 surrounds the orthographic projection of the first organic insulating layer 21 on the base substrate 1.
  • the display substrate includes a pixel circuit located in the display area AA and metal traces located in the non-display area.
  • the pixel circuit 100 includes a thin film transistor (TFT) 3 and a storage capacitor 4 and other device structures.
  • the gate layer (for example, the gate metal layer) may include the gate 31 of the TFT 3, the bottom electrode 41 and the top electrode 42 of the storage capacitor 4, and the gate layer metal trace 91 in the non-display area.
  • the source and drain layer (for example, the source and drain metal layer) may include the source 32 and the drain 33 of the TFT 3, the connecting lead 43 of the bottom electrode 41 of the storage capacitor 4, and the source and drain layer metal traces 92 and the non-display area. Connection terminal 93 and other structures.
  • an interlayer insulating layer 2 is provided between the gate metal wiring layer and the source and drain metal wiring layers.
  • the interlayer insulating layer 2 is combined with the first organic insulating layer 21 and the first inorganic insulating layer 22 Structure, wherein the first organic insulating layer 21 covers the display area AA and part of the non-display area, which can effectively buffer the stress, thereby protecting the gate metal layer and the source and drain metal layers on the upper and lower sides, compared with the conventional inorganic interlayer
  • the insulating layer can effectively improve the bending resistance of the display substrate.
  • the orthographic projection of the boundary of the encapsulation layer 5 surrounds the orthographic projection of the first organic insulating layer 21, that is, the first organic insulating layer 21 is located within the encapsulation layer 5, and the boundary of the first organic insulating layer 21 does not exceed the boundary of the encapsulation layer 5. Furthermore, the intrusion of water vapor through the first organic insulating layer 21 can be effectively prevented, and the packaging yield can be ensured. In addition, the arrangement of the first inorganic insulating layer 22 can achieve a good insulation protection effect, prevent the metal traces from breakdown and burnout, and thereby ensure the yield of the display substrate driving circuit.
  • the display substrate disclosed in the embodiments of the present application can improve the bending resistance of the flexible display substrate by improving the structure of the interlayer insulating layer of the thin film transistor in the flexible display panel, and avoid packaging defects and wiring breakdown and burnout.
  • it is especially suitable for folding or heterogeneous AMOLED displays that require high bending strength.
  • the non-display area includes a fan-shaped routing area (Fanout area) CC and a binding area (Bongding area) BB located on the first side of the display area AA, and located in the display area AA At least one of the gate drive circuit regions (GOA regions) DD of the opposite two sides is adjacent to the first side.
  • a fan-shaped routing area (Fanout area) CC and a binding area (Bongding area) BB located on the first side of the display area AA, and located in the display area AA
  • At least one of the gate drive circuit regions (GOA regions) DD of the opposite two sides is adjacent to the first side.
  • the first organic insulating layer 21 covers the gate driving circuit region DD. As shown in FIGS. 2 and 4, the orthographic projection of the first organic insulating layer 21 on the base substrate 1 does not overlap with the bonding area BB.
  • the bending line generally passes through the gate drive circuit area DD on the opposite sides of the display area AA and the display area AA, and the first organic insulating layer 21 covers the gate drive circuit area DD. Effectively improve the bending resistance of the gate drive circuit area DD, thereby improving the overall bending performance of the display substrate, so that the display substrate can meet the requirements of large-angle bending strength.
  • the bonding area BB is outside the boundary of the encapsulation layer 5 and is not covered by the encapsulation layer 5 above it.
  • the orthographic projection of the first organic insulating layer 21 does not overlap with the bonding area BB, which can prevent water vapor from invading the substrate along the first organic insulating layer 21 Internally, the package yield rate is guaranteed.
  • the first inorganic insulating layer 22 covers at least part of the non-display area, and the orthographic projection of the first inorganic insulating layer 22 in the non-display area is in contrast to the first organic insulating layer 21 in the non-display area.
  • the orthographic projections of the display areas overlap.
  • the first inorganic insulating layer 22 covers the sector-shaped wiring area CC and the bonding area BB.
  • the non-display area has fewer insulating film layers and densely distributed metal traces, such as the fan-shaped wiring area CC and the bonding area BB, so it is easier to cause wiring breakdown and burnout.
  • the first inorganic insulating layer 22 covers the non-display area, which can effectively prevent the display substrate from wire burnout, thereby ensuring the yield of the display substrate drive circuit.
  • the orthographic projection of the first inorganic insulating layer 22 in the non-display area overlaps with the orthographic projection of the first organic insulating layer 21 in the non-display area, which can prevent water vapor from entering the substrate along the first organic insulating layer 21, thereby effectively improving the display The package waterproof performance of the substrate.
  • the orthographic projection of the first inorganic insulating layer 22 on the base substrate 1 is located in the non-display area and surrounds the display area AA, and the first inorganic insulating layer 22 is located in the second
  • An organic insulating layer 21 is on a side away from the gate layer, and the first inorganic insulating layer 22 covers the boundary of the first organic insulating layer 21.
  • the first inorganic insulating layer 22 is located on the side of the first organic insulating layer 21 away from the gate layer, that is, the gate layer, the first organic insulating layer 21, and the first inorganic insulating layer 22 are sequentially arranged on the base substrate 1. And the source and drain layer. At this time, in the interlayer insulating layer 2, the first inorganic insulating layer 22 is located above the first organic insulating layer 21. Compared with the first organic insulating layer 21, the first inorganic insulating layer 22 has an influence on the bending performance of the gate layer.
  • the first inorganic insulating layer 22 is only arranged in the non-display area, that is, the display area AA is not covered by the first inorganic insulating layer 22, which can improve the bending performance of the entire display area AA, thereby effectively improving The bending performance of the entire display substrate.
  • the first inorganic insulating layer 22 is located above the first organic insulating layer 21 and covers the boundary of the first organic insulating layer 21, which can effectively prevent water vapor from entering the inside of the panel through the first organic insulating layer 21, thereby effectively improving the packaging of the display substrate. Waterproof performance.
  • the orthographic projection of the first inorganic insulating layer 22 on the base substrate 1 does not overlap with the gate driving circuit area DD, that is, the first inorganic insulating layer 22 does not cover the display area AA opposite.
  • Gate drive circuit area (GOA area) DD on both sides. In this way, the bending performance of the non-display areas on both sides of the display area AA can be further improved, thereby further improving the bending performance of the entire display substrate.
  • the first inorganic insulating layer 22 is located between the gate layer and the first organic insulating layer 21; the first inorganic insulating layer 22 covers the display area AA and non- Display area.
  • the first inorganic insulating layer 22 is located between the gate layer and the first organic insulating layer 21, that is, the gate layer, the first inorganic insulating layer 22, the first organic insulating layer 21, and the first organic insulating layer 21 are sequentially arranged on the base substrate 1. Source and drain layer. At this time, in the interlayer insulating layer 2, the first organic insulating layer 21 is located above the first inorganic insulating layer 22. Compared with the first inorganic insulating layer 22, the first organic insulating layer 21 has an influence on the bending performance of the gate layer. Larger, the first organic insulating layer 21 can effectively protect the underlying gate layer from bending damage, thereby effectively improving the bending performance of the display substrate.
  • the first inorganic insulating layer 22 can be set to cover both the display area AA and the non-display area.
  • the patterning process steps of the first inorganic insulating layer 22 can be reduced, and on the other hand, the display area can be increased. Insulation effect between AA metal layers.
  • the portion of the first inorganic insulating layer 22 covering the display area AA may be provided with a hollow portion 220, and the hollow portion 220 does not overlap the pattern of the gate layer. That is, the area of the first inorganic insulating layer 22 without the gate layer pattern in the display area AA may be hollowed out.
  • the pixel circuit includes a device structure with a gate metal pattern such as a thin film transistor 3 (TFT) and a storage capacitor 4, the first inorganic insulating layer 22 covers the gate layer pattern in the thin film transistor 3 and the storage capacitor 4, and the first inorganic
  • the insulating layer 22 is provided with a hollow portion 220 between the thin film transistor 3 and the storage capacitor 4, that is, the first inorganic insulating layer 22 does not cover the portion between the thin film transistor 3 and the storage capacitor 4 without the gate layer pattern.
  • the first inorganic insulating layer 22 is provided with a hollow portion 220 in the region without the gate layer pattern, which can not only ensure the insulating effect of the first inorganic insulating layer 22 between the gate metal layer and the source and drain metal layers, but also When the display substrate is bent, the stress near the first inorganic insulating layer 22 is released, thereby improving the stress buffer effect of the display area, and improving the bending performance of the display substrate.
  • the first organic insulating layer 21 can also cover the first organic insulating layer at the same time. The inorganic insulating layer 22 and the hollow portion thereof can improve the adhesion between the first organic insulating layer 21 and the base substrate 1, thereby avoiding problems such as peeling of the first organic insulating layer 21.
  • the specific arrangement of the first inorganic insulating layer 22 is not limited to the description in the embodiment of the present application.
  • the first inorganic insulating layer 22 may also be arranged.
  • the first inorganic insulating layer 22 may also cover the display area AA, and a hollow portion is provided in the first inorganic insulating layer 22 to avoid affecting the bending performance of the display area AA.
  • the display substrate of the present application further includes at least one layer of blocking dams 6 located in the non-display area and sequentially arranged along the direction from the display area AA to the non-display area.
  • the barrier dam 6 can be prepared in the same layer as the pixel defining structure 7, or it can also include other film patterns.
  • the encapsulation layer 5 generally includes two inorganic layers 51 and an organic layer 52.
  • the barrier dam 6 is mainly used to avoid encapsulation.
  • the organic layer 52 of layer 5 extends beyond the encapsulation area and prevents water vapor from entering the encapsulation area.
  • the orthographic projection of the boundary of the first organic insulating layer 21 on the base substrate 1 is located on the side of the barrier dam 6 of the last layer facing the display area AA, that is, the boundary of the first organic insulating layer 21 does not exceed the barrier dam 6 , It will not extend beyond the encapsulation area, so that water vapor can be prevented from entering the interior of the substrate through the first organic insulating layer 21.
  • the thickness of the first organic insulating layer 21 in the interlayer insulating layer 2 is much greater than the thickness of the first inorganic insulating layer 22.
  • the thickness of the first organic insulating layer 21 may be about 1 ⁇ m-2 ⁇ m; the thickness of the first inorganic insulating layer 22 may be about 50 nm-150 nm.
  • the approximation here refers to the value within the range of allowable process error and measurement error without strictly limiting the value.
  • the pixel circuit includes a thin film transistor (TFT) 3 and a storage capacitor 4.
  • the thin film transistor 3 may include an active layer 34, a gate 31, a source 32, a drain 33, and a storage
  • the capacitor 4 includes a bottom electrode 41 and a top electrode 42.
  • the display substrate also includes a first gate insulating layer 81, a second gate insulating layer 82, a passivation layer (not shown in the figure), a planarization layer 83, a pixel defining structure 7, an encapsulation layer 5, etc., these layer structures Normal settings can be used, so I won’t repeat them here.
  • An embodiment of the present application also provides a display panel, which includes any one of the above-mentioned display substrates.
  • the display panel may be a flexible LTPS AMOLED display panel, and the display substrate is a flexible backplane.
  • An embodiment of the present application also provides a display device, which includes the above-mentioned display panel.
  • the above-mentioned display device can be applied to various electronic devices such as televisions, monitors, tablet computers, and smart phones.
  • the embodiment of the present application also provides a method for preparing a display substrate. As shown in FIG. 6, the method includes the following steps:
  • Step 101 preparing a gate layer (such as a gate metal layer) on a base substrate; the base substrate has a display area and a non-display area surrounding the display area;
  • a gate layer such as a gate metal layer
  • Step 102 preparing an interlayer insulating layer on the gate layer.
  • the interlayer insulating layer includes a first organic insulating layer and a first inorganic insulating layer; the first organic insulating layer covers the display area and part of the non-display area;
  • Step 103 preparing a source-drain layer (for example, a source-drain metal layer) on the interlayer insulating layer;
  • a source-drain layer for example, a source-drain metal layer
  • Step 104 Prepare an encapsulation layer on the source and drain layers, the encapsulation layer covers the display area and part of the non-display area, and the orthographic projection of the boundary of the encapsulation layer on the base substrate surrounds the front of the first organic insulating layer on the base substrate. projection.
  • step 101 the following steps may be included:
  • an active layer 34 is prepared on the base substrate 1; a first gate insulating layer 81 is deposited on the active layer 34.
  • a gate layer is prepared on a base substrate, which may specifically include, as shown in (1) in FIG. 7:
  • a first metal layer is deposited on the base substrate 1, and a pattern of the first gate metal layer is formed by a patterning process.
  • the first gate metal layer pattern includes the gate electrode 31 of the TFT 3, the bottom electrode 41 of the storage capacitor 4, and the gate electrode. Layer wiring and other structures;
  • a second metal layer is deposited on the second gate insulating layer 82, and a pattern of the second gate metal layer is formed through a patterning process.
  • the second gate metal layer pattern includes the top electrode 42 of the storage capacitor.
  • step 102 preparing an interlayer insulating layer on the gate layer, may specifically include:
  • a first organic insulating layer 21 is deposited on the gate layer, and a pattern of the first organic insulating layer 21 is formed through a patterning process; the pattern of the first organic insulating layer 21 covers the display Area and part of the non-display area, and the first organic insulating layer 21 has a first via 210 in the pattern.
  • the first via hole may include a via hole for connecting the source and drain electrodes to the heavily doped region of the TFT active layer and a via hole for connecting the bottom electrode connection lead of the storage capacitor to the bottom electrode.
  • a first inorganic insulating layer 22 is deposited on the first organic insulating layer 21, and a pattern of the first inorganic insulating layer 22 is formed through a patterning process; specifically, the first inorganic insulating layer 22
  • the orthographic projection of the pattern of the insulating layer 22 on the base substrate 1 is located in the non-display area and surrounds the display area. Therefore, the display area shown in (5) in FIG. 7 is not covered by the first inorganic insulating layer, and only the second An organic insulating layer 21.
  • the process of forming the first inorganic insulating layer pattern through a patterning process may specifically include:
  • the second pass through the first inorganic insulating layer and the gate insulating layer is formed by the first patterning and etching.
  • Hole 221, the second via hole 221 is located in the first via hole 211, and exposes the heavily doped area of the TFT active layer and the bottom electrode of the storage capacitor; the first inorganic insulating layer in the display area is completely covered by the second patterning Etched away, so that the orthographic projection of the first inorganic insulating layer is located in the non-display area and surrounds the display area, as shown in (5) in FIG.
  • step 102 preparing an interlayer insulating layer on the gate layer, specifically includes:
  • a first inorganic insulating layer 22 is deposited on the gate layer, and a pattern of the first inorganic insulating layer 22 is formed through a patterning process;
  • a first organic insulating layer 21 is deposited on the first inorganic insulating layer 22, and a pattern of the first organic insulating layer 21 is formed through a patterning process.
  • forming a pattern of the first inorganic insulating layer through a patterning process may specifically include:
  • the portion of the first inorganic insulating layer 22 covering the display area is etched by a patterning process to form a hollow portion 220; specifically, the hollow portion 220 may be located between the thin film transistor and the storage capacitor.
  • forming a pattern of the first organic insulating layer through a patterning process may specifically include:
  • the first via 211 penetrating through the first organic insulating layer 21 is formed by the first patterning and etching; as shown in (5) in FIG.
  • the first inorganic insulating layer 22 and the gate insulating layer (including the first gate insulating layer and the first gate insulating layer) under the first via hole are further etched, so that the first via hole further penetrates the first inorganic insulating layer.
  • the insulating layer and the gate insulating layer form the second via hole 221, thereby exposing the heavily doped region of the TFT active layer and the bottom electrode of the storage capacitor.
  • step 103 preparing the source and drain layers on the interlayer insulating layer, may specifically include:
  • a third metal layer is deposited on the interlayer insulating layer, and the pattern of the source and drain electrode metal layers is formed by a patterning process.
  • the pattern of the source and drain electrode metal layers includes the source 32 and the drain of the TFT.
  • the electrode 33 and the connecting lead 43 of the bottom electrode 41 of the storage capacitor, the source 32 and drain 33 of the TFT are respectively connected to the heavily doped region of the TFT active layer 34 through a second via hole, and the connecting lead 43 of the bottom electrode 41 of the storage capacitor It is connected to the bottom electrode 41 of the storage capacitor through the second via hole.
  • the display substrate provided by the embodiment of the present application is a flexible substrate
  • the base substrate is a flexible substrate (PI).
  • the preparation method of the display substrate provided by the embodiment of the present application may further include: as shown in (1) in FIG. 7, preparing a flexible base substrate 1 on a rigid base (glass base) 10, and preparing a flexible base substrate 1 on the flexible base substrate 1. Steps such as the buffer layer 11 may also include steps such as peeling off the rigid substrate 10. Conventional techniques can be used for these, so I won't repeat them here.
  • the preparation method of the display substrate may further include more steps, which may be determined according to actual needs, and the embodiments of the present disclosure do not limit this, and the detailed description and technical effects thereof You can refer to the above description of the display substrate, which will not be repeated here.
  • the specific process methods and preparation processes of steps 101, 102, and 103 are not limited to the above-mentioned embodiments, and other process methods and steps may also be used for preparation. Refer to the above description of each layer structure in the display substrate, which will not be repeated here.

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Abstract

本申请涉及显示技术领域，公开了一种显示基板及其制备方法、显示面板，目的是改善柔性显示面板的耐弯折形，提高柔性显示产品良率。其中，显示基板，包括：衬底基板，具有显示区和围绕所述显示区的非显示区；栅极层，位于所述衬底基板上；层间绝缘层，位于所述栅极层背离所述衬底基板的一侧，包括第一有机绝缘层和第一无机绝缘层；所述第一有机绝缘层覆盖所述显示区与部分所述非显示区；源漏极层，位于所述层间绝缘层背离所述衬底基板的一侧；封装层，覆盖所述显示区与部分所述非显示区，且所述封装层的边界在衬底基板上的正投影包围所述第一有机绝缘层在衬底基板上的正投影。

Description

显示基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及其制备方法、显示面板。
背景技术
随着智能手机、可穿戴设备、车载显示、AR/VR等搭载柔性显示的电子产品快速发展和普及，中小尺寸产品市场呈现旺盛的需求态势，特别是以AMOLED技术为代表的高性能新型显示技术，正以其在显示性能、轻薄、可弯曲、可折叠等方面独有的性能优势，加速进军高端智能手机市场。
常规AMOLED在背板制作过程中，主要是采用Poly TFTs以及PI基底来实现暂时性的局部弯曲，而弯曲只能是在一定范围内进行。所以如何提升背板的耐弯折性一直是AMOLED的重点研究方向之一。
发明内容
本申请公开了一种显示基板及其制备方法、显示面板，目的是改善柔性显示面板的耐弯折形，提高柔性显示产品良率。
一种显示基板，包括：
衬底基板，具有显示区和围绕所述显示区的非显示区；
栅极层，位于所述衬底基板上；
层间绝缘层，位于所述栅极层背离所述衬底基板的一侧，包括第一有机绝缘层和第一无机绝缘层；所述第一有机绝缘层覆盖所述显示区与部分所述非显示区；
源漏极层，位于所述层间绝缘层背离所述衬底基板的一侧；
封装层，覆盖所述显示区与部分所述非显示区，且所述封装层的边界在衬底基板上的正投影包围所述第一有机绝缘层在衬底基板上的正投影。
可选的，所述非显示区包括位于所述显示区第一侧的扇形走线区和绑定区，以及位于所述显示区相对两侧中至少一侧的栅极驱动电路区，所述相对两侧与所述第一侧相邻；
所述第一有机绝缘层覆盖所述栅极驱动电路区，且所述第一有机绝缘层在所述衬底基板上的正投影与所述绑定区无交叠。
可选的，所述第一无机绝缘层至少覆盖部分所述非显示区，且所述第一无机绝缘层在所述非显示区的正投影与所述第一有机绝缘层在所述非显示区的正投影相交叠。
可选的，所述第一无机绝缘层覆盖所述扇形走线区和所述绑定区。
可选的，所述第一无机绝缘层在衬底基板上的正投影位于所述非显示区并包围所述显示区，所述第一无机绝缘层位于所述第一有机绝缘层背离所述栅极层的一侧，且所述第一无机绝缘层覆盖所述第一有机绝缘层的边界。
可选的，所述第一无机绝缘层在衬底基板上的正投影与所述栅极驱动电路区无交叠。
可选的，所述第一无机绝缘层位于所述栅极层与所述第一有机绝缘层之间；所述第一无机绝缘层覆盖所述显示区与所述非显示区。
可选的，所述第一无机绝缘层覆盖所述显示区的部分设有镂空部，所述镂空部与所述栅极层的图案无交叠。
可选的，所述的显示基板，还包括位于所述非显示区且沿所述显示区至所述非显示区方向依次设置的至少一层阻挡坝；
所述第一有机绝缘层的边界在衬底基板上的正投影位于所述最后一层阻挡坝朝向所述显示区的一侧。
可选的，所述第一有机绝缘层的厚度为1μm-2μm；所述第一无机绝缘层的厚度为50nm-150nm。
一种显示面板，包括如上述任一项所述的显示基板。
一种显示基板的制备方法，包括：
在衬底基板上制备栅极层；所述衬底基板具有显示区和包围所述显示区 的非显示区；
在所述栅极层上制备层间绝缘层，所述层间绝缘层包括第一有机绝缘层和第一无机绝缘层；所述第一有机绝缘层覆盖所述显示区与部分所述非显示区；
在所述层间绝缘层上制备源漏极层；
在所述源漏极层上制备封装层，所述封装层覆盖所述显示区与部分所述非显示区，且所述封装层的边界在衬底基板上的正投影包围所述第一有机绝缘层在衬底基板上的正投影。
可选的，在所述栅极层上制备层间绝缘层，具体包括：
在所述栅极层上沉积第一有机绝缘层，通过构图工艺形成所述第一有机绝缘层的图形；
在所述第一有机绝缘层上沉积第一无机绝缘层，通过构图工艺形成所述第一无机绝缘层的图形；所述第一无机绝缘层的图形在衬底基板上的正投影位于所述非显示区并包围所述显示区，且所述第一无机绝缘层的图形覆盖所述第一有机绝缘层的边界。
可选的，在所述栅极层上制备层间绝缘层，具体包括：
在所述栅极层上沉积第一无机绝缘层，通过构图工艺形成所述第一无机绝缘层的图形；
在所述第一无机绝缘层上沉积第一有机绝缘层，通过构图工艺形成所述第一有机绝缘层的图形。
附图说明
图1为本申请实施例提供的一种显示基板的正面结构示意图：
图2为本申请一实施例提供的一种显示基板沿图1中X1-X2方向的部分截面结构示意图；
图3为本申请一实施例提供的一种显示基板沿图1中X3-X4方向的部分截面结构示意图；
图4为本申请另一实施例提供的一种显示基板沿图1中X1-X2方向的部分截面结构示意图；
图5为本申请另一实施例提供的一种显示基板沿图1中X3-X4方向的部分截面结构示意图；
图6为本申请一实施例提供的一种显示基板的制备方法流程图；
图7为本申请一实施例提供的一种显示基板在制作过程中的部分截面结构示意图；
图8为本申请另一实施例提供的一种显示基板在制作过程中的部分截面结构示意图。
具体实施方式
相关AMOLED在背板制作过程中，主要是采用多晶硅薄膜晶体管(Poly TFTs)以及柔性衬底(PI基底)来实现暂时性的局部弯曲，而弯曲只能是在一定范围内进行，弯曲性能较差。发明人发现，在背板制作过程中，栅极金属走线层和源漏极金属走线层等金属层的弯折稳定性和可靠性是制约柔性背板的主要因素之一，因此可以通过对栅极金属走线层和源漏极金属走线层之间的层间绝缘层进行改进，以改善栅极金属走线层和源漏极金属走线层的弯折可靠性，提高背板弯折性能，具体可以通过选取有机层间绝缘层替代无机层间绝缘层来提升背板的耐弯折性。但是在有机层间绝缘层替代无机层的情况下，很容易会出现封装不良以及走线发生击穿烧损等等情况，从而导致显示基板失效不良。
鉴于上述问题，本申请实施例公开显示基板及其制备方法、显示面板，具体通过改善柔性显示面板中薄膜晶体管的层间绝缘层结构，提高柔性显示基板的耐弯折性能，并避免封装不良以及走线击穿烧损等情况，进而提高柔性显示产品良率。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而 不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参考图1至图5。其中，图1为显示基板的平面结构示意图，图2和图3是显示基板在一种具体实施例情况下的截面图；图4和图5是显示基板在另一种具体实施例情况下的截面图。具体的，图2和图4是图1中显示基板沿X1-X2方向的截面示意图；图3和图5是图1中显示基板沿X3-X4方向的截面示意图。需要说明的是，为了尽可能表达清楚显示基板中各结构大致位置和形态，图2和图4的截面示意图与图3和图5的截面示意图中所表现出来的具体结构情况不完全一致，例如，图2和图4的截面图在显示区AA部分示意出了像素电路中的TFT 3和存储电容4，而图3和图5中在显示区AA部分仅大致示意出像素电路100的位置并主要示意出了像素电路100所驱动的发光结构200，另外，图3和图5中示意出了封装层5中无机层51与有机层52复合的结构以及阻挡坝6结构，而图2和图4中则未示出。虽然图2和图4的截面示意图以及图3和图5的截面示意图分别只是着重体现了一部分具体结构情况，但是，本领域技术人员根据公知常识完全能够了解其截面的整体结构情况，此处不再赘述。
具体的，如图1至图5所示，本申请实施例提供一种显示基板，包括：
衬底基板1，具有显示区AA和围绕显示区AA的非显示区；
栅极层(例如栅极金属层)，位于衬底基板1上；
层间绝缘层2，位于栅极层背离衬底基板1的一侧，包括第一有机绝缘层21和第一无机绝缘层22；第一有机绝缘层21覆盖显示区AA与部分非显示区；
源漏极层(例如源漏极金属层)，位于层间绝缘层2背离衬底基板1的一侧；
封装层5，覆盖显示区AA与部分非显示区，且封装层5的边界在衬底基板1上的正投影包围第一有机绝缘层21在衬底基板1上的正投影。
示例性的，显示基板包括位于显示区AA的像素电路以及位于非显示区 的金属走线，如图2和图4所示，像素电路100包括薄膜晶体管(TFT)3和存储电容4等器件结构。具体的，栅极层(例如栅极金属层)可以包括TFT 3的栅极31，存储电容4的底电极41和顶电极42，以及非显示区的栅极层金属走线91等结构。源漏极层(例如源漏极金属层)可以包括TFT 3的源极32和漏极33，存储电容4底电极41的连接引线43，以及非显示区的源漏极层金属走线92和连接端子93等结构。
上述显示基板，在栅极金属走线层和源漏极金属走线层之间设置有层间绝缘层2，该层间绝缘层2采用第一有机绝缘层21与第一无机绝缘层22复合结构，其中，第一有机绝缘层21覆盖显示区AA与部分非显示区，可以有效缓冲应力，从而保护其上下两侧的栅极金属层和源漏极金属层，相对于常规的无机层间绝缘层，可以有效地改善显示基板的耐弯折性。并且，由于封装层5的边界正投影包围第一有机绝缘层21的正投影，即第一有机绝缘层21位于封装层5之内，第一有机绝缘层21边界未超出封装层5的边界，进而，可以有效避免水汽通过第一有机绝缘层21入侵，保证封装良率。另外，第一无机绝缘层22的设置可以起到良好的绝缘保护效果，防止金属走线发生击穿烧损的情况，进而保证显示基板驱动电路的良率。
综上所述，本申请实施例公开显示基板，通过改善柔性显示面板中薄膜晶体管的层间绝缘层结构，可以提高柔性显示基板的耐弯折性能，并避免封装不良以及走线击穿烧损等情况，进而提高柔性显示产品良率，尤其适用于弯折要求力度大的折叠或异性AMOLED显示器。
如图1至图5所示，一些实施例中，非显示区包括位于显示区AA第一侧的扇形走线区(Fanout区)CC和绑定区(Bongding区)BB，以及位于显示区AA相对两侧中至少一侧的栅极驱动电路区(GOA区)DD，该相对两侧与第一侧相邻。
具体的，如图3和图5所示，第一有机绝缘层21覆盖栅极驱动电路区DD。如图2和图4所示，第一有机绝缘层21在衬底基板1上的正投影与绑定区BB无交叠。
具体的，在显示基板弯折过程中，弯折线一般会穿过显示区AA和显示区AA相对两侧的栅极驱动电路区DD，第一有机绝缘层21覆盖栅极驱动电路区DD，可以有效改善栅极驱动电路区DD的耐弯折性能，从而提高显示基板的整体弯折性能，使得显示基板能够满足大角度弯折力度的要求。另外，绑定区BB在封装层5边界以外，其上方无封装层5覆盖，第一有机绝缘层21正投影与绑定区BB无交叠，可以避免水汽沿第一有机绝缘层21入侵基板内部，保证封装良率。
如图2至图5所示，一些实施例中，第一无机绝缘层22至少覆盖部分非显示区，且第一无机绝缘层22在非显示区的正投影与第一有机绝缘层21在非显示区的正投影相交叠。
示例性的，第一无机绝缘层22覆盖扇形走线区CC和绑定区BB。
具体的，非显示区的绝缘膜层较少，且金属走线分布密集，例如扇形走线区CC和绑定区BB，因此较容易发生走线击穿烧损的情况，第一无机绝缘层22覆盖非显示区，可以有效防止显示基板发生走线烧损的情况，进而保证显示基板驱动电路的良率。另外，第一无机绝缘层22在非显示区的正投影与第一有机绝缘层21在非显示区的正投影相交叠，可以防止水汽沿第一有机绝缘层21进入基板内部，进而有效提高显示基板的封装防水性能。
如图1、图2和图3所示，一些实施例中，第一无机绝缘层22在衬底基板1上的正投影位于非显示区并包围显示区AA，第一无机绝缘层22位于第一有机绝缘层21背离栅极层的一侧，且第一无机绝缘层22覆盖第一有机绝缘层21的边界。
具体的，第一无机绝缘层22位于第一有机绝缘层21背离栅极层的一侧，即在衬底基板1上依次设置栅极层、第一有机绝缘层21、第一无机绝缘层22以及源漏极层。此时，层间绝缘层2中，第一无机绝缘层22位于第一有机绝缘层21的上方，相对于第一有机绝缘层21，第一无机绝缘层22对栅极层的弯折性能影响较大，本实施例中，将第一无机绝缘层22仅设置在非显示区，即使得显示区AA没有第一无机绝缘层22覆盖，可以提高整个显示区AA的 弯折性能，从而有效改善整个显示基板的弯折性能。
另外，第一无机绝缘层22位于第一有机绝缘层21的上方并覆盖第一有机绝缘层21的边界，可以有效防止水汽通过第一有机绝缘层21进入面板内部，进而有效提高显示基板的封装防水性能。
示例性的，如图3所示，第一无机绝缘层22在衬底基板1上的正投影与栅极驱动电路区DD无交叠，即第一无机绝缘层22不覆盖位于显示区AA相对两侧的栅极驱动电路区(GOA区)DD。这样，可以进一步提高显示区AA两侧的非显示区的弯折性能，从而进一步改善整个显示基板的弯折性能。
如图1、图4和图5所示，另一些实施例中，第一无机绝缘层22位于栅极层与第一有机绝缘层21之间；第一无机绝缘层22覆盖显示区AA与非显示区。
具体的，第一无机绝缘层22位于栅极层与第一有机绝缘层21之间，即在衬底基板1上依次设置栅极层、第一无机绝缘层22、第一有机绝缘层21以及源漏极层。此时，层间绝缘层2中，第一有机绝缘层21位于第一无机绝缘层22的上方，相对于第一无机绝缘层22，第一有机绝缘层21对栅极层的弯折性能影响较大，第一有机绝缘层21可以有效保护下方的栅极层以避免其弯折受损，从而有效提高显示基板的弯折性能。进而本实施例中，可以将第一无机绝缘层22设置为既覆盖显示区AA又覆盖非显示区，一方面可以减少第一无机绝缘层22的构图工艺步骤，另一方面也可以提高显示区AA金属层之间的绝缘效果。
示例性的，如图4所示，第一无机绝缘层22覆盖显示区AA的部分可以设有镂空部220，该镂空部220与栅极层的图案无交叠。即第一无机绝缘层22在显示区AA中没有栅极层图案的区域可以为镂空设置。
例如，像素电路包括薄膜晶体管3(TFT)和存储电容4等具有栅极金属图案的器件结构，第一无机绝缘层22覆盖薄膜晶体管3与存储电容4中的栅极层图案，且第一无机绝缘层22在薄膜晶体管3与存储电容4之间设置有镂空部220，即第一无机绝缘层22不覆盖薄膜晶体管3与存储电容4之间无栅 极层图案的部分。
具体的，第一无机绝缘层22在没有栅极层图案的区域设置镂空部220，既可以保证第一无机绝缘层22对于栅极金属层与源漏极金属层之间的绝缘效果，又可以在显示基板弯曲时使得第一无机绝缘层22附近的应力得以释放，从而提高显示区应力缓冲效果，改善显示基板的弯折性能，再者，还可以使得第一有机绝缘层21同时覆盖第一无机绝缘层22及其镂空部，从而提高第一有机绝缘层21与衬底基板1之间的粘附性，进而避免第一有机绝缘层21剥离(peeling)等问题。
当然，第一无机绝缘层22的具体设置不限于本申请实施例中的描述，例如，当第一有机绝缘层21位于第一无机绝缘层22的上方时，第一无机绝缘层22也可以设置为仅覆盖非显示区，以避免对显示区AA弯折性能产生影响；或者，当第一无机绝缘层22位于第一有机绝缘层21的上方时，第一无机绝缘层22也可以覆盖显示区AA，并通过在第一无机绝缘层22中设置镂空部，以避免对显示区AA弯折性能产生影响。对于上述设置的具体效果，具体可以参照前面实施例，此处不再赘述。
如图1、图3和图5所示，一些实施例中，本申请的显示基板还包括位于非显示区且沿显示区AA至非显示区方向依次设置的至少一层阻挡坝6。具体的，阻挡坝6可以与像素界定结构7同层制备，或者也可以包括其他膜层图案，封装层5一般包括两层无机层51和一层有机层52，阻挡坝6主要用于避免封装层5的有机层52超出封装区域，并防止水汽进入封装区域内。
示例性的，第一有机绝缘层21的边界在衬底基板1上的正投影位于最后一层阻挡坝6朝向显示区AA的一侧，即第一有机绝缘层21的边界不超过阻挡坝6，也不会延伸至封装区域以外，这样可以避免水汽通过第一有机绝缘层21进入基板内部。
一些实施例中，层间绝缘层2中的第一有机绝缘层21的厚度远大于第一无机绝缘层22的厚度。示例性的，第一有机绝缘层21的厚度可以约为1μm-2μm；第一无机绝缘层22的厚度可以为约50nm-150nm。此处的约是指 不严格限定数值的边界，允许工艺误差和测量误差范围内的数值。
示例性的，本申请实施例的显示基板中，像素电路包括薄膜晶体管(TFT)3和存储电容4，薄膜晶体管3可以包括有源层34、栅极31、源极32、漏极33，存储电容4包括底电极41、顶电极42。显示基板还包括第一栅极绝缘层81，第二栅极绝缘层82，钝化层(图中未示出)，平坦化层83，像素界定结构7，封装层5等等，这些层结构可以采用常规设置，此处不再赘述。
本申请实施例还提供一种显示面板，该显示面板包括上述任一项的显示基板。
具体的，该显示面板可以是柔性LTPS AMOLED显示面板，显示基板为柔性背板。
本申请实施例还提供一种显示装置，该显示装置包括上述显示面板。
具体的，上述显示装置可以应用于电视、显示器、平板电脑、智能手机等各种电子设备。
另外，基于本申请实施例提供的显示基板，本申请实施例还提供一种显示基板的制备方法，如图6所示，该方法包括以下步骤：
步骤101，在衬底基板上制备栅极层(例如栅极金属层)；衬底基板具有显示区和围绕显示区的非显示区；
步骤102，在栅极层上制备层间绝缘层，层间绝缘层包括第一有机绝缘层和第一无机绝缘层；第一有机绝缘层覆盖显示区与部分非显示区；
步骤103，在层间绝缘层上制备源漏极层(例如源漏极金属层)；
步骤104，在源漏极层上制备封装层，封装层覆盖显示区与部分非显示区，且封装层的边界在衬底基板上的正投影包围第一有机绝缘层在衬底基板上的正投影。
一些实施例中，步骤101之前，可以包括以下步骤：
如图7中的(1)所示，在衬底基板1上制备有源层34；在有源层34上沉积第一栅极绝缘层81。
具体的，步骤101，在衬底基板上制备栅极层，具体可以包括，如图7中 的(1)所示：
在衬底基板1上沉积第一金属层，通过构图工艺形成第一栅极金属层的图形，第一栅极金属层图形包括TFT 3的栅极31，存储电容4的底电极41，栅极层走线等结构；
在第一金属层上沉积第二栅极绝缘层82；
在第二栅极绝缘层82上沉积第二金属层，通过构图工艺形成第二栅极金属层的图形，第二栅极金属层图形包括存储电容的顶电极42。
一些实施例中，步骤102，在栅极层上制备层间绝缘层，具体可以包括：
如图7中的(1)至(2)所示，在栅极层上沉积第一有机绝缘层21，通过构图工艺形成第一有机绝缘层21的图形；第一有机绝缘层21图形覆盖显示区和部分非显示区，且第一有机绝缘层21图形中设有第一过孔210。示例性的，第一过孔可以包括用于源漏电极与TFT有源层的重掺杂区相连的过孔以及用于存储电容底电极连接引线与底电极相连的过孔。
如图7中的(3)至(5)所示，在第一有机绝缘层21上沉积第一无机绝缘层22，通过构图工艺形成第一无机绝缘层22的图形；具体的，第一无机绝缘层22的图形在衬底基板1上的正投影位于非显示区并包围显示区，因此，图7中的(5)所示的显示区中无第一无机绝缘层覆盖，仅剩下第一有机绝缘层21。
示例性的，通过构图工艺形成第一无机绝缘层图形的过程，具体可以包括：
如图7中的(4)所示，通过第一次构图刻蚀形成贯穿第一无机绝缘层和栅极绝缘层(包括第一栅极绝缘层和第一栅极绝缘层)的第二过孔221，第二过孔221位于第一过孔211中，并暴露出TFT有源层的重掺杂区以及存储电容的底电极；通过第二次构图将显示区的第一无机绝缘层全部刻蚀掉，使得第一无机绝缘层的正投影位于非显示区并包围显示区，如图7中的(5)所示，此时显示区中无第一无机绝缘层覆盖，仅剩下第一有机绝缘层21。
另一些实施例中，步骤102，在栅极层上制备层间绝缘层，具体包括：
如图8中的(1)至(2)所示，在栅极层上沉积第一无机绝缘层22，通过构图工艺形成第一无机绝缘层22的图形；
如图8中的(3)至(6)所示，在第一无机绝缘层22上沉积第一有机绝缘层21，通过构图工艺形成第一有机绝缘层21的图形。
示例性的，通过构图工艺形成第一无机绝缘层的图形，具体可以包括：
如图8中的(2)所示，通过构图工艺在第一无机绝缘层22覆盖显示区的部分上刻蚀形成镂空部220；具体的，镂空部220可以位于薄膜晶体管与存储电容之间。
示例性的，通过构图工艺形成第一有机绝缘层的图形，具体可以包括：
如图8中的(4)所示，通过第一次构图刻蚀形成贯穿第一有机绝缘层21的第一过孔211；如图8中的(5)所示，通过第二次构图对上述第一过孔下方的第一无机绝缘层22和栅极绝缘层(包括第一栅极绝缘层和第一栅极绝缘层)进一步刻蚀，以使得上述第一过孔进一步贯穿第一无机绝缘层和栅极绝缘层以形成第二过孔221，从而暴露出TFT有源层的重掺杂区以及存储电容的底电极。
一些实施例中，步骤103，在层间绝缘层上制备源漏极层，具体可以包括：
如图8中的(6)所示，在层间绝缘层上沉积第三金属层，通过构图工艺形成源漏电极金属层的图形，源漏电极金属层的图形包括TFT的源极32、漏极33以及存储电容底电极41的连接引线43，TFT的源极32和漏极33分别通过第二过孔与TFT有源层34的重掺杂区相连，存储电容底电极41的连接引线43通过第二过孔与存储电容的底电极41相连。
示例性的，本申请实施例提供的显示基板为柔性基板，衬底基板为柔性衬底(PI)。本申请实施例提供的显示基板的制备方法还可以包括：如图7中的(1)所示，在刚性基底(玻璃基底)10上制备柔性衬底基板1，在柔性衬底基板1上制备缓冲层11等步骤，还可以包括将刚性基底10剥离等步骤。这些都可以采用常规技术，此处不再赘述。
需要说明的是，本公开的一些实施例中，显示基板的制备方法还可以包 括更多的步骤，这可以根据实际需求而定，本公开的实施例对此不作限制，其详细说明和技术效果可以参考上文中关于显示基板的描述，此处不再赘述。另外，本公开实施例提供的显示基板制备方法中，步骤101、102和103的具体工艺方法和制备过程并不限于上述给出的实施例，也可以采用其他的工艺方式和步骤制备，具体可以参考上文中关于显示基板中对各层结构的描述，此处不再赘述。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示基板，包括：
    衬底基板，具有显示区和围绕所述显示区的非显示区；
    栅极层，位于所述衬底基板上；
    层间绝缘层，位于所述栅极层背离所述衬底基板的一侧，包括第一有机绝缘层和第一无机绝缘层；所述第一有机绝缘层覆盖所述显示区与部分所述非显示区；
    源漏极层，位于所述层间绝缘层背离所述衬底基板的一侧；
    封装层，覆盖所述显示区与部分所述非显示区，且所述封装层的边界在衬底基板上的正投影包围所述第一有机绝缘层在衬底基板上的正投影。
  2. 如权利要求1所述的显示基板，其中，所述非显示区包括位于所述显示区第一侧的扇形走线区和绑定区，以及位于所述显示区相对两侧中至少一侧的栅极驱动电路区，所述相对两侧与所述第一侧相邻；
    所述第一有机绝缘层覆盖所述栅极驱动电路区，且所述第一有机绝缘层在所述衬底基板上的正投影与所述绑定区无交叠。
  3. 如权利要求2所述的显示基板，其中，所述第一无机绝缘层至少覆盖部分所述非显示区，且所述第一无机绝缘层在所述非显示区的正投影与所述第一有机绝缘层在所述非显示区的正投影相交叠。
  4. 如权利要求3所述的显示基板，其中，所述第一无机绝缘层覆盖所述扇形走线区和所述绑定区。
  5. 如权利要求4所述的显示基板，其中，
    所述第一无机绝缘层在衬底基板上的正投影位于所述非显示区并包围所述显示区，所述第一无机绝缘层位于所述第一有机绝缘层背离所述栅极层的一侧，且所述第一无机绝缘层覆盖所述第一有机绝缘层的边界。
  6. 如权利要求5所述的显示基板，其中，
    所述第一无机绝缘层在衬底基板上的正投影与所述栅极驱动电路区无 交叠。
  7. 如权利要求4所述的显示基板，其中，所述第一无机绝缘层位于所述栅极层与所述第一有机绝缘层之间；所述第一无机绝缘层覆盖所述显示区与所述非显示区。
  8. 如权利要求7所述的显示基板，其中，所述第一无机绝缘层覆盖所述显示区的部分设有镂空部，所述镂空部与所述栅极层的图案无交叠。
  9. 如权利要求1-8任一项所述的显示基板，其中，还包括位于所述非显示区且沿所述显示区至所述非显示区方向依次设置的至少一层阻挡坝；
    所述第一有机绝缘层的边界在衬底基板上的正投影位于所述最后一层阻挡坝朝向所述显示区的一侧。
  10. 如权利要求1-8任一项所述的显示基板，其中，所述第一有机绝缘层的厚度为1μm-2μm；所述第一无机绝缘层的厚度为50nm-150nm。
  11. 一种显示面板，包括如权利要求1-10任一项所述的显示基板。
  12. 一种显示基板的制备方法，包括：
    在衬底基板上制备栅极层；所述衬底基板具有显示区和包围所述显示区的非显示区；
    在所述栅极层上制备层间绝缘层，所述层间绝缘层包括第一有机绝缘层和第一无机绝缘层；所述第一有机绝缘层覆盖所述显示区与部分所述非显示区；
    在所述层间绝缘层上制备源漏极层；
    在所述源漏极层上制备封装层，所述封装层覆盖所述显示区与部分所述非显示区，且所述封装层的边界在衬底基板上的正投影包围所述第一有机绝缘层在衬底基板上的正投影。
  13. 如权利要求12所述的制备方法，其中，在所述栅极层上制备层间绝缘层，具体包括：
    在所述栅极层上沉积第一有机绝缘层，通过构图工艺形成所述第一有机绝缘层的图形；
    在所述第一有机绝缘层上沉积第一无机绝缘层，通过构图工艺形成所述第一无机绝缘层的图形；所述第一无机绝缘层的图形在衬底基板上的正投影位于所述非显示区并包围所述显示区，且所述第一无机绝缘层的图形覆盖所述第一有机绝缘层的边界。
  14. 如权利要求12所述的制备方法，其中，在所述栅极层上制备层间绝缘层，具体包括：
    在所述栅极层上沉积第一无机绝缘层，通过构图工艺形成所述第一无机绝缘层的图形；
    在所述第一无机绝缘层上沉积第一有机绝缘层，通过构图工艺形成所述第一有机绝缘层的图形。
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