US20120270392A1 - Fabricating method of active device array substrate - Google Patents
Fabricating method of active device array substrate Download PDFInfo
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- US20120270392A1 US20120270392A1 US13/537,054 US201213537054A US2012270392A1 US 20120270392 A1 US20120270392 A1 US 20120270392A1 US 201213537054 A US201213537054 A US 201213537054A US 2012270392 A1 US2012270392 A1 US 2012270392A1
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- trapezoid
- layer
- copper layer
- base angle
- copper
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 115
- 229910052802 copper Inorganic materials 0.000 claims abstract description 110
- 239000010949 copper Substances 0.000 claims abstract description 110
- 230000001154 acute effect Effects 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims description 37
- 230000008021 deposition Effects 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 26
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 188
- 239000000463 material Substances 0.000 description 16
- 238000002161 passivation Methods 0.000 description 9
- 239000010409 thin film Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000012780 transparent material Substances 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 229910001182 Mo alloy Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910001069 Ti alloy Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000007847 structural defect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3492—Variation of parameters during sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Definitions
- the invention is related to a fabricating method of an active device array substrate, and in particular to a fabricating method of an active device array substrate which has a copper conductive layer.
- the invention provides an active device array substrate which has better electrical characteristics.
- the invention provides an active device array substrate which effectively reduces the disconnection rate of wires.
- the invention provides an active device array substrate which has at least one patterned conductive layer.
- the patterned conductive layer includes a copper layer.
- a cross-section of the copper layer which is substantially parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid.
- a base angle of the first trapezoid and a base angle of the second trapezoid are acute angles.
- a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
- the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, from about 7° to about 13°.
- the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, about 10°.
- the patterned conductive layer further includes a barrier layer.
- the copper layer is stacked on the barrier layer.
- the material of the barrier layer is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy.
- the height of the first trapezoid is, for example, greater than the height of the second trapezoid.
- the height of the first trapezoid is, for example, from about 1500 angstroms to about 5000 angstroms
- the height of the second trapezoid is, for example, from about 50 angstroms to about 1500 angstroms.
- the height of the first trapezoid is, for example, from about 2500 angstroms to about 5000 angstroms
- the height of the second trapezoid is, for example, from about 50 angstroms to about 2500 angstroms.
- the patterned conductive layer forms a plurality of gates of a plurality of active devices.
- the patterned conductive layer forms a plurality of sources/drains of a plurality of active devices.
- the invention provides a fabricating method of an active device array substrate which includes the following steps. First, a first copper layer is deposited at a first deposition rate on a substrate. Next, a second copper layer is deposited at a second deposition rate on the first copper layer, wherein the first deposition rate is greater than the second deposition rate. The first copper layer and the second copper layer are then patterned.
- a first cross-section of the first copper layer which is parallel to a normal line direction of the first copper layer is, for example, a first trapezoid
- a second cross-section of the second copper layer which is parallel to the normal line direction of the first copper layer is, for example, a second trapezoid.
- a base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
- the depositing method of the first copper layer and the second copper layer includes sputtering.
- the first deposition rate is at least two times the second deposition rate.
- a step of depositing a barrier layer on the substrate is further included.
- the first copper layer is deposited on the barrier layer.
- the active device array substrate since the base angle of the first trapezoid and the base angle of the second trapezoid are acute angles, and the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°, the active device array substrate has a better exterior structure, so that formation of structural defects are effectively prevented, thereby improving electrical characteristics.
- the second copper layer has a better arrangement of atoms, less thin film defects, and a lower oxidation rate, so that the disconnection rate of wires is effectively lowered.
- FIGS. 1A to 1G are schematic cross-sectional views showing a fabrication process of an active device array substrate according to an embodiment of the invention.
- FIG. 2 is a schematic cross-sectional view along another direction of a patterned conductive layer 122 in FIG. 1E , wherein the cross-section direction of FIG. 2 is perpendicular to the cross-section direction of FIG. 1E .
- FIGS. 1A to 1G are schematic cross-sectional views showing a fabrication process of an active device array substrate according to an embodiment of the invention.
- FIG. 2 is a schematic cross-sectional view along another direction of a patterned conductive layer 122 in FIG. 1E , wherein the cross-section direction of FIG. 2 is perpendicular to the cross-section direction of FIG. 1E .
- a substrate 100 is provided.
- the material of the substrate 100 is a transparent material, a non-transparent material, a flexible material, or any combination of the above.
- a barrier layer 102 is optionally/selectively formed on the substrate 100 .
- the material of the barrier layer 102 is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy.
- the method of forming the barrier layer 102 is, for example, a physical vapor deposition method.
- a copper layer 104 is deposited at a first deposition rate on the barrier layer 102 .
- the method of forming the copper layer 104 is, for example, sputtering.
- a copper layer 106 is deposited at a second deposition rate on the copper layer 104 , wherein the first deposition rate is substantially greater than the second deposition rate.
- the first deposition rate is, for example, at least two times the second deposition rate.
- the method of forming the copper layer 106 and the copper layer 104 is, for example, a sputtering method.
- the copper layer 106 , the copper layer 104 , and the barrier layer 102 are patterned, so as to form a patterned conductive layer 108 , which is used as a gate, on the substrate 100 .
- the patterned conductive layer 108 includes a copper layer 106 a, a copper layer 104 a, and a barrier layer 102 a formed by patterning the copper layer 106 , the copper layer 104 , and the barrier layer 102 .
- a cross-section of the copper layer 104 a which is substantially parallel to a normal line direction N of the copper layer 104 a is, for example, a trapezoid T 1
- a cross-section of the copper layer 106 a which is substantially parallel to the normal line direction N of the copper layer 104 a is, for example, a trapezoid T 2
- a base angle ⁇ 1 of the trapezoid T 1 and a base angle ⁇ 2 of the trapezoid T 2 are acute angles
- the difference between the base angle ⁇ 1 of the trapezoid T 1 and the base angle ⁇ 2 of the trapezoid T 2 is, for example, from about 5° to about 30°.
- the difference between the base angle ⁇ 1 of the trapezoid T 1 and the base angle ⁇ 2 of the trapezoid T 2 is from about 7° to about 13°, for example about 10°.
- the base angle ⁇ 1 is, for example, substantially smaller than the base angle ⁇ 2 .
- the base angle ⁇ 1 is substantially smaller than 70°, and the base angle ⁇ 2 is substantially smaller than 80°.
- the height of the trapezoid T 1 is substantially greater than the height of the trapezoid T 2 , but the height of the trapezoid T 2 may be substantially greater than or substantially equal to the height of the trapezoid T 1 in other embodiments.
- the height of the trapezoid T 1 and T 2 is from about 50 angstroms to about 5000 angstroms.
- the height of the trapezoid T 1 is, for example, from about 2500 angstroms to about 5000 angstroms
- the height of the trapezoid T 2 is, for example, from about 50 angstroms to about 2500 angstroms.
- the height of the trapezoid T 1 is, for example, from about 1500 angstroms to about 5000 angstroms
- the height of the trapezoid T 2 is, for example, from about 50 angstroms to about 1500 angstroms.
- the term “trapezoid” includes any shape that is substantially a trapezoid. In other words, as long as a shape is substantially similar to a trapezoid in appearance, the shape is a so-called trapezoid according to the present embodiment.
- the base angles of the trapezoid are what are conventionally known as “taper angles”.
- a dielectric layer 110 is formed on the substrate 100 , so as to cover the patterned conductive layer 108 .
- the method of forming the dielectric layer 110 is, for example, a chemical vapor deposition method or other suitable thin film deposition techniques. The invention, however, is not limited to the above.
- the dielectric layer 110 may have a single-layered or multiple-layered structure, and the material thereof may be an inorganic material, organic material, another dielectric material, or combinations of the above.
- the present embodiment is illustrated in a way that the material of the dielectric layer 110 is a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials.
- a channel layer 112 and an ohmic contact layer 114 are formed in a manner in which the channel layer 112 and the ohmic contact layer 114 are stacked on the patterned conductive layer 108 and the dielectric layer 110 .
- the channel layer 112 and the ohmic contact layer 114 are, for example, semiconductor layers which have different dopant concentrations.
- the method of forming the channel layer 112 and the ohmic contact layer 114 is, for example, a suitable deposition method and patterning method which are not repeatedly described.
- a barrier layer 116 is optionally/selectively formed on the substrate 100 .
- the barrier layer 116 covers the dielectric layer and the ohmic contact layer 114 .
- the material of the barrier layer 116 is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy.
- the method of forming the barrier layer 116 is, for example, a physical vapor deposition method.
- a copper layer 118 is deposited at a third deposition rate on the barrier layer 116 .
- the method of forming the copper layer 118 is, for example, a sputtering method.
- a copper layer 120 is deposited at a fourth deposition rate on the copper layer 118 , wherein the third deposition rate is substantially greater than the fourth deposition rate, and the third deposition rate is, for example, at least two times the fourth deposition rate.
- the method of forming the copper layer 120 and the copper layer 118 is, for example, sputtering.
- the copper layer 120 , the copper layer 118 , and the barrier layer 116 are patterned, and the patterned conductive layer 122 which is used as a source and drain is formed on the channel layer 112 which is on two sides of the patterned conductive layer 108 .
- the patterned conductive layer 122 is formed, a portion of the ohmic contact layer 114 may be removed, so as to form the ohmic contact layer 114 a .
- the patterned conductive layer 122 includes a copper layer 120 a , a copper layer 118 a , and a barrier layer 116 a formed by patterning the copper layer 120 , the copper layer 118 , and the barrier layer 116 .
- a cross-section of the copper layer 118 a which is substantially parallel to the normal line direction N of the copper layer 118 a is, for example, a trapezoid T 3
- a cross-section of the copper layer 120 a which is substantially parallel to the normal line direction N of the copper layer 118 a is, for example, a trapezoid T 4
- a base angle ⁇ 3 of the trapezoid T 3 and a base angle ⁇ 4 of the trapezoid T 4 are acute angles, and the difference between the base angle ⁇ 3 of the trapezoid T 3 and the base angle ⁇ 4 the trapezoid T 4 is, for example, from about 5° to about 30°.
- the difference between the base angle ⁇ 3 of the trapezoid T 3 and the base angle ⁇ 4 of the trapezoid T 4 is from about 7° to about 13°, for example about 10°.
- the base angle ⁇ 3 is, for example, smaller than the base angle ⁇ 4 .
- the base angle ⁇ 1 is substantially smaller than 70 ⁇ 1 is, for example, smaller than 70°
- the base angle ⁇ 2 is substantially smaller than 80 ⁇ 2 is, for example, smaller than 80°, for example.
- the height of the trapezoid T 3 is, for example, substantially greater than the height of the trapezoid T 4 .
- the height of the trapezoid T 3 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T 4 is, for example, from about 50 angstroms to about 1500 angstroms.
- the thin film transistor 124 includes the patterned conductive layer 108 (which is used as the gate), the channel layer 112 , the ohmic contact layer 114 a , and the patterned conductive layer 122 (which is used as the source and the drain).
- a passivation layer 126 is formed on the thin film transistor 124 , wherein the passivation layer 126 has an opening 128 .
- the opening 128 exposes a portion of the patterned conductive layer 122 which is used as the drain.
- the passivation layer 126 may have a single-layered or multiple-layered structure, and the material thereof may be an inorganic material, organic material, another dielectric material, or combinations of the above.
- the method of forming the passivation layer 126 which has the opening is, for example, forming a passivation material layer (not shown) over the whole substrate 100 , and then performing a patterning process on the passivation material layer.
- a pixel electrode 130 is formed on the passivation layer 126 , wherein the pixel electrode 130 is electrically connected, via the opening 128 , to the portion of the patterned conductive layer 122 of the thin film transistor 124 that is used as the drain.
- the pixel electrode 130 may have a single-layered or multiple-layered structure, and the material thereof may be a transparent material, a non-transparent material, or combinations of the above.
- the present embodiment is illustrated in a way that indium tin oxide (ITO) and/or a transparent material of indium zinc oxide (IZO) is used as an example.
- ITO indium tin oxide
- IZO indium zinc oxide
- the method of forming the pixel electrode 130 is, for example, forming a pixel electrode layer (not shown) by sputtering, and then performing a patterning process on the pixel electrode.
- the copper layers 106 a and 120 a have better arrangements of atoms, less thin film defects, and lower oxidation rates, thereby greatly reducing the disconnection rate of wires in the active device array substrate.
- the invention is not limited to the above.
- any situation, in which any of the gate, the scan line, the source, the drain, the data line, other metal lines, and other metal electrodes is fabricated by the above fabricating method of the patterned conductive layer, is within the scope of the fabricating method of the active device array substrate of the invention.
- the active device array substrate may be applied to liquid crystal displays (LCD), thin film transistor-organic light emitting diodes (TFT-OLED), electronic paper, or other products.
- LCD liquid crystal displays
- TFT-OLED thin film transistor-organic light emitting diodes
- the active device array substrate has at least a patterned conductive layer.
- the patterned conductive layer includes a copper layer.
- the copper layer in the patterned conductive layer may be a single-layered or multiple-layered structure. As long as a cross-section of the copper layer which is substantially parallel to a normal line direction of the copper layer includes two trapezoid which are stacked, and that the base angles are acute angles which have a difference from about 5° to about 30°, the patterned conductive layer is within the scope of the invention.
- the patterned conductive layer in the active device array substrate is the patterned conductive layer 108 which is used as the gate and the patterned conductive layer 122 which is used as the source and the drain.
- the copper layer in the patterned conductive layer 108 is, for example, a double-layered structure formed by stacking of the copper layers 104 a and 106 a
- the copper layer in the patterned conductive layer 122 is, for example, a double-layered structure formed by stacking of the copper layers 118 a and 120 a.
- the invention is not limited to the above.
- the cross-section of the copper layer of the patterned conductive layer 108 which is substantially parallel to the normal line direction N of the copper layer includes the trapezoid T 1 (which is the cross-section of the copper layer 104 a ) and the trapezoid T 2 (which is the cross-section of the copper layer 106 a ) stacked on the trapezoid T 1 .
- the base angle ⁇ 1 of the trapezoid T 1 and the base angle ⁇ 2 of the trapezoid T 2 substantially are acute angles, and the difference between the base angle ⁇ 1 of the trapezoid T 1 and the base angle ⁇ 2 of the trapezoid T 2 is, for example, from about 5° to about 30°.
- the difference between the base angle ⁇ 1 of the trapezoid T 1 and the base angle ⁇ 2 of the trapezoid T 2 is from about 7° to about 13°, for example about 10°.
- the base angle ⁇ 1 is, for example, substantially smaller than the base angle ⁇ 2 .
- the base angle ⁇ 1 is substantially smaller than 70 ⁇ 1 is, for example, smaller than 70°
- the base angle ⁇ 2 is substantially smaller than 80 ⁇ 2 is, for example, smaller than 80°, for example.
- the height of the trapezoid T 1 is substantially greater than the height of the trapezoid T 2 .
- the height of the trapezoid T 1 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T 2 is, for example, from about 50 angstroms to about 1500 angstroms.
- the cross-section of the copper layer of the patterned conductive layer 122 which is substantially parallel to the normal line direction N of the copper layer includes the trapezoid T 3 (which is the cross-section of the copper layer 118 a ) and the trapezoid T 4 (which is the cross-section of the copper layer 120 a ) stacked on the trapezoid T 3 .
- the base angle ⁇ 3 of the trapezoid T 3 and the base angle ⁇ 4 of the trapezoid T 4 are acute angles, and the difference between the base angle ⁇ 3 of the trapezoid T 3 and the base angle ⁇ 4 the trapezoid T 4 is from about 5° to about 30°, for example.
- the difference between the base angle ⁇ 3 of the trapezoid T 3 and the base angle ⁇ 4 of the trapezoid T 4 is from about 7° to about 13°, for example about 10°.
- the base angle ⁇ 3 is, for example, substantially smaller than the base angle ⁇ 4 .
- the base angle ⁇ 1 is substantially smaller than 70°, and the base angle ⁇ 2 is substantially smaller than 80°, for example.
- the height of the trapezoid T 3 is, for example, substantially greater than the height of the trapezoid T 4 .
- the height of the trapezoid T 3 and T 4 is from about 50 angstroms to about 5000 angstroms.
- the height of the trapezoid T 3 is, for example, from about 2500 angstroms to about 5000 angstroms, and the height of the trapezoid T 4 is, for example, from about 50 angstroms to about 2500 angstroms.
- the height of the trapezoid T 3 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T 4 is, for example, from about 50 angstroms to about 1500 angstroms.
- the patterned conductive layers 108 and 112 may further include the barrier layers 102 a and 116 a, respectively.
- the copper layer 104 a is stacked on the barrier layer 102 a
- the copper layer 118 a is stacked on the barrier layer 116 a.
- the materials of the barrier layers 102 a and 116 a is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy.
- the active device array substrate further includes elements such as the substrate 100 , the dielectric layer 110 , the channel layer 112 , the ohmic contact layer 114 a , the passivation layer 126 , and the pixel electrode 130 .
- elements such as the substrate 100 , the dielectric layer 110 , the channel layer 112 , the ohmic contact layer 114 a , the passivation layer 126 , and the pixel electrode 130 .
- the manner in which these elements are disposed, the materials of these elements, and the method of forming these elements have already been elaborated above and are hence not repeatedly described.
- the active device array substrate since the base angle ⁇ 1 (or ⁇ 3 ) of the trapezoid T 1 (or T 3 ) and the base angle ⁇ 2 (or ⁇ 4 ) trapezoid T 2 (or T 4 ) substantially are acute angles, and the difference between the base angle ⁇ 1 (or ⁇ 3 ) of the trapezoid T 1 (or T 3 ) and the base angle ⁇ 2 (or ⁇ 4 ) of the trapezoid T 2 (or T 4 ) is from about 5° to about 30°, the active device array substrate has a better exterior structure, so that formation of structural defects are effectively prevented, thereby improving electrical characteristics.
- the patterned conductive layer according to the present embodiment is illustrated in an exemplary way that the patterned conductive layer is used as the gate (the patterned conductive layer 108 ) and the source and the drain (the patterned conductive layer 122 ). Any situation in which any of the gate, the scan line, the source, the drain, the data line, other metal lines, and other metal electrodes has the structure of the above patterned conductive layer is within the scope of the invention.
- Table 1 is a comparison chart of disconnection rates of wires according to the conventional art and the invention.
- the copper layer when a copper layer is formed, the copper layer is formed only by a single, rapid, and high power deposition process, so that after the copper layer is patterned to form a copper wire, the cross-section is a single trapezoid, and the copper wire has a higher disconnection rate.
- a lower copper layer is formed by a rapid and high power deposition, and an upper copper layer is then formed by a slow and low power deposition process (which has a power 1 ⁇ 3 of the high power deposition process), and the upper copper layer is stacked on the lower copper layer to form stacked copper layers.
- the cross-section has two trapezoids, and the copper wire has a lower disconnection rate.
- the active device array substrate has better electrical characteristics.
Abstract
A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
Description
- This is a divisional application of and claims the priority benefit of patent application Ser. No. 12/822,201, filed on Jun. 24, 2010, now pending, which claims the priority benefit of Taiwan application serial no. 99108356, filed on Mar. 22, 2010. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The invention is related to a fabricating method of an active device array substrate, and in particular to a fabricating method of an active device array substrate which has a copper conductive layer.
- 2. Description of Related Art
- As panel sizes of thin film transistor liquid crystal displays (TFT-LCD) become larger and larger, this enlargement is accompanied by resistor capacitor (RC) delay effects caused by resistance values of metal wires which are not low enough. Signals are hence distorted during transmission, thereby affecting the display quality of the panels. By using a single layer of copper which has low resistance as a metal wire, RC delay effects are effectively reduced. However, after the copper is fabricated, copper oxide is formed on the surface of the copper. Since the rates at which the copper oxide on the surface of the copper and the copper are etched are different, disconnection of wires may easily occur during etching.
- The invention provides an active device array substrate which has better electrical characteristics.
- The invention provides an active device array substrate which effectively reduces the disconnection rate of wires.
- The invention provides an active device array substrate which has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is substantially parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles. A difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
- According to an embodiment of the invention, the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, from about 7° to about 13°.
- According to an embodiment of the invention, the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, about 10°.
- According to an embodiment of the invention, the patterned conductive layer further includes a barrier layer. The copper layer is stacked on the barrier layer.
- According to an embodiment of the invention, the material of the barrier layer is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy.
- According to an embodiment of the invention, the height of the first trapezoid is, for example, greater than the height of the second trapezoid.
- According to an embodiment of the invention, the height of the first trapezoid is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the second trapezoid is, for example, from about 50 angstroms to about 1500 angstroms.
- According to an embodiment of the invention, the height of the first trapezoid is, for example, from about 2500 angstroms to about 5000 angstroms, and the height of the second trapezoid is, for example, from about 50 angstroms to about 2500 angstroms.
- According to an embodiment of the invention, the patterned conductive layer forms a plurality of gates of a plurality of active devices.
- According to an embodiment of the invention, the patterned conductive layer forms a plurality of sources/drains of a plurality of active devices.
- The invention provides a fabricating method of an active device array substrate which includes the following steps. First, a first copper layer is deposited at a first deposition rate on a substrate. Next, a second copper layer is deposited at a second deposition rate on the first copper layer, wherein the first deposition rate is greater than the second deposition rate. The first copper layer and the second copper layer are then patterned.
- According to an embodiment of the invention, after the first copper layer and the second copper layer are patterned, a first cross-section of the first copper layer which is parallel to a normal line direction of the first copper layer is, for example, a first trapezoid, and a second cross-section of the second copper layer which is parallel to the normal line direction of the first copper layer is, for example, a second trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
- According to an embodiment of the invention, the depositing method of the first copper layer and the second copper layer includes sputtering.
- According to an embodiment of the invention, the first deposition rate is at least two times the second deposition rate.
- According to an embodiment of the invention, before the first copper layer is deposited, a step of depositing a barrier layer on the substrate is further included. The first copper layer is deposited on the barrier layer.
- Due to the above, in the active device array substrate provided by the invention, since the base angle of the first trapezoid and the base angle of the second trapezoid are acute angles, and the difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°, the active device array substrate has a better exterior structure, so that formation of structural defects are effectively prevented, thereby improving electrical characteristics.
- In addition, in the fabricating method of the active device array substrate provided by the invention, since the first deposition rate is greater than the second deposition rate, the second copper layer has a better arrangement of atoms, less thin film defects, and a lower oxidation rate, so that the disconnection rate of wires is effectively lowered.
- In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, embodiments accompanied with figures are described in detail below.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIGS. 1A to 1G are schematic cross-sectional views showing a fabrication process of an active device array substrate according to an embodiment of the invention. -
FIG. 2 is a schematic cross-sectional view along another direction of a patternedconductive layer 122 inFIG. 1E , wherein the cross-section direction ofFIG. 2 is perpendicular to the cross-section direction ofFIG. 1E . -
FIGS. 1A to 1G are schematic cross-sectional views showing a fabrication process of an active device array substrate according to an embodiment of the invention.FIG. 2 is a schematic cross-sectional view along another direction of a patternedconductive layer 122 inFIG. 1E , wherein the cross-section direction ofFIG. 2 is perpendicular to the cross-section direction ofFIG. 1E . - First, please refer to
FIG. 1A . Asubstrate 100 is provided. The material of thesubstrate 100 is a transparent material, a non-transparent material, a flexible material, or any combination of the above. - Next, a
barrier layer 102 is optionally/selectively formed on thesubstrate 100. The material of thebarrier layer 102 is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy. The method of forming thebarrier layer 102 is, for example, a physical vapor deposition method. - Next, a
copper layer 104 is deposited at a first deposition rate on thebarrier layer 102. The method of forming thecopper layer 104 is, for example, sputtering. - Next, a
copper layer 106 is deposited at a second deposition rate on thecopper layer 104, wherein the first deposition rate is substantially greater than the second deposition rate. The first deposition rate is, for example, at least two times the second deposition rate. The method of forming thecopper layer 106 and thecopper layer 104 is, for example, a sputtering method. - Afterwards, please refer to
FIG. 1B . Thecopper layer 106, thecopper layer 104, and thebarrier layer 102 are patterned, so as to form a patternedconductive layer 108, which is used as a gate, on thesubstrate 100. The patternedconductive layer 108 includes acopper layer 106 a, acopper layer 104 a, and abarrier layer 102 a formed by patterning thecopper layer 106, thecopper layer 104, and thebarrier layer 102. - Here, a cross-section of the
copper layer 104 a which is substantially parallel to a normal line direction N of thecopper layer 104 a is, for example, a trapezoid T1, a cross-section of thecopper layer 106 a which is substantially parallel to the normal line direction N of thecopper layer 104 a is, for example, a trapezoid T2. A base angle θ1 of the trapezoid T1 and a base angle θ2 of the trapezoid T2 are acute angles, and the difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is, for example, from about 5° to about 30°. According to an embodiment of the invention, the difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is from about 7° to about 13°, for example about 10°. The base angle θ1 is, for example, substantially smaller than the base angle θ2. The base angle θ1 is substantially smaller than 70°, and the base angle θ2 is substantially smaller than 80°. - In addition, the height of the trapezoid T1 is substantially greater than the height of the trapezoid T2, but the height of the trapezoid T2 may be substantially greater than or substantially equal to the height of the trapezoid T1 in other embodiments. The height of the trapezoid T1 and T2 is from about 50 angstroms to about 5000 angstroms. Generally speaking, the height of the trapezoid T1 is, for example, from about 2500 angstroms to about 5000 angstroms, and the height of the trapezoid T2 is, for example, from about 50 angstroms to about 2500 angstroms. In some embodiment, the height of the trapezoid T1 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T2 is, for example, from about 50 angstroms to about 1500 angstroms.
- It should be noted that according the present embodiment, the term “trapezoid” includes any shape that is substantially a trapezoid. In other words, as long as a shape is substantially similar to a trapezoid in appearance, the shape is a so-called trapezoid according to the present embodiment. In addition, according to the present embodiment, the base angles of the trapezoid are what are conventionally known as “taper angles”.
- Afterwards, please refer to
FIG. 1C . Adielectric layer 110 is formed on thesubstrate 100, so as to cover the patternedconductive layer 108. The method of forming thedielectric layer 110 is, for example, a chemical vapor deposition method or other suitable thin film deposition techniques. The invention, however, is not limited to the above. Thedielectric layer 110 may have a single-layered or multiple-layered structure, and the material thereof may be an inorganic material, organic material, another dielectric material, or combinations of the above. The present embodiment is illustrated in a way that the material of thedielectric layer 110 is a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials. - Next, a
channel layer 112 and anohmic contact layer 114 are formed in a manner in which thechannel layer 112 and theohmic contact layer 114 are stacked on the patternedconductive layer 108 and thedielectric layer 110. Thechannel layer 112 and theohmic contact layer 114 are, for example, semiconductor layers which have different dopant concentrations. The method of forming thechannel layer 112 and theohmic contact layer 114 is, for example, a suitable deposition method and patterning method which are not repeatedly described. - Please refer to
FIG. 1D . Abarrier layer 116 is optionally/selectively formed on thesubstrate 100. Thebarrier layer 116 covers the dielectric layer and theohmic contact layer 114. The material of thebarrier layer 116 is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy. The method of forming thebarrier layer 116 is, for example, a physical vapor deposition method. - Then, a
copper layer 118 is deposited at a third deposition rate on thebarrier layer 116. The method of forming thecopper layer 118 is, for example, a sputtering method. - Next, a
copper layer 120 is deposited at a fourth deposition rate on thecopper layer 118, wherein the third deposition rate is substantially greater than the fourth deposition rate, and the third deposition rate is, for example, at least two times the fourth deposition rate. The method of forming thecopper layer 120 and thecopper layer 118 is, for example, sputtering. - Afterwards, please refer to
FIG. 1E . Thecopper layer 120, thecopper layer 118, and thebarrier layer 116 are patterned, and the patternedconductive layer 122 which is used as a source and drain is formed on thechannel layer 112 which is on two sides of the patternedconductive layer 108. After the patternedconductive layer 122 is formed, a portion of theohmic contact layer 114 may be removed, so as to form theohmic contact layer 114 a. The patternedconductive layer 122 includes acopper layer 120 a, acopper layer 118 a, and abarrier layer 116 a formed by patterning thecopper layer 120, thecopper layer 118, and thebarrier layer 116. - Please also refer to
FIG. 2 . A cross-section of thecopper layer 118 a which is substantially parallel to the normal line direction N of thecopper layer 118 a is, for example, a trapezoid T3, a cross-section of thecopper layer 120 a which is substantially parallel to the normal line direction N of thecopper layer 118 a is, for example, a trapezoid T4. A base angle θ3 of the trapezoid T3 and a base angle θ4 of the trapezoid T4 are acute angles, and the difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 the trapezoid T4 is, for example, from about 5° to about 30°. According to an embodiment of the invention, the difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 is from about 7° to about 13°, for example about 10°. The base angle θ3 is, for example, smaller than the base angle θ4. The base angle θ1 is substantially smaller than 70θ1 is, for example, smaller than 70°, and the base angle θ2 is substantially smaller than 80θ2 is, for example, smaller than 80°, for example. - In addition, the height of the trapezoid T3 is, for example, substantially greater than the height of the trapezoid T4. The height of the trapezoid T3 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T4 is, for example, from about 50 angstroms to about 1500 angstroms.
- By implementing the above, primary steps of fabricating the
thin film transistor 124 have been completed. Thethin film transistor 124 includes the patterned conductive layer 108 (which is used as the gate), thechannel layer 112, theohmic contact layer 114 a, and the patterned conductive layer 122 (which is used as the source and the drain). - Next, please refer to
FIG. 1F . Apassivation layer 126 is formed on thethin film transistor 124, wherein thepassivation layer 126 has anopening 128. Theopening 128 exposes a portion of the patternedconductive layer 122 which is used as the drain. Thepassivation layer 126 may have a single-layered or multiple-layered structure, and the material thereof may be an inorganic material, organic material, another dielectric material, or combinations of the above. When the material of thepassivation layer 126 is an inorganic material such as silicon nitride, or silicon oxide, or other suitable materials, the method of forming thepassivation layer 126 which has the opening is, for example, forming a passivation material layer (not shown) over thewhole substrate 100, and then performing a patterning process on the passivation material layer. - Please refer to
FIG. 1G . Apixel electrode 130 is formed on thepassivation layer 126, wherein thepixel electrode 130 is electrically connected, via theopening 128, to the portion of the patternedconductive layer 122 of thethin film transistor 124 that is used as the drain. Thepixel electrode 130 may have a single-layered or multiple-layered structure, and the material thereof may be a transparent material, a non-transparent material, or combinations of the above. The present embodiment is illustrated in a way that indium tin oxide (ITO) and/or a transparent material of indium zinc oxide (IZO) is used as an example. The invention, however, is not limited to the above. The method of forming thepixel electrode 130 is, for example, forming a pixel electrode layer (not shown) by sputtering, and then performing a patterning process on the pixel electrode. - It is known from the above embodiment that compared with the deposition rates of the copper layers 104 a and 108 a, since the deposition rates of the copper layers 106 a and 120 a respectively covering the copper layers 104 a and 118 a are substantially slower, the copper layers 106 a and 120 a have better arrangements of atoms, less thin film defects, and lower oxidation rates, thereby greatly reducing the disconnection rate of wires in the active device array substrate.
- It should be noted that although to the above embodiment is described in a way that the method of forming the patterned conductive layer is used as an example to form each of the gate (the patterned conductive layer 108) and the source and the drain (the patterned conductive layer 122), the invention is not limited to the above. In other words, any situation, in which any of the gate, the scan line, the source, the drain, the data line, other metal lines, and other metal electrodes is fabricated by the above fabricating method of the patterned conductive layer, is within the scope of the fabricating method of the active device array substrate of the invention.
- In the following, the active device array substrate according to an embodiment of the invention is illustrated by using
FIG. 1G . The active device array substrate may be applied to liquid crystal displays (LCD), thin film transistor-organic light emitting diodes (TFT-OLED), electronic paper, or other products. - Please refer to
FIG. 1G . The active device array substrate has at least a patterned conductive layer. The patterned conductive layer includes a copper layer. The copper layer in the patterned conductive layer may be a single-layered or multiple-layered structure. As long as a cross-section of the copper layer which is substantially parallel to a normal line direction of the copper layer includes two trapezoid which are stacked, and that the base angles are acute angles which have a difference from about 5° to about 30°, the patterned conductive layer is within the scope of the invention. - For example, in the active device array substrate shown in
FIG. 1G , the patterned conductive layer in the active device array substrate is the patternedconductive layer 108 which is used as the gate and the patternedconductive layer 122 which is used as the source and the drain. The copper layer in the patternedconductive layer 108 is, for example, a double-layered structure formed by stacking of the copper layers 104 a and 106 a, and the copper layer in the patternedconductive layer 122 is, for example, a double-layered structure formed by stacking of the copper layers 118 a and 120 a. The invention, however, is not limited to the above. - The cross-section of the copper layer of the patterned
conductive layer 108 which is substantially parallel to the normal line direction N of the copper layer includes the trapezoid T1 (which is the cross-section of thecopper layer 104 a) and the trapezoid T2 (which is the cross-section of thecopper layer 106 a) stacked on the trapezoid T1. The base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 substantially are acute angles, and the difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is, for example, from about 5° to about 30°. According to an embodiment of the invention, the difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is from about 7° to about 13°, for example about 10°. The base angle θ1 is, for example, substantially smaller than the base angle θ2. The base angle θ1 is substantially smaller than 70θ1 is, for example, smaller than 70°, and the base angle θ2 is substantially smaller than 80θ2 is, for example, smaller than 80°, for example. In addition, the height of the trapezoid T1 is substantially greater than the height of the trapezoid T2. The height of the trapezoid T1 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T2 is, for example, from about 50 angstroms to about 1500 angstroms. - Please also refer to
FIG. 2 . The cross-section of the copper layer of the patternedconductive layer 122 which is substantially parallel to the normal line direction N of the copper layer includes the trapezoid T3 (which is the cross-section of thecopper layer 118 a) and the trapezoid T4 (which is the cross-section of thecopper layer 120 a) stacked on the trapezoid T3. The base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 are acute angles, and the difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 the trapezoid T4 is from about 5° to about 30°, for example. According to an embodiment of the invention, the difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 is from about 7° to about 13°, for example about 10°. The base angle θ3 is, for example, substantially smaller than the base angle θ4. The base angle θ1 is substantially smaller than 70°, and the base angle θ2 is substantially smaller than 80°, for example. In addition, the height of the trapezoid T3 is, for example, substantially greater than the height of the trapezoid T4. The height of the trapezoid T3 and T4 is from about 50 angstroms to about 5000 angstroms. Generally speaking, the height of the trapezoid T3 is, for example, from about 2500 angstroms to about 5000 angstroms, and the height of the trapezoid T4 is, for example, from about 50 angstroms to about 2500 angstroms. In some embodiment, the height of the trapezoid T3 is, for example, from about 1500 angstroms to about 5000 angstroms, and the height of the trapezoid T4 is, for example, from about 50 angstroms to about 1500 angstroms. - In addition, the patterned
conductive layers copper layer 104 a is stacked on thebarrier layer 102 a, and thecopper layer 118 a is stacked on thebarrier layer 116 a. The materials of the barrier layers 102 a and 116 a is at least one selected from the group consisting of molybdenum, a molybdenum alloy, titanium, a titanium alloy, an aluminum alloy, and a copper alloy. - Moreover, the active device array substrate further includes elements such as the
substrate 100, thedielectric layer 110, thechannel layer 112, theohmic contact layer 114 a, thepassivation layer 126, and thepixel electrode 130. The manner in which these elements are disposed, the materials of these elements, and the method of forming these elements have already been elaborated above and are hence not repeatedly described. - Due to the above, in the active device array substrate provided by the invention, since the base angle θ1 (or θ3) of the trapezoid T1 (or T3) and the base angle θ2 (or θ4) trapezoid T2 (or T4) substantially are acute angles, and the difference between the base angle θ1 (or θ3) of the trapezoid T1 (or T3) and the base angle θ2 (or θ4) of the trapezoid T2 (or T4) is from about 5° to about 30°, the active device array substrate has a better exterior structure, so that formation of structural defects are effectively prevented, thereby improving electrical characteristics.
- However, the patterned conductive layer according to the present embodiment is illustrated in an exemplary way that the patterned conductive layer is used as the gate (the patterned conductive layer 108) and the source and the drain (the patterned conductive layer 122). Any situation in which any of the gate, the scan line, the source, the drain, the data line, other metal lines, and other metal electrodes has the structure of the above patterned conductive layer is within the scope of the invention.
- Table 1 is a comparison chart of disconnection rates of wires according to the conventional art and the invention.
-
TABLE 1 Thickness of Thickness Disconnection lower of upper rate of wires Copper wire copper layer copper layer (opening/square structure Cross-section (angstroms) (angstroms) meter) Comparative Single-layer Single about 5000 about 0.55 embodiment 1 trapezoid Comparative Single-layer Single about 5000 about 0.32 embodiment 2 trapezoid Experimental Double-layer Two about 4500 about 500 about 0.18 embodiment 1 trapezoids Experimental Double-layer Two about 4500 about 500 about 0.23 embodiment 2 trapezoids Experimental Double-layer Two about 4500 about 500 about 0.10 embodiment 3 trapezoids - According to Table 1, in comparative embodiments 1 and 2, when a copper layer is formed, the copper layer is formed only by a single, rapid, and high power deposition process, so that after the copper layer is patterned to form a copper wire, the cross-section is a single trapezoid, and the copper wire has a higher disconnection rate.
- In experimental embodiments 1, 2, and 3, when a copper layer is formed, a lower copper layer is formed by a rapid and high power deposition, and an upper copper layer is then formed by a slow and low power deposition process (which has a power ⅓ of the high power deposition process), and the upper copper layer is stacked on the lower copper layer to form stacked copper layers. Hence, after the stacked copper layers are patterned to form a copper wire, the cross-section has two trapezoids, and the copper wire has a lower disconnection rate.
- In summary, the above embodiments have at least the following advantages.
- 1. The above fabricating method of the active device array substrate effectively reduces the disconnection rate of wires.
- 2. The active device array substrate has better electrical characteristics.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (5)
1. A fabricating method of an active device array substrate, comprising:
depositing a first copper layer at a first deposition rate on a substrate;
depositing a second copper layer at a second deposition rate on the first copper layer, wherein the first deposition rate is substantially greater than the second deposition rate; and
patterning the first copper layer and the second copper layer.
2. The fabricating method of the active deice array substrate as claimed in claim 1 , wherein after the first copper layer and the second copper layer are patterned, a first cross-section of the first copper layer which is substantially parallel to a normal line direction of the first copper layer is a first trapezoid, a second cross-section of the second copper layer which is parallel to the normal line direction of the first copper layer is a second trapezoid, a base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.
3. The fabricating method of the active device array substrate as claimed in claim 1 , wherein a depositing method of the first copper layer and the second copper layer comprises sputtering.
4. The fabricating method of the active device array substrate as claimed in claim 1 , wherein the first deposition rate is at least two times the second deposition rate.
5. The fabricating method of the active device array substrate as claimed in claim 1 , further comprising depositing a barrier layer on the substrate before the step of depositing the first copper layer, wherein the first copper layer is deposited on the barrier layer.
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TWI528074B (en) * | 2014-03-28 | 2016-04-01 | 群創光電股份有限公司 | Display panel |
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TWI578504B (en) * | 2016-02-05 | 2017-04-11 | 友達光電股份有限公司 | Pixel structure and fabricating method thereof |
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Also Published As
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US20110228502A1 (en) | 2011-09-22 |
TWI482239B (en) | 2015-04-21 |
US8270178B2 (en) | 2012-09-18 |
TW201133707A (en) | 2011-10-01 |
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