WO2021051846A1 - 一种显示面板及显示装置 - Google Patents
一种显示面板及显示装置 Download PDFInfo
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- WO2021051846A1 WO2021051846A1 PCT/CN2020/091313 CN2020091313W WO2021051846A1 WO 2021051846 A1 WO2021051846 A1 WO 2021051846A1 CN 2020091313 W CN2020091313 W CN 2020091313W WO 2021051846 A1 WO2021051846 A1 WO 2021051846A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/341—Short-circuit prevention
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- the embodiments of the present application relate to display technology, for example, to a display panel and a display device.
- the full-screen technology is sought after by market users.
- the frame of the display panel is getting smaller and smaller.
- the space for metal wiring is getting smaller and smaller. , Causing the metal traces to be easily shorted.
- the present application provides a display panel and a display device, so as to ensure that the display panel has a smaller frame, while avoiding the short circuit of the interconnection lines of the first interconnection line layer, so as to ensure that the display panel has a higher display performance.
- the embodiment of the present application provides a display panel, including:
- a substrate including a display area, a bonding area provided on one side of the display area, and a fan-out area provided between the bonding area and the display area;
- the fan-out area includes at least two metal layers stacked on the surface of the substrate, a first planarization layer, and a first interconnection layer.
- An embodiment of the present application also provides a display device, including the display panel described in any embodiment of the present application.
- a first planarization layer is provided between the first interconnection line layer and at least two metal layers.
- the first planarization layer can planarize the uneven surface caused by the process of the at least two metal line layers.
- FIG. 1 is a schematic top view of a display panel provided by an embodiment of the present application.
- FIG. 2 is a schematic cross-sectional view of a fan-out area provided by an embodiment of the present application
- FIG. 3 is a schematic cross-sectional view of another fan-out area provided by an embodiment of the present application.
- FIG. 4 is a schematic top view of another display panel provided by an embodiment of the present application.
- FIG. 5 is a schematic cross-sectional view of a bending area provided by an embodiment of the present application.
- FIG. 6 is a schematic cross-sectional view of another fan-out area provided by an embodiment of the present application.
- FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present application.
- the wiring space of the metal wiring becomes smaller and smaller, which causes the metal wiring to be easily short-circuited.
- the reason for this problem is that multiple metal wire layers are usually arranged in the frame area of the display panel. Since the insulating layer between the metal wire layers is usually an inorganic layer, the thickness of the inorganic layer is relatively thin. When the metal wire layer is formed, there will be unevenness on the surface after the metal wire layer is formed, which leads to photoresist residues in the subsequent preparation of the metal wire layer, which causes part of the metal to be unable to be etched off, resulting in a short circuit between the metal wires.
- the display panel includes: a substrate 10, the substrate 10 includes a display area 11, a bonding area 12 disposed on one side of the display area 11, and a bonding area 12 disposed between the bonding area 12 and the display area 11.
- the fan-out zone 13 includes at least two metal layers 20, a first planarization layer 30, and a first interconnection layer 40 stacked on the surface of the substrate 10.
- the bonding area 12 is set as a bonding driver chip, and the fan-out area 13 is the area between the bonding area 12 and the display area 11, which is used to set the data line and power line of the display area 11 to be led out to the bonding area 12.
- the lead-out lines, and the scan signal lines and reset signal lines that provide scan signals and reset signals to the pixel drive circuit in the setting part.
- the first interconnection line layer 40 may include a plurality of scan signal lines, reset signal lines, and power lead-out lines.
- the first planarization layer 30 is made of organic materials, and exemplarily, an organic glue for exposure can be used.
- the first planarization layer 30 can planarize the uneven surface caused by the manufacturing process of the at least two metal wire layers 20, so that the first interconnection wire layer 40 can be fabricated on a flat surface, and avoid the uneven surface.
- the first interconnection line layer 40 is formed by a photolithography process, there is a photoresist residue, which causes part of the metal to be unable to be etched away, resulting in a short circuit between interconnection lines. Therefore, in the solution of this embodiment, by providing the first planarization layer 30 between the first interconnection layer 40 and the at least two metal layers 20, it is possible to avoid the first interconnection line while ensuring that the display panel has a smaller frame.
- the interconnection lines of layer 40 are short-circuited to ensure that the display panel has a higher display performance.
- the first interconnecting line layer 40 includes a plurality of first interconnecting lines 41, and the distance D between adjacent first interconnecting lines 41 is less than or equal to 8 micrometers.
- the first interconnection line 41 may include a scan signal line, a reset signal line, and a power lead-out line.
- the power lead-out line may include a first power signal lead-out line and a second power signal lead-out line.
- the first power signal lead-out line is configured to provide the first power signal VDD to the pixel driving circuit.
- the second power signal lead-out line is configured to provide the second power signal VSS to the cathode of the organic light emitting diode.
- the solution of this embodiment provides a first planarization layer 30 between the first interconnection line layer 40 and at least two metal layers 20, so that when the distance D between adjacent first interconnection lines 41 is less than or equal to 8 microns Next, no short circuit occurs between the first interconnecting lines 41, which ensures that the display panel has a smaller frame and higher display performance.
- FIG. 1 only exemplarily shows that the first interconnection line 41 extends along the extension direction of the intersecting boundary of the display area 11 and the fan-out area 13, which is not a limitation of the present application.
- the first interconnection line 41 is also Can extend in other directions.
- this embodiment does not limit the spacing between the first interconnecting lines 41, and can be set according to the needs of the panel.
- the spacing between the first interconnecting lines 41 may be set to 5 microns, so that when the spacing D between adjacent first interconnecting lines 41 is small, no short circuit occurs between the first interconnecting lines 41 to ensure The display panel has a smaller frame and a higher display performance.
- the fan-out area 30 further includes an insulating layer, and an insulating layer is provided between two adjacent metal layers.
- the thickness of the first planarization layer 30 is in the range of 1-2 microns.
- the thickness of the first planarization layer 30 When the thickness of the first planarization layer 30 is too small, the planarization effect of the first planarization layer 30 is poor. When the thickness of the first planarization layer is too large, it is not conducive to reducing the thickness of the display panel. By setting the thickness of the first planarization layer 30 in the range of 1-2 microns, it is better to avoid the short circuit between interconnection lines caused by the uneven surface caused by the process of at least two layers of metal 20, while ensuring that the display panel has a small size. The thickness of the display panel is in line with the development trend of thinner and lighter display panels.
- the thickness of the first planarization layer 30 can be determined according to the degree of surface unevenness caused by the manufacturing process of at least two metal layers 20, and it can be set as an example. It is 1.3 microns, 1.5 microns, 1.7 microns, etc.
- the display panel further includes: a first insulating layer 50 disposed between at least two metal layers 20 and the first planarization layer 30.
- the first insulating layer 50 is made of inorganic materials, for example, materials such as silicon nitride or silicon oxide can be used. Due to the better insulation of inorganic materials relative to organic materials, the provision of the first insulating layer 50 can better protect the metal lines in the metal layers adjacent to the first interconnection layer 40 among the at least two metal layers 20 and the first flat layer.
- the metal layer 30 has a better insulation effect, and at the same time, it can provide a better insulation effect between the metal layer adjacent to the first interconnection line layer 40 and the first interconnection line 40 in the at least two metal layers 20, avoiding The multiple metal wires interfere with each other to ensure that the display panel has better display performance.
- the substrate 10 further includes a bending area 14 disposed between the fan-out area 13 and the bonding area 12; the bending area 14 includes an organic layer 60 disposed on the surface of the substrate 10, the first flat
- the chemical layer 30 and the organic layer 60 are provided in the same layer.
- the bending area 14 is the area where the display panel is bent and deformed.
- the bending area 14 is bent to the side of the substrate 10 away from the light emitting surface of the display panel, so that the bonding area 12 is bent to the back of the display panel, and the display panel is further reduced. Border.
- the first planarization layer 30 and the organic layer 60 of the bending region 14 are arranged in the same layer, so that the first planarization layer 30 and the organic layer 60 can be prepared in the same process using the same material and the same mask, reducing the display panel Material cost and manufacturing process cost.
- the bending area 14 further includes a first metal layer 70 disposed on a side of the organic layer 60 away from the substrate 10, and the first metal layer 70 is disposed in the same layer as the first interconnect layer 40.
- the first metal layer 70 includes a plurality of first metal lines, and the first metal lines may include lead lines that lead out the data lines and power lines of the display area 11 to the bonding area 12.
- the first metal layer 70 and the first interconnection line layer 40 are provided in the same layer.
- the first metal layer 70 and the first interconnection line layer 40 can be prepared in the same process using the same material and the same mask, which reduces the material cost of the display panel And the cost of production process.
- the first interconnection line 41 adopts a Ti/Al/Ti laminated structure.
- the first interconnection line 41 adopts a Ti/Al/Ti laminated structure. Since the first metal layer 70 and the first interconnection line 41 can be made of the same material, the first metal layer 70 The Ti/Al/Ti laminated structure can effectively prevent the first metal wire from breaking after the bending zone 14 is bent, and improve the bending resistance of the display panel.
- the fan-out area 13 further includes a second insulating layer 80, a second planarization layer 90, and a second interconnection layer 100 stacked on the side of the first interconnection layer 40 away from the substrate 10.
- the second planarization layer 90 covers the display area 11.
- the second interconnection line layer 100 includes a plurality of second interconnection lines, and the second interconnection lines may also include scan signal lines, reset signal lines, and power lead-out lines.
- the scan signal line, the reset signal line, and the power lead-out line can be arranged on the first interconnection line layer 40 or the second interconnection line layer 100 as required.
- both the scan signal line and the reset signal line may be arranged on the first interconnection line layer 40, and the power lead wires may be arranged on the second interconnection line layer 100.
- the second planarization layer 90 may use organic materials.
- a second planarization layer 90 is provided between the second interconnection line layer 100 and the first interconnection line layer 40, and the second planarization layer 90 has a planarizing effect, so that the second interconnection line layer 100 can be prepared on a relatively flat surface, Avoid making it on an uneven surface when there is photoresist residue when forming the second interconnection line layer 100 through a photolithography process, which will result in a part of the metal that cannot be etched away, resulting in a short circuit between the interconnection lines.
- the organic light-emitting structure of the display panel is required after the second interconnect layer 100, by providing the second planarization layer 90 to cover the display area 11, the display area 11 and the fan-out area 13 can be planarized at the same time, which is convenient for subsequent preparation. Organic light emitting structure.
- the bending area 14 may also include a fourth metal layer 110.
- the fourth metal layer 110 and the second interconnection layer 100 are arranged in the same layer, and the data lines and power lines of the display area 11 are led out to the bonding area 12
- the lead wires may be distributed in the first metal layer 70 and the fourth metal layer.
- the second interconnect layer 100 and the fourth metal layer 110 can also adopt a Ti/Al/Ti laminated structure to avoid the breakage of the slowing line in the fourth metal layer after the bending area 14 is bent, and improve the bending resistance of the display panel. Sex.
- the display area 11 includes a gate layer 31, a capacitor plate layer 32, a source and drain layer 33, and a power signal layer 34 stacked on the substrate 10; at least two metal layers 20 include a second metal layer 21 And the third metal layer 22, a third insulating layer 23 is provided between the second metal layer 21 and the third metal layer 22; the second metal layer 21 and the gate layer 31 are provided in the same layer, and the third metal layer 22 and the capacitor electrode
- the board layer 32 is arranged in the same layer, the first interconnection line layer 40 and the source and drain layer 33 are arranged in the same layer, and the second interconnection line layer 100 and the power signal layer 34 are arranged in the same layer.
- the gate layer 31 includes metal structures such as the gates and scan lines of the thin film transistors in the pixel drive circuit
- the capacitor plate layer 32 includes metal structures such as the capacitor plates in the pixel drive circuit
- the source and drain layer 33 includes Metal structures such as the source and drain of the thin film transistor and the data line.
- the power signal layer 34 includes a first power signal line and a second power signal line to provide a power signal for the pixel driving circuit.
- the second metal layer 21 and the third metal layer 22 include lead-out lines of data lines, and the lead-out lines are electrically connected to the data lines in the display area 11.
- the third metal layer 22 and the capacitor plate layer 32 are provided in the same layer
- the first interconnection line layer 40 and the source and drain layer 33 are provided in the same layer
- the second interconnection The line layer 100 is arranged in the same layer as the power signal layer 34
- the second metal layer 21, the third metal layer 22, the first interconnection line layer 40, and the second interconnection line layer 100 can be connected to the gate layer 31 and the capacitor plate layer 32, respectively.
- the source drain layer 33 and the power signal layer 34 are made of the same material and the same mask in the same process, which reduces the material cost and manufacturing process cost of the display panel.
- FIG. 7 is a schematic structural diagram of a display device provided in an embodiment of the present application.
- the display device 200 provided in this embodiment includes the display panel 300 provided in any one of the foregoing embodiments.
- the display device 200 provided in the embodiment of the present application may be a display device such as a mobile phone, a wearable device with display function, a computer, etc. Repeat it again.
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Abstract
本申请实施例公开了一种显示面板及显示装置。显示面板包括：衬底，所述衬底包括显示区、设置于所述显示区的一侧的邦定区以及设置于所述邦定区和所述显示区之间的扇出区；所述扇出区包括层叠设置于所述衬底表面的至少两层金属层、第一平坦化层以及第一互联线层。
Description
本申请要求在2019年09月19日提交中国专利局、申请号为201910888406.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
本申请实施例涉及显示技术，例如涉及一种显示面板及显示装置。
随着手机市场的发展，全面屏技术受到市场用户的追捧，在实现全面屏时，显示面板的边框越来越小，然而随着边框的减小，金属走线的走线空间越来越小，导致金属走线容易短路。
发明内容
本申请提供一种显示面板及显示装置，以实现在保证显示面板具有较小的边框的同时，可以避免第一互联线层的互联线短路，保证显示面板具有较高的显示性能。
本申请实施例提供了一种显示面板，包括：
衬底，所述衬底包括显示区、设置于所述显示区的一侧的邦定区以及设置于所述邦定区和所述显示区之间的扇出区；
所述扇出区包括层叠设置于所述衬底表面的至少两层金属层、第一平坦化层以及第一互联线层。
本申请实施例还提供了一种显示装置，包括本申请任意实施例所述的显示面板。
本申请实施例通过在第一互联线层与至少两层金属层之间设置第一平坦化层，第一平坦化层可以对至少两层金属线层制程带来的凹凸不平的表面进行平 坦化，使得第一互联线层可以制作于平整的表面，避免制作于不平整的表面时，在通过光刻工艺形成第一互联线层时存在光刻胶残留，导致部分金属无法刻掉，造成互联线之间短路。因此本实施例的方案在保证显示面板具有较小的边框的同时可以避免第一互联线层的互联线短路，保证显示面板具有较高的显示性能。
图1是本申请实施例提供的一种显示面板的俯视示意图；
图2是本申请实施例提供的一种扇出区的剖面示意图；
图3是本申请实施例提供的又一种扇出区的剖面示意图；
图4是本申请实施例提供的又一种显示面板的俯视示意图；
图5是本申请实施例提供的一种弯折区的剖面示意图；
图6是本申请实施例提供的又一种扇出区的剖面示意图；
图7是本申请实施例提供的一种显示装置的结构示意图。
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。另外，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
正如背景技术中提到的，随着显示面板边框的减小，金属走线的走线空间越来越小，导致金属走线容易短路。出现这种问题的原因在于，在显示面板的边框区通常设置有多层金属线层，由于金属线层之间的绝缘层通常为无机层，无机层厚度较薄，随着金属线层层数的增多，形成金属线层后的表面会出现凹凸不平，导致后续制备金属线层时容易出现光刻胶残留，从而导致部分金属无法刻掉，造成金属线之间短路。
本实施例提供了一种显示面板。参考图1和图2，显示面板包括：衬底10，衬底10包括显示区11、设置于显示区11的一侧的邦定区域12以及设置于邦定区12和显示区11之间的扇出区13；扇出区13包括层叠设置于衬底10表面的至少两层金属层20、第一平坦化层30以及第一互联线层40。
邦定区12设置为邦定驱动芯片，扇出区13为设置于邦定区12和显示区11之间的区域，用于设置将显示区11的数据线和电源线引出到邦定区12的引出线，以及设置部分向像素驱动电路提供扫描信号和复位信号的扫描信号线和复位信号线等。第一互联线层40可以包括多条扫描信号线、复位信号线和电源引出线。第一平坦化层30采用有机材料，示例性的可以采用曝光用的有机胶。
第一平坦化层30可以对至少两层金属线层20制程带来的凹凸不平的表面进行平坦化，使得第一互联线层40可以制作于平整的表面，避免制作于不平整的表面时，在通过光刻工艺形成第一互联线层40时存在光刻胶残留，导致部分金属无法刻掉，造成互联线之间短路。因此，本实施例的方案通过在第一互联线层40与至少两层金属层20之间设置第一平坦化层30，在保证显示面板具有较小的边框的同时，可以避免第一互联线层40的互联线短路，保证显示面板具有较高的显示性能。
第一互联线层40包括多条第一互联线41，相邻第一互联线41的间距D小于或等于8微米。
第一互联线41可以包括扫描信号线、复位信号线和电源引出线。示例性的，电源引出线可以包括第一电源信号引出线和第二电源信号引出线。第一电源信号引出线设置为向像素驱动电路提供第一电源信号VDD。第二电源信号引出线设置为向有机发光二极管的阴极提供第二电源信号VSS。
通过设置相邻第一互联线41的间距小于或等于8微米，可以保证扇出区13 具有较小的宽度，从而保证显示面板具有较小的边框。且本实施例的方案通过在第一互联线层40与至少两层金属层20之间设置第一平坦化层30，使得在相邻第一互联线41的间距D小于或等于8微米的情况下，第一互联线41之间不会发生短路，保证显示面板具有较小的边框的同时具有较高的显示性能。
图1仅示例性的示出了第一互联线41沿显示区11与扇出区13的相交的边界的延伸方向延伸，并非对本申请的限定，在其他实施方式中，第一互联线41还可以沿其他方向延伸。此外，本实施例对第一互联线41之间的间距并不做限定，可以根据面板需要进行设置。示例性的，可以设置第一互联线41之间的间距为5微米，使得在相邻第一互联线41的间距D较小的情况下，第一互联线41之间不会发生短路，保证显示面板具有较小的边框的同时具有较高的显示性能。
在一实施例中，扇出区30还包括绝缘层，相邻两层金属层之间设置有绝缘层。
可选的，第一平坦化层30的厚度范围为1-2微米。
在第一平坦化层30的厚度过小时，第一平坦化层30的平坦化作用较差，在第一平坦化层的厚度过大时，不利于减薄显示面板的厚度。通过设置第一平坦化层30的厚度范围为1-2微米，在较好的避免至少两层金属20制程带来的表面不平整导致的互联线之间短路的同时，保证显示面板具有较小的厚度，符合显示面板轻薄化的发展趋势。
本实施例对第一平坦化层30的厚度并不做限定，可以根据至少两层金属层20制程带来的表面不平整的程度等确定第一平坦化层30的厚度，示例性的可以设置为1.3微米、1.5微米或1.7微米等。
参考图3，显示面板还包括：第一绝缘层50，第一绝缘层50设置于至少两 层金属层20和第一平坦化层30之间。
第一绝缘层50采用无机材料，例如，可以采用氮化硅或氧化硅等材料。由于无机材料相对于有机材料的绝缘性更好，通过设置第一绝缘层50可以更好地对至少两层金属层20中邻近第一互联线层40的金属层中的金属线与第一平坦化层30之间起到较好的绝缘作用，同时可以对至少两层金属层20中邻近第一互联线层40的金属层和第一互联线40之间起到较好的绝缘作用，避免多个金属线之间相互干扰，保证显示面板具有较好的显示性能。
参考图4和图5，衬底10还包括设置于扇出区13和邦定区12之间的弯折区14；弯折区14包括设置于衬底10表面的有机层60，第一平坦化层30与有机层60同层设置。
弯折区14即显示面板发生弯折形变的区域，弯折区14向衬底10远离显示面板发光面的一侧弯折，使邦定区12弯折到显示面板背面，进一步减小显示面板的边框。
第一平坦化层30和弯折区14的有机层60同层设置，使得第一平坦化层30可以和有机层60采用相同的材料采用同一掩膜版在同一工艺中制备，降低显示面板的材料成本和制作工艺成本。
可选的，弯折区14还包括设置于有机层60远离衬底10一侧的第一金属层70，第一金属层70与第一互联线层40同层设置。
第一金属层70包括多条第一金属线，第一金属线可以包括将显示区11的数据线和电源线引出到邦定区12的引出线。
第一金属层70与第一互联线层40同层设置，第一金属层70与第一互联线层40可以采用相同的材料和同一掩膜版在同一工艺中制备，降低显示面板的材料成本和制作工艺成本。
可选的，第一互联线41采用Ti/Al/Ti层叠结构。
由于铝Al的耐弯折性比较好，第一互联线41采用Ti/Al/Ti层叠结构，由于第一金属层70与第一互联线41可以采用相同的材料制备，则第一金属层70采用Ti/Al/Ti层叠结构，可以有效避免弯折区14弯折后第一金属线断裂，提升显示面板的耐弯折性。
可选的，参考图6，扇出区13还包括层叠设置于第一互联线层40远离衬底10一侧的第二绝缘层80、第二平坦化层90和第二互联线层100，第二平坦化层90覆盖显示区11。
第二互联线层100包括多条第二互联线，第二互联线也可以包括扫描信号线、复位信号线和电源引出线。扫描信号线、复位信号线和电源引出线可以根据需要设置于第一互联线层40或第二互联线层100。示例性的，可以将扫描信号线和复位信号线均设置于第一互联线层40，将电源引出线均设置于第二互联线层100。
第二平坦化层90可以采用有机材料。第二互联线层100与第一互联线层40之间设置第二平坦化层90，第二平坦化层90起到平坦化作用，使得第二互联线层100可以制备于较为平坦的表面，避免制作于不平整的表面的情况下，在通过光刻工艺形成第二互联线层100时存在光刻胶残留，导致部分金属无法刻掉，造成互联线之间短路。
此外，由于在第二互联线层100之后需要显示面板的有机发光结构，通过设置第二平坦化层90覆盖显示区11，可以对显示区11和扇出区13同时进行平坦化，便于后续制备有机发光结构。
参见图5，弯折区14还可以包括第四金属层110，第四金属层110与第二互联线层100同层设置，将显示区11的数据线和电源线引出到邦定区12的引 出线可以分布于第一金属层70和第四金属层。
此外，第二互联线层100和第四金属层110也可以采用Ti/Al/Ti层叠结构，避免弯折区14弯折后第四金属层中的减缓线断裂，提升显示面板的耐弯折性。
参考图6，显示区11包括层叠设置于衬底10上的栅极层31、电容极板层32、源漏极层33和电源信号层34；至少两层金属层20包括第二金属层21和第三金属层22，第二金属层21和第三金属层22之间设置有第三绝缘层23；第二金属层21与栅极层31同层设置，第三金属层22与电容极板层32同层设置，第一互联线层40与源漏极层33同层设置，第二互联线层100与电源信号层34同层设置。
在显示区11，栅极层31包括像素驱动电路中薄膜晶体管的栅极、扫描线等金属结构，电容极板层32包括像素驱动电路中电容的极板等金属结构，源漏极层33包括薄膜晶体管的源漏极以及数据线等金属结构，电源信号层34包括第一电源信号线和第二电源信号线，为像素驱动电路提供电源信号。在扇出区13，第二金属层21和第三金属层22包括数据线的引出线，引出线与显示区11中的数据线电连接。
通过设置第二金属层21与栅极层31同层设置，第三金属层22与电容极板层32同层设置，第一互联线层40与源漏极层33同层设置，第二互联线层100与电源信号层34同层设置，第二金属层21、第三金属层22、第一互联线层40和第二互联线层100可以分别与栅极层31、电容极板层32、源漏极层33和电源信号层34采用同种材料采用同一掩膜版在同一工艺中制备，降低显示面板的材料成本和制作工艺成本。
本实施例还提供了一种显示装置，图7是本申请实施例提供的一种显示装置的结构示意图。参见图7，本实施例提供的显示装置200包括上述任一实施例 提出的显示面板300。
本申请实施例提供的显示装置200可以为手机、具有显示功能的可穿戴设备、计算机等显示装置，本申请实施例提供的显示装置200包括上述任一实施例提出的显示面板200，在此不再赘述。
Claims (20)
- 一种显示面板，包括：衬底，所述衬底包括显示区、设置于所述显示区的一侧的邦定区以及设置于所述邦定区和所述显示区之间的扇出区；所述扇出区包括层叠设置于所述衬底表面的至少两层金属层、第一平坦化层以及第一互联线层。
- 根据权利要求1所述的显示面板，其中：所述第一互联线层包括多条第一互联线，相邻第一互联线之间的间距小于或等于8微米。
- 根据权利要求2所述的显示面板，其中：所述第一互联线沿所述显示区与所述扇出区相交的边界的延伸方向延伸。
- 根据权利要求1所述的显示面板，其中：所述第一平坦化层的厚度范围为1-2微米。
- 根据权利要求1所述的显示面板，还包括：第一绝缘层，所述第一绝缘层设置于所述至少两层金属层和所述第一平坦化层之间。
- 根据权利要求1或2所述的显示面板，其中：所述衬底还包括设置于所述扇出区和所述邦定区之间的弯折区；所述弯折区包括设置于所述衬底表面的有机层，所述第一平坦化层与所述有机层同层设置。
- 根据权利要求6所述的显示面板，其中：所述弯折区还包括设置于所述有机层远离所述衬底一侧的第一金属层，所述第一金属层与所述第一互联线层同层设置。
- 根据权利要求7所述的显示面板，其中：所述第一金属层包括多条第一 金属线，所述第一金属线包括将显示区的数据线和电源线引出到所述邦定区的引出线。
- 根据权利要求1所述的显示面板，其中：所述扇出区还包括层叠设置于所述第一互联线层远离所述衬底一侧的第二绝缘层、第二平坦化层和第二互联线层，所述第二平坦化层覆盖所述显示区。
- 根据权利要求9所述的显示面板，其中：所述第一互联线层或第二互联线层上设置扫描信号线、复位信号线、电源引出线中的至少一种。
- 根据权利要求9所述的显示面板，其中：所述显示区包括层叠设置于所述衬底上的栅极层、电容极板层、源漏极层和电源信号层；所述至少两层金属层包括第二金属层和第三金属层，所述第二金属层和所述第三金属层之间设置有第三绝缘层；所述第二金属层与所述栅极层同层设置，所述第三金属层与所述电容极板层同层设置，所述第一互联线层与所述源漏极层同层设置，所述第二互联线层与所述电源信号层同层设置。
- 根据权利要求9所述的显示面板，其中：所述第一互联线采用Ti/Al/Ti层叠结构。
- 根据权利要求1所述的显示面板，其中，所述第一平坦化层的材料为有机胶。
- 根据权利要求5所述的显示面板，其中：所述第一绝缘层的材料为氮化硅或氧化硅。
- 根据权利要求9所述的显示面板，其中：所述第二平坦化层的材料为有机材料。
- 根据权利要求6所述的显示面板，其中：所述弯折区向衬底远离显示面板发光面的一侧弯折。
- 根据权利要求6所述的显示面板，其中：所述弯折区还包括第四金属层，所述第四金属层与所述第二互联网线层同层设置。
- 根据权利要求17所述的显示面板，其中：所述第四金属层与所述第二互联网线层采用Ti/Al/Ti层叠结构。
- 根据权利要求17所述的显示面板，其中：所述第一金属层和第四金属层分布有将显示区的数据线和电源线引出到所述邦定区的引出线。
- 根据权利要求1所述的显示面板，其中：所述扇出区还包括绝缘层，相邻两层金属层之间设置有所述绝缘层。
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