WO2021190034A1 - 显示基板、其制备方法及显示装置 - Google Patents

显示基板、其制备方法及显示装置 Download PDF

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Publication number
WO2021190034A1
WO2021190034A1 PCT/CN2020/140442 CN2020140442W WO2021190034A1 WO 2021190034 A1 WO2021190034 A1 WO 2021190034A1 CN 2020140442 W CN2020140442 W CN 2020140442W WO 2021190034 A1 WO2021190034 A1 WO 2021190034A1
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WIPO (PCT)
Prior art keywords
layer
conductive
display
area
base substrate
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Application number
PCT/CN2020/140442
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English (en)
French (fr)
Inventor
韩林宏
姜晓峰
高永益
张毅
周洋
王予
秦世开
刘庭良
青海刚
张顺
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/312,085 priority Critical patent/US20220406868A1/en
Publication of WO2021190034A1 publication Critical patent/WO2021190034A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • the base substrate includes a display area and a binding area located on at least one side of the display area;
  • the insulating protection layer is located on the side of the conductive layer away from the base substrate.
  • the insulating protection layer has a hollow area and a pattern area, the hollow area covers the first conductive terminal, and the pattern area covers the The gap between the plurality of first conductive terminals.
  • the conductive layer further includes: a plurality of traces electrically connected to the plurality of first conductive terminals, and the plurality of traces are connected to the The metal signal lines in the display area are electrically connected; the pattern area covers the multiple wiring lines.
  • the pattern area further covers the side of the first conductive terminal that is in contact with the base substrate.
  • the plurality of first conductive terminals are divided into a first group of first conductive terminals and a second group of first conductive terminals, the second group of first conductive terminals Conductive terminals are located on a side of the first group of first conductive terminals close to the display area;
  • the pattern area at least covers the gap between the first conductive terminals in the first group of first conductive terminals.
  • the pattern area further includes covering a gap between each first conductive terminal in the second group of first conductive terminals.
  • the pattern area further covers the gap between the first group of first conductive terminals and the second group of first conductive terminals.
  • the material of the insulating protection layer is an organic material or an inorganic material.
  • the display area further includes:
  • the pixel drive circuit is located on the base substrate;
  • At least one flat layer located on a side of the pixel driving circuit away from the base substrate, the flat layer having a flat surface and via holes;
  • a light emitting element located on the flat surface and electrically connected to the pixel driving circuit through the via hole;
  • the insulating protection layer and the flat layer are provided in the same layer.
  • the thickness of the insulating protection layer is half of the thickness of the flat layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes an encapsulation layer covering the display area, and the insulating protective layer is provided in the same layer as one of the encapsulation layers.
  • the encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer that are stacked in sequence, and the insulating protective layer and the first inorganic layer , One of the organic layer and the second inorganic layer is arranged in the same layer.
  • the metal signal line is a data line
  • the first conductive terminal and the data line are provided in the same layer.
  • the metal signal line is a gate line, and the first conductive terminal and the gate line are provided in the same layer.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display substrate.
  • the above-mentioned display device provided by the embodiment of the present disclosure further includes a chip, the chip includes a plurality of second conductive terminals; the second conductive terminal is crimped with the first conductive terminal of the display substrate.
  • the orthographic projection of the second conductive terminal on the base substrate is located on the right side of the hollow area of the insulating protective layer on the base substrate. Within the projection range.
  • the display device further includes a chip-on-chip film, the chip-on-chip film includes a plurality of third conductive terminals; the third conductive terminal and the first conductive terminal of the display substrate Terminal crimping.
  • embodiments of the present disclosure also provide a method for preparing a display substrate, including:
  • An insulating protection layer having a plurality of hollow areas and pattern areas is formed on the side of the conductive layer away from the base substrate; wherein the hollow areas cover the first conductive terminals, and the pattern areas cover the plurality of hollow areas. The gap between the first conductive terminals.
  • FIG. 1 is a schematic diagram of a top view structure of the area division of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a top view structure of a display substrate binding area provided by an embodiment of the present disclosure
  • Fig. 3 is a schematic cross-sectional view of Fig. 2 along the AA' direction;
  • FIG. 4 is a schematic diagram showing the structure of the binding area of the substrate before crimping in the related art
  • FIG. 5 is a schematic diagram showing the structure of the bonding area of the substrate after crimping in the related art
  • FIG. 6 is a schematic diagram of the structure of the binding area of the display substrate before crimping according to an embodiment of the disclosure
  • FIG. 7 is a schematic diagram of the structure of the binding area of the display substrate after crimping provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a structure of a display area of a display substrate provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a structure of an encapsulation layer covering a display area of a display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 11A and 11B are schematic cross-sectional structural diagrams after performing each step in the preparation method provided by the embodiments of the present disclosure.
  • FIG. 12 is a schematic top view of the structure of a display device provided by an embodiment of the disclosure.
  • the integrated circuit (IC) in the flexible display device is generally bonded by a chip on film (COF) bonding method, that is, the IC is first bonded on the flexible circuit board , And then press the flexible circuit board bound with the IC on the display panel. Since the flexible circuit board is made of soft material, it will not cause the circuit of the array substrate of the display panel to be broken when the IC is pressed. However, due to the COF The cost is high, and the COF circuit cannot be made too thin, so the COF cannot be used on high-resolution products. Based on this, the method of directly bonding IC (Chip On Plastic, COP) on the display panel has become the direction of future development.
  • COF chip on film
  • the flexible display device adopts a flexible substrate, it can be bent into a shape such as a bend, but things have two sides, and this advantage of the flexible substrate has also become its disadvantage, such as being easily deformed by force.
  • the flexible substrate will bend and deform due to the force during the binding, resulting in a short circuit between the flexible substrate and the COF or IC.
  • a display substrate provided by an embodiment of the present disclosure may include: a base substrate 100, the base substrate 100 includes a display area AA and a non-display area BB surrounding the display area AA, at least located in the display area AA
  • the non-display area BB on the side includes a bonding area CC.
  • the area for bonding ICs in the non-display area BB is called the bonding area CC.
  • the bonding area CC is provided with a plurality of first conductive terminals 10, which are bound by COP
  • the first conductive terminal 10 is used for crimping with a second conductive terminal (described later) on the IC to realize the electrical connection between the IC and the first conductive terminal 10.
  • the bonding area CC of the base substrate 100 is provided with a conductive layer 200, and the conductive layer 200 located in the bonding area CC includes a plurality of first conductive terminals 10 and is electrically connected to the first conductive terminals 10.
  • the second conductive terminal 20 on the IC is electrically connected to the first conductive terminal 10 on the display substrate to input the signal on the IC to the first conductive terminal 10
  • a conductive terminal 10 or the signal on the first conductive terminal 10 is output to the IC
  • the trace 101 located in the bonding area CC is electrically connected to the metal signal line (such as gate line, data line, etc.) in the display area AA, thus displaying
  • the signal on the metal signal line in the area AA can be input to the first conductive terminal 10, or the signal on the first conductive terminal 10 can be input to the metal signal line in the display area AA.
  • FIG. 3 is a cross-sectional view along the AA' direction in FIG. 2.
  • the bonding area CC of the display substrate includes a conductive layer on the base substrate 100 200.
  • the conductive layer 200 includes a plurality of first conductive terminals 10 and a plurality of traces 101 electrically connected to the first conductive terminals 10.
  • the trace 101 shown on the left side in FIG. The gate lines, data lines, etc.) are electrically connected, and the trace 101 shown on the right side of FIG. 3 is used for electrical connection with a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • FIG. 4 is a schematic diagram of the structure before the IC and the display substrate are crimped
  • FIG. 5 is a schematic diagram of the structure after the IC and the display substrate are crimped.
  • a certain amount of pressure needs to be applied to ensure the bonding effect, but this pressure will cause the base substrate to warp, resulting in warping as shown in Figure 5, which will cause a short circuit or contact between the IC and the trace 101, and then Affect signal transmission and cause poor display.
  • the binding area CC further includes an insulating protection layer 300 on the side of the conductive layer 200 away from the base substrate 100, and the insulating protection layer 300 has a plurality of hollow areas 01 and the pattern area 02, the hollow area 01 covers the first conductive terminal 10, and the pattern area 02 covers the gaps between the plurality of first conductive terminals 10.
  • the hollow area 01 of the insulating protection layer 300 of the bonding area CC exposes the first conductive terminal 10.
  • FIG. 6 is a schematic diagram of the structure before the IC and the display substrate are crimped in this disclosure
  • FIG. 7 is The schematic diagram of the structure after the IC and the display substrate are crimped in the publication.
  • the binding area CC of the display substrate includes an insulating protection layer 300 on the side of the conductive layer 200 away from the base substrate 100. Because the insulating protection layer 300 has a hollow area 01 and a pattern area 02. The hollow area 01 covers the first conductive terminal 10, and the pattern area 02 covers the wiring 101 located in the gap between the plurality of first conductive terminals 10. Therefore, the hollow area 01 of the insulating protection layer 300 in the bonding area CC exposes the first conductive terminal 10, and the pattern area 02 covers the wiring 101.
  • the insulating protection layer 300 can prevent the bonding area CC of the base substrate 100 from being warped during crimping, etc., from short-circuiting in the bonding area.
  • the base substrate provided by the present disclosure is a flexible base substrate, and the material of the flexible base substrate is not specifically limited.
  • the material of the flexible base substrate is not specifically limited.
  • it may be polyimide, polyvinyl ether phthalate, and polynaphthalene.
  • Plastic substrates with excellent heat resistance and durability such as ethylene glycol dicarboxylate, polycarbonate, polyarylate, polyetherimide, or polyethersulfone.
  • the pattern area 02 It also covers the side of the first conductive terminal 10 that is in contact with the base substrate 100.
  • the wiring is completely covered by the pattern area 02 of the insulating protection layer 300, which can completely avoid the problem of short circuit in the bonding area caused by warpage of the bonding area CC of the base substrate 100 during crimping.
  • the plurality of first conductive terminals 10 are divided into a first group of first conductive terminals A1 and a second group of first conductive terminals A2,
  • the second group of first conductive terminals A2 are located on the side of the first group of first conductive terminals A1 close to the display area AA;
  • the pattern area 02 in FIG. 3 at least covers the first group of first conductive terminals in FIG. The gap between the first conductive terminals 10 in the terminal A1.
  • the base substrate is a flexible base substrate, during crimping, the corresponding base substrate at each position of the binding area may be deformed. Therefore, in the above-mentioned display provided by the embodiment of the present disclosure, the corresponding base substrate may be deformed.
  • the pattern area 02 shown in FIG. 3 further includes covering the gaps between the first conductive terminals 10 in the second group of first conductive terminals A2 shown in FIG. 1.
  • the pattern area 02 shown in FIG. 3 also covers the first group of the first group shown in FIG. A gap between a conductive terminal A1 and the second group of first conductive terminals A2.
  • the gaps between all the first conductive terminals 10 in the bonding area CC are provided with an insulating protective layer 300, which can effectively avoid bonding caused by warping of the bonding area CC of the base substrate 100 during crimping. There is a short circuit problem in the area.
  • the material of the insulating protective layer is not specifically limited, and it may be an organic material or an inorganic material. Generally, any material with an insulating function can be used to make the insulating protective layer in the present disclosure.
  • the insulating protection layer may be formed of resin, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof.
  • the insulating protective layer can be produced at the same time as the existing film layer of the display substrate itself, or can be produced separately in the binding area, which is not specifically limited.
  • the display substrate provided by the embodiment of the present disclosure may be a display substrate or a display panel.
  • the display substrate provided by the embodiment of the present disclosure may also adopt the COF binding method.
  • the insulating protective layer provided in the binding area of the display substrate provided by the present disclosure is also applicable to the binding method using COF.
  • the IC is fabricated on the flexible circuit board, and then the flexible circuit board bound with the IC is pressed on the base substrate.
  • the position where the COF is crimped with the base substrate has a third conductive terminal.
  • the display area AA generally includes a plurality of sub-pixels, and each sub-pixel includes a pixel driving circuit located on the base substrate 100, and the pixel driving is generally It includes a transistor located on a base substrate 100.
  • the transistor includes an active layer 401, a gate insulating layer 402, a gate layer 403, an interlayer insulating layer 404, and a source-drain layer (source 405 , Drain 406)
  • the display area AA also includes at least one flat layer 500 located on the side of the pixel driving circuit (transistor 400) away from the base substrate 100 (this disclosure takes one flat layer 500 as an example, of course, two flat layers 500 can also be provided.
  • the flat layer 500 has a flat surface and a via hole V; it also includes a pixel definition layer 600 defining a plurality of sub-pixels on the flat layer 500, and each sub-pixel also includes a light-emitting element electrically connected to a transistor, which emits light
  • the element includes an anode 1, a light-emitting layer 2 and a cathode 3 that are stacked, and the anode 1 is electrically connected to the drain 406 of the transistor through a via hole V penetrating the planarization layer 500.
  • the insulating protection layer 300 of the binding area CC in the present disclosure may be provided in the same layer as the flat layer 500 located in the display area AA. .
  • the pattern of the insulating protective layer 300 and the flat layer 500 can be formed by one patterning process, without adding a separate manufacturing process of the insulating protective layer 300, which can simplify the manufacturing process Process, save production cost and improve production efficiency.
  • FIG. 8 in the embodiment of the present disclosure is illustrated by including one flat layer as an example. Of course, in specific implementation, it may also include two or even multiple flat layers. In the case of multiple flat layers or even multiple flat layers, the insulating protection layer can be provided in the same layer as any one of the flat layers.
  • the insulating protective layer 300 since the insulating protective layer 300 needs to expose the first conductive terminals 10, ideally, all the first conductive terminals 10 are exposed. , But in order to completely cover the wiring 101, the insulating protective layer 300 generally covers the edge of the first conductive terminal 10. Therefore, when the IC is crimped with the first conductive terminal 10, in order to make the IC and the first conductive terminal 10 effective For electrical connection, the thickness of the insulating protection layer 300 should not be too thick, otherwise the IC and the first conductive terminal 10 may not be electrically connected due to the thick insulating protection layer 300 between them.
  • the insulating protection layer 300 in the present disclosure The thickness of may be half of the thickness of the flat layer 500.
  • the thickness of the insulating protection layer 300 being half of the thickness of the flat layer 500 can also reduce the weight of the display substrate. Specifically, during production, a flat layer 500 is formed in the display area through a patterning process, and a flat layer is formed in the bonding area CC, and then a half-tone process can be used to perform the flat layer in the bonding area CC.
  • the thickness of the insulating protection layer 300 is half the thickness of the flat layer 500, which does not mean that the thickness of the insulating protection layer 300 can only be half the thickness of the flat layer 500.
  • the thickness of the insulating protection layer 300 should be designed according to actual needs. It can also be a little thinner or a little thicker than half of the thickness of the flat layer 500, both of which belong to the protection scope of the present disclosure.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may be a display substrate in a liquid crystal display device, or may be a display substrate in an organic electroluminescence display device.
  • the display substrate provided by the embodiment of the present disclosure is a display substrate in an organic electroluminescence display device
  • the light-emitting device after the light-emitting device is formed by vapor deposition on the display substrate, in order to prevent external moisture from affecting the performance of the light-emitting device, the light-emitting device will be affected.
  • the device is packaged. Therefore, in the above-mentioned display substrate provided by the embodiments of the present disclosure, it further includes an encapsulation layer covering the display area.
  • the encapsulation layer may include one layer, or may include two or more layers.
  • the insulation protection layer and the encapsulation layer One of the layers is set on the same layer.
  • the insulating protection layer and one of the encapsulation layers are arranged in the same layer, when one of the insulating protection layer and the encapsulation layer is made, it is only necessary to change the original pattern when forming one of the encapsulation layers ,
  • the pattern of one of the insulating protection layer and the encapsulation layer can be formed by one patterning process, without adding a separate process for preparing the insulating protection layer, which simplifies the preparation process, saves production costs, and improves production efficiency.
  • the encapsulation layer covering the display area may include a first inorganic layer 701, an organic layer 702, and a second inorganic layer 703 that are sequentially stacked on top of the light emitting device.
  • the insulating protective layer 300 in FIG. It may be provided in the same layer as the first inorganic layer 701, or the insulating protective layer 300 in FIG. 3 may be provided in the same layer as the organic layer 702, or the insulating protective layer 300 in FIG. 3 may also be provided in the same layer as the second inorganic layer 703.
  • the insulation protection layer and one of the first inorganic layer, the organic layer, and the second inorganic layer are provided in the same layer, in order to enable the IC to be electrically connected to the first conductive terminal effectively and to reduce the weight of the display substrate, the insulation protection
  • the thickness of the layer may be half of the thickness of one of the first inorganic layer, the organic layer, and the second inorganic layer.
  • the materials of the first inorganic layer 701 and the second inorganic layer 703 are not specifically limited, as long as they are inorganic materials.
  • the material of the first inorganic layer 701 and the second inorganic layer 703 may be at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the material of the first inorganic layer 701 and the material of the second inorganic layer 703 may be the same or different.
  • the metal signal line may be a data line
  • the first conductive terminal may be provided in the same layer as the data line.
  • the metal signal line may be a data line
  • the first conductive terminal may be provided in the same layer as the data line.
  • the metal signal line may be a gate line
  • the first conductive terminal may be provided in the same layer as the gate line.
  • the pattern of the first conductive terminal and the gate line can be formed by a patterning process. There is no need to increase the process of preparing the first conductive terminal separately, which can simplify the manufacturing process and save Production cost, improve production efficiency.
  • the hollow area 01 and the first conductive terminal 10 may correspond one to one.
  • one hollow area 01 can also correspond to multiple first conductive terminals 10, which can be set according to actual needs.
  • the embodiment of the present disclosure provides a method for preparing a display substrate. Since the principle of the method for solving the problem is similar to the principle of solving the problem for the above-mentioned display substrate, the embodiment of the present disclosure provides the implementation of the method for preparing the display substrate. Reference may be made to the implementation of the above-mentioned display substrate provided in the embodiments of the present disclosure, and the repetitive parts will not be repeated.
  • the manufacturing method of the display substrate of the embodiment of the present disclosure includes the following steps:
  • an insulating protection layer having a plurality of hollow areas and pattern areas on the side of the conductive layer away from the base substrate; wherein the hollow areas cover the first conductive terminals, and the pattern areas cover the gaps between the plurality of first conductive terminals.
  • the method further includes: forming at least one flat layer disposed in the display area; and forming the insulating protective layer and the flat layer through a single patterning process.
  • the manufacturing method of the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes: forming an encapsulation layer covering the display area; and forming one of the insulating protective layer and the encapsulation layer through a single patterning process.
  • the patterning process involved in forming each layer structure may not only include deposition, photoresist coating, mask masking, exposure, development, etching, Part or all of the process, such as photoresist stripping, may also include other processes, and the details are subject to the pattern formed in the actual manufacturing process, which is not limited here.
  • a post-baking process may also be included after development and before etching.
  • the deposition process can be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which is not limited here;
  • the mask used in the mask process can be a half-tone mask (Half Tone Mask). ), Modifide Single Mask, Single Slit Mask or Gray Tone Mask, which are not limited here;
  • the etching can be dry etching or wet The method of etching is not limited here.
  • the preparation process of the display substrate shown in FIG. 3 and FIG. 8 will be described in detail below, and the insulating protection layer 300 of the display substrate shown in FIG.
  • the same layer arrangement of the flat layer 500 is taken as an example.
  • the preparation process of the display substrate shown in FIG. 3 and FIG. 8 is as follows:
  • a base substrate 100 such as a flexible substrate made of polyimide (PI); deposit an oxide layer on the display area AA of the base substrate 100, and pattern the oxide layer to form the active layer 401;
  • a gate insulating layer 402 is deposited on the source layer 401;
  • a metal material is deposited on the gate insulating layer 402, and the metal material film is patterned to form a gate 403;
  • an interlayer insulating layer 404 is deposited on the gate 403; on the interlayer insulating layer
  • a source-drain layer including a source electrode 405, a drain electrode 406 and a data line (not shown) is prepared in the display area AA through a patterning process, and a conductive layer 200, the conductive layer 200 and the source-drain layer are formed in the bonding area CC It is arranged in the same layer (the conductive layer 200 can also be made when the gate 403 is made), wherein the conductive layer 200 includes a plurality of first conductive terminals 10 and wires 101
  • An organic material film layer is deposited on the transistors in the display area AA and on the bonding area CC of the base substrate 100, and the organic material film layer is patterned, and a drain connecting the transistor is formed on the organic material film layer located in the display area AA.
  • the organic material film layer located in the binding area CC is exposed and developed by a patterning process to form a plurality of hollow areas 01 and the insulating protection layer 300 whose thickness is half the thickness of the flat layer 500, the orthographic projection of the hollow area 01 on the base substrate 100 covers the orthographic projection of the first conductive terminal 10 on the base substrate 100, and the pattern of the insulating protection layer 300 is The orthographic projection on the base substrate 100 covers the orthographic projection of the wiring 101 on the base substrate 100, as shown in FIG. 11B;
  • the binding area CC also includes a process of crimping the IC and the first conductive terminal 10.
  • the crimping of the IC and the first conductive terminal 10 please refer to the above-mentioned embodiment of the display substrate.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display substrate provided by the embodiments of the present disclosure.
  • the principle of solving the problems of the display device is similar to that of the aforementioned display substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display substrate, and the repetitive points will not be repeated here.
  • the IC may be bound on the display substrate in a binding manner of COP.
  • the display device further includes a chip IC.
  • the IC includes a plurality of second conductive terminals 20; the second conductive terminals 20 are crimped with the first conductive terminals 10 of the display substrate.
  • the second conductive terminal 20 of the chip IC is crimped with the first conductive terminal 10 of the display substrate. Since the first conductive terminal 10 is electrically connected to the signal line of the display area, the signal on the chip IC can be input to the signal line. Or the signal on the signal line can be input to the chip IC.
  • the second conductive terminal 20 of the chip IC passes through the hollow area 01 of the insulating protective layer 300 in the display substrate and the second conductive terminal on the base substrate 100.
  • a conductive terminal 10 is crimped.
  • the orthographic projection of the second conductive terminal 20 on the base substrate 100 should be located in the hollow area 01 of the insulating protective layer 300. Within the orthographic projection range on the base substrate 100, or the orthographic projection of the second conductive terminal 20 on the base substrate 100 overlaps with the orthographic projection of the hollow area 01 of the insulating protective layer 300 on the base substrate 100.
  • the second conductive terminal 20 is preferably on the base substrate 100 in the present disclosure.
  • the orthographic projection of is located within the orthographic projection range of the hollow area 01 of the insulating protective layer 300 on the base substrate 100.
  • the non-display area BB also includes a flexible printed circuit (FPC), which is used to connect the IC to the IC through the wiring 101. connect.
  • FPC flexible printed circuit
  • the IC may be bound on the display substrate in a COF bonding manner.
  • the display device further includes a chip on film, and the chip on film includes a plurality of The third conductive terminal; the third conductive terminal and the first conductive terminal of the display substrate are crimped.
  • the orthographic projection of the third conductive terminal on the base substrate should be located within the orthographic projection range of the hollow area of the insulating protective layer on the base substrate, or the third conductive terminal The orthographic projection of the terminal on the base substrate overlaps the orthographic projection of the hollow area of the insulating protection layer on the base substrate.
  • the orthographic projection of the third conductive terminal on the base substrate is preferably located on the insulating substrate.
  • the hollow area of the protective layer is within the orthographic projection range on the base substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the binding area of the display substrate includes an insulating protective layer on the side of the conductive layer away from the base substrate. Since the insulating protective layer has a hollow area, the hollow area is The orthographic projection on the base substrate covers the orthographic projection of the first conductive terminal on the base substrate, and the orthographic projection of the pattern of the insulating protection layer on the base substrate covers the orthographic projection of the wiring on the base substrate. Therefore, the hollow area of the insulating protection layer in the bonding area exposes the first conductive terminal, and the pattern of the insulating protection layer partially covers the wiring.
  • the COP bonding when the IC is bonded to the first conductive terminal of the bonding area
  • the insulating protective layer covers the wiring, the IC and the display substrate will not be short-circuited. Therefore, the provision of the insulating protective layer can prevent the bonding area from being short-circuited due to warpage of the bonding area of the base substrate during crimping.

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Abstract

本公开实施例公开了一种显示基板、其制备方法及显示装置，其中，显示基板包括：衬底基板，包括显示区域和位于所述显示区域至少一侧的绑定区域；导电层，位于所述衬底基板之上，且位于所述绑定区域，所述导电层包括多个第一导电端子；绝缘保护层，位于所述导电层背离所述衬底基板的一侧，所述绝缘保护层具有镂空区域和图案区域，所述镂空区域覆盖所述第一导电端子，所述图案区域覆盖所述多个第一导电端子之间的间隙。

Description

显示基板、其制备方法及显示装置
相关申请的交叉引用
本申请要求在2020年03月23日提交中国专利局、申请号为202010209248.4、申请名称为“显示基板、其制备方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及显示基板、其制备方法及显示装置。
背景技术
随着显示技术的不断发展，柔性显示装置由于具有良好的抗冲击性、轻薄等优点而在电子设备中得到了越来越广泛的应用。
发明内容
本公开实施例提供的显示基板，包括：
衬底基板，包括显示区域和位于所述显示区域至少一侧的绑定区域；
导电层，位于所述衬底基板之上，且位于所述绑定区域，所述导电层包括多个第一导电端子；
绝缘保护层，位于所述导电层背离所述衬底基板的一侧，所述绝缘保护层具有镂空区域和图案区域，所述镂空区域覆盖所述第一导电端子，所述图案区域覆盖所述多个第一导电端子之间的间隙。
可选地，在本公开实施例提供的上述显示基板中，所述导电层还包括：与所述多个第一导电端子电连接的多条走线，所述多条走线与位于所述显示区域的金属信号线电连接；所述图案区域覆盖所述多条走线。
可选地，在本公开实施例提供的上述显示基板中，所述图案区域还覆盖所述第一导电端子中与所述衬底基板接触的侧边。
可选地，在本公开实施例提供的上述显示基板中，所述多个第一导电端子被划分为第一组第一导电端子和第二组第一导电端子，所述第二组第一导电端子位于所述第一组第一导电端子靠近所述显示区域的一侧；
所述图案区域至少覆盖所述第一组第一导电端子中各第一导电端子之间的间隙。
可选地，在本公开实施例提供的上述显示基板中，所述图案区域还包括覆盖所述第二组第一导电端子中各第一导电端子之间的间隙。
可选地，在本公开实施例提供的上述显示基板中，所述图案区域还覆盖所述第一组第一导电端子和所述第二组第一导电端子之间的间隙。
可选地，在本公开实施例提供的上述显示基板中，所述绝缘保护层的材料为有机材料或无机材料。
可选地，在本公开实施例提供的上述显示基板中，所述显示区域还包括：
像素驱动电路，位于所述衬底基板之上；
至少一层平坦层，位于所述像素驱动电路远离所述衬底基板的一侧，所述平坦层具有平坦表面以及过孔；
发光元件，位于所述平坦表面上且通过所述过孔与所述像素驱动电路电连接；
其中，所述绝缘保护层与所述平坦层同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述绝缘保护层的厚度为所述平坦层厚度的一半。
可选地，在本公开实施例提供的上述显示基板中，还包括覆盖所述显示区域的封装层，所述绝缘保护层与所述封装层中的其中一层同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述封装层包括依次层叠设置的第一无机层、有机层和第二无机层，所述绝缘保护层与所述第一无机层、所述有机层、所述第二无机层其中一层同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述金属信号线为数据线，所述第一导电端子与所述数据线同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述金属信号线为栅线，所述第一导电端子与所述栅线同层设置。
基于同一发明构思，本公开实施例还提供了显示装置，包括上述显示基板。
可选地，在本公开实施例提供的上述显示装置中，还包括芯片，所述芯片包括多个第二导电端子；所述第二导电端子和所述显示基板的第一导电端子压接。
可选地，在本公开实施例提供的上述显示装置中，所述第二导电端子在所述衬底基板上的正投影位于所述绝缘保护层的镂空区域在所述衬底基板上的正投影范围内。
可选地，在本公开实施例提供的上述显示装置中，还包括覆晶薄膜，所述覆晶薄膜包括多个第三导电端子；所述第三导电端子和所述显示基板的第一导电端子压接。
基于同一发明构思，本公开实施例还提供了显示基板的制备方法，包括：
在衬底基板的绑定区域形成包括多个第一导电端子的导电层；
在所述导电层背离所述衬底基板一侧形成具有多个镂空区域和图案区域的绝缘保护层；其中，所述镂空区域覆盖所述第一导电端子，所述图案区域覆盖所述多个第一导电端子之间的间隙。
附图说明
图1为本公开实施例提供的显示基板区域划分的俯视结构示意图；
图2为本公开实施例提供的显示基板绑定区域的俯视结构示意图；
图3为图2沿AA’方向上的剖视结构示意图；
图4为相关技术中显示基板的绑定区域在压接前的结构示意图；
图5为相关技术中显示基板的绑定区域在压接后的结构示意图；
图6为本公开实施例提供的显示基板的绑定区域在压接前的结构示意图；
图7为本公开实施例提供的显示基板的绑定区域在压接后的结构示意图；
图8为本公开实施例提供的显示基板的显示区域的结构示意图；
图9为本公开实施例提供的显示基板的覆盖显示区域的封装层结构示意图；
图10为本公开实施例提供的显示基板的制备方法的流程图；
图11A和图11B为本公开实施例提供的制备方法中在执行每一步骤之后的剖视结构示意图；
图12为本公开实施例提供的显示装置的俯视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
相关技术中柔性显示装置中的集成电路(Integrated Circuit，IC)一般采用覆晶薄膜(Chip On Film，COF)绑定的方式进行绑定，即先将IC绑定(bonding)在柔性线路板上，再将绑定有IC的柔性线路板压合在显示面板上，由于柔性线路板为软性材质，因此IC压合时不会造成显示面板的阵列(Array)基板的线路断裂，但是由于COF成本较高，且COF的线路不能做的太细，因而COF不能在高分辨率的产品上使用。基于此，利用直接在显示面板上绑定IC(Chip On Plastic，COP)的方式成为今后发展的方向。
柔性显示装置因为采用柔性基底所以可以弯折为弯曲等形态，但事物都有两面性，柔性基底的这个优势也成为它的劣势，如受力容易形变。在将COF或IC绑定到柔性基底上时，柔性基底在绑定时由于受力会发生弯折形变，导致柔性基底与COF或IC发生短路(short)。
本公开实施例提供的一种显示基板，如图1所示，可以包括：衬底基板100，衬底基板100包括显示区域AA和包围显示区域AA的非显示区域BB，至少位于显示区域AA一侧的非显示区域BB包括绑定区域CC，一般将非显示区域BB中用于绑定IC的区域称为绑定区域CC，绑定区域CC设置有多个第一导电端子10，以COP绑定方式为例，第一导电端子10用于与IC上的第二导电端子(后面介绍)压接以实现IC与第一导电端子10电连接。具体地，如图2所示，衬底基板100的绑定区域CC设置有导电层200，位于绑定区域CC的导电层200包括多个第一导电端子10以及与第一导电端子10电连接的多条走线101，例如当IC与显示基板压接时，IC上的第二导电端子20会与显示基板上的第一导电端子10电连接在一起，以将IC上的信号输入至第一导电端子10或将第一导电端子10上的信号输出至IC上；位于绑定区域CC的走线101与显示区域AA的金属信号线(如栅线、数据线等)电连接，这样显示区域AA的金属信号线上的信号便可以输入至第一导电端子10，或者第一导电端子10上的信号可以输入至显示区域AA的金属信号线上。
具体地，本公开实施例提供的上述显示基板，如图3所示，图3为图2中沿AA’方向的剖视图，该显示基板的绑定区域CC包括位于衬底基板100 上的导电层200，导电层200包括多个第一导电端子10以及与第一导电端子10电连接的多条走线101，图3中左侧示意的走线101用于与显示区域的金属信号线(如栅线、数据线等)电连接，图3中右侧示意的走线101用于与柔性印刷电路板(Flexible Printed Circuit，FPC)电连接。
相关技术中，如图4和图5所示，图4为IC与显示基板压接前的结构示意图，图5为IC与显示基板压接后的结构示意图，当IC与显示基板进行绑定的时候，需要施加一定大的压力来保证绑定效果，但是该压力会导致衬底基板发生翘曲，导致如图5所示的翘曲，从而导致IC与走线101发生短路或碰触，进而影响信号传输而导致显示不良。
因此，本公开实施例提供的上述显示基板，如图3所示，绑定区域CC还包括位于导电层200背离衬底基板100一侧的绝缘保护层300，绝缘保护层300具有多个镂空区域01和图案区域02，镂空区域01覆盖第一导电端子10，图案区域02覆盖多个第一导电端子10之间的间隙。这样，绑定区域CC的绝缘保护层300具有的镂空区域01露出了第一导电端子10，由于走线101位于多个第一导电端子10之间的间隙处，因此绝缘保护层300的图案区域02覆盖住位于多个第一导电端子10之间间隙处的走线101，如图6和图7所示，图6为本公开中IC与显示基板压接前的结构示意图，图7为本公开中IC与显示基板压接后的结构示意图，当IC与显示基板压接时，即使衬底基板100在绑定时由于受力发生弯折形变(如图7中的翘曲现象)，由于绝缘保护层300的图案区域02覆盖住走线101，因此衬底基板100上的走线101与COF或IC不会发生短路(short)。
在本公开实施例提供的上述显示基板中，该显示基板的绑定区域CC包括位于导电层200背离衬底基板100的一侧绝缘保护层300，由于绝缘保护层300具有镂空区域01和图案区域02，镂空区域01覆盖第一导电端子10，图案区域02覆盖位于多个第一导电端子10之间间隙处的走线101。因此位于绑定区域CC绝缘保护层300的镂空区域01露出了第一导电端子10，图案区域02覆盖住了走线101，当本公开采用COP绑定时，当IC与绑定区域CC的第 一导电端子10压接以将IC上的第二导电端子与第一导电端子10电连接时，即使衬底基板100两侧发生翘曲，由于绝缘保护层300的图案区域02覆盖住了走线101，因此IC与显示基板不会发生短路。因此，绝缘保护层300的设置可以防止由于衬底基板100的绑定区域CC在压接时发生翘曲等导致的绑定区域发生短路的问题。
需要说明的是，本公开提供的衬底基板为柔性衬底基板，对于柔性衬底基板的材料不做具体限定，例如可以为聚酰亚胺、聚乙烯醚邻苯二甲酸酯、聚萘二甲酸乙二醇酯、聚碳酸酯、多芳基化合物、聚醚酰亚胺或聚醚砜等具有优良的耐热性和耐久性的塑料基板。
可选地，由于走线一般与第一导电端子的侧边电连接，为了尽可能的完全覆盖住走线，在本公开实施例提供的上述显示基板中，如图3所示，图案区域02还覆盖第一导电端子10中与衬底基板100接触的侧边。这样走线被绝缘保护层300的图案区域02完全覆盖，这样可以完全避免由于衬底基板100的绑定区域CC在压接时发生翘曲等导致的绑定区域发生短路的问题。
可选地，在本公开实施例提供的上述显示基板中，如图1所示，多个第一导电端子10被划分为第一组第一导电端子A1和第二组第一导电端子A2，第二组第一导电端子A2位于第一组第一导电端子A1靠近显示区域AA的一侧；
由于第一组第一导电端子A1位于远离显示区域AA的外侧区域，在压接时该外侧区域最容易发生翘曲，因此图3中的图案区域02至少覆盖图1中第一组第一导电端子A1中各第一导电端子10之间的间隙。
可选地，由于，衬底基板是柔性衬底基板，在压接时，绑定区域的每一位置处对应的衬底基板均有可能发生变形，因此，在本公开实施例提供的上述显示基板中，图3所示的图案区域02还包括覆盖图1中所示的第二组第一导电端子A2中各第一导电端子10之间的间隙。
可选地，为了进一步避免绑定区域不会发生任何的短路问题，在本公开实施例提供的上述显示基板中，图3所示的图案区域02还覆盖图1中所示的 第一组第一导电端子A1和第二组第一导电端子A2之间的间隙。这样绑定区域CC中所有第一导电端子10之间的间隙均设置有绝缘保护层300，从而可以有效避免由于衬底基板100的绑定区域CC在压接时发生翘曲等导致的绑定区域发生短路的问题。
可选地，在本公开实施例提供的上述显示基板中，对绝缘保护层的材料不做具体限定，可以为有机材料，也可以为无机材料。一般只要是具有绝缘作用的材料均可以用于制作本公开中的绝缘保护层。
可选地，绝缘保护层可以由树脂、氧化硅、氮化硅、氮氧化硅、其他合适的材料、或其组合来形成。
可选地，绝缘保护层可以与显示基板本身就有的膜层同时制作，也可以是单独在绑定区域制作，不进行具体限定。
具体地，本公开实施例提供的显示基板可以是一个显示基板，也可以是一个显示面板。
可选地，本公开实施例提供的显示基板也可以采用COF绑定方式，本公开提供的显示基板的绑定区域设置的绝缘保护层同样适用于采用COF的绑定方式，当本公开采用COF绑定时，IC制作在柔性线路板上，再将绑定有IC的柔性线路板压合在衬底基板上，COF上与衬底基板压接的位置具有第三导电端子，当COF的第三导电端子与绑定区域CC的第一导电端子压接以将COF的第三导电端子与第一导电端子电连接时，即使衬底基板发生翘曲或由于对位不准导致第三导电端子压到走线时，由于绝缘保护层300覆盖住了走线101，因此COF与显示基板的走线101也不会发生短路。
可选地，在本公开实施例提供的上述显示基板中，如图8所示，显示区域AA一般包括多个子像素，每个子像素包括位于衬底基板100上的像素驱动电路，该像素驱动一般包括位于衬底基板100上的晶体管，该晶体管包括位于衬底基板100上依次设置的有源层401、栅绝缘层402、栅极层403、层间绝缘层404和源漏层(源极405、漏极406)，显示区域AA还包括位于像素驱动电路(晶体管400)背离衬底基板100一侧的至少一层平坦层500(本 公开以一层平坦层500为例，当然也可以设置两层或多层平坦层)，平坦层500具有平坦表面以及过孔V；还包括位于平坦层500上限定多个子像素的像素定义层600，每个子像素还包括与晶体管电连接的发光元件，发光元件包括层叠设置的阳极1、发光层2和阴极3，阳极1通过贯穿平坦层500的过孔V与晶体管的漏极406电连接。
可选地，在本公开实施例提供的上述显示基板中，如图3和图8所示，本公开中绑定区域CC的绝缘保护层300可以与位于显示区域AA的平坦层500同层设置。这样，只需要在形成平坦层500时改变原有的构图图形，即可通过一次构图工艺形成绝缘保护层300与平坦层500的图形，不用增加单独制备绝缘保护层300的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
需要说明的是，本公开实施例中图8所示的结构中是以包括一层平坦层为例进行说明的，当然在具体实施时，也可以包括两层甚至多层平坦层，当包括两层甚至多层平坦层时，绝缘保护层可以与其中任意一层平坦层同层设置。
可选地，在本公开实施例提供的上述显示基板中，如图3和图8所示，由于绝缘保护层300需要露出第一导电端子10，理想情况下是将第一导电端子10全部露出，但是为了完全覆盖住走线101，绝缘保护层300一般会覆盖第一导电端子10的边缘部分，因此在IC与第一导电端子10压接时，为了能够使IC与第一导电端子10有效电连接，绝缘保护层300的厚度不宜过厚，否则IC与第一导电端子10由于较厚的绝缘保护层300可能导致二者之间存在间隙为无法电连接，因此本公开中绝缘保护层300的厚度可以为平坦层500厚度的一半。另外，绝缘保护层300的厚度为平坦层500厚度的一半还可以降低显示基板的重量。具体地，在制作时，通过一次构图工艺在显示区域形成平坦层500，以及在绑定区域CC形成平坦层，然后可以利用半掩膜(Half-tone)工艺对绑定区域CC的平坦层进行光刻，绑定区域CC的平坦层中对应第一导电端子10的部分全曝光，对应走线101的部分曝光50％，从而 形成厚度为显示区域平坦层500厚度一半的绝缘保护层300。
需要说明的是，绝缘保护层300的厚度为平坦层500厚度的一半，不代表绝缘保护层300的厚度仅可以为平坦层500厚度的一半，当然根据实际需要进行设计绝缘保护层300的厚度，还可以比平坦层500厚度的一半稍薄一点或者稍厚一点，均属于本公开的保护范围。
具体地，本公开实施例提供的上述显示基板可以是液晶显示装置中的显示基板，也可以是有机电致发光显示装置中的显示基板。
具体地，当本公开实施例提供的显示基板为有机电致发光显示装置中的显示基板时，在显示基板上蒸镀形成发光器件之后，为了防止外界水汽影响发光器件的性能，还会对发光器件进行封装。因此，在本公开实施例提供的上述显示基板中，还包括覆盖显示区域的封装层，封装层可以包括一层，也可以包括两层或两层以上的多层，绝缘保护层与封装层中的其中一层同层设置。由于绝缘保护层与封装层中的其中一层同层设置，因此绝缘保护层和封装层中的其中一层在制作时，只需要在形成封装层中的其中一层时改变原有的构图图形，即可通过一次构图工艺形成绝缘保护层与封装层中的其中一层的图形，不用增加单独制备绝缘保护层的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
具体地，如图9所示，覆盖显示区域的封装层可以包括位于发光器件之上依次层叠设置的第一无机层701、有机层702和第二无机层703，图3中的绝缘保护层300可以与第一无机层701同层设置，或者图3中的绝缘保护层300可以与有机层702同层设置，或者图3中的绝缘保护层300也可以与第二无机层703同层设置。
具体地，当绝缘保护层与第一无机层、有机层、第二无机层其中之一层同层设置时，为了能够使IC与第一导电端子有效电连接以及降低显示基板的重量，绝缘保护层的厚度可以为第一无机层、有机层、第二无机层其中之一层厚度的一半。
可选地，对于第一无机层701和第二无机层703的材料不做具体限定， 只要是无机材料均可。具体地，第一无机层701和第二无机层703的材料可以为氮化硅、氧化硅或氮氧化硅中的至少一种。第一无机层701的材料和第二无机层703的材料可以相同，也可以不相同。
可选地，在本公开实施例提供的上述显示基板中，金属信号线可以为数据线，第一导电端子可以采用与数据线同层设置。这样只需要在形成数据线时改变原有的构图图形，即可通过一次构图工艺形成第一导电端子与数据线的图形，不用增加单独制备第一导电端子的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
可选地，在本公开实施例提供的上述显示基板中，金属信号线可以为栅线，第一导电端子可以采用与栅线同层设置。这样只需要在形成栅线时改变原有的构图图形，即可通过一次构图工艺形成第一导电端子与栅线的图形，不用增加单独制备第一导电端子的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
可选地，在本公开实施例提供的上述显示基板中，如图3所示，镂空区域01与第一导电端子10可以一一对应。当然，也可以一个镂空区域01对应多个第一导电端子10，根据实际需要进行设定。
基于同一发明构思，本公开实施例提供了一种显示基板的制备方法，由于该制备方法解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该制备方法的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
具体地，本公开实施例的显示基板的制备方法，如图10所示，包括以下步骤：
S101、在衬底基板的绑定区域形成包括多个第一导电端子的导电层；
S102、在导电层背离衬底基板一侧形成具有多个镂空区域和图案区域的绝缘保护层；其中，镂空区域覆盖第一导电端子，图案区域覆盖多个第一导电端子之间的间隙。
可选地，在本公开实施例提供的上述显示基板的制备方法中，还包括： 形成设置在显示区域的至少一层平坦层；通过一次构图工艺形成绝缘保护层和平坦层。
可选地，在本公开实施例提供的上述显示基板的制备方法中，还包括：形成覆盖显示区域的封装层；通过一次构图工艺形成绝缘保护层和封装层中的其中之一膜层。
需要说明的是，在本公开实施例提供的上述制备方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、半透掩膜板(Modifide Single Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
为更好地理解本公开的技术方案，以下将对图3和图8所示显示基板的制备过程进行详细说明，且以图3所示显示基板的绝缘保护层300与位于图8中显示区域的平坦层500同层设置为例。
具体地，图3和图8所示显示基板的制备过程如下：
提供一衬底基板100，例如材料为聚酰亚胺(PI)的柔性基板；在衬底基板100的显示区域AA沉积氧化物层，并对氧化物层进行构图形成有源层401；在有源层401上沉积栅绝缘层402；在栅绝缘层402上沉积金属材料，并对金属材料膜层进行构图形成栅极403；在栅极403上沉积层间绝缘层404；在层间绝缘层404上通过一次构图工艺在显示区域AA制备包括源极405、漏极406和数据线(未示出)的源漏层，以及在绑定区域CC形成导电层200，导电层200与源漏层同层设置(也可以在制作栅极403时制作导电层200)，其中导电层200包括多个第一导电端子10以及与第一导电端子10电连接的走线101，至此完成 显示区域AA晶体管的制备以及完成绑定区域导电层200的制备，如图11A所示；
在显示区域AA的晶体管之上和在衬底基板100的绑定区域CC沉积有机材料膜层，对有机材料膜层进行图形化，在位于显示区域AA的有机材料膜层上形成连接晶体管的漏极406与后续制作的发光器件的阳极1的过孔，以在显示区域AA形成平坦层500，同时采用构图工艺对位于绑定区域CC的有机材料膜层进行曝光显影，形成具有多个镂空区域01且厚度为平坦层500厚度一半的绝缘保护层300，镂空区域01在衬底基板100上的正投影覆盖第一导电端子10在衬底基板100上的正投影，绝缘保护层300的图案在衬底基板100上的正投影覆盖走线101在衬底基板100上的正投影覆，如图11B所示；
至此，完成了图3和图8所示显示基板的制备。
具体地，在图11B之后还包括制作阳极1、像素定义层600、发光层2、阴极3、封装层等，这些膜层与相关技术中的制备方法相同，在此不做详述。绑定区域CC还包括将IC与第一导电端子10压接过程，IC与第一导电端子10压接的描述可以参见上述显示基板的实施例。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示基板。该显示装置解决问题的原理与前述显示基板相似，因此该显示装置的实施可以参见前述显示基板的实施，重复之处在此不再赘述。
可选地，在本公开实施例提供的上述显示装置中，可以采用COP的绑定方式将IC绑定在显示基板上，具体地，如图6所示，该显示装置还包括芯片IC，芯片IC包括多个第二导电端子20；第二导电端子20和显示基板的第一导电端子10压接。具体地，芯片IC的第二导电端子20与显示基板的第一导电端子10压接，由于第一导电端子10与显示区域的信号线电连接，这样芯片IC上的信号便可以输入至信号线或者信号线上的信号可以输入至芯片IC。
可选地，在本公开实施例提供的上述显示装置中，如图6所示，芯片IC的第二导电端子20通过显示基板中绝缘保护层300的镂空区域01与衬底基板100上的第一导电端子10压接，为了确保第二导电端子20与第一导电端 子10电连接，因此第二导电端子20在衬底基板100上的正投影应该位于绝缘保护层300的镂空区域01在衬底基板100上的正投影范围内，或者第二导电端子20在衬底基板100上的正投影与绝缘保护层300的镂空区域01在衬底基板100上的正投影重叠。在芯片IC与显示基板压接时，为了便于芯片IC上的第二导电端子20与衬底基板100上的第一导电端子10电连接，本公开优选第二导电端子20在衬底基板100上的正投影位于绝缘保护层300的镂空区域01在衬底基板100上的正投影范围内。
需要说明的是，如图12所示，显示装置中IC与显示基板压接后，非显示区域BB还包括柔性印刷电路板(Flexible Printed Circuit，FPC)，FPC用于通过走线101与IC电连接。
可选地，在本公开实施例提供的上述显示装置中，可以采用COF的绑定方式将IC绑定在显示基板上，具体地，该显示装置还包括覆晶薄膜，覆晶薄膜包括多个第三导电端子；第三导电端子和显示基板的第一导电端子压接。为了确保第三导电端子与第一导电端子电连接，因此第三导电端子在衬底基板上的正投影应该位于绝缘保护层的镂空区域在衬底基板上的正投影范围内，或者第三导电端子在衬底基板上的正投影与绝缘保护层的镂空区域在衬底基板上的正投影重叠。在芯片IC与显示基板压接时，为了便于芯片IC上的第三导电端子与衬底基板上的第一导电端子电连接，本公开优选第三导电端子在衬底基板上的正投影位于绝缘保护层的镂空区域在衬底基板上的正投影范围内。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的上述显示基板、其制备方法及显示装置，该显示基板的绑定区域包括位于导电层背离衬底基板的一侧绝缘保护层，由于绝缘保护层具有镂空区域，镂空区域在衬底基板上的正投影覆盖第一导电端子在衬 底基板上的正投影，绝缘保护层的图案在衬底基板上的正投影覆盖走线在衬底基板上的正投影。因此位于绑定区域绝缘保护层的镂空区域露出了第一导电端子，绝缘保护层的图案部分覆盖住了走线，当本公开采用COP绑定时，当IC与绑定区域的第一导电端子压接以将IC上的第二导电端子与第一导电端子电连接时，即使衬底基板两侧发生翘曲，由于绝缘保护层覆盖住了走线，因此IC与显示基板不会发生短路。因此，绝缘保护层的设置可以防止由于衬底基板的绑定区域在压接时发生翘曲等导致的绑定区域发生短路的问题。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种显示基板，其中，包括：
    衬底基板，包括显示区域和位于所述显示区域至少一侧的绑定区域；
    导电层，位于所述衬底基板之上，且位于所述绑定区域，所述导电层包括多个第一导电端子；
    绝缘保护层，位于所述导电层背离所述衬底基板的一侧，所述绝缘保护层具有镂空区域和图案区域，所述镂空区域覆盖所述第一导电端子，所述图案区域覆盖所述多个第一导电端子之间的间隙。
  2. 如权利要求1所述的显示基板，其中，所述导电层还包括：与所述多个第一导电端子电连接的多条走线，所述多条走线与位于所述显示区域的金属信号线电连接；所述图案区域覆盖所述多条走线。
  3. 如权利要求1所述的显示基板，其中，所述图案区域还覆盖所述第一导电端子中与所述衬底基板接触的侧边。
  4. 如权利要求1所述的显示基板，其中，所述多个第一导电端子被划分为第一组第一导电端子和第二组第一导电端子，所述第二组第一导电端子位于所述第一组第一导电端子靠近所述显示区域的一侧；
    所述图案区域至少覆盖所述第一组第一导电端子中各第一导电端子之间的间隙。
  5. 如权利要求4所述的显示基板，其中，所述图案区域还包括覆盖所述第二组第一导电端子中各第一导电端子之间的间隙。
  6. 如权利要求5所述的显示基板，其中，所述图案区域还覆盖所述第一组第一导电端子和所述第二组第一导电端子之间的间隙。
  7. 如权利要求1所述的显示基板，其中，所述绝缘保护层的材料为有机材料或无机材料。
  8. 如权利要求1所述的显示基板，其中，所述显示区域还包括：
    像素驱动电路，位于所述衬底基板之上；
    至少一层平坦层，位于所述像素驱动电路远离所述衬底基板的一侧，所述平坦层具有平坦表面以及过孔；
    发光元件，位于所述平坦表面上且通过所述过孔与所述像素驱动电路电连接；
    其中，所述绝缘保护层与所述平坦层同层设置。
  9. 如权利要求8所述的显示基板，其中，所述绝缘保护层的厚度为所述平坦层厚度的一半。
  10. 如权利要求1所述的显示基板，其中，还包括覆盖所述显示区域的封装层，所述绝缘保护层与所述封装层中的其中一层同层设置。
  11. 如权利要求10所述的显示基板，其中，所述封装层包括依次层叠设置的第一无机层、有机层和第二无机层，所述绝缘保护层与所述第一无机层、所述有机层、所述第二无机层其中一层同层设置。
  12. 如权利要求1所述的显示基板，其中，所述金属信号线为数据线，所述第一导电端子与所述数据线同层设置。
  13. 如权利要求1所述的显示基板，其中，所述金属信号线为栅线，所述第一导电端子与所述栅线同层设置。
  14. 一种显示装置，其中，包括如权利要求1-13任一项所述的显示基板。
  15. 如权利要求14所述的显示装置，其中，还包括芯片，所述芯片包括多个第二导电端子；所述第二导电端子和所述显示基板的第一导电端子压接。
  16. 如权利要求15所述的显示装置，其中，所述第二导电端子在所述衬底基板上的正投影位于所述绝缘保护层的镂空区域在所述衬底基板上的正投影范围内。
  17. 如权利要求14所述的显示装置，其中，还包括覆晶薄膜，所述覆晶薄膜包括多个第三导电端子；所述第三导电端子和所述显示基板的第一导电端子压接。
  18. 一种显示基板的制备方法，其中，包括：
    在衬底基板的绑定区域形成包括多个第一导电端子的导电层；
    在所述导电层背离所述衬底基板一侧形成具有多个镂空区域和图案区域的绝缘保护层；其中，所述镂空区域衬底基板覆盖所述第一导电端子衬底基板，所述图案区域衬底基板覆盖所述多个第一导电端子之间的间隙衬底基板。
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