TWI747914B - 顯示設備 - Google Patents
顯示設備 Download PDFInfo
- Publication number
- TWI747914B TWI747914B TW106121061A TW106121061A TWI747914B TW I747914 B TWI747914 B TW I747914B TW 106121061 A TW106121061 A TW 106121061A TW 106121061 A TW106121061 A TW 106121061A TW I747914 B TWI747914 B TW I747914B
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- Prior art keywords
- conductive layer
- conductive
- layer
- display device
- electrode
- Prior art date
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- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims description 111
- 239000010409 thin film Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 235
- 239000003990 capacitor Substances 0.000 description 23
- 239000000853 adhesive Substances 0.000 description 17
- 230000001070 adhesive effect Effects 0.000 description 17
- 239000010936 titanium Substances 0.000 description 11
- 230000008018 melting Effects 0.000 description 10
- 238000002844 melting Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 238000005452 bending Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- RMPWIIKNWPVWNG-UHFFFAOYSA-N 1,2,3,4-tetrachloro-5-(2,3,4-trichlorophenyl)benzene Chemical compound ClC1=C(Cl)C(Cl)=CC=C1C1=CC(Cl)=C(Cl)C(Cl)=C1Cl RMPWIIKNWPVWNG-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920005570 flexible polymer Polymers 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- -1 molybdenum (Mo) Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- H10K50/00—Organic light-emitting devices
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/129—Chiplets
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/179—Interconnections, e.g. wiring lines or terminals
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
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- H10K77/10—Substrates, e.g. flexible substrates
- H10K77/111—Flexible substrates
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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Abstract
本發明提供了一種顯示設備。該顯示設備包括顯示基板和佈置在顯示基板上方的多個焊盤。多個焊盤中的每一個包括第一導電層,其至少一部分被絕緣膜覆蓋;佈置在第一導電層上方的第二導電層;和形成在第二導電層中的夾持部分。
Description
相關申請案之交互參照
本申請主張於2016年6月24日提出申請的韓國專利申請案10-2016-0079286的權益,其全部內容透過引用併入本文。
一個或多個實施例係與顯示設備相關聯。
顯示設備可應用於諸如智慧型手機、膝上型電腦、數位相機、攝影機、便攜式信息終端機、筆記型電腦和桌上型個人電腦(PC)的移動設備中,或諸如桌上型電腦、電視機、戶外廣告牌以及展示設備的電子設備中。
近來,已推出更薄的顯示設備。
柔性顯示設備易於攜帶並且可應用於具有各種形狀的設備。其中,以有機發光顯示技術為基礎的柔性顯示設備是最強大的柔性顯示設備。
在顯示設備中,顯示面板上的焊盤可電連接到驅動器的焊盤。如果顯示面板上的焊盤和驅動器的焊盤彼此未可靠地連接,則可能劣化顯示設備的可靠性。
一個或多個實施例包含其中焊盤和驅動端子彼此可靠地連接的顯示設備。
其他態樣部分將在下面的描述中闡述,而部分將從描述中變得顯而易見,或者可通過實踐所呈現實施例來了解。
根據一個或多個實施例,顯示設備包括:顯示基板以及佈置在顯示基板上方的多個焊盤,其中多個焊盤中的每一個焊盤包括:至少一部分被絕緣膜覆蓋的第一導電層;佈置在第一導電層上方的多個第二導電層;以及形成在第二導電層中的夾持部分。
第二導電層包括可在第一導電層上方彼此間隔開的多個第二導電層。
絕緣膜可包括暴露第一導電層的頂表面的多個接觸孔,且多個第二導電層可以通過接觸孔電連接到第一導電層。
夾持部分可包括佈置在相鄰的第二導電層的相對側壁上的底切。
第二導電層可包括多層的導電部分,並且底切可以通過將多層的導電部分形成為具有不同的寬度來提供。
第二導電層可包括:連接到第一導電層的第一導電部分;佈置在第一導電部分上方的第二導電部分;以及佈置在第二導電部分上方的第三導電部分,並且底切對應於第二導電部分的寬度可比第一導電部分的寬度和第三導電部分的寬度窄的區域。
第二導電層可包括至少一層的導電部分,底切可對應於第二導電層的側壁傾斜的區域。
第二導電層可包括至少一層的導電部分,底切可對應於第二導電層的側壁彎曲的區域。
顯示設備還可包括佈置在第二導電層上方的第三導電層。
第二導電層可包括至少一層的導電部分,顯示設備還可包括佈置在第二導電層上方的第三導電層,並且底切中的第二導電層的寬度可窄於第三導電層的寬度。
顯示面板可包括:包括半導體主動層、閘極電極、源極電極和汲極電極的至少一個薄膜電晶體在顯示基板上方;電連接到薄膜電晶體的有機發光顯示裝置,有機發光顯示裝置包括第一電極、發光層和第二電極;以及佈置在薄膜電晶體和有機發光顯示設備之間的至少一層的絕緣膜,並且第一導電層可連接到從閘極電極、源極電極、汲極電極、第一電極和第二電極延伸的佈線,並且第二導電層可在第一導電層上方佈置成具有島型。
第一導電層可由與閘極電極相同的材料形成,並且第二導電層可由與源極電極和汲極電極相同的材料形成。
顯示設備還可包括設置在第二導電層上的第三導電層,其中第一至第三導電層可以是選自閘極電極、源極電極、汲極電極、第一電極和第二電極的多個電極的組合。
根據一個或多個實施例,顯示設備包括:包括其中佈置有多個焊墊的顯示基板和佈置在顯示基板上方的薄膜封裝層之顯示面板;包括電連接到多個焊盤的多個驅動端子之驅動器;以及佈置在多個焊盤和驅動器之間的黏合劑,其中多個焊盤中的每一個焊盤包括:至少一部分被絕緣膜覆蓋的第一導電層;佈置在第一導電層上方的多個第二導電層;以及佈置在相鄰的第二導電層之間的夾持部分。
絕緣膜可包括暴露第一導電層的頂表面的多個接觸孔,並且第二導電層可分別通過接觸孔電連接到第一導電層。
夾持部分可包括佈置在相鄰的第二導電層的相對側壁上的底切。
驅動端子可填充相鄰的第二導電層之間的間隙並且接觸佈置有底切的第二導電層的側壁。
驅動端子可延伸超過第一導電層接觸第二導電層接觸的區域並且在相鄰的第二導電層之間延伸。
多個焊盤中的每一個焊盤可與驅動端子表面接觸。黏合劑可包括非導電膜。
根據一個或多個實施例,顯示設備包括:包括其中佈置多個焊墊之顯示基板的顯示面板;以及包括分別電連接到多個焊盤的多個驅動端子之驅動器,其中多個焊盤中的每一個焊盤包括:第一導電層;設置在第一導電層上的絕緣層和設置在絕緣層上並通過形成在絕緣層中的接觸孔連接到第一導電層的第二導電層,並且其中第二導電層包括具有底切的夾持部分並且多個驅動終端中的一個填充底切。
第二導電層可以包括第一導電部分和設置在第一導電部分上的第二導電部分,並且底切可形成在第一導電部分中。
底切可具有從第二導電部分的邊緣凹陷的凹陷部分,並且凹陷部分可為約1μm至約20μm。
夾持部分可形成在第二導電層的中心。
第二導電層可包括設置在第一導電層上的多個第二導電層,並且夾持部分可形成在相鄰的第二導電層之間。
100:顯示設備
110,300:顯示面板
111:有效區域
112:無效區域
113,322:佈線
120,301:顯示基板
130,317:薄膜封裝層
140:功能膜
150,400,401:焊盤
160:驅動器
170:柔性印刷電路板
180,610:驅動積體電路
190,640:驅動端子
210,650:黏合劑
302:阻擋膜
303:半導體主動層
304:源極區
305:汲極區
306:溝道區域
307:閘極絕緣膜
308:閘極電極
309:層間絕緣膜
310:源極電極
311:汲極電極
312:保護膜
313:第一電極
314:中間層
315:第二電極
316:像素限定層
318:第一無機膜
319:第二無機膜
320:有機膜
321:偏振層
331:第一絕緣膜
332:第二絕緣膜
333:第三絕緣膜
410,1010:第一導電層
420,420a,420b,720,720a,720b,820,820a,820b,920,920a,920b,1020:第二導電層
421:第一導電部分
422:第二導電部分
423:第三導電部分
424,724,824,924,1024:夾持部分
425,725,825,925,1025:底切
430:接觸孔
431:第一接觸孔
432:第二接觸孔
620:電路圖案
630:絕緣膜
641:凸塊
642:熔化層
930,1030,1020a,1020b:第三導電層
1101:電介質層
BA:彎曲區域
BL:彎曲線
PA:焊盤區域
DA:顯示區域
CE1:第一電容器電極
CE2:第二電容器電極
W1,W2,W3,W4,W5:寬度
結合附圖,從以下對實施例的描述中,這些和/或其他態樣將變得顯而易見並且更容易理解,其中:
圖1是根據實施例的顯示設備的平面圖。
圖2是圖1的顯示設備的橫截面圖。
圖3是根據實施例的顯示面板的橫截面圖。
圖4是圖3的顯示面板上的焊盤的平面圖。
圖5是沿圖4的線V-V截取的橫截面圖。
圖6A是描繪驅動端子連接到圖5的顯示面板上的焊盤之前的狀態的橫截面圖。
圖6B是描繪驅動端子連接到圖6A的焊盤時的狀態的橫截面圖。
圖7至圖10是根據實施例描繪驅動端子連接到顯示面板上的焊盤時的狀態的橫截面圖。
圖11是根據另一實施例的顯示面板的一個子像素的橫截面圖。
圖12是根據實施例的一個焊盤的平面圖。
圖13是沿圖12的線XIII-XIII'截取的橫截面圖。
圖14是根據實施例的一個焊盤的平面圖。
圖15是沿圖14的線XV-XV'截取的橫截面圖。
圖16是根據實施例的一個焊盤的平面圖。
圖17是沿圖16的線XVII-XVII'截取的橫截面圖。
現在將詳細參考實施例,其範例描繪在附圖中,其中相同的附圖標記從頭到尾表示相同的元件。在這方面,本實施例可具有不同的形式,並且不應被解釋為限於本文所闡述的描述。因此,下面僅通過參考附圖來描述實施例以解釋本說明書的態樣。
可對實施例進行各種變更和修改,其中一些將在附圖和實施方式中詳細說明。然而,應當理解的是,這些實施例不被解釋為限於所示的形式,並且包括本發明構思的思想和技術範圍內的所有變更、均等物或替代。然而,在以下描述和附圖中,如果公知功能和結構的描述被認為不必要地模糊了本發明構思的要點,則將省略對公知功能和結構的描述。
應當理解的是,儘管「第一」、「第二」等詞彙可用於本文中以描述各種組件,但是這些組件不應受這些詞彙限制。這些詞彙僅用於將一個組件與另一個組件區分開來。
本文使用的詞彙僅用於描述特定實施例的目的,且不旨在限制本發明構思的範圍。如本文所使用的,單數形式「一(a)」、「一(an)」和「該(the)」也旨在包括複數形式,除非上下文另有明確指示。應當理解,本文使用的用語「包含(comprise)」、「包括(include)」和「具有(have)」特指所述特徵、整體、步驟、操作、元件、組件或其組合的存在,但不排除存在或添加一個或多個其他特徵、整體、步驟、操作、元件、組件或其組合。
下文中將參考附圖詳細描述根據一個或多個實施例的顯示設備。在整份附圖和說明書中,相似的附圖標記被分配給相似的元件,並且將省略其冗餘描述。
圖1是根據實施例的顯示設備100的平面圖,圖2是圖1的顯示設備100的橫截面圖。
參考圖1和圖2,顯示設備100包括顯示面板110。根據實施例,顯示設備100可以是有機發光顯示裝置。根據另一實施例,顯示設備100可以是液晶顯示器(LCD)、場發光顯示器(FED)或電泳顯示器(EPD)。
顯示面板110可包括含有多個元件的顯示基板120和佈置在顯示基板120上方的薄膜封裝(TFE)層130。多個薄膜電晶體和分別連接到多個薄膜
電晶體的多個發光元件可佈置在顯示基板120的上方。可在TFE層130上方佈置例如偏振層、觸摸屏和蓋窗的功能膜140。
顯示面板110可具有圖像顯示於其上的有效區域(AA)111和圍繞有效區域111的無效區域(IAA)112。
TFE層130可覆蓋有效區域111。
無效區域112圍繞有效區域111。無效區域112可具有其中顯示面板110可彎曲的彎曲區域BA且焊盤區域PA設置在彎曲區域BA的外部。
顯示面板110可沿著作為彎曲區域BA中的參考線的彎曲線BL彎曲。
焊盤區域PA可佈置在顯示基板120的一個邊緣處。多個焊盤150可佈置在焊盤區域PA中。多個焊盤150可在顯示基板120的X方向上彼此間隔開。焊盤150可以連接從有效區域111延伸的佈線113。
驅動器160可電連接到多個焊盤150。
驅動器160可包括驅動電路,並且可以是塑膠基板上的晶片(chip on plastic,COP)。驅動器160包括其中電路佈線被圖案化的柔性印刷電路板(PCB)170,佈置在顯示基板120上方的驅動積體電路(IC)180以及佈置在驅動IC 180下方的多個驅動端子190。柔性PCB 170可電連接到驅動IC 180。柔性PCB 170可以電連接到外部板(未示出)。
根據另一個實施例,驅動器160可以是晶粒軟膜接合(chip on film,COF)。根據另一個實施例,驅動器160可以是晶粒玻璃接合(chip on glass,COG)。
多個焊盤150可電連接到多個驅動端子190。多個焊盤150可直接電連接到多個驅動端子190。
黏合劑210可佈置在多個焊盤150和多個驅動端子190之間。黏合劑210可在多個焊盤150和多個驅動端子190之間提供黏合力。黏合劑210可佈置在多個焊盤150連接到多個驅動端子190的區域周圍。
具體地,當多個焊盤150連接到多個驅動端子190時,黏合劑210可流向多個焊盤150連接到多個驅動端子190的區域的周邊。因此,黏合劑210可不存在於多個焊盤150通過黏合劑210直接連接到多個驅動端子190的區域中。
具有上述結構的顯示設備100可通過使用諸如熱棒的壓力裝置將焊盤150電連接到驅動端子190。上面已經描述了顯示基板120上方的焊盤150連接到驅動器160的驅動端子190的情況,本實施例可應用於其中佈置在不同部件中的端子彼此直接連接的任何結構。
根據實施例,多個焊盤150可佈置在顯示基板120上方的同一平面上。
根據實施例,多個焊盤150中的每一個焊盤包括至少一個導電層。
根據實施例,多個焊盤150可佈置在顯示基板120上方的不同線上。
根據實施例,佈置在不同線上的多個焊盤150可交替地佈置。例如,多個焊盤150可以是Z字形排列。
圖3是根據實施例的顯示面板300的橫截面圖,圖4是圖3的一個焊盤的平面圖。圖5是沿圖4的線V-V截取的橫截面圖。
參考圖3至圖5,顯示面板300包括顯示基板301和TFE層317。根據實施例,顯示面板300可以是有機發光二極體(OLED)面板。
顯示面板300可具有佈置在有效區域(AA)中的顯示區域DA和佈置在無效區域(IAA)中的焊盤區域PA。焊盤400可以佈置在焊盤區域PA中。
顯示基板301可以是柔性玻璃基板、柔性聚合物基板、剛性玻璃基板或剛性聚合物基板。顯示基板301可以是透明的、半透明的或不透明的。
阻擋膜302可佈置在顯示基板301的上方。阻擋膜302可覆蓋顯示基板301。阻擋膜302可以是有機膜或無機膜。阻擋膜302可以是單層膜或多層膜。
至少一個薄膜電晶體TFT和至少一個電容器Cst可佈置在顯示區域DA的上方。根據實施例,薄膜電晶體TFT的數量和電容器Cst的數量不受限制。
半導體主動層303可佈置在阻擋膜302上方。半導體主動層303包括通過摻雜N型雜質離子或P型雜質離子排列的源極區304和汲極區305。未摻雜雜質的溝道區域306可設置在源極區304和汲極區305之間。半導體主動層303可以是有機半導體或無機半導體,例如非晶矽、多晶矽和氧化物半導體。
閘極絕緣膜307可佈置在半導體主動層303上方。閘極絕緣膜307可以是無機膜。閘極絕緣膜307可以是單層膜或多層膜。
閘極電極308可佈置在閘極絕緣膜307上方。閘極電極308可包括具有導電性的導電材料,例如像是鉬(Mo)、鋁(Al)、銅(Cu)和鈦(Ti)的金屬。閘極電極308可以是單層膜或多層膜。
層間絕緣膜309可佈置在閘極電極308的上方。層間絕緣膜309可以是有機膜或無機膜。
源極電極310和汲極電極311可佈置在層間絕緣膜309的上方。可以通過去除閘極絕緣膜307的一部分和層間絕緣膜309的一部分來形成接觸孔。源極電極310可通過一個接觸孔與源極區電連接,並且汲極電極311可通過一個接觸孔電連接到汲極區305。
源極電極310和汲極電極311可包括具有導電性的導電材料。例如,源極電極310和汲極電極311包括諸如Mo、Al、Cu和Ti的金屬。源極電極310
和汲極311可以是單層膜或多層膜。例如,源極電極310和汲極電極311可具有包括Ti/Al/Ti的堆疊結構。
保護膜312可佈置在源極電極310和汲極電極311的上方。保護膜312可以是有機膜或無機膜。保護膜312可包括鈍化膜和平坦化膜。可省略鈍化膜和平坦化膜中的任一個。
電容器Cst包括第一電容器電極CE1、第二電容器電極CE2和佈置在其間的電介質層。根據本實施例,電介質層可對應於層間絕緣膜309。第一電容器電極CE1可包括與閘極電極308相同的材料,並且可佈置在與閘極電極308相同的平面上。第二電容器電極CE2可包括與源極電極310和汲極電極311相同的材料,並且可佈置在與源極電極310和汲極電極311相同的平面上。保護膜312可覆蓋第二電容器電極CE2。
根據另一個實施例,電容器Cst可與薄膜電晶體TFT重疊。
例如,參考圖11,薄膜電晶體TFT的閘極電極308可用作為第一電容器電極CE1。第二電容器電極CE2可與第一電容器電極CE1重疊,電介質層1101佈置在它們之間。第二電容器電極CE2可包括具有導電性的導電材料,例如金屬。第二電容器電極CE2包括Mo、Al、Cu或Ti。第二電容器電極CE2可以是單層膜或多層膜。
再次參考圖3、4和5,薄膜電晶體TFT可電連接到OLED。
OLED可佈置在保護膜312上方。OLED包括第一電極313、中間層314和第二電極315。
第一電極313可用作為陽極並且可包括各種導電材料。第一電極313可包括透明電極或反射電極。例如,當第一電極313是透明電極時,第一電極313包括透明導電膜。當第一電極313是反射電極時,第一電極313包括反射膜和佈置在反射膜上方的透明導電膜。
像素限定層316可佈置在保護膜312上方。像素限定層316可覆蓋第一電極313的一部分。像素限定層316圍繞第一電極313的邊緣以限定每個子像素的發光區域。可在每個子像素中圖案化第一電極313。像素限定層316可以是有機膜或無機膜。像素限定層316可以是單層膜或多層膜。
中間層314可在對應於通過蝕刻像素限定層316的一部分而暴露的第一電極313的區域中佈置於第一電極313上方。中間層314可通過沉積工藝形成。
中間層314可包括有機發光層。
根據替代實例,中間層314可包括有機發光層,並且還可包括空穴注入層(HIL)、空穴傳輸層(HTL)、電子傳輸層(ETL)和電子注入層(EIL)。
根據實施例,中間層314可包括有機發光層,並且還可包括各種功能層。
第二電極315可佈置在中間層314的上方。
第二電極315可用作為陰極。第二電極315可包括透明電極或反射電極。例如,當第二電極315是透明電極時,第二電極315包括金屬膜和佈置在金屬膜上方的透明導電膜。當第二電極315是反射電極時,第二電極315包括金屬膜。
根據實施例,多個子像素可佈置在顯示基板301的上方。例如,紅色子像素、綠色子像素、藍色子像素或白色子像素可形成在顯示基板301上。然而,本公開不限於此。
TFE層317可以覆蓋OLED。
TFE層317可包括交替堆疊的第一無機膜318、第二無機膜319以及有機膜320。例如,第一無機膜318、有機膜320和第二無機膜319可依次層疊在
OLED的上方。可以對包含在TFE層317中的無機膜和有機膜的堆疊結構進行各種修改。
偏振層321可佈置在TFE層317的上方。偏振層321可減少外部光反射。根據另一實施例,可省略偏振層321,並且可通過使用黑矩陣和濾色器來減少外部光反射。
電連接到驅動端子的多個焊盤400可佈置在焊盤區域PA中。多個焊盤400中的每一個焊盤401可在顯示基板301的一個方向上間隔開。
多個焊盤400的每一個焊盤401可包括第一導電層410和佈置在第一導電層410上方的第二導電層420。
下面將描述其細節。
第一絕緣膜331可佈置在焊盤區域PA中的顯示基板301的上方。第一絕緣膜331可佈置在與阻擋膜302相同的平面上。第一絕緣膜331和阻擋膜302可通過使用相同的材料以相同的工藝形成。
第二絕緣膜332可佈置在第一絕緣膜331的上方。第二絕緣膜332可佈置在與閘極絕緣膜307相同的平面上。第二絕緣膜332和閘極絕緣膜307可通過使用相同的材料在相同的工藝中形成。
包括在每一個焊盤401中的第一導電層410可佈置在第二絕緣膜332的上方。第一導電層410可電連接到從閘極電極308延伸的佈線322。第一導電層410可佈置在與閘極電極308相同的平面上。第一導電層410和閘極電極308可通過使用相同的材料在相同的工藝中形成。第一導電層410可在顯示基板301的一個方向上彼此間隔開。
第三絕緣膜333可佈置在第一導電層410的上方。第三絕緣膜333可佈置在與層間絕緣膜309相同的平面上。第三絕緣膜333和層間絕緣膜309可通過使用相同的材料在相同的工藝中形成。
第三絕緣膜333可以覆蓋第一導電層410的至少一部分。多個接觸孔430可通過去除第三絕緣膜333的部分而形成在第一導電層410的上方。在形成接觸孔430的區域中,第一導電層410的頂表面可暴露於外。
接觸孔430包括第一接觸孔431和鄰近第一接觸孔431佈置的第二接觸孔432。上面已經描述了兩個接觸孔430佈置在第一導電層410上方的情況,但是實施例不限於此,只要接觸孔430的數量為2個以上即可。
多個第二導電層420可佈置在第一導電層410的暴露區域的上方。第二導電層420可通過接觸孔430電連接到第一導電層410。
多個第二導電層420可分別佈置在多個接觸孔430中。例如,一個第二導電層420a可佈置在第一接觸孔431的上方,而另一個第二導電層420b可佈置在第二接觸孔432的上方。多個第二導電層420a和420b可在第一導電層410上方彼此間隔開。然而,多個第二導電層420a和420b可在第一導電層410上方彼此連接。
多個第二導電層420可在第一導電層410上方佈置成具有島型。根據另一實施例,第二導電層420可電連接到從顯示區域DA延伸的佈線。
第二導電層420可佈置在與源極電極310和汲極電極311相同的平面上。第二導電層420、源極電極310和汲極電極311可通過使用相同的材料在相同的工藝中形成。
第二導電層420可具有多層結構。根據實施例,第二導電層420包括多層的導電部分。第二導電層420包括第一導電部分421、第二導電部分422和第三導電部分423。
第一導電部分421可佈置在第一導電層410的上方。第一導電部分421包括Ti。第一導電部分421可直接連接到第一導電層410。第二導電部分422可佈置在第一導電部分421的上方。第二導電部分422包括Al。第三導電部分423
可佈置在第二導電部分422的上方。第三導電部分423包括Ti。上面已經描述了第二導電層420具有包括Ti/Al/Ti的堆疊結構的情況,但是可以對第二導電層420的堆疊結構進行各種修改。
連接到驅動器的驅動端子(圖6A的640)的至少一部分的夾持部分424可佈置在包括在第二導電層420中的相鄰的第二導電層420a和420b之間。夾持部分424可形成在第三絕緣膜333上,以在俯視圖中與第三絕緣膜333完全重疊。夾持部分424包括形成在相鄰的第二導電層420a和420b中的底切425。在一實施例中,夾持部分可形成在第二導電層的中心。
可通過將第一導電部分421、第二導電部分422和第三導電部分423形成為具有不同寬度來提供底切425。底切425可形成在其中第二導電部分422的寬度W2比第一導電部分421的寬度W1和第三導電部分423的寬度W3窄約1μm到約20μm處的第二導電部分422中。第一導電部分421的寬度W1可基本上等於第三導電部分423的寬度W3。
可通過蝕刻工藝對第二導電層420進行圖案化。當蝕刻第二導電層420時,第一導電部分421和第三導電部分423的蝕刻速率可不同於第二導電部分422的蝕刻速率。例如,包括Al的第二導電部分422的蝕刻速率可大於各包括Ti的第一導電部分421和第三導電部分423的蝕刻速率。因此,底切425可以形成在相鄰的第二導電層420a和420b的相對側壁上,使第二導電部分422具有凹部。
驅動器的驅動端子(圖6A的640)可牢固地連接到具有上述結構的焊盤401。
圖6A是描繪驅動端子640連接到圖5的焊盤401之前的狀態的橫截面圖,而圖6B是描繪驅動端子640連接到圖6A的焊盤401時的狀態的橫截面圖。
參考圖6A,驅動IC 610可佈置在焊盤401的上方。電路圖案620可佈置在驅動IC 610下方。絕緣膜630可覆蓋電路圖案620的一部分。驅動端子640
可電連接到電路圖案620。驅動端子640包括凸塊641。凸塊641可包括金(Au)、銅(Cu)和銦(In)。熔化層642還可佈置在凸塊641的頂端。根據實施例,熔化層642可以是焊料層。
黏合劑650可佈置在焊盤401和驅動端子640之間。黏合劑650可以是非導電膜(NCF)。黏合劑650可不包括導電材料。黏合劑650可在焊盤401和驅動端子640之間提供黏合力。黏合劑650可佈置在多個焊盤400的每一個焊盤401連接到與其對應的每一個驅動端子640的區域周圍。
焊盤401和凸塊641的連接可以使用熱壓接合工藝進行。當通過使用諸如熱棒的熱壓接合工藝設備從驅動IC 610的上方施加一定的熱和壓力時,設置在凸塊641中的熔化層642被熔化,使焊盤401電連接(或結合)到驅動端子640,如圖6B所示。
在接合之後,由於在多個焊盤400的每一個焊盤401與對應於其的驅動端子640連接的區域周圍佈置的黏合劑650的溼氣吸收,焊盤401和驅動端子640之間可能會發生分層。
根據本實施例,由於包括底切425的夾持部分424佈置在包括於第二導電層420中的相鄰的第二導電層420a和420b的相對的側壁上,所以焊盤400的每一個焊盤401可緊密地結合到與其對應的驅動端子640。
在接合期間,設置在凸塊641上的熔化層642流入佈置在相鄰的第二導電層420a和420b的相對側壁上的底切425。熔化層642可填充相鄰的第二導電層420a和420b之間的間隙,且可接觸相鄰的第二導電層420a和420b的相對側壁。
根據實施例,設置在凸塊641上的熔化層642可延伸超過第一導電層410接觸第二導電層420的區域,並在相鄰的第二導電層420a和420b之間延伸。
根據實施例,設置在凸塊641上的熔化層642可完全覆蓋相鄰的第二導電層420a和420b。
根據實施例,每一個焊盤401通過設置在凸塊641上的熔化層642與對應於其的驅動端子640表面接觸。由於熔化層642填充相鄰的第二導電層420a和420b之間的底切,可以減小焊盤400的每一個焊盤401與驅動端子640之間的接觸電阻。
隨後,如果執行固化過程,則焊盤401可牢固地連接到驅動端子640。
根據實施例,焊盤401可被修改為具有各種形狀,只要設置在凸塊641中的熔化層642可填充導電層之間的底切即可。
圖12是根據實施例的一個焊盤的平面圖,而圖13是沿圖12的線XIII-XIII'截取的橫截面圖。參見圖12和圖13,第二導電層420形成為一塊並且在中心具有去除部分。
圖14是根據實施例的一個焊盤的平面圖,而圖15是沿圖14的線XV-XV'截取的橫截面圖。參見圖14和圖15,多個隔離的第二導電層420以矩陣形式佈置在第一導電層410上。
圖16是根據實施例的一個焊盤的平面圖,而圖17是沿圖16的線XVII-XVII'截取的橫截面圖。參見圖如圖16和圖17,第二導電層420形成為網狀,且在第一導電層410上具有以矩陣形狀佈置的多個去除部分。
在下文中,將描述根據各種實施例的連接到驅動端子640的至少一部分的夾持部分。
參考圖7,連接到驅動端子640的至少一部分的夾持部分724可佈置在包括在第二導電層720中的相鄰的第二導電層720a和720b之間。夾持部分724包括佈置在相鄰的第二導電層720a和720b的相對側壁的底切725。第一導電
層410可佈置在與圖3的閘極電極308相同的平面上。第二導電層720可佈置在與圖3的源極電極310和汲極電極311相同的平面上。
第二導電層720可以是單層膜或多層膜。例如,第二導電層720包括至少一層的導電部分。底切725可對應於第二導電層720的側壁傾斜的區域。
根據實施例,第二導電層720可具有倒錐形形狀。
參考圖8,夾持部分824可佈置在包括於第二導電層820中的相鄰的第二導電層820a和820b之間。夾持部分824包括佈置在相鄰的第二導電層820a和820b的相對側壁上的底切825。
第二導電層820包括至少一層的導電部分。底切825可對應於第二導電層820的側壁彎曲的區域。
參考圖9,夾持部分924可佈置在包含於第二導電層920中相鄰的第二導電層920a和920b之間。夾持部分924包括佈置在相鄰的第二導電層920a和920b的相對側壁上的底切925。
第二導電層920包括至少一層的導電部分。底切925可對應於第二導電層920的側壁彎曲的區域。
與圖8不同,第三導電層930可進一步佈置在第二導電層920的上方。第一導電層410可佈置在與圖11的閘極電極308相同的平面上。第二導電層920可以佈置在與圖11的第二電容器電極CE2相同的平面上。第三導電層930可以佈置在與圖11的源極電極310和汲極電極311相同的平面上。
根據實施例,可以通過組合選自圖3和圖11的閘極電極308、源極電極310、汲極電極311、第一電容器電極CE1、第二電容器電極CE2、第一電極313和第二電極315中的多個電極來對第一至第三導電層410、920和930進行各式各樣的修改。
參考圖10,第三導電層1030可進一步佈置在第二導電層1020的上方。夾持部分1024可佈置在包括在第二導電層1020中的相鄰的第二導電層1020a和1020b之間。夾持部分1024包括佈置在相鄰的第二導電層1020a和1020b的相對側壁上的底切1025。
第二導電層1020包括至少一層的導電部分。底切1025可對應於第二導電層1020的寬度W4與第三導電層1030的寬度W5不同的區域。第二導電層1020的寬度W4可以比第三導電層1030的寬度W5窄。
第一導電層1010可佈置在與圖11的閘極電極308相同的平面上。第二導電層1020可佈置在與圖11的第二電容器電極CE2相同的平面上。第三導電層1030可佈置在與圖11的源極電極310和汲極電極311相同的平面上。
根據實施例,可以通過組合選自圖3和圖11的閘極電極308、源極電極310、汲極電極311、第一電容器電極CE1、第二電容器電極CE2、第一電極313和第二電極315中的多個電極來對第一至第三導電層1010、1020和1030進行各式各樣的修改。
如上所述,根據一個或多個實施例的顯示設備能夠改善焊盤和驅動端子之間的連接力。因此,可以提高焊盤與驅動端子之間的連接可靠性。
應當理解的是,本文描述的實施例應被認為僅為係描述性意義,而不意圖為限制。每個實施例中的特徵或態樣的描述通常應被認為可用於其它實施例中其他類似的特徵或態樣。
雖然已經參考附圖描述了一個或多個實施例,但相關領域中具有通常知識者將會理解,在不脫離如以下申請專利範圍所定義的精神和範圍的情況下,可對其進行形式和細節上的各種改變。
333:第三絕緣膜
401:焊盤
410:第一導電層
420,420a,420b:第二導電層
421:第一導電部分
422:第二導電部分
423:第三導電部分
424:夾持部分
425:底切
430:接觸孔
431:第一接觸孔
432:第二接觸孔
W1,W2,W3:寬度
Claims (11)
- 一種顯示設備,其包括:一顯示基板;複數個焊盤,佈置在該顯示基板上方;和複數個驅動端子,位於該複數個焊盤上方,並電連接到該複數個焊盤,其中該複數個焊盤中的每一個焊盤包括:一第一導電層,其至少一部分被一絕緣膜覆蓋;一第二導電層,佈置在該第一導電層上方;和一夾持部分,形成在該第二導電層中,其中該第二導電層包括在該第一導電層上方彼此間隔開的複數個該第二導電層,該夾持部分包括佈置在相鄰的該第二導電層的相對側壁上的一底切,該複數個驅動端子分別填充該第一導電層上的複數個該第二導電層之間的一間隙,並接觸該夾持部分的該底切。
- 如請求項1所述的顯示設備,其中該絕緣膜包括暴露該第一導電層的頂表面的複數個接觸孔,且複數個該第二導電層通過該複數個接觸孔與該第一導電層電連接。
- 如請求項1所述的顯示設備,其中該第二導電層包括具有多層的一導電部分,且該底切係通過使具有多層的該導電部分形成為具有不同的寬度來提供。
- 如請求項3所述的顯示設備,其中該第二導電層包括:一第一導電部分,連接到該第一導電層;一第二導電部分,佈置在該第一導電部分上方;以及一第三導電部分,佈置在該第二導電部分上方,且該底切對應於該第二導電部分的寬度比該第一導電部分的寬度和該第三導電部分的寬度窄的區域。
- 如請求項1所述的顯示設備,其中該第二導電層包括具有至少一層的一導電部分,且該底切對應於該第二導電層的側壁傾斜的區域。
- 如請求項1所述的顯示設備,其中該第二導電層包括具有至少一層的一導電部分,且該底切對應於該第二導電層的側壁彎曲的區域。
- 如請求項6所述的顯示設備,其進一步包括:一第三導電層,佈置在該第二導電層上方。
- 如請求項6所述的顯示設備,其中該第二導電層包括具有至少一層的一導電部分,該顯示設備進一步包括佈置在該第二導電層上方的一第三導電層,且該底切中該第二導電層的寬度比該第三導電層的寬度窄。
- 如請求項1所述的顯示設備,其中一顯示面板包括:至少一個薄膜電晶體,包括一半導體主動層、一閘極電極、一源極電極和一汲極電極在該顯示基板上方;一有機發光顯示裝置,電連接到該薄膜電晶體,該有機發光顯示裝置包括一第一電極、一發光層和一第二電極;和 具有至少一層的一絕緣膜,佈置在該薄膜電晶體和該有機發光顯示裝置之間,且該第一導電層與從該閘極電極、該源極電極、該汲極電極、該第一電極和該第二電極中的任一個延伸的佈線連接,且該第二導電層於該第一導電層上被佈置為具有島型。
- 如請求項9所述的顯示設備,其中該第一導電層係由與該閘極電極相同的材料形成,且該第二導電層係由與該源極電極和該汲極電極相同的材料形成。
- 如請求項9所述的顯示設備,其進一步包括:一第三導電層,佈置在該第二導電層上方。
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KR1020160079286A KR102663140B1 (ko) | 2016-06-24 | 2016-06-24 | 디스플레이 장치 |
KR10-2016-0079286 | 2016-06-24 | ||
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US (1) | US11171194B2 (zh) |
EP (1) | EP3261143A1 (zh) |
KR (1) | KR102663140B1 (zh) |
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KR102591811B1 (ko) * | 2018-05-18 | 2023-10-23 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판, 이의 제조 방법 및 이를 포함하는 표시 장치 |
KR102636629B1 (ko) * | 2018-12-20 | 2024-02-13 | 엘지디스플레이 주식회사 | 표시장치 |
CN116387270A (zh) * | 2019-06-11 | 2023-07-04 | 群创光电股份有限公司 | 电子装置 |
KR20210081941A (ko) * | 2019-12-24 | 2021-07-02 | 엘지디스플레이 주식회사 | 유기발광 표시장치 |
KR20210106605A (ko) * | 2020-02-20 | 2021-08-31 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
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CN107546242A (zh) | 2018-01-05 |
TW201810757A (zh) | 2018-03-16 |
EP3261143A1 (en) | 2017-12-27 |
KR102663140B1 (ko) | 2024-05-08 |
US11171194B2 (en) | 2021-11-09 |
US20170373028A1 (en) | 2017-12-28 |
KR20180001640A (ko) | 2018-01-05 |
CN107546242B (zh) | 2023-09-08 |
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