CN107546242A - 显示设备 - Google Patents

显示设备 Download PDF

Info

Publication number
CN107546242A
CN107546242A CN201710493745.XA CN201710493745A CN107546242A CN 107546242 A CN107546242 A CN 107546242A CN 201710493745 A CN201710493745 A CN 201710493745A CN 107546242 A CN107546242 A CN 107546242A
Authority
CN
China
Prior art keywords
conductive layer
display device
electrode
layer
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710493745.XA
Other languages
English (en)
Other versions
CN107546242B (zh
Inventor
柳承洙
金炳容
宋常铉
梁正道
赵正然
河承和
黃晸護
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020160079286A external-priority patent/KR102663140B1/ko
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of CN107546242A publication Critical patent/CN107546242A/zh
Application granted granted Critical
Publication of CN107546242B publication Critical patent/CN107546242B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/129—Chiplets
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/8148—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/82385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Abstract

提供了一种显示设备。该显示设备包括显示基板和布置在显示基板上方的多个焊盘。多个焊盘中的每个焊盘包括：其至少一部分被绝缘膜覆盖的第一导电层；布置在第一导电层上方的第二导电层；以及形成在第二导电层中的夹持部分。

Description

显示设备
相关申请的交叉引用
本申请要求2016年6月24日提交至韩国知识产权局的第10-2016-0079286号韩国专利申请的权益，该韩国专利申请的公开内容通过引用整体地并入本文。
技术领域
一个或多个实施方式涉及显示设备。
背景技术
显示设备可用于诸如智能电话、膝上型计算机、数字相机、摄像机、便携式信息终端、笔记本和平板个人计算机(PC)的移动设备中，或者可用于诸如台式计算机、电视、户外广告牌和展览显示设备的电子设备中。
近来，已经推出更薄的显示设备。
柔性显示设备易于携带并且可适用于具有各种形状的设备。在它们之中，基于有机发光显示技术的柔性显示设备是最具影响力的柔性显示设备。
在该显示设备中，显示面板上的焊盘可电连接到驱动器的焊盘。如果显示面板上的焊盘和驱动器的焊盘没有可靠地彼此连接，则显示设备的可靠性可能劣化。
发明内容
一个或多个实施方式包括其中焊盘和驱动终端彼此可靠地连接的显示设备。
另外的方面将在以下描述中部分地阐述，并且通过该描述将部分地显而易见，或者可以通过实践所提出的实施方式而被习得。
根据一个或多个实施方式，显示设备包括显示基板以及布置在显示基板上方的多个焊盘，其中，多个焊盘中的每个焊盘包括：其至少一部分被绝缘膜覆盖的第一导电层、布置在第一导电层上方的多个第二导电层以及形成在第二导电层中的夹持部分。
第二导电层包括可以在第一导电层上方彼此间隔开的多个第二导电层。
绝缘膜可包括暴露第一导电层的顶表面的多个接触孔，并且多个第二导电层可以通过接触孔电连接到第一导电层。
夹持部分可包括布置在相邻的第二导电层的相对侧壁上的底切。
第二导电层可包括多层导电部分，并且可以通过使多层导电部分形成为具有不同的宽度来提供底切。
第二导电层可包括：连接到第一导电层的第一导电部分；布置在第一导电部分上方的第二导电部分；以及布置在第二导电部分上方的第三导电部分，并且底切对应于其中第二导电部分的宽度可窄于第一导电部分的宽度和第三导电部分的宽度的区域。
第二导电层可包括至少一层导电部分，并且底切可对应于第二导电层的侧壁倾斜的区域。
第二导电层可包括至少一层导电部分，并且底切可对应于第二导电层的侧壁弯曲的区域。
显示设备还可包括布置在第二导电层上方的第三导电层。
第二导电层可包括至少一层导电部分，显示设备还可包括布置在第二导电层上方的第三导电层，并且在底切中第二导电层的宽度可以窄于第三导电层。
显示面板可包括至少一个薄膜晶体管、有机发光显示装置和至少一层绝缘膜，其中，至少一个薄膜晶体管包括在显示基板上方的半导体有源层、栅电极、源电极和漏电极；有机发光显示装置电连接到薄膜晶体管，有机发光显示装置包括第一电极、发射层和第二电极；以及至少一层绝缘膜布置在薄膜晶体管与有机发光显示装置之间，并且第一导电层可连接到从栅电极、源电极、漏电极、第一电极和第二电极延伸出的布线，并且第二导电层可布置成在第一导电层上方具有岛形状。
第一导电层可以由与栅电极的材料相同的材料形成，并且第二导电层可以由与源电极和漏电极的材料相同的材料形成。
显示设备还可包括设置在第二导电层上的第三导电层，其中第一至第三导电层可以是选自栅电极、源电极、漏电极、电容器电极、第一电极和第二电极的多个电极的组合。
根据一个或多个实施方式，一种显示设备包括显示面板、驱动器和粘合剂，其中，显示面板包括布置有多个焊盘的显示基板和布置在显示基板上方的薄膜封装层；驱动器包括电连接到多个焊盘的多个驱动终端；以及粘合剂布置在多个焊盘与驱动器之间，其中多个焊盘中的每个焊盘包括：其至少一部分被绝缘膜覆盖的第一导电层、布置在第一导电层上方的多个第二导电层以及布置在相邻的第二导电层之间的夹持部分。
绝缘膜可包括暴露第一导电层的顶表面的多个接触孔，并且第二导电层可以分别通过接触孔电连接到第一导电层。
夹持部分可包括布置在相邻的第二导电层的相对侧壁上的底切。
驱动终端可以填充相邻的第二导电层之间的间隙并且接触第二导电层的布置有底切的侧壁。
驱动终端可以在第一导电层与第二导电层接触的区域上方以及在相邻的第二导电层之间延伸。
多个焊盘中的每个焊盘可以与驱动终端进行表面接触。粘合剂可包括非导电膜。
根据一个或多个实施方式，显示设备包括显示面板和驱动器，其中，显示面板包括其中布置多个焊盘的显示基板；以及驱动器包括分别电连接到多个焊盘的多个驱动终端，其中多个焊盘中的每个焊盘包括：第一导电层、设置在第一导电层上的绝缘层、以及设置在绝缘层上并且通过形成在绝缘层中的接触孔连接到第一导电层的第二导电层，以及，其中第二导电层包括具有底切的夹持部分并且多个驱动终端之一填充所述底切。
第二导电层可包括第一导电部分和设置在第一导电部分上的第二导电部分，并且底切可以形成在第一导电部分中。
底切可具有从第二导电部分的边缘凹进的凹进部分，并且所述凹进部分可以为从约1μm至约20μm。
夹持部分可以形成在第二导电层的中央处。
第二导电层可包括设置在第一导电层上的多个第二导电层，并且夹持部分可以形成在相邻的第二导电层之间。
附图说明
根据结合附图对实施方式的以下描述，这些和/或其他方面将变得明显且更容易理解，在附图中：
图1是根据实施方式的显示设备的平面图；
图2是图1的显示设备的侧视图；
图3是根据实施方式的显示面板的剖视图；
图4是图3的显示面板上的焊盘的平面图；
图5是沿着图4的线V-V′截取的剖视图；
图6A是示出在驱动终端连接到图5的显示面板上的焊盘之前的状态的剖视图；
图6B是示出当驱动终端连接到图6A的焊盘时的状态的剖视图；
图7至图10是示出根据实施方式当驱动终端连接到显示面板上的焊盘的状态的剖视图；
图11是根据另一个实施方式显示面板的一个子像素的剖视图；
图12是根据实施方式的一个焊盘的平面图；
图13是沿着图12的线XIII-XIII′截取的剖视图；
图14是根据实施方式的一个焊盘的平面图；
图15是沿着图14的线XV-XV′截取的剖视图；
图16是根据实施方式的一个焊盘的平面图；以及
图17是沿着图16的线XVII-XVII′截取的剖视图。
具体实施方式
现在将详细参考其示例在附图中示出的各实施方式，在附图中，相同的参考数字始终指代相同的元件。在这方面，本实施方式可具有不同的形式，并且不应解释为限于本文所阐述的描述。因此，以下通过参照附图仅描述所述实施方式，以解释说明书的各方面。
可以对实施方式进行各种改变和修改，这些实施方式中的一些将在附图和具体描述中详细说明。然而，应当理解，这些实施方式不应解释为限于所示的形式，并且包括本发明构思的思想和技术范围内的所有改变、等同物或替代物。然而，在以下描述和附图中，如果认为对公知的功能和构造的描述不必要地混淆本发明构思的要点，则将省略该描述。
将理解，尽管术语“第一”、“第二”等在本文中可以用于描述各组件，但是这些组件不应受这些术语限制。这些术语仅用于将一个组件与另一组件区分开。
本文使用的术语仅用于描述具体实施方式的目的，并且不旨在限制本发明构思的范围。如本文所使用的，除非上下文另有明确指示，否则单数形式“一”、“一个”和“所述”也旨在包括复数形式。将理解，本文使用的术语“包括”、“包含”和“具有”指出存在所阐述的特征、整体、步骤、操作、元件、组件或其组合，但不排除存在或增添一个或多个其他特征、整数、步骤、操作、元件、组件或其组合。
在下文中，将参照附图详细描述根据一个或多个实施方式的显示设备。贯穿附图和本说明书，相同的参考数字被分配给相同的元件，并且将省略它冗余的描述。
图1是根据实施方式的显示设备100的平面图，以及图2是图1的显示设备100的侧视图。
参考图1和图2，显示设备100包括显示面板110。根据实施方式，显示设备100可以是有机发光显示装置(OLED)。根据另一个实施方式，显示设备100可以是液晶显示器(LCD)、场发射显示器(FED)或电泳显示器(EPD)。
显示面板110可包括具有多个元件的显示基板120以及布置在显示基板120上方的薄膜封装(TFE)层130。在显示基板120上方，可布置有多个薄膜晶体管以及分别连接到所述多个薄膜晶体管的多个发光元件。在TFE层130上方，可布置有诸如偏振层、触摸屏和覆盖窗的功能膜140。
显示面板110可具有上面显示图像的有源区(AA)111以及围绕有源区111的非有源区(IAA)112。
TFE层130可覆盖有源区111。
非有源区112围绕有源区111。非有源区112可具有其中显示面板110可弯曲的弯曲区BA以及设置在弯曲区BA外部的焊盘区PA。
显示面板110可以沿着作为弯曲区BA中的基准线的弯曲线BL弯曲。
焊盘区PA可布置在显示基板120的一个边缘处。在焊盘区PA中可布置有多个焊盘150。多个焊盘150可在显示基板120的X方向上彼此间隔开。焊盘150可连接到从有源区111延伸出的布线113。
驱动器160可电连接到多个焊盘150。
驱动器160可包括驱动电路，并且可以是塑料上芯片(COP)。驱动器160包括：其中电路布线被图案化的柔性印刷电路板(PCB)170；布置在显示基板120上方的驱动集成电路(IC)180；以及布置在驱动IC 180下方的多个驱动终端190。柔性PCB 170可电连接到驱动IC180。柔性PCB 170可电连接到外部板(未示出)。
根据另一个实施方式，驱动器160可以是膜上芯片(COF)。根据另一个实施方式，驱动器160可以是玻璃上芯片(COG)。
多个焊盘150可电连接到多个驱动终端190。多个焊盘150可以直接电连接到多个驱动终端190。
粘合剂210可布置在多个焊盘150与多个驱动终端190之间。粘合剂210可以在多个焊盘150与多个驱动终端190之间提供粘附力。粘合剂210可以布置成围绕其中多个焊盘150连接到多个驱动终端190的区域。
具体地，当多个焊盘150连接到多个驱动终端190时，粘合剂210可以朝向其中多个焊盘150连接到多个驱动终端190的区域的周边流动。因此，在多个焊盘150直接连接到多个驱动终端190的区域中，可以不存在粘合剂210。
具有上述结构的显示设备100可以通过使用诸如热压焊机的压力装置将焊盘150电连接到驱动终端190。以上已经描述了显示基板120上方的焊盘150连接到驱动器160的驱动终端190的情况，然而，本实施方式可以应用于其中布置在不同组件中的终端彼此直接连接的任何结构。
根据实施方式，多个焊盘150可布置在显示基板120上方的同一层上。
根据实施方式，多个焊盘150中的每个焊盘包括至少一个导电层。
根据实施方式，多个焊盘150可布置在显示基板120上方的不同线路上。
根据实施方式，布置在不同线路上的多个焊盘150可以交替布置。例如，多个焊盘150可以呈之字形布置。
图3是根据实施方式的显示面板300的剖视图，图4是图3的一个焊盘的平面图，以及图5是沿着图4的线V-V′截取的剖视图。
参考图3至图5，显示面板300包括显示基板301和TFE层317。根据实施方式，显示面板300可以是OLED面板。
显示面板300可具有布置在有源区AA中的显示区DA和布置在非有源区IAA中的焊盘区PA。在焊盘区PA中，可布置有焊盘400。
显示基板301可以是柔性玻璃基板、柔性聚合物基板、刚性玻璃基板或刚性聚合物基板。显示基板301可以是透明的、半透明的或不透明的。
阻挡膜302可布置在显示基板301上方。阻挡膜302可覆盖显示基板301。阻挡膜302可以是有机膜或无机膜。阻挡膜302可以是单一膜或多层膜。
至少一个薄膜晶体管TFT和至少一个电容器Cst可布置在显示区DA上方。根据实施方式，薄膜晶体管TFT的数量和电容器Cst的数量不受限制。
半导体有源层303可布置在阻挡膜302上方。半导体有源层303包括通过掺杂N型杂质离子或P型杂质离子而布置的源区304和漏区305。不掺杂杂质的沟道区306可以设置在源区304与漏区305之间。半导体有源层303可以是有机半导体或无机半导体，诸如非晶硅、多晶硅和氧化物半导体。
栅极绝缘膜307可布置在半导体有源层303上方。栅极绝缘膜307可以是无机膜。栅极绝缘膜307可以是单一膜或多层膜。
栅电极308可布置在栅极绝缘膜307上方。栅电极308可包含具有导电性的导电材料，例如像钼(Mo)、铝(Al)、铜(Cu)和钛(Ti)的金属。栅电极308可以是单一膜或多层膜。
层间绝缘膜309可布置在栅电极308上方。层间绝缘膜309可以是有机膜或无机膜。
源电极310和漏电极311可布置在层间绝缘膜309上方。可以通过移除栅极绝缘膜307的部分和层间绝缘膜309的部分来形成接触孔。源电极310可以通过接触孔之一电连接到源区304，并且漏电极311可以通过接触孔之一电连接到漏区305。
源电极310和漏电极311可包含具有导电性的导电材料。例如，源电极310和漏电极311包括诸如Mo、Al、Cu和Ti的金属。源电极310和漏电极311可以是单一膜或多层膜。例如，源电极310和漏电极311可具有包括Ti/Al/Ti的堆叠结构。
保护膜312可布置在源电极310和漏电极311上方。保护膜312可以是有机膜或无机膜。保护膜312可包括钝化膜和平坦化膜。可以省略钝化膜和平坦化膜中的任一者。
电容器Cst包括第一电容器电极CE1、第二电容器电极CE2和布置在它们之间的介电层。根据本实施方式，介电层可对应于层间绝缘膜309。第一电容器电极CE1可包含与栅电极308的材料相同的材料，并且可以与栅电极308布置在同一层上。第二电容器电极CE2可包含与源电极310和漏电极311的材料相同的材料，并且可以与源电极310和漏电极311布置在同一层上。保护膜312可覆盖第二电容器电极CE2。
根据另一个实施方式，电容器Cst可以与薄膜晶体管TFT重叠。
例如，参考图11，薄膜晶体管TFT的栅电极308可充当第一电容器电极CE1。第二电容器电极CE2可以与第一电容器电极CE1重叠，并且在它们之间布置有介电层1101。第二电容器电极CE2可包含具有导电性的导电材料，例如金属。第二电容器电极CE2包括Mo、Al、Cu或Ti。第二电容器电极CE2可以是单一膜或多层膜。
再次参考图3、图4和图5，薄膜晶体管TFT可电连接到OLED。
OLED可布置在保护膜312上方。OLED包括第一电极313、中间层314和第二电极315。
第一电极313可充当阳极并且可包含各种导电材料。第一电极313可包括透明电极或反射电极。例如，当第一电极313是透明电极时，第一电极313包括透明导电膜。当第一电极313是反射电极时，第一电极313包括反射膜和布置在反射膜上方的透明导电膜。
像素限定层316可布置在保护膜312上方。像素限定层316可覆盖第一电极313的一部分。像素限定层316包围第一电极313的边缘以限定每个子像素的发射区域。可以在每个子像素中对第一电极313进行图案化。像素限定层316可以是有机膜或无机膜。像素限定层316可以是单一膜或多层膜。
中间层314可以在与通过蚀刻像素限定层316的一部分而暴露的第一电极313对应的区域中布置在第一电极313上方。可以通过沉积工艺形成中间层314。
中间层314可包括有机发射层。
根据替代示例，中间层314可包括有机发射层，并且还可包括空穴注入层(HIL)、空穴传输层(HTL)、电子传输层(ETL)和电子注入层(EIL)。
根据实施方式，中间层314可包括有机发射层，并且还可包括各种功能层。
第二电极315可布置在中间层314上方。
第二电极315可充当阴极。第二电极315可包括透明电极或反射电极。例如，当第二电极315是透明电极时，第二电极315包括金属膜和布置在金属膜上方的透明导电膜。当第二电极315是反射电极时，第二电极315包括金属膜。
根据实施方式，在显示基板301上方可布置有多个子像素。例如，可在显示基板301上形成红色子像素、绿色子像素、蓝色子像素或白色子像素。然而，本公开不限于此。
TFE层317可覆盖OLED。
TFE层317可包括交替堆叠的第一无机膜318和第二无机膜319以及有机膜320。例如，第一无机膜318、有机膜320和第二无机膜319可以顺序地堆叠在OLED上方。可以对包括在TFE层317中的无机膜和有机膜的堆叠结构进行各种修改。
偏振层321可布置在TFE层317上方。偏振层321可以减少外部光反射。根据另一个实施方式，可以省略偏振层321，并且可以通过使用黑矩阵和滤色器来减少外部光反射。
电连接到驱动终端的多个焊盘400可布置在焊盘区PA中。多个焊盘400中的每个焊盘401可以在显示基板301的一个方向上间隔开。
多个焊盘400中的每个焊盘401可包括第一导电层410和布置在第一导电层410上方的第二导电层420。
以下对它们的细节进行描述。
第一绝缘膜331可以在焊盘区PA中布置在显示基板301上方。第一绝缘膜331可以与阻挡膜302布置在同一层上。可以通过使用相同的材料以相同的工艺形成第一绝缘膜331和阻挡膜302。
第二绝缘膜332可布置在第一绝缘膜331上方。第二绝缘膜332可以与栅极绝缘膜307布置在同一层上。可以通过使用相同的材料以相同的工艺形成第二绝缘膜332和栅极绝缘膜307。
每个焊盘401中所包括的第一导电层410可布置在第二绝缘膜332上方。第一导电层410可电连接到从栅电极308延伸出的布线322。第一导电层410可以与栅电极308布置在同一层上。可以通过使用相同的材料以相同的工艺形成第一导电层410和栅电极308。各第一导电层410可以在显示基板301的一个方向上彼此间隔开。
第三绝缘膜333可布置在第一导电层410上方。第三绝缘膜333可以与层间绝缘膜309布置在同一层上。可以通过使用相同的材料以相同的工艺形成第三绝缘膜333和层间绝缘膜309。
第三绝缘膜333可覆盖第一导电层410的至少一部分。通过移除第三绝缘膜333的部分，可以在第一导电层410上方形成多个接触孔430。在形成接触孔430的区域中，第一导电层410的顶表面可以暴露于外部。
接触孔430包括第一接触孔431和邻近第一接触孔431布置的第二接触孔432。以上已经描述了两个接触孔430布置在第一导电层410上方的情况，但是实施方式不受限制，只要接触孔430的数量是两个或更多即可。
多个第二导电层420可布置在第一导电层410的暴露区域上方。第二导电层420可以通过接触孔430电连接到第一导电层410。
多个第二导电层420可以分别布置在多个接触孔430中。例如，一个第二导电层420a可布置在第一接触孔431上方，并且另一个第二导电层420b可布置在第二接触孔432上方。多个第二导电层420a和420b可以在第一导电层410上方彼此间隔开。然而，多个第二导电层420a和420b可以在第一导电层410上方彼此连接。
多个第二导电层420可布置成在第一导电层410上方具有岛形状。根据另一个实施方式，第二导电层420可电连接到从显示区DA延伸出的布线。
第二导电层420可以与源电极310和漏电极311布置在同一层上。可以通过使用相同的材料以相同的工艺形成第二导电层420、源电极310和漏电极311。
第二导电层420可具有多层结构。根据实施方式，第二导电层420包括具有多层的导电部分。第二导电层420包括第一导电部分421、第二导电部分422和第三导电部分423。
第一导电部分421可布置在第一导电层410上方。第一导电部分421包括Ti。第一导电部分421可以直接连接到第一导电层410。第二导电部分422可布置在第一导电部分421上方。第二导电部分422包括Al。第三导电部分423可布置在第二导电部分422上方。第三导电部分423包括Ti。以上已经描述了第二导电层420具有包括Ti/Al/Ti的堆叠结构的情况，但是可以对第二导电层420的堆叠结构进行各种修改。
在第二导电层420中所包括的相邻的第二导电层420a与420b之间，可布置有连接到驱动器的驱动终端(图6A的640)的至少一部分的夹持部分424。夹持部分424可以形成在第三绝缘膜333上，以在平面图中与第三绝缘膜333完全重叠。夹持部分424包括形成在相邻的第二导电层420a和420b中的底切425。
可以通过形成具有不同宽度的第一导电部分421、第二导电部分422和第三导电部分423来提供底切425。底切425可以形成在第二导电部分422中，其中第二导电部分422的宽度W2比第一导电部分421的宽度W1和第三导电部分423的宽度W3窄了约1μm至约20μm。第一导电部421的宽度W1可以基本上等于第三导电部423的宽度W3。
可以通过蚀刻工艺对第二导电层420进行图案化。当蚀刻第二导电层420时，第一导电部分421和第三导电部分423的蚀刻速率可以不同于第二导电部分422的蚀刻速率。例如，包含Al的第二导电部分422的蚀刻速率可以大于各自包含Ti的第一导电部分421和第三导电部分423的蚀刻速率。因此，底切425可以形成在相邻的第二导电层420a和420b的相对侧壁上，使得第二导电部分422具有凹进部分。
驱动器的驱动终端(图6A的640)可以牢固地连接到具有上述结构的焊盘400。
图6A是示出在驱动终端640连接到焊盘400(例如，图5的焊盘401)之前的状态的剖视图，以及图6B是示出当驱动终端640连接到焊盘400(例如，图6A的焊盘401)时的状态的剖视图。
参考图6A，驱动IC 610可布置在焊盘400上方。电路图案620可布置在驱动IC 610下方。绝缘膜630可覆盖电路图案620的一部分。驱动终端640可电连接到电路图案620。驱动终端640包括凸块(bump)641。凸块641可包含金(Au)、Cu或铟(In)。焊料层642可进一步布置在凸块641的尖端处。根据实施方式，焊料层642可以是熔融层。
粘合剂650可布置在焊盘400与驱动终端640之间。粘合剂650可以是非导电膜(NCF)。粘合剂650可以不包含导电材料。粘合剂650可以在焊盘400与驱动终端640之间提供粘附力。粘合剂650可以布置成围绕其中多个焊盘400中的每个焊盘401连接到与之对应的每个驱动终端640的区域。
可以使用热压结合工艺来执行焊盘400和凸块641的附接。当通过使用诸如热压焊机的热压结合处理设备从驱动IC 610上方施加一定热量和压力时，如图6B所示，设置在凸块641的尖端处的焊料层642被熔化，使得焊盘400电连接(或结合)到驱动终端640。
在结合之后，由于布置在其中多个焊盘400中的每个焊盘401连接到与之对应的驱动终端640的区域周围的粘合剂650的吸湿性，焊盘401与驱动终端640之间可发生分层。
根据本实施方式，由于包括底切425的夹持部分424布置在第二导电层420中所包括的相邻的第二导电层420a和420b的相对侧壁上，所以焊盘400中的每个焊盘401可以紧密地结合到与之对应的驱动终端640。
在结合期间，设置在凸块641的尖端处的焊料层642流到布置在相邻的第二导电层420a和420b的相对侧壁上的底切425中。焊料层642可以填充相邻的第二导电层420a与420b之间的间隙，并且可以接触相邻的第二导电层420a和420b的相对侧壁。
根据实施方式，设置在凸块641上的焊料层642可以在其中第一导电层410与第二导电层420接触的区域上方以及在相邻的第二导电层420a与420b之间延伸。
根据实施方式，设置在凸块641上的焊料层642可以完全覆盖相邻的第二导电层420a和420b。
根据实施方式，每个焊盘401通过设置在凸块641的尖端处的焊料层642与其所对应的驱动终端640进行表面接触。由于焊料层642填充相邻的第二导电层420a与420b之间的间隙，所以可以减小焊盘400与驱动终端640之间的接触阻抗。
随后，如果执行固化处理，则焊盘401可以牢固地连接到驱动终端640。
根据实施方式，可以将焊盘400修改为具有各种形状，只要设置在凸块641的尖端处的焊料层642可以填充各导电层之间的底切即可。
图12是根据实施方式的一个焊盘的平面图，以及图13是沿着图12的线XIII-XIII′截取的剖视图。参考图12和图13，第二导电层420形成为一个件并且在中央处具有移除部分。
图14是根据实施方式的一个焊盘的平面图，以及图15是沿着图14的线XV-XV′截取的剖视图。参考图14和图15，多个隔离的第二导电层420以矩阵构型布置在第一导电层410上。
图16是根据实施方式的一个焊盘的平面图，以及图17是沿着图16的线XVII-XVII′截取的剖视图。参考图16和图17，第二导电层420形成为网格形状，并且在第一导电层410上具有以矩阵形状布置的多个移除部分。
在下文中，将描述根据各实施方式连接到驱动终端640的至少一部分的夹持部分。
参考图7，连接到驱动终端640的至少一部分的夹持部分724可布置在第二导电层720中所包括的相邻的第二导电层720a与720b之间。夹持部分724包括布置在相邻的第二导电层720a和720b的相对侧壁上的底切725。第一导电层410可以与图3的栅电极308布置在同一层上。第二导电层720可以与图3的源电极310和漏电极311布置在同一层上。
第二导电层720可以是单一膜或多层膜。例如，第二导电层720包括至少一层的导电部分。底切725可对应于第二导电层720的侧壁倾斜的区域。
根据实施方式，第二导电层720可具有倒锥形形状。
参考图8，夹持部分824可布置在第二导电层820中所包括的相邻的第二导电层820a与820b之间。夹持部分824包括布置在相邻的第二导电层820a和820b的相对侧壁上的底切825。
第二导电层820包括至少一层的导电部分。底切825可对应于第二导电层820的侧壁弯曲的区域。
参考图9，夹持部分924可布置在第二导电层920中所包括的相邻的第二导电层920a与920b之间。夹持部分924包括布置在相邻的第二导电层920a和920b的相对侧壁上的底切925。
第二导电层920包括至少一层的导电部分。底切925可对应于第二导电层920的侧壁弯曲的区域。
不同于图8，第二导电层920上方可以进一步布置有第三导电层930。第一导电层410可以与图11的栅电极308布置在同一层上。第二导电层920可以与图11的第二电容器电极CE2布置在同一层上。第三导电层930可以与图11的源电极310和漏电极311布置在同一层上。
根据实施方式，可以通过将从图3和图11的栅电极308、源电极310、漏电极311、第一和第二电容器电极CE1和CE2、第一电极313和第二电极315中选择的多个电极进行组合，来对第一至第三导电层410、920和930进行各种修改。
参考图10，第二导电层1020上方可以进一步布置有第三导电层1030。夹持部分1024可布置在第二导电层1020中所包括的相邻的第二导电层1020a与1020b之间。夹持部分1024包括布置在相邻的第二导电层1020a和1020b的相对侧壁上的底切1025。
第二导电层1020包括至少一层的导电部分。底切1025可对应于第二导电层1020的宽度W2与第三导电层1030的宽度W3不同的区域。第二导电层1020的宽度W2可以窄于第三导电层1030的宽度W3。
第一导电层1010可以与图11的栅电极308布置在同一层上。第二导电层1020可以与图11的第二电容器电极CE2布置在同一层上。第三导电层1030可以与图11的源电极310和漏电极311布置在同一层上。
根据实施方式，可以通过将选自图3和图11的栅电极308、源电极310、漏电极311、第一和第二电容器电极CE1和CE2、第一电极313和第二电极315的多个电极进行组合，来对第一至第三导电层1010、1020和1030进行各种修改。
如上所述，根据一个或多个实施方式的显示设备能够改善焊盘与驱动终端之间的连接力。因此，可以改善焊盘与驱动终端之间的连接可靠性。
应当理解，本文描述的实施方式应当仅在描述性意义上进行考虑，而不是为了限制的目的。每个实施方式内的特征或方面的描述通常被认为可用于其他实施方式中的其他类似的特征或方面。
虽然已经参考附图描述了一个或多个实施方式，但是本领域普通技术人员将理解，在不脱离如由所附权利要求限定的精神的范围的情况下，可以在形式和细节上对这些实施方式进行各种改变。

Claims (13)

1.一种显示设备，包括：
显示基板；以及
多个焊盘，布置在所述显示基板上方，
其中所述多个焊盘中的每个焊盘包括：
第一导电层，所述第一导电层的至少一部分被绝缘膜覆盖；
第二导电层，布置在所述第一导电层上方；以及
夹持部分，形成在所述第二导电层中。
2.如权利要求1所述的显示设备，其中
所述第二导电层包括在所述第一导电层上方彼此间隔开的多个第二导电层。
3.如权利要求2所述的显示设备，其中
所述绝缘膜包括暴露所述第一导电层的顶表面的多个接触孔，以及
所述多个第二导电层通过所述接触孔电连接到所述第一导电层。
4.如权利要求2所述的显示设备，其中
所述夹持部分包括布置在相邻的所述第二导电层的相对侧壁上的底切。
5.如权利要求4所述的显示设备，其中
所述第二导电层包括多层导电部分，以及
通过使所述多层导电部分形成为具有不同宽度来提供所述底切。
6.如权利要求5所述的显示设备，其中
所述第二导电层包括：
第一导电部分，连接到所述第一导电层；
第二导电部分，布置在所述第一导电部分上方；以及
第三导电部分，布置在所述第二导电部分上方，以及
所述底切对应于所述第二导电部分的宽度窄于所述第一导电部分的宽度和所述第三导电部分的宽度的区域。
7.如权利要求4所述的显示设备，其中
所述第二导电层包括至少一层导电部分，以及
所述底切对应于所述第二导电层的侧壁倾斜的区域。
8.如权利要求4所述的显示设备，其中
所述第二导电层包括至少一层导电部分，以及
所述底切对应于所述第二导电层的侧壁弯曲的区域。
9.如权利要求8所述的显示设备，还包括：
第三导电层，布置在所述第二导电层上方。
10.如权利要求4所述的显示设备，其中
所述第二导电层包括至少一层导电部分，
所述显示设备还包括布置在所述第二导电层上方的第三导电层，并且
在所述底切中，所述第二导电层的宽度窄于所述第三导电层的宽度。
11.如权利要求1所述的显示设备，其中
所述显示基板包括：
至少一个薄膜晶体管，包括位于所述显示基板上方的半导体有源层、栅电极、源电极和漏电极；
有机发光显示装置，电连接到所述薄膜晶体管，所述有机发光显示装置包括第一电极、发射层和第二电极；以及
至少一层绝缘膜，布置在所述薄膜晶体管与所述有机发光显示装置之间，以及
所述第一导电层连接到从所述栅电极、所述源电极、所述漏电极、所述第一电极和所述第二电极中的任一者延伸出的布线，并且所述第二导电层配置成在所述第一导电层上方具有岛形状。
12.如权利要求11所述的显示设备，其中
所述第一导电层由与所述栅电极的材料相同的材料形成，以及
所述第二导电层由与所述源电极和所述漏电极的材料相同的材料形成。
13.如权利要求11所述的显示设备，还包括：
第三导电层，布置在所述第二导电层上方，
其中所述第一导电层至所述第三导电层是选自所述栅电极、所述源电极、所述漏电极、所述第一电极和所述第二电极中的多个电极的组合。
CN201710493745.XA 2016-06-24 2017-06-26 显示设备 Active CN107546242B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160079286A KR102663140B1 (ko) 2016-06-24 디스플레이 장치
KR10-2016-0079286 2016-06-24

Publications (2)

Publication Number Publication Date
CN107546242A true CN107546242A (zh) 2018-01-05
CN107546242B CN107546242B (zh) 2023-09-08

Family

ID=59239790

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710493745.XA Active CN107546242B (zh) 2016-06-24 2017-06-26 显示设备

Country Status (4)

Country Link
US (1) US11171194B2 (zh)
EP (1) EP3261143A1 (zh)
CN (1) CN107546242B (zh)
TW (1) TWI747914B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035908A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102591811B1 (ko) * 2018-05-18 2023-10-23 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이의 제조 방법 및 이를 포함하는 표시 장치
CN116387270A (zh) * 2019-06-11 2023-07-04 群创光电股份有限公司 电子装置
KR20210106605A (ko) * 2020-02-20 2021-08-31 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050032349A1 (en) * 2001-03-05 2005-02-10 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20070075313A1 (en) * 2005-09-30 2007-04-05 Won-Kyu Kwak Flat panel display device
US20110291119A1 (en) * 2010-05-28 2011-12-01 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
US20130026476A1 (en) * 2011-07-28 2013-01-31 Sun Park Organic light emitting display apparatus
US20140042394A1 (en) * 2012-08-09 2014-02-13 Samsung Display Co., Ltd. Organic Light-Emitting Display Apparatus and Method of Manufacturing Organic Light-Emitting Display Apparatus
US20140042397A1 (en) * 2012-08-10 2014-02-13 Lg Display Co., Ltd. Organic light emitting diode display device and method of fabricating the same
US20140327133A1 (en) * 2013-05-06 2014-11-06 Himax Technologies Limited Metal bump structure for use in driver ic and method for forming the same
US20150008438A1 (en) * 2013-07-04 2015-01-08 Samsung Display Co. Ltd. Display device
US20150378202A1 (en) * 2013-12-31 2015-12-31 Shenzhen China Star Optoelectronics Technology Co. Ltd. Liquid crystal panel and manufacturing method of the liquid crystal panel
EP2966705A1 (en) * 2014-07-11 2016-01-13 LG Display Co., Ltd. Organic light-emitting diode display device and method of fabricating the same
US20160070314A1 (en) * 2014-09-05 2016-03-10 Semiconductor Energy Laboratory Co., Ltd. Display Panel, Input/output Device, and Data Processor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2555987B2 (ja) * 1994-06-23 1996-11-20 日本電気株式会社 アクティブマトリクス基板
US5705885A (en) 1994-11-25 1998-01-06 Kabushiki Kaisha Toshiba Brazing structure for X-ray image intensifier
US5705855A (en) 1995-01-13 1998-01-06 Motorola, Inc. Integrated circuit for directly attaching to a glass substrate and method for manufacturing the same
US5937320A (en) 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
JP2000151057A (ja) 1998-11-09 2000-05-30 Hitachi Ltd 電子部品実装構造体およびその製造方法並びに無線ｉｃカードおよびその製造方法
JP2001109395A (ja) 1999-10-01 2001-04-20 Sanyo Electric Co Ltd Ｅｌ表示装置
KR100790144B1 (ko) 2002-01-04 2007-12-31 삼성전자주식회사 볼 그리드 어레이 패키지의 솔더 볼 및 이를 실장하기위한 피씨비 패드 제조방법
US6774026B1 (en) * 2002-06-20 2004-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for low-stress concentration solder bumps
JP2005070360A (ja) 2003-08-22 2005-03-17 Sony Corp 電気回路基板
KR20060134662A (ko) 2005-06-23 2006-12-28 엘지.필립스 엘시디 주식회사 씨오지 방식의 액정표시장치
KR101131230B1 (ko) 2009-05-06 2012-03-28 삼성전기주식회사 범프 지지부를 갖는 인쇄회로기판 및 그 제조방법
US8647974B2 (en) 2011-03-25 2014-02-11 Ati Technologies Ulc Method of fabricating a semiconductor chip with supportive terminal pad

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050032349A1 (en) * 2001-03-05 2005-02-10 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20070075313A1 (en) * 2005-09-30 2007-04-05 Won-Kyu Kwak Flat panel display device
US20110291119A1 (en) * 2010-05-28 2011-12-01 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
US20130026476A1 (en) * 2011-07-28 2013-01-31 Sun Park Organic light emitting display apparatus
US20140042394A1 (en) * 2012-08-09 2014-02-13 Samsung Display Co., Ltd. Organic Light-Emitting Display Apparatus and Method of Manufacturing Organic Light-Emitting Display Apparatus
US20140042397A1 (en) * 2012-08-10 2014-02-13 Lg Display Co., Ltd. Organic light emitting diode display device and method of fabricating the same
US20140327133A1 (en) * 2013-05-06 2014-11-06 Himax Technologies Limited Metal bump structure for use in driver ic and method for forming the same
US20150008438A1 (en) * 2013-07-04 2015-01-08 Samsung Display Co. Ltd. Display device
US20150378202A1 (en) * 2013-12-31 2015-12-31 Shenzhen China Star Optoelectronics Technology Co. Ltd. Liquid crystal panel and manufacturing method of the liquid crystal panel
EP2966705A1 (en) * 2014-07-11 2016-01-13 LG Display Co., Ltd. Organic light-emitting diode display device and method of fabricating the same
US20160070314A1 (en) * 2014-09-05 2016-03-10 Semiconductor Energy Laboratory Co., Ltd. Display Panel, Input/output Device, and Data Processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035908A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置

Also Published As

Publication number Publication date
US11171194B2 (en) 2021-11-09
TWI747914B (zh) 2021-12-01
CN107546242B (zh) 2023-09-08
TW201810757A (zh) 2018-03-16
KR20180001640A (ko) 2018-01-05
EP3261143A1 (en) 2017-12-27
US20170373028A1 (en) 2017-12-28

Similar Documents

Publication Publication Date Title
US11605697B2 (en) Display apparatus having grooved terminals
CN107492565B (zh) 显示装置
US10748853B2 (en) Flexible display device
US9997487B2 (en) Display device with improved anisotropic conductive film
KR20180047536A (ko) 유기발광 표시장치
CN107546242A (zh) 显示设备
KR102322766B1 (ko) 디스플레이 장치
KR20170140764A (ko) 디스플레이 장치
KR102575480B1 (ko) 디스플레이 장치
KR102663140B1 (ko) 디스플레이 장치
EP4311391A1 (en) Display device and method of providing the same
US20240121989A1 (en) Display device and method of manufacturing the same
KR20240001764A (ko) 표시 장치 및 이의 제조 방법
KR20180046511A (ko) 유기발광 표시장치

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant