TWI600129B - 玻璃覆晶接合結構 - Google Patents

玻璃覆晶接合結構 Download PDF

Info

Publication number
TWI600129B
TWI600129B TW103113751A TW103113751A TWI600129B TW I600129 B TWI600129 B TW I600129B TW 103113751 A TW103113751 A TW 103113751A TW 103113751 A TW103113751 A TW 103113751A TW I600129 B TWI600129 B TW I600129B
Authority
TW
Taiwan
Prior art keywords
layer
glass
chip bonding
cap layer
bonding structure
Prior art date
Application number
TW103113751A
Other languages
English (en)
Other versions
TW201444037A (zh
Inventor
林久順
Original Assignee
奇景光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 奇景光電股份有限公司 filed Critical 奇景光電股份有限公司
Publication of TW201444037A publication Critical patent/TW201444037A/zh
Application granted granted Critical
Publication of TWI600129B publication Critical patent/TWI600129B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • H01L2224/03614Physical or chemical etching by chemical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • H01L2224/05582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825Plating, e.g. electroplating, electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1355Shape
    • H01L2224/13551Shape being non uniform
    • H01L2224/13552Shape being non uniform comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1357Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13575Plural coating layers
    • H01L2224/1358Plural coating layers being stacked
    • H01L2224/13582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Led Device Packages (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

玻璃覆晶接合結構
本發明大致上關於一種玻璃覆晶接合結構。本發明特別是關於一種包含帽蓋層與導電粒子層彼此直接接觸之玻璃覆晶接合結構。
因應當今消費性電子產品的輕、薄、短、小趨勢,電子組裝技術亦隨著不斷改進。近幾年來,半導體封裝技術已發展趨於多樣,例如用於顯示器之驅動積體電路(IC)之封裝技術。
覆晶接合技術正是此種積體電路的封裝技術。例如,玻璃覆晶接合(chip-on-glass,COG)技術是運用玻璃作為封裝晶片的載體,將晶片上的金凸塊(Gold bump)與透明導電引腳(lead)經由例如異方性導電膠膜(anisotropic conductive film,ACF)的導電性膠膜相接合(bonding)的技術。
使用金凸塊的優勢在於,黃金具有極低的化學活性,使得封裝後的積體電路的可靠度十分穩定。但是,由於原物料成本不斷地增加,所以使用屬於貴金屬的黃金作為晶片上凸塊(bump)的材料,就很難具有價格競爭上的優勢。
本發明於是提出一種玻璃覆晶接合結構。在此玻璃覆晶接合結構中,使用帽蓋層來完全覆蓋金屬凸塊。另外,玻璃基板上之引腳層,則使用導電粒子層來作為外導電(outward electrically connecting)的媒介。特別是,導電粒子層與帽蓋層直接接觸。
本發明之玻璃覆晶接合結構,包含金屬銲墊、護層、黏著層、金 屬凸塊、帽蓋層、與基板。位於金屬銲墊上之護層,定義出位於金屬銲墊上之凹穴。完全位於凹穴中之黏著層則位於金屬銲墊上,又部份位於護層上。黏著層直接接觸金屬銲墊與護層。金屬凸塊部份位於凹穴中並覆蓋黏著層。帽蓋層位於金屬凸塊上並完全覆蓋金屬凸塊,而使得金屬凸塊完全不會暴露出來。用來電連接帽蓋層的基板,包含玻璃層、引腳(lead)層、與導電粒子層(conductive particle layer)。引腳層與玻璃層直接相連。導電粒子層用來電連接帽蓋層與引腳層。
在本發明一實施方式中,帽蓋層自行對準於金屬凸塊。
在本發明另一實施方式中,帽蓋層、黏著層、與護層間具有嵌穴(notch)。
在本發明另一實施方式中,金屬凸塊由銅或金所組成。
在本發明另一實施方式中,當金屬凸塊由銅所組成時,帽蓋層包含錫、鎳、金、鈀其中至少一者。當金屬凸塊由金所組成時,帽蓋層包含錫、鎳、鈀其中至少一者。
在本發明另一實施方式中,帽蓋層與金屬凸塊形成合金,而防止金屬凸塊穿出帽蓋層。
在本發明另一實施方式中,帽蓋層與金屬凸塊之界面沒有合金。
在本發明另一實施方式中,帽蓋層為複合結構。
在本發明另一實施方式中,引腳層由透明導電材料所組成。
在本發明另一實施方式中,導電粒子層包含異方性導電膠。
在本發明另一實施方式中,導電粒子層之面積不小於帽蓋層之面積。
在本發明另一實施方式中,導電粒子層與帽蓋層對齊。
在本發明另一實施方式中,導電粒子層與帽蓋層形成異方性導電連接。
在本發明另一實施方式中,導電粒子層直接接觸該帽蓋層。
在本發明另一實施方式中,玻璃覆晶接合結構更包含位於護層與玻璃層間之樹脂,而夾住並密封引腳層與金屬凸塊。
在本發明另一實施方式中,樹脂層直接接觸引腳層與帽蓋層。
在本發明另一實施方式中,樹脂層填入嵌穴中。
在本發明另一實施方式中,玻璃覆晶接合結構位於顯示器中。
1‧‧‧玻璃覆晶接合結構
9‧‧‧金屬凸塊結構
10‧‧‧底材
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
14’‧‧‧光阻層
14‧‧‧圖案化光阻層
15‧‧‧凹穴
16‧‧‧開口
20’‧‧‧金屬凸塊材料
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層
41‧‧‧合金
42‧‧‧內層
43‧‧‧最外層
50‧‧‧玻璃板
51‧‧‧玻璃層
52‧‧‧引腳層
53‧‧‧導電粒子層
53’‧‧‧導電粒子
60‧‧‧封膠
第1圖至第13圖繪示本發明形成玻璃覆晶接合結構的方法。
第8A圖繪示僅帽蓋層40的內層42填滿嵌穴30。
第10A圖繪示僅帽蓋層40的內層42填滿嵌穴30。
第14圖繪示本發明之玻璃覆晶接合結構的一種實例。
第15圖繪示本發明之玻璃覆晶接合結構的另一種實例。
本發明首先提供一種形成玻璃覆晶接合結構的方法,可以將驅動積體電路晶片(driver IC)與顯示器之電路進行電連接,特別適用於玻璃覆晶接合封裝(chip-on-glass,COG)技術中。第1圖至第13圖繪示本發明形成玻璃覆晶接合結構的方法。首先,在第一方面先說明如何將金屬凸塊形成在底材上。如第1圖所繪示,提供底材10。底材10包括金屬銲墊11、護層12與黏著層13。
絕緣層9為底材10之基礎部份,用來支撐其它之元件,例如用來支撐金屬銲墊11、護層12、黏著層13與第3圖中之圖案化光阻層14。金屬銲墊11可以是一種質輕之金屬材料,例如鋁,並經過圖案化。但是,其它之金屬亦可採用,而並不限於鋁。
護層12即位於金屬銲墊11之上,同時還具有圖案以定義凹穴15,使得凹穴15亦位於金屬銲墊11之上。護層12可以是一種電絕緣之材料, 例如氮化矽或是氧化矽。通常來說,凹穴15的大小會小於金屬銲墊11的大小。
黏著層13又位於凹穴15之中。此外,黏著層13還會覆蓋金屬銲墊11與護層12,使得黏著層13會直接接觸金屬銲墊11與護層12。黏著層13用來幫助後續形成之金屬凸塊材料(圖未示)牢牢地附著在凹穴15之中。黏著層13可以是一種合金層,例如鈦鎢合金層。
黏著層13的形成方法可以是,利用濺鍍一層鈦鎢合金與晶種層,例如銅的方法,來均勻地覆蓋底材10,例如完全地覆蓋金屬銲墊11、護層12、與凹穴15。結果例示於第1圖中。形成圖案化光阻層14之方式,可以參考如下所示之方式。
其次,如第2圖所繪示,將光阻層14’整體形成在黏著層13上,並同時填滿凹穴15。光阻層14’可以是光敏性的材料,例如是有機的光敏材料。
再來,如第3圖所繪示,將光阻層14’圖案化。圖案化的光阻層14是形成在黏著層13上來定義出開口16。開口16用來暴露出位於凹穴15中與護層12上的黏著層13,因此,在本發明之一實施例中,開口16會稍微大於凹穴15。換句話說,開口16可以用來定義出後續所形成之金屬凸塊材料(圖未示)所在的空間,而此空間本身即容置了凹穴15。
然後,整體的光阻層14’會經過適當的曝光與顯影步驟,而轉換成圖案化光阻層14,而具有曝光與顯影所賦與預定的圖案。圖案是經由開口16所定義出的,其結果即繪示於第3圖所中。
接下來,如第4圖所繪示,使用金屬凸塊材料20’來填入開口16中。請注意,金屬凸塊材料20’可能只僅僅填入開口16中,而沒有填滿開口16。黏著層13即因此夾置於金屬凸塊材料20’,與金屬銲墊11或護層12之間。例如,由於金屬銲墊11與黏著層13均為導電性材料,所以金屬凸塊材料20’可以由電鍍之方式來形成。視情況需要,金屬凸塊材料20’可以是鈀、 銀、銅或是金,以尋求較佳之導電性,與越低越好之化學活性。
一但將金屬凸塊材料20’形成好了之後,就不再需要圖案化光阻 層14了。於是,如第5圖所繪示,移除圖案化光阻層14,使得金屬凸塊材料20’成為各自獨立之金屬凸塊20。可以使用傳統的方式來移除圖案化光阻層14。於是,各自獨立之金屬凸塊20於是完全位於黏著層13之上,並直接接觸黏著層13。
由於黏著層13是導電性的,這會導致所有的金屬凸塊20彼此短 路,所以多於的黏著層13必須要移除。再來,如第6圖所繪示,沒有被金屬凸塊20所覆蓋的黏著層13經由蝕刻步驟來移除,又部份地暴露出下方之護層12,使得所有的金屬凸塊20,藉由電絕緣材料,亦即護層12的隔離,成為彼此電絕緣。如此一來,所有的金屬凸塊20即自我對準於黏著層13。例如,可以使用過氧化氫來蝕刻黏著層13。視情況需要,蝕刻步驟後還可以加熱金屬凸塊20,例如在250℃-300℃之退火條件下維持約30分鐘,來將金屬凸塊20調整到所需的硬度,例如不超過130維氏硬度(Hv),較佳者不大於110維氏硬度,更佳者介於50維氏硬度至110維氏硬度之間。
此時可以注意到,在第6圖中,在移除黏著層13時,在金屬凸塊 20、黏著層13、與護層12之間又形成了一嵌穴30,因為蝕刻步驟不只會完全移除沒有被金屬凸塊20所覆蓋的黏著層13,蝕刻步驟還會更進一步移除沒有被金屬凸塊20所覆蓋的黏著層13以外的黏著層13,例如,夾置於金屬凸塊20、與護層12間之黏著層13。而結果是,在金屬凸塊20、黏著層13、與護層12之間形成了一只嵌穴30,其成為本發明結構的特徵之一。嵌穴30可能橫向深入1微米(μm)-2微米左右。
由於各自獨立之金屬凸塊20仍然因為暴露於周圍的大氣環境中 而失之脆弱,所以需要再特意形成帽蓋層來完全覆蓋金屬凸塊20,使得金屬凸塊20不會暴露於周圍的大氣環境中。請參考第7圖、第8圖、第8A圖所繪示,形成帽蓋層40來完全覆蓋金屬凸塊20,於是得到受保護的金屬凸塊 結構9。帽蓋層40可以包含內層42、最外層43之多種保護性的材料。如果是銅製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。 如果是金製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、鈀其中至少一者。 如果是銀製成的金屬凸塊20,帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊20,帽蓋層40可以包含錫。帽蓋層40可以不含鎳。不過,如第7圖所繪示,所形成帽蓋層40可能只會減小嵌穴30的尺寸,或是如第8圖所繪示,因為內層42與最外層43一起完全填滿了嵌穴30,使得嵌穴30消失不見,或是如第8A圖所繪示,僅僅是帽蓋層40的內層42填滿嵌穴30。
較佳者,可以經由無電極電鍍法來形成帽蓋層40,例如可以在小 於4之酸鹼值、硫酸鹽之輔助下進行無電極電鍍法。由於護層12是一種電絕緣材料,帽蓋層40只會特定而專一地形成在金屬凸塊20上。換句話說,帽蓋層40即自我對準在金屬凸塊20上。帽蓋層40可以是單層結構或是複合結構,而包含多層之帽蓋材料,例如帽蓋層40可以不含鎳。另外,依據無電極電鍍法的不同電鍍配方或是電鍍條件,帽蓋層40還可以有不同的厚度與其它的形狀。例如,帽蓋層40可能是合金41、內層42、與最外層43之搭配或組合。較佳者,最外層43為金,其優點在於有利於重工(re-work),又可以減低材料的成本。當帽蓋層40含鈀時,鈀層的厚度可以是0.15微米-0.4微米左右。當帽蓋層40含金時,金層的厚度可以是在2微米以下,較佳者不大於0.1微米,甚至於可以只有0.006微米而已。表1列舉電鍍帽蓋層40之可行步驟與製程參數。其中在每個步驟之後,均可以再加入純水洗滌之清潔步驟。
在本發明之一實施例中,帽蓋層40會完全包覆金屬凸塊20但又 不與金屬凸塊20形成伴生之合金層,例如銅不容易與鎳或鈀形成伴生之合金層。在本發明之一實施例中,又可以進行一熟化(curing)步驟,使得帽蓋層40會完全包覆金屬凸塊20而且與金屬凸塊20形成合金。例如,請參考第9圖或第10圖所繪示,形成在金屬凸塊20上的帽蓋層40被加熱到,例如在150℃~180℃與30分鐘之條件下,與金屬凸塊20形成合金41。第9圖繪示,帽蓋層40只會減小嵌穴30的尺寸。第10圖所繪示,內層42與最外層43一起使得嵌穴30消失不見、或是如第10A圖所繪示,僅僅是帽蓋層40的內層42填滿嵌穴30。銅與錫在不同的條件下,可以形成多種的合金,例如Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3
合金41的形成,刻意用來防止金屬凸塊20在極端的情形下可能 穿過帽蓋層40。在帽蓋層40的保護下,不管有或是沒有合金41,金屬凸塊20都不會暴露於周圍的大氣環境中。
接下來,另一方面將說明如何將金屬凸塊20與玻璃板(glass plate) 形成電連接。首先,如第11圖所繪示,提供玻璃板50。玻璃板50包含有玻璃層51、引腳(lead)層52、與導電粒子層(conductive particle layer)53的一種基板。基板用來與金屬凸塊20形成電連接。玻璃板50即作為金屬凸塊20的支撐結構。玻璃層51是玻璃覆晶接合封裝所用的玻璃材料。引腳層52位於玻璃層51上並與玻璃層51直接相連。引腳層52較佳是透明的導電材料,例如銦錫氧化物(ITO)、摻鋁氧化鋅(AZO)、摻鎵氧化鋅(GZO)、摻銦氧化鋅(IZO)等。導電粒子層53會部分覆蓋引腳層52,例如只覆蓋接觸面,而其中之導電粒子53’即使得導電粒子層53具有導電性。導電粒子層53 較佳為異方性導電膠,而每個金屬凸塊20(例如接觸面為1000平方微米(μm))上會帶有至少3個導電粒子53’。
其次,如第12圖所繪示,將玻璃板50上的引腳層52對準底材 10上的金屬凸塊20,來將引腳層52與金屬凸塊20彼此對準貼合在一起。如第13圖所繪示,經過適當時間與溫度的壓合,將引腳層52與金屬凸塊20的接觸面彼此對準貼合在一起。於是導電粒子層53中的導電粒子53’可以同時接觸引腳層52與帽蓋層40的接觸面,而得到導電粒子53’電連接引腳層52與帽蓋層40的結果。
還有,如第14圖所繪示,為了能將引腳層52與金屬凸塊20接合 能更加密封牢固,還可以塗上封膠60,使得封膠塗在玻璃板50與護層12之間,來密封引腳層52與金屬凸塊20。所使用的封膠種類,例如可以是以環氧樹脂(epoxy)為主要材料底部填充膠(underfill),利用毛細作用填入玻璃板50與護層12之間的空隙,所以塗上封膠的步驟可以在引腳層52與金屬凸塊20彼此對準貼合在一起之前進行,或是在引腳層52與金屬凸塊20彼此對準貼合在一起之後才進行。由於封膠60填入玻璃板50與護層12之間的空隙,所以可以密封引腳層52與金屬凸塊20。封膠60也可能填入嵌穴30中。
在經過以上之步驟後,就可以得到一種玻璃覆晶接合結構1,如 第14圖或第15圖所繪示。本發明之玻璃覆晶接合結構1,包含底材10、金屬銲墊11、護層12、黏著層13、金屬凸塊20、帽蓋層40、玻璃板50、導電粒子層53與封膠60。絕緣層9為底材10之基礎部份,用來支撐其它之元件,例如金屬銲墊11、護層12與黏著層13。金屬銲墊11可以是一種質輕之金屬材料,例如鋁,並經過圖案化。但是,其它之金屬亦可採用,而並不限於鋁。 護層12可以是一種電絕緣之材料,例如氮化矽或是氧化矽。黏著層13可以是一種合金層,例如鈦鎢合金層,用來幫助金屬凸塊20牢牢地附著在凹穴15之中,所以黏著層13會直接接觸金屬銲墊11與護層12。
金屬凸塊20部份位於凹穴15中並覆蓋黏著層13,而可以是鈀、 銀、銅或是金,以尋求較佳之導電性,與越低越好之化學活性。還有,在金屬凸塊20、黏著層13、與護層12之間還可能會有一只嵌穴30,其成為本發明結構的特徵之一。
帽蓋層40位於金屬凸塊20上並完全覆蓋金屬凸塊20,而使得金 屬凸塊20完全不會暴露出來。帽蓋層40可以是單層結構或是複合結構。如第14圖所繪示,單層結構的帽蓋層40只會完全包覆金屬凸塊20,但又不與金屬凸塊20形成伴生之合金層,例如銅不容易與鎳或鈀形成伴生之合金層。 或是如第15圖所繪示,複合結構之帽蓋層40,可以包含多層之帽蓋材料,例如合金41、內層42及/或外層43。帽蓋層40可能會減小嵌穴30的尺寸,或是因為完全填滿了嵌穴30,而使得嵌穴30消失不見,如第8圖所繪示。
帽蓋層40可以包含多種保護性的材料,而可能是合金41、內層 42、與最外層43之組合。如果是銅製成的金屬凸塊,帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的金屬凸塊,帽蓋層40可以包含錫、鎳、鈀其中至少一者。如果是銀製成的金屬凸塊,帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊,帽蓋層40可以包含錫。帽蓋層40也可以不含鎳。 與金屬凸塊20直接接觸之帽蓋材料,例如內層42,可以與金屬凸塊20形成合金41。銅與錫在不同的條件下,可以形成多種的合金,例如Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3。合金41的形成,刻意用來防止金屬凸塊20在極端的情形下可能穿過帽蓋層40。
玻璃板50是包含有玻璃層51、引腳層52、與導電粒子層53的一種基板。玻璃板50即作為金屬凸塊20的支撐結構。玻璃層51是玻璃覆晶接合封裝所用的玻璃材料。引腳層52位於玻璃層51上並與玻璃層51直接相連。引腳層52較佳是透明的導電材料,例如銦錫氧化物(ITO)、摻鋁氧化鋅(AZO)、摻鎵氧化鋅(GZO)、摻銦氧化鋅(IZO)等。導電粒子層53會部分覆蓋引腳層52,而其中之導電粒子53’即使得導電粒子層53具有導電性。導電粒子層53較佳為異方性導電膠,而每個金屬凸塊20(例如接觸面為1000 平方微米(μm))上會帶有至少3個導電粒子53’。
封膠60塗在玻璃板50與護層12之間,來密封引腳層52與金屬凸塊20。所使用的封膠種類,例如可以是以環氧樹脂為主要材料底部填充膠。由於封膠60填入玻璃板50與護層12之間的空隙,所以可以密封引腳層52與金屬凸塊20,封膠60也可能填入嵌穴30中與直接接觸引腳層52/導電粒子層53。
1‧‧‧玻璃覆晶接合結構
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層
41‧‧‧合金
42‧‧‧內層
43‧‧‧最外層
50‧‧‧玻璃板
51‧‧‧玻璃層
52‧‧‧引腳層
53‧‧‧導電粒子層
53’‧‧‧導電粒子
60‧‧‧封膠

Claims (15)

  1. 一種玻璃覆晶接合(Chip on Glass,COG)結構,包含:一金屬銲墊;一護層,位於該金屬銲墊上,並定義出位於該金屬銲墊上之一凹穴;一黏著層,位於該凹穴中、位於該金屬銲墊上、又部份位於該護層上,其中該黏著層直接接觸該金屬銲墊與該護層;一金屬凸塊,由銅所組成,部份位於該凹穴中並覆蓋該黏著層;一帽蓋層,位於該金屬凸塊上並完全覆蓋該金屬凸塊,而使得該金屬凸塊不會暴露出來,其中該帽蓋層自行對準於該金屬凸塊;一基板,用來電連接該帽蓋層,其包含:一玻璃層;一引腳(lead)層,與該玻璃層直接相連;一導電粒子層(coductive layer),電連接該帽蓋層與該引腳層,其中該導電粒子層與該帽蓋層對齊。
  2. 如請求項1之玻璃覆晶接合結構,其中該帽蓋層、該黏著層、與該護層間具有一嵌穴(notch)。
  3. 如請求項1之玻璃覆晶接合結構,其中該帽蓋層包含錫、鎳、金、鈀其中至少一者。
  4. 如請求項1之玻璃覆晶接合結構,其中該帽蓋層與該金屬凸塊形成一合金,而防止該金屬凸塊穿出該帽蓋層。
  5. 如請求項1之玻璃覆晶接合結構,其中該帽蓋層與該金屬凸塊之界面沒有合金。
  6. 如請求項1之玻璃覆晶接合結構,其中該帽蓋層為一複合結構。
  7. 如請求項1之玻璃覆晶接合結構,其中該引腳層由透明導電材料所組成。
  8. 如請求項1之玻璃覆晶接合結構,其中該導電粒子層包含異方性導電膠。
  9. 如請求項1之玻璃覆晶接合結構,其中該導電粒子層之面積不小於該帽蓋層之面積。
  10. 如請求項1之玻璃覆晶接合結構,其中每個該金屬凸塊上有至少3個導電粒子層中的導電粒子。
  11. 如請求項1之玻璃覆晶接合結構,其中該導電粒子層直接接觸該帽蓋層。
  12. 如請求項1之玻璃覆晶接合結構,更包含:一樹脂,位於該護層與該玻璃層之間,而夾住並密封該引腳層與該金屬凸塊。
  13. 如請求項12之玻璃覆晶接合結構,其中該樹脂層直接接觸該引腳層與該帽蓋層。
  14. 如請求項12之玻璃覆晶接合結構,其中該帽蓋層、該黏著層、與該護層間具有一嵌穴(notch),該樹脂層填入該嵌穴中。
  15. 如請求項1之玻璃覆晶接合結構,在一顯示器中。
TW103113751A 2013-05-06 2014-04-15 玻璃覆晶接合結構 TWI600129B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361820152P 2013-05-06 2013-05-06

Publications (2)

Publication Number Publication Date
TW201444037A TW201444037A (zh) 2014-11-16
TWI600129B true TWI600129B (zh) 2017-09-21

Family

ID=51841032

Family Applications (3)

Application Number Title Priority Date Filing Date
TW103113751A TWI600129B (zh) 2013-05-06 2014-04-15 玻璃覆晶接合結構
TW103115992A TWI573205B (zh) 2013-05-06 2014-05-05 金屬凸塊結構
TW103116132A TWI600130B (zh) 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW103115992A TWI573205B (zh) 2013-05-06 2014-05-05 金屬凸塊結構
TW103116132A TWI600130B (zh) 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法

Country Status (4)

Country Link
US (2) US9450061B2 (zh)
KR (3) KR101611376B1 (zh)
CN (4) CN104143538B (zh)
TW (3) TWI600129B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
JP6250864B2 (ja) * 2015-03-10 2017-12-20 三菱電機株式会社 パワー半導体装置
KR102663140B1 (ko) * 2016-06-24 2024-05-08 삼성디스플레이 주식회사 디스플레이 장치
KR102508527B1 (ko) 2016-07-01 2023-03-09 삼성전자주식회사 필름형 반도체 패키지
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
IT201700087309A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
US10522501B2 (en) * 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10741482B2 (en) 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP7122593B2 (ja) * 2018-05-08 2022-08-22 パナソニックIpマネジメント株式会社 半導体装置の製造方法、半導体装置の製造装置、及び半導体装置
US11469194B2 (en) * 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
CN110854066A (zh) * 2019-11-28 2020-02-28 无锡微视传感科技有限公司 一种半导体电镀方法
WO2021184188A1 (zh) * 2020-03-17 2021-09-23 元锦生物科技股份有限公司 可拆式接合结构
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205099A (en) * 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
AU2003269066A1 (en) * 2002-05-16 2003-12-02 Agency For Science, Technology And Research Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
US7008867B2 (en) 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JP2007531247A (ja) * 2003-07-16 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 側壁用絶縁体を有する金属バンプ及びこのような金属バンプを有するチップを製造する方法
TWI222198B (en) 2003-09-04 2004-10-11 Fupo Electronics Corp Fine pitch gold bump fabrication process and its package article
JP4718809B2 (ja) 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
KR100642765B1 (ko) * 2004-09-15 2006-11-10 삼성전자주식회사 하이브리드 범프를 포함하는 미세전자소자칩, 이의패키지, 이를 포함하는 액정디스플레이장치 및 이러한미세전자소자칩의 제조방법
TWI286454B (en) * 2005-03-09 2007-09-01 Phoenix Prec Technology Corp Electrical connector structure of circuit board and method for fabricating the same
KR100801073B1 (ko) 2005-10-06 2008-02-11 삼성전자주식회사 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법
US7601566B2 (en) 2005-10-18 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
JP2007317979A (ja) * 2006-05-29 2007-12-06 Toshiba Corp 半導体装置の製造方法
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
KR20080102545A (ko) 2007-05-21 2008-11-26 주식회사 엘지화학 Cof 실장용 2층 동박 적층판 및 그 제조 방법
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
TW201044527A (en) * 2009-06-11 2010-12-16 Int Semiconductor Tech Ltd Chip architecture having film-faced metal bumps and semiconductor flip-chip device applied from the same
TWI469288B (zh) 2009-06-11 2015-01-11 Chipbond Technology Corp 凸塊化晶片結構及其應用之半導體覆晶裝置
KR20110090332A (ko) 2010-02-03 2011-08-10 한양대학교 산학협력단 이방성 전도 필름을 이용하여 기판이 접합된 반도체 소자 및 기판 접합방법
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
KR20120139115A (ko) * 2011-06-16 2012-12-27 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US8643196B2 (en) * 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
JP6035714B2 (ja) 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US20130193570A1 (en) * 2012-02-01 2013-08-01 Chipbond Technology Corporation Bumping process and structure thereof
US8501614B1 (en) * 2012-03-22 2013-08-06 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US9646951B2 (en) * 2013-12-10 2017-05-09 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor

Also Published As

Publication number Publication date
US20140327133A1 (en) 2014-11-06
KR101611376B1 (ko) 2016-04-11
CN104143538B (zh) 2018-01-02
KR101611846B1 (ko) 2016-04-12
CN104143540A (zh) 2014-11-12
CN104143540B (zh) 2017-05-03
KR20140131876A (ko) 2014-11-14
KR101641993B1 (ko) 2016-07-22
US9450061B2 (en) 2016-09-20
CN104143539B (zh) 2018-04-10
KR20140131884A (ko) 2014-11-14
US20140327134A1 (en) 2014-11-06
CN104143539A (zh) 2014-11-12
TW201444042A (zh) 2014-11-16
TWI573205B (zh) 2017-03-01
KR20140131871A (ko) 2014-11-14
TWI600130B (zh) 2017-09-21
TW201444037A (zh) 2014-11-16
CN104143543A (zh) 2014-11-12
TW201444006A (zh) 2014-11-16
US10128348B2 (en) 2018-11-13
CN104143538A (zh) 2014-11-12
CN104143543B (zh) 2017-10-03

Similar Documents

Publication Publication Date Title
TWI600129B (zh) 玻璃覆晶接合結構
US9013037B2 (en) Semiconductor package with improved pillar bump process and structure
JP2008218926A (ja) 半導体装置及びその製造方法
TW200834841A (en) Package with a marking structure and method of the same
TWI690045B (zh) 構裝結構、其接合方法及用於其的線路板
JP2004055628A (ja) ウエハレベルの半導体装置及びその作製方法
TW200903763A (en) Inter-connecting structure for semiconductor device package and method of the same
CN114093772A (zh) 一种扇出型封装结构及封装方法
KR102210802B1 (ko) 반도체 장치 및 그 제조 방법
TW201039415A (en) Package substrate structure and flip-chip package structure and methods of fabricating the same
JP2010528472A (ja) 熱性能の向上のためにフタをはんだ付けされた集積回路パッケージ
TWI336516B (en) Surface structure of package substrate and method for manufacturing the same
CN106887420A (zh) 凸块构造与其构成的内连结构
TW200941675A (en) Package substrate and fabrication method thereof
TWM629323U (zh) 覆晶封裝結構
US20200273834A1 (en) Electronic device and manufacturing method thereof
JP2005268442A (ja) 半導体装置およびその製造方法
WO2018220868A1 (ja) 半導体装置および半導体装置の製造方法
CN205488041U (zh) 一种铜柱凸点的封装结构
TW200901419A (en) Packaging substrate surface structure and method for fabricating the same
TWI282160B (en) Circuit board structure integrated with chip and method for fabricating the same
JP2021501459A (ja) 半導体パッケージングのための構造及び方法
JP6569288B2 (ja) 半導体装置及び半導体装置の製造方法
TWI238507B (en) Integrated circuit package substrate with presolder structure and method for fabricating the same
TW523842B (en) Method for manufacturing i/o terminals and the structure thereof