TW201444042A - 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法 - Google Patents

薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法 Download PDF

Info

Publication number
TW201444042A
TW201444042A TW103116132A TW103116132A TW201444042A TW 201444042 A TW201444042 A TW 201444042A TW 103116132 A TW103116132 A TW 103116132A TW 103116132 A TW103116132 A TW 103116132A TW 201444042 A TW201444042 A TW 201444042A
Authority
TW
Taiwan
Prior art keywords
layer
metal
bump
alloy
cap
Prior art date
Application number
TW103116132A
Other languages
English (en)
Other versions
TWI600130B (zh
Inventor
Chiu-Shun Lin
Original Assignee
Himax Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Tech Ltd filed Critical Himax Tech Ltd
Publication of TW201444042A publication Critical patent/TW201444042A/zh
Application granted granted Critical
Publication of TWI600130B publication Critical patent/TWI600130B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1355—Shape
    • H01L2224/13551—Shape being non uniform
    • H01L2224/13552—Shape being non uniform comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Led Device Packages (AREA)

Abstract

一種薄膜覆晶結構，包含用來完全覆蓋位於金屬銲墊上的金屬凸塊的帽蓋層、夾置於金屬凸塊與帽蓋層間之凸塊合金層、完全覆蓋與聚合材料層連接的引腳層的覆層、直接夾置於引腳層與覆層間之引腳合金層。凸塊合金層、引腳合金層與介面合金層分別具有梯度組成。

Description

薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法
本發明大致上關於一種薄膜覆晶結構、金屬凸塊結構及其形成的方法。特別是，本發明關於一種適用於顯示器中、使用合金保護的薄膜覆晶結構與金屬凸塊結構，及其形成的方法。
在電子電路中，薄膜覆晶結構用來讓電子裝置變的更輕與更小。彈性印刷電路板是薄膜覆晶結構的載體。覆晶上的金凸塊則與彈性印刷電路板上的引腳連結。
一般說來，金是作為金屬凸塊理想的材料，因為它的化學性質不活潑，而且夠軟，所以產品相當可靠。然而，一直居高不下的金價使得黃金變的不是划算的材料。所以仍然需要一種用於薄膜覆晶結構新穎的解決方法，來降低製造成本。
有鑒於此，本發明首先提出一種薄膜覆晶結構，其可用於顯示器中。此等薄膜覆晶結構，基本上在製造時比較便宜，而且更有利的是，在極端環境或是異常環境下不會發生迦凡尼效應(Galvanic effect)。
本發明之薄膜覆晶結構，包含金屬銲墊、護層、黏著層、金屬凸塊、帽蓋層、凸塊合金層、基材與介面合金層。護層位於金屬銲墊上，並定義出位於金屬銲墊上之凹穴。黏著層完全位於凹穴中、位於金屬銲墊上、又部份位於護層上，使得黏著層又直接接觸金屬銲墊與護層。由第一金屬所組 成的金屬凸塊部份位於凹穴中並覆蓋黏著層。由第二金屬所組成的帽蓋層位於金屬凸塊上並幾乎完全並覆蓋金屬凸塊，帽蓋層使得金屬凸塊不會暴露出來。凸塊合金層是第一金屬與第二金屬的第一合金，並具有第一梯度組成。基材用來電連接帽蓋層，並包含聚合材料層、引腳層、覆層與引腳合金層。引腳層由第一金屬所組成，且直接連接至聚合材料層。覆層由第二金屬所組成且完全覆蓋引腳層，而使得引腳不會暴露出來。引腳合金層直接夾置於引腳層與覆層之間。引腳合金層是第一金屬與第二金屬的第二合金，並具有第二梯度組成。介面合金層直接夾置於覆層與帽蓋層之間。介面合金層是第一金屬與第二金屬的第三合金，並具有第三梯度組成。
在本發明一實施方式中，帽蓋層自行對準於金屬凸塊。
在本發明另一實施方式中，帽蓋層、黏著層、與護層間具有嵌穴(notch)。
在本發明另一實施方式中，覆層之表面積不小於帽蓋層之表面積。
在本發明另一實施方式中，覆層對準於帽蓋層。
在本發明另一實施方式中，薄膜覆晶結構更包含位於護層與聚合材料層間之樹脂，以密封介面合金層、覆層與帽蓋層。
本發明另外提出一種形成薄膜覆晶結構的方法。首先，製備載體，載體包含金屬銲墊、護層、黏著層、金屬凸塊、帽蓋層與凸塊合金層。護層位於金屬銲墊上，並定義出位於金屬銲墊上之凹穴。黏著層完全位於凹穴中、位於金屬銲墊上、又部份位於護層上，使得黏著層又直接接觸金屬銲墊與護層。由第一金屬所組成的金屬凸塊部份位於凹穴中並覆蓋黏著層。由第二金屬所組成的帽蓋層位於金屬凸塊上並幾乎完全並覆蓋金屬凸塊。帽蓋層能使得金屬凸塊不會暴露出來。凸塊合金層直接夾置於金屬凸塊與帽蓋層之間，是第一金屬與第二金屬的第一合金，並具有第一梯度組成。
其次，提供基材，用來電連接帽蓋層。基材包含聚合材料層、引腳層、覆層與引腳合金層。引腳層由第一金屬所組成，且直接連接至聚合材料層。覆層由第二金屬所組成且完全覆蓋引腳層，而使得引腳不會暴露出來。引腳合金層直接夾置於引腳層與覆層之間。引腳合金層是第一金屬與第二金屬的第二合金，並具有第二梯度組成。
然後，將載體連接至基材，而使得覆層直接接觸帽蓋層。繼續，進行連接步驟，而形成直接夾置於覆層與帽蓋層間之介面合金層。介面合金層是第一金屬與第二金屬的第三合金，並具有第三梯度組成。
在本發明一實施方式中，製備載體包含以下的步驟。首先，提供底材，底材包含金屬銲墊、護層、黏著層、與圖案化光阻。護層位於金屬銲墊上，並定義出位於金屬銲墊上之凹穴。黏著層位於凹穴中，覆蓋並直接接觸金屬銲墊與護層。圖案化光阻位於黏著層上，並包含有開口，此開口暴露位於凹穴中與護層上之黏著層。其次，以金屬凸塊材料填入開口中。然後，移除圖案化光阻，使得金屬凸塊材料成為位於黏著層上之金屬凸塊。再來，移除沒有被金屬凸塊材料所覆蓋之黏著層，同時部分暴露位於下方之護層。繼續，形成覆蓋金屬凸塊的帽蓋層。
在本發明另一實施方式中，移除黏著層時，過移除(over-removed)黏著層，以形成位於帽蓋層、黏著層、與護層間之嵌穴(notch)。
在本發明另一實施方式中，形成薄膜覆晶結構的方法，更包含經由熟化金屬凸塊以調整金屬凸塊之硬度。
在本發明另一實施方式中，將基材連接至載體時，覆層對準於帽蓋層。
在本發明另一實施方式中，形成薄膜覆晶結構的方法，更包含形成位於護層與聚合材料層間之樹脂，以密封介面合金層、覆層與帽蓋層。
在本發明另一實施方式中，形成薄膜覆晶結構的方法，更包含形成位於護層與聚合材料層間之樹脂，以密封介面合金層、覆層與帽蓋層，樹 脂並填入嵌穴中。
本發明又提出一種金屬凸塊結構，其可用於顯示器的驅動積體電路(driver IC)中。本發明之金屬凸塊結構包含金屬銲墊、護層、黏著層、金屬凸塊與帽蓋層。護層位於金屬銲墊上，並定義出位於金屬銲墊上之凹穴。黏著層位於凹穴中、位於金屬銲墊上、又部份位於護層上，黏著層又直接接觸金屬銲墊與護層。包含第一金屬之金屬凸塊部份位於凹穴中並覆蓋黏著層。包含第二金屬之帽蓋層位於金屬凸塊上、並覆蓋金屬凸塊，而使得金屬凸塊不會暴露出來。
在本發明一實施方式中，帽蓋層自行對準於金屬凸塊。
在本發明另一實施方式中，帽蓋層、黏著層、與護層間具有嵌穴(notch)。
在本發明另一實施方式中，帽蓋層更包含外層。
在本發明另一實施方式中，覆層之表面積不小於帽蓋層之表面積。
在本發明另一實施方式中，覆層對準於帽蓋層。
在本發明另一實施方式中，金屬凸塊結構更包含位於護層與聚合材料層間之樹脂，以密封介面合金層、覆層與帽蓋層。
在本發明另一實施方式中，樹脂填入位於帽蓋層、黏著層、與護層間之嵌穴中。
1‧‧‧金屬凸塊結構
2‧‧‧薄膜覆晶結構
9‧‧‧絕緣層
10‧‧‧底材
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
14‧‧‧光阻層
14‧‧‧光阻層’
15‧‧‧凹穴
16‧‧‧開口
20’‧‧‧金屬凸塊材料
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層
41‧‧‧合金
42‧‧‧內層
43‧‧‧外層
50‧‧‧基材
51‧‧‧聚合材料層
52‧‧‧引腳層
53‧‧‧覆層
54‧‧‧引腳合金層
60‧‧‧介面合金層
70‧‧‧封膠
第1圖至第12C圖繪示本發明形成薄膜覆晶的金屬凸塊結構方法，其中第8A圖、第10A圖、12A圖、第12B圖繪示不同之實施例。
第13A圖、第13B圖、第13C圖、第14A圖、第14B圖與第14C圖繪示本發明薄膜覆晶結構與金屬凸塊結構。
本發明首先提供一種形成可以用於顯示器中的薄膜覆晶結構的方法。第1圖至第12B圖繪示本發明形成薄膜覆晶結構的方法。這種薄膜覆晶結構，基本上在製造時比較便宜，而且更有利的是，因為多重梯度合金層與密封樹脂的存在，即使在極端環境或是異常環境下也不會發生迦凡尼效應。
首先，製備載體10並提供基材50。本發明之載體10至少包括金屬銲墊11、護層12、黏著層13、金屬凸塊20、帽蓋層40與凸塊合金層41。基材50用來電連接帽蓋層40。基材50包含聚合材料層51、引腳層52、覆層53與引腳合金層54。
一方面，載體10可以使用如下之方式來製備。首先，如第1圖所繪示，提供底材10。底材10包括金屬銲墊11、護層12與黏著層13。
絕緣層9為底材10之基礎部份，用來支撐其它之元件，例如用來支撐金屬銲墊11、護層12、黏著層13與後續圖中之圖案化光阻層。金屬銲墊11可以是一種質輕之金屬材料，例如鋁，並經過圖案化。但是，其它之金屬亦可採用，而並不僅限於鋁。
護層12即位於金屬銲墊11之上，同時還具有定義出凹穴15的圖案，使得凹穴15亦位於金屬銲墊11之上。護層12可以是一種電絕緣之材料，例如是氮化矽、氧化矽或是其組合。通常來說，凹穴15的大小會小於金屬銲墊11的大小。
黏著層13又位於凹穴15之中。此外，黏著層13還會覆蓋金屬銲墊11與護層12，使得黏著層13會直接接觸金屬銲墊11與護層12。黏著層13用來幫助後續形成之金屬凸塊材料(圖未示)牢牢地附著在凹穴15之中。黏著層13可以是一種合金層，例如鈦鎢合金層或是鈦金屬層。
黏著層13的形成方法可以是，利用濺鍍一層鈦鎢合金，與例如銅的晶種層的方法，來均勻地覆蓋底材10，例如完全地覆蓋金屬銲墊11、護層 12、與凹穴15的表面。結果例示於第1圖中。形成圖案化光阻層之方式，可以參考如下所示之方式。
如第2圖所繪示，將一大片光阻層14’整體形成在黏著層13上，並同時填滿凹穴15。光阻層14’可以是光敏性的材料，例如是有機的光敏材料。
再來，如第3圖所繪示，將光阻層14’圖案化。圖案化光阻層14的方式可以是如下所述。光阻層14形成在黏著層13上來定義出開口16。開口16用來暴露出位於凹穴15中與護層12上的黏著層13，因此，在本發明之一實施例中，開口16會稍微大於凹穴15。換句話說，開口16可以用來定義出後續所形成之金屬凸塊材料(圖未示)所位在的空間，而此空間本身即容置了凹穴15。
然後，整體的光阻層14’又會經過適當的曝光與顯影步驟，而轉換成圖案化光阻層14，而具有曝光與顯影所賦與的預定圖案。圖案是經由開口16所定義出的，其結果即繪示於第3圖所中。
接下來，如第4圖所繪示，使用金屬凸塊材料20’來填入開口16中。請注意，金屬凸塊材料20’可能僅僅只是「填入」開口16中，而沒有「填滿」開口16。此時，黏著層13即因此夾置於金屬凸塊材料20’與金屬銲墊11之間，以及夾置於金屬凸塊材料20’與護層12之間。例如，由於金屬銲墊11與黏著層13均為導電性材料，所以金屬凸塊材料20’可以經由電鍍之方式來形成。視情況需要，金屬凸塊材料20’可以使用鈀、銀、銅或是金，以尋求較佳之導電性，與越低越好之化學活性。
一但將金屬凸塊材料20’形成好了之後，就不再需要圖案化光阻層14了。於是，如第5圖所繪示，移除圖案化光阻層14，使得金屬凸塊材料20’成為各自獨立之金屬凸塊20。可以使用傳統的方式來移除圖案化光阻層14。於是，各自獨立之金屬凸塊20，就會完全位於黏著層13之上，並直接接觸黏著層13。
由於黏著層13是導電的，這會導致所有的金屬凸塊20彼此短路，所以多餘的黏著層13必須要移除。再來，如第6圖所繪示，沒有被金屬凸塊20所覆蓋的黏著層13經由蝕刻步驟來移除，又部份地暴露出下方之護層12，使得所有的金屬凸塊20，藉由電絕緣材料，亦即護層12的隔離，成為彼此電絕緣。如此一來，所有的金屬凸塊20即自我對準於黏著層13。例如，可以使用過氧化氫來蝕刻黏著層13的鈦鎢合金。
視情況需要，蝕刻步驟之後還可以進行加熱金屬凸塊20的熟化，來調整金屬凸塊20達到所需的硬度。例如，在大於300℃或是維持超過90分鐘之退火條件。一般說來，較低的硬度需要較高的熟化溫度與較短的熟化時間，而較高的硬度需要較低的熟化溫度與較長的熟化時間，來將金屬凸塊20調整到所需的適當硬度，例如不超過130維氏硬度(Hv)，較佳者不大於110維氏硬度，更佳者介於50維氏硬度至110維氏硬度之間。
此時可以注意到在第6圖中，在移除黏著層13時，在金屬凸塊20、黏著層13、與護層12之間形成了一只嵌穴30，因為蝕刻步驟不只會完全移除沒有被金屬凸塊20所覆蓋的黏著層13，蝕刻步驟也可能會更進一步移除沒有被金屬凸塊20所覆蓋的黏著層13以外其他的黏著層13，例如，夾置於金屬凸塊20、與護層12間之黏著層13。而結果是，在金屬凸塊20、黏著層13、與護層12之間便形成了一只嵌穴30，而成為本發明結構的特徵之一。在有嵌穴30存在時，金屬凸塊20會幾乎覆蓋所有的黏著層13。另外，嵌穴30則可能橫向地深入1微米(μm)-2微米左右的尺寸。
由於各自獨立之金屬凸塊20，仍然可能因為暴露於周圍的大氣環境中而失之脆弱，所以需要再特意形成帽蓋層來盡量覆蓋金屬凸塊20，使得金屬凸塊20盡量不會暴露於周圍的大氣環境中。請參考第7圖所繪示，形成帽蓋層40來幾乎完全覆蓋金屬凸塊20，而在有嵌穴30之存在下，得到了理想的金屬凸塊結構1。
帽蓋層40可以包含一種或多種保護性的材料。如果是銅製成的金 屬凸塊20，帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的金屬凸塊20，帽蓋層40可以包含錫、鎳、鈀其中至少一者。如果是銀製成的金屬凸塊20，帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊20，帽蓋層40可以包含錫。不過，所形成帽蓋層40可能如第7圖所繪示，只會減小嵌穴30的尺寸，或是如第8圖或第8A圖所繪示，因為完全填滿了嵌穴30，使得嵌穴30消失不見。所以，形成帽蓋層40用來完全覆蓋金屬凸塊20。
例如，請參考第7圖、第8圖或第8A圖所繪示，帽蓋層40包含內層42與外層43，其各別可以為單層結構或是多層結構。內層42與外層43可以是相同的材料或是不同的材料，像是錫42/43(相同的材料)、鎳42/金43(各別為單層的不同材料)、鈀42/金43或鎳42/鈀+金43(單層結構42與多層結構43的組合)。
較佳者，可以經由無電極電鍍法來形成帽蓋層40，例如可以在小於4之酸鹼值、硫酸鹽之輔助下進行無電極電鍍法。由於護層12是一種電絕緣材料，所以帽蓋層40很可能只會特定而專一地形成在金屬凸塊20上。換句話說，帽蓋層40即自我對準在金屬凸塊20上。
另外，依據無電極電鍍法的不同電鍍配方或是電鍍條件，帽蓋層40還可以有不同的厚度與其它的形狀。例如，帽蓋層40可能是合金41、內層42與外層43之搭配或組合。較佳者，帽蓋層40含有金，其優點在於有利於重工(re-work)，又可以減低材料的成本。當帽蓋層40含鈀時，鈀層的厚度可以是0.15微米-0.4微米左右。帽蓋層40的厚度，可以是在2微米以下，較佳者不大於0.1微米，甚至於可以只有0.006微米而已。由於護層為電絕緣材料，帽蓋層40只會特定形成在金屬凸塊20上。表1列舉電鍍帽蓋層40、內層42與外層43之可行步驟與製程參數做為參考。其中在每個步驟之後，均可以再加入純水洗滌之清潔步驟。
在本發明之一實施例中，又可以引入另一熟化(curing)步驟，使得帽蓋層40與金屬凸塊20形成合金41，稱為凸塊合金層41。例如，請參考第9圖、第10圖或第10A圖所繪示，形成在金屬凸塊20上的帽蓋層40被加熱到，例如在150℃~180℃與30~60分鐘之條件下，與金屬凸塊20形成凸塊合金層41。銅與錫在不同的條件下，可以形成多種的合金，例如Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3。在本發明之一較佳實施例中，凸塊合金層41是一種混合物，並具有第一梯度組成。例如，凸塊合金層41的梯度組成可以是Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3。溫度與時間通常會影響到形成合金相的速率。一般說來，比較接近銅的合金相含銅率比較高，而比較遠離銅的合金相含銅率比較低，所以凸塊合金層41可以有梯度組成。
凸塊合金層41的形成，刻意用來防止金屬凸塊20在極端的情形下可能穿過帽蓋層40。在帽蓋層40的保護下又有合金41，金屬凸塊20都不會暴露於周圍的大氣環境中。第9圖繪示，在嵌穴30的存在下，熟化金屬凸塊20形成合金41。第10圖所繪示，熟化金屬凸塊20形成合金41，但沒有嵌穴30。
另一方面，如第11圖所繪示，基材50可以是市售的，或是預先製得的。基材50至少包含聚合材料層51、引腳層52、覆層53與引腳合金層54。聚合材料層51可以是堅韌又有彈性的有機材料，例如聚醯亞胺。聚合材料層51可以是經過裁切或是未經裁切的捲條(reel)，所以聚合材料層51的 形式可以是未經裁切的捲條或是經裁切的長條。
引腳層52可以是由純金屬所製得，例如鈀、銀、銅、或是金，來追求盡量低的電阻與化學活性。引腳層52直接連接至聚合材料層51。覆層53可以是由保護性的純金屬所製得。如果是銅製成的引腳層52，覆層53可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的引腳層52，覆層53可以包含錫、鎳、鈀其中至少一者。如果是銀製成的引腳層52，覆層53可以包含錫。如果是鈀製成的引腳層52，覆層53可以包含錫。覆層53的厚度可以是0.5微米至1微米。較佳者，覆層53完全覆蓋引腳層52，而使得引腳層52的引腳不會暴露出來。
類似地，引腳合金層54是來自覆層53與引腳層52的，並夾置在覆層53與引腳層52之間。引腳合金層54是一種混合物，並具有第二梯度組成。例如，引腳合金層54的梯度組成，可以是Cu6Sn5在中間、而Cu3Sn接近凸塊或是薄膜覆晶(COF)的引腳。
接下來，請參考第12A圖、第12B圖或第12C圖所繪示，將載體10連接至基材50，而使得覆層53直接接觸帽蓋層40。繼續，請參考第13A圖、第13B圖或第13C圖所繪示，進行一連接步驟，而形成直接夾置於覆層53與帽蓋層40間之介面合金層60。連接步驟可以是一種超音波連接步驟。例如，超音波連接步驟可以在：器材溫度為室溫至260℃的範圍內、接合施力為15牛頓至300牛頓、階段溫度為室溫至150℃的範圍內、接合時間為0.5至60秒鐘的條件下進行。
介面合金層60也是一種覆層53與帽蓋層40的混合物。類似地，介面合金層60具有第三梯度組成。例如，介面合金層60的梯度組成，可以是Cu6Sn5位在中間、而Cu3Sn接近凸塊或是薄膜覆晶的引腳。第13A圖繪示載體10可以有嵌穴30。第13B圖繪示只有內層42填入嵌穴30而外層43覆蓋在外。也可能如第13C圖所繪示，載體10沒有嵌穴30是因為帽蓋層40填滿了嵌穴30。
視情況需要，如第14A圖、第14B圖或第14C圖所繪示，還可以使用封膠70，來密封介面合金層60、覆層53與帽蓋層40。封膠70可以是如環氧樹脂之底部填充膠(Underfill)。由於封膠70環繞載體10與基材50之間的空間，所以封膠70於是氣密性地密封介面合金層60、覆層53與帽蓋層40。如果有嵌穴30，封膠70可以填入嵌穴30中，如第14A圖所繪示。或是，如果沒有嵌穴30，也可以是只有內層42填入嵌穴30而外層43覆蓋在外，如第14B圖所繪示。又，也可以是以帽蓋層40填滿了嵌穴30，如第14C圖所繪示。
在經過以上之步驟後，就可以得到一種薄膜覆晶結構2。本發明之薄膜覆晶結構2，適合用於薄膜覆晶(COF)封裝結構，因此可以用於顯示器裝置(display device)中。請參閱第14A圖、第14B圖或第14C圖，本發明之薄膜覆晶結構2包含載體10、基材50與介面合金層60。載體10包括金屬銲墊11、護層12、黏著層13、金屬凸塊20、帽蓋層40與凸塊合金層41。基材50用來電連接帽蓋層40。基材50包含聚合材料層51、引腳層52、覆層53與引腳合金層54。
金屬銲墊11可以是一種質輕之金屬材料，例如鋁，並經過圖案化。但是，其它之金屬亦可採用，而並不限於鋁。護層12即位於金屬銲墊11之上，同時還具有圖案化而定義出的凹穴15，使得凹穴15亦位於金屬銲墊11之上。護層12可以是一種電絕緣之材料，例如是氮化矽、氧化矽或是其組合。通常來說，凹穴15的大小會小於金屬銲墊11的大小。
凹穴15之中完全填有黏著層13。此外，黏著層13還位於金屬銲墊11之上，來覆蓋並直接接觸金屬銲墊11。然而，部分的黏著層13位於護層12上，來覆蓋並直接接觸護層12。黏著層13用來幫助金屬凸塊20牢牢地附著在凹穴15之中。黏著層13可以是一種合金層，例如鈦鎢合金層，或是鈦金屬層。
金屬凸塊20部份地位於凹穴15中並覆蓋黏著層13，使得黏著層 13夾置於金屬凸塊20與金屬銲墊11之間，以及夾置於金屬凸塊20與護層12之間。特別是，金屬凸塊20會自我對準於黏著層13。視情況需要，金屬凸塊20的材料可以是鈀、銀、銅或是金，以尋求較佳之導電性，與越低越好之化學活性。
特別是，如14A圖、第14B圖或第14C圖所繪示，可以注意到本發明結構的特徵之一，在金屬凸塊20、黏著層13、與護層12之間還可能會有一只嵌穴30，使得嵌穴30可能會是個使得黏著層13部分暴露出來的孔洞。請注意，較厚的帽蓋層40可能會減小嵌穴30的尺寸，或是只有內層42填入嵌穴30，或是帽蓋層40填滿了嵌穴30而使得嵌穴30消失，如14A圖、第14B圖或第14C圖所繪示。
帽蓋層40位在金屬凸塊20上是用來完全覆蓋金屬凸塊20，使得帽蓋層40使得金屬凸塊20可以免於暴露於大氣環境中。換句話說，帽蓋層40可以自我對準於金屬凸塊20。帽蓋層40可以包含多種保護性的材料。如果是銅製成的金屬凸塊20，帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的金屬凸塊20，帽蓋層40可以包含錫、鎳、鈀其中至少一者。如果是銀製成的金屬凸塊20，帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊20，帽蓋層40可以包含錫。
由於帽蓋層40是特別形成在金屬凸塊20上的，帽蓋層40即可以自我對準在金屬凸塊20上。在本發明的一實施例中，在金屬凸塊20上的帽蓋層40與金屬凸塊20形成合金41，稱為凸塊合金層41。如第14A圖、第14B圖或第14C圖所繪示。在本發明之一較佳實施例中，凸塊合金層41是一種混合物，並具有梯度組成。例如，凸塊合金層41的梯度組成可以是可以是Cu6Sn5在中間、而Cu3Sn接近凸塊或是薄膜覆晶(COF)的引腳。
凸塊合金層41的形成，刻意用來防止金屬凸塊20在極端的情形下可能穿過帽蓋層40。在帽蓋層40的保護下又有凸塊合金層41，金屬凸塊20都不會暴露於周圍的大氣環境中。第14A圖繪示，在嵌穴30的存在下， 熟化金屬凸塊20形成合金41。第14B圖或第14C圖繪示，熟化金屬凸塊20形成合金41，但沒有嵌穴30。
基材50可以是市售的，或是預先製得的。基材50至少包含聚合材料層51、引腳層52、覆層53與引腳合金層54。聚合材料層51可以是堅韌又有彈性的有機材料，例如聚醯亞胺。聚合材料層51可以是經過裁切或是未經裁切的捲條，所以聚合材料層51的形式可以是捲條或是長條。
引腳層52可以是由純金屬所製得，例如鈀、銀、銅、或是金，來追求盡量低的電阻與化學活性。引腳層52直接連接至聚合材料層51。覆層53可以是由保護性的純金屬所製得。如果是銅製成的引腳層52，覆層53可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的引腳層52，覆層53可以包含錫、鎳、鈀其中至少一者。如果是銀製成的引腳層52，覆層53可以包含錫。如果是鈀製成的引腳層52，覆層53可以包含錫。覆層53的厚度可以是0.5微米至1微米。較佳者，覆層53完全覆蓋引腳層52，而使得引腳層52的引腳不會暴露出來。
類似地，覆層53與引腳層52一起形成引腳合金層54，使得引腳合金層54夾置在覆層53與引腳層52之間。引腳合金層54是一種混合物，並具有第二梯度組成。例如，引腳合金層54的梯度組成，可以是Cu6Sn5在中間、而Cu3Sn接近凸塊或是薄膜覆晶(COF)的引腳。
覆層53與帽蓋層40，形成了另一層合金層，稱為介面合金層60，所以介面合金層60直接夾置於覆層53與帽蓋層40之間。介面合金層60也是一種覆層53與帽蓋層40的材料的混合物。類似地，介面合金層60具有第三梯度組成。例如，介面合金層60的梯度組成，可以是Cu6Sn5位在中間、而Cu3Sn接近凸塊或是薄膜覆晶的引腳。第14A圖繪示載體10可以有嵌穴30。第14B圖與第13C圖繪示，載體10有可能沒有嵌穴30。
視情況需要，如第14A圖、第14B圖或第14C圖所繪示，封膠70位於載體10與基材50之間，來密封介面合金層60、覆層53與帽蓋層40。 封膠70可以是如環氧樹脂之底部填充膠。由於封膠70環繞載體10與基材50間的空間，所以封膠70於是氣密性地密封介面合金層60、覆層53與帽蓋層40。如果有嵌穴30，封膠70可以填入嵌穴30中，如第14A圖所繪示。或是，如果沒有嵌穴30，也可以是只有內層42填入嵌穴30而外層43覆蓋在外，如第14B圖或第14C圖所繪示。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
2‧‧‧薄膜覆晶結構
9‧‧‧絕緣層
10‧‧‧底材
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層
41‧‧‧合金
50‧‧‧基材
51‧‧‧聚合材料層
52‧‧‧引腳層
53‧‧‧覆層
54‧‧‧引腳合金層
60‧‧‧介面合金層

Claims (21)

  1. 一種薄膜覆晶(chip on flex,COF)結構，包含：一金屬銲墊；一護層，位於該金屬銲墊上，並定義出位於該金屬銲墊上之一凹穴；一黏著層，位於該凹穴中、位於該金屬銲墊上、又部份位於該護層上，其中該黏著層直接接觸該金屬銲墊與該護層；一金屬凸塊，由一第一金屬所組成且部份位於該凹穴中並覆蓋該黏著層；一帽蓋層，由一第二金屬所組成、位於該金屬凸塊上並覆蓋該金屬凸塊，而使得該金屬凸塊不會暴露出來；一凸塊合金層，直接夾置於該金屬凸塊與該帽蓋層間，其中該凸塊合金層是該第一金屬與該第二金屬的一第一合金，並具有一第一梯度組成；一基材，用來電連接該帽蓋層，其包含：一聚合材料層；一引腳層(lead layer)，由該第一金屬所組成且直接連接至該聚合材料層；一覆層(cover layer)，由該第二金屬所組成且完全覆蓋該引腳層，而使得該引腳不會暴露出來；一引腳合金層，直接夾置於該引腳層與該覆層間，其中該引腳合金層是該第一金屬與該第二金屬的一第二合金，並具有一第二梯度組成；以及一介面合金層，直接夾置於該覆層與該帽蓋層間，其中該介面合金層是該第一金屬與該第二金屬的一第三合金，並具有一第三梯度組成。
  2. 如請求項1之薄膜覆晶結構，其中該帽蓋層自行對準於該金屬凸塊。
  3. 如請求項1之薄膜覆晶結構，其中該帽蓋層、該黏著層、與該護層間具有一嵌穴(notch)。
  4. 如請求項1之薄膜覆晶結構，其中該覆層之表面積不小於該帽蓋層之表面積。
  5. 如請求項1之薄膜覆晶結構，其中該覆層對準於該帽蓋層。
  6. 如請求項1之薄膜覆晶結構，更包含：一樹脂，位於該護層與該聚合材料層間，以密封該介面合金層、該覆層與該帽蓋層。
  7. 一種形成薄膜覆晶結構的方法，包含：製備一載體，其包含：一金屬銲墊；一護層，位於該金屬銲墊上，並定義出位於該金屬銲墊上之一凹穴；一黏著層，位於該凹穴中、位於該金屬銲墊上又部分位於該護層上，其中該黏著層直接接觸該金屬銲墊與該護層；一金屬凸塊，由一第一金屬所組成且部份位於該凹穴中並覆蓋該黏著層；一帽蓋層，由一第二金屬所組成、位於該金屬凸塊上並覆蓋該金屬凸塊，而使得該金屬凸塊不會暴露出來；一凸塊合金層，直接夾置於該金屬凸塊與該帽蓋層間，其中該凸塊合金層是該第一金屬與該第二金屬的一第一合金，並具有一第一梯度組成；提供一基材，包含：一聚合材料層； 一引腳層，由該第一金屬所組成且直接連接至該聚合材料層；一覆層，由該第二金屬所組成且完全覆蓋該引腳層，而使得該引腳不會暴露出來；以及一引腳合金層，直接夾置於該引腳層與該覆層間，其中該引腳合金層是該第一金屬與該第二金屬的一第二合金，並具有一第二梯度組成；將該基材連接至該載體，而使得該覆層直接接觸該帽蓋層；以及進行一連接步驟，而形成直接夾置於該覆層與該帽蓋層間之一介面合金層，其中該介面合金層是該第一金屬與該第二金屬的一第三合金，並具有一第三梯度組成。
  8. 如請求項7形成薄膜覆晶結構的方法，其中製備該載體包含：提供一底材，包含：一金屬銲墊；一護層，位於該金屬銲墊上，並定義出位於該金屬銲墊上之一凹穴；一黏著層，位於該凹穴中、覆蓋並直接接觸該金屬銲墊與該護層；以及一圖案化光阻，位於該黏著層上，並包含暴露位於該凹穴中與該護層上之該黏著層之一開口；以一金屬凸塊材料填入該開口中；移除該圖案化光阻，使得該金屬凸塊材料成為位於該黏著層上之一金屬凸塊；移除沒有被該金屬凸塊材料所覆蓋之該黏著層，以部分暴露位於下方之該護層；以及形成該第二金屬的一帽蓋層，以完全覆蓋該金屬凸塊。
  9. 如請求項8形成薄膜覆晶結構的方法，其中移除該黏著層時，過移除 (over-removed)該黏著層，以形成位於該帽蓋層、該黏著層、與該護層間之一嵌穴(notch)。
  10. 如請求項8形成薄膜覆晶結構的方法，更包含：經由熟化該金屬凸塊以調整該金屬凸塊之硬度。
  11. 如請求項7形成薄膜覆晶的方法，其中將該基材連接至該載體時，該覆層對準於該帽蓋層。
  12. 如請求項7形成薄膜覆晶結構的方法，更包含：形成一樹脂，位於該護層與該聚合材料層間，以密封該介面合金層、該覆層與該帽蓋層。
  13. 如請求項7形成薄膜覆晶結構的方法，更包含：形成一樹脂，位於該護層與該聚合材料層間，以密封該介面合金層、該覆層與該帽蓋層，並填入該嵌穴中。
  14. 一種金屬凸塊(metal bump)結構，其用於一驅動積體電路(driver IC)中並包含：一金屬銲墊；一護層，位於該金屬銲墊上，並定義出位於該金屬銲墊上之一凹穴；一黏著層，位於該凹穴中、位於該金屬銲墊上、又部份位於該護層上，其中該黏著層直接接觸該金屬銲墊與該護層；一金屬凸塊，包含一第一金屬且部份位於該凹穴中並覆蓋該黏著層；一帽蓋層，包含一第二金屬、位於該金屬凸塊上並完全覆蓋該金屬凸塊，而使得該金屬凸塊不會暴露出來。
  15. 如請求項14之金屬凸塊結構，其中該帽蓋層自行對準於該金屬凸塊。
  16. 如請求項14之金屬凸塊結構，其中該帽蓋層、該黏著層、與該護層間具有一嵌穴(notch)。
  17. 如請求項14之金屬凸塊結構，其中該帽蓋層更包含一外層。
  18. 如請求項14之金屬凸塊結構，其中該覆層之表面積不小於該帽蓋層之表面積。
  19. 如請求項14之金屬凸塊結構，其中該覆層對準於該帽蓋層。
  20. 如請求項14之金屬凸塊結構，更包含：一樹脂，位於該護層與該聚合材料層間，以密封該介面合金層、該覆層與該帽蓋層。
  21. 如請求項20之金屬凸塊結構，其中該樹脂填入位於該帽蓋層、該黏著層、與該護層間之該嵌穴中。
TW103116132A 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法 TWI600130B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361820152P 2013-05-06 2013-05-06

Publications (2)

Publication Number Publication Date
TW201444042A true TW201444042A (zh) 2014-11-16
TWI600130B TWI600130B (zh) 2017-09-21

Family

ID=51841032

Family Applications (3)

Application Number Title Priority Date Filing Date
TW103113751A TWI600129B (zh) 2013-05-06 2014-04-15 玻璃覆晶接合結構
TW103115992A TWI573205B (zh) 2013-05-06 2014-05-05 金屬凸塊結構
TW103116132A TWI600130B (zh) 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW103113751A TWI600129B (zh) 2013-05-06 2014-04-15 玻璃覆晶接合結構
TW103115992A TWI573205B (zh) 2013-05-06 2014-05-05 金屬凸塊結構

Country Status (4)

Country Link
US (2) US10128348B2 (zh)
KR (3) KR101611376B1 (zh)
CN (4) CN104143538B (zh)
TW (3) TWI600129B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
WO2016143557A1 (ja) * 2015-03-10 2016-09-15 三菱電機株式会社 パワー半導体装置
KR102663140B1 (ko) * 2016-06-24 2024-05-08 삼성디스플레이 주식회사 디스플레이 장치
KR102508527B1 (ko) 2016-07-01 2023-03-09 삼성전자주식회사 필름형 반도체 패키지
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
IT201700087309A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici
IT201700087318A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10741482B2 (en) 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP7122593B2 (ja) * 2018-05-08 2022-08-22 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法、半導体装置の製造装置、及び半導体装置
US11469194B2 (en) * 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
CN110854066A (zh) * 2019-11-28 2020-02-28 无锡微视传感科技有限公司 一种半导体电镀方法
WO2021184188A1 (zh) * 2020-03-17 2021-09-23 元锦生物科技股份有限公司 可拆式接合结构
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205099A (en) * 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
KR20050060032A (ko) * 2002-05-16 2005-06-21 내셔널 유니버시티 오브 싱가포르 웨이퍼 레벨 무전해 구리 금속화 및 범핑 공정, 및 반도체웨이퍼 및 마이크로칩용 도금액
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JP2007531247A (ja) * 2003-07-16 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 側壁用絶縁体を有する金属バンプ及びこのような金属バンプを有するチップを製造する方法
TWI222198B (en) 2003-09-04 2004-10-11 Fupo Electronics Corp Fine pitch gold bump fabrication process and its package article
JP4718809B2 (ja) 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
KR100642765B1 (ko) 2004-09-15 2006-11-10 삼성전자주식회사 하이브리드 범프를 포함하는 미세전자소자칩, 이의패키지, 이를 포함하는 액정디스플레이장치 및 이러한미세전자소자칩의 제조방법
TWI286454B (en) * 2005-03-09 2007-09-01 Phoenix Prec Technology Corp Electrical connector structure of circuit board and method for fabricating the same
KR100801073B1 (ko) 2005-10-06 2008-02-11 삼성전자주식회사 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법
US7601566B2 (en) 2005-10-18 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
JP2007317979A (ja) * 2006-05-29 2007-12-06 Toshiba Corp 半導体装置の製造方法
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
KR20080102545A (ko) 2007-05-21 2008-11-26 주식회사 엘지화학 Ｃｏｆ 실장용 2층 동박 적층판 및 그 제조 방법
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
TW201044527A (en) * 2009-06-11 2010-12-16 Int Semiconductor Tech Ltd Chip architecture having film-faced metal bumps and semiconductor flip-chip device applied from the same
TWI469288B (zh) 2009-06-11 2015-01-11 Chipbond Technology Corp 凸塊化晶片結構及其應用之半導體覆晶裝置
KR20110090332A (ko) 2010-02-03 2011-08-10 한양대학교 산학협력단 이방성 전도 필름을 이용하여 기판이 접합된 반도체 소자 및 기판 접합방법
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
KR20120139115A (ko) * 2011-06-16 2012-12-27 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US8643196B2 (en) 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
JP6035714B2 (ja) 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US20130193570A1 (en) * 2012-02-01 2013-08-01 Chipbond Technology Corporation Bumping process and structure thereof
US8501614B1 (en) * 2012-03-22 2013-08-06 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US9646951B2 (en) * 2013-12-10 2017-05-09 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor

Also Published As

Publication number Publication date
CN104143543A (zh) 2014-11-12
CN104143540B (zh) 2017-05-03
TWI600130B (zh) 2017-09-21
CN104143539A (zh) 2014-11-12
TW201444037A (zh) 2014-11-16
US20140327134A1 (en) 2014-11-06
TW201444006A (zh) 2014-11-16
KR20140131876A (ko) 2014-11-14
US10128348B2 (en) 2018-11-13
TWI573205B (zh) 2017-03-01
CN104143543B (zh) 2017-10-03
CN104143538B (zh) 2018-01-02
TWI600129B (zh) 2017-09-21
CN104143540A (zh) 2014-11-12
US9450061B2 (en) 2016-09-20
US20140327133A1 (en) 2014-11-06
CN104143538A (zh) 2014-11-12
KR20140131884A (ko) 2014-11-14
KR101611846B1 (ko) 2016-04-12
KR101641993B1 (ko) 2016-07-22
KR101611376B1 (ko) 2016-04-11
KR20140131871A (ko) 2014-11-14
CN104143539B (zh) 2018-04-10

Similar Documents

Publication Publication Date Title
TWI600130B (zh) 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法
US8101864B2 (en) Electronic device substrate and its fabrication method, and electronic device and its fabrication method
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP2008218926A (ja) 半導体装置及びその製造方法
JP2013004881A (ja) インターポーザ及びその製造方法と半導体装置
JP2004055628A (ja) ウエハレベルの半導体装置及びその作製方法
JP4121542B1 (ja) 電子装置の製造方法
TWI690045B (zh) 構裝結構、其接合方法及用於其的線路板
JP2019075578A (ja) 半導体パッケージ及びその製造方法
CN110943067A (zh) 半导体装置及其制造方法
JP2016213283A (ja) 製造方法、および貫通電極付配線基板
US20200273834A1 (en) Electronic device and manufacturing method thereof
WO2018220868A1 (ja) 半導体装置および半導体装置の製造方法
JP2010092974A (ja) 半導体装置及びその製造方法、並びに電子装置
TW200901419A (en) Packaging substrate surface structure and method for fabricating the same
JP2021027122A (ja) 半導体装置
JP2002118210A (ja) 半導体装置用インタポーザ及びこれを用いた半導体装置
JP2006302933A (ja) 半導体装置及びその製造方法
JP2012146784A (ja) 半導体装置、スタックドパッケージ型半導体装置および半導体装置の製造方法
JP6515243B2 (ja) 半導体装置の製造方法
JP6569288B2 (ja) 半導体装置及び半導体装置の製造方法
CN107170715B (zh) 半导体封装结构及其制作方法
JP5098655B2 (ja) 電子装置
TW200941681A (en) Package substrate with high heat dissipation capability and method of fabricating the same
JP2008258552A (ja) 半導体チップ積層実装体の製造方法