200941681 九、發明說明： 【發明所屬之技術領域】 / 本發明係有關於一種封裝基板及其製法，尤指一種高 :散熱封裝基板及其製法。 【先前技術】 由於電子產品曰趨輕薄短小，故對於用於承載半導體 晶片或電子元件之封裝基板亦需隨之縮減，而半導體封裝 技術的演進已開發出不同的封裝型態，其中如球栅陣列式 ❿（Ball grid array, BGA)，係為一種先進的半導體封裝技 術，能在相同單位面積之封裝基板上可以容納更多輪入/ 輸出連接端（I/O connection)以符合高度集積化 (Integration)之半導體晶片所需。 以開窗型球栅陣列式（Wind〇w Ball Grid ΑπΜ ， Window BGA)半導體封裝爲例，由於其能有效缩小bga 封裝產品之封裝尺寸，因而得以期符合電子產品輕薄短小 的發展趨勢。開窗型球珊陣列式封裝之特徵在於其電路板 開設至少-貫穿該電路板之開口，以供一半導體晶 於該電路板之-表面，且封住該開口之一端，並藉由穿過 該開口之係如金線之導線，使該半導體晶片電性連接至該 電路板另一表面之電性連接塾。為提升電性連接墊與導線 之間之電性搞合，通常會在該電性連接塾之外露表面形成 -錄/金（Ni/Au)層’此外亦可#此避免因外界環境影塑而 導致該電性連接塾本體，一般為鋼金屬之氧化，該電性連 接塾，可例如為半導體晶片封裝電路板之打線墊（B〇nding 110642 5 200941681 finger)，並於該電性連接墊外露之表面覆蓋有一鎳/公 .層，俾於後續之打線作業（Wi re Bondi ng)時，得藉由金^ 與電路板之打線墊均具有相同金屬之材質有較佳之結^ ’性’以提昇兩者之電性耦合。 σ 請參閱第1圖，係為習知開窗型球柵陣列式⑺时⑽ BGA)之半導體封裝結構之剖視圖，該半導體封裝結構包人 二基板10及半導體晶片u，其中該基板iQ具有至少: 貫穿該基板1G之開口⑽，而該半導體晶片u具有一作 ©用面lh及非作用* llb，該作用面Ua具有複數電極墊 =該半導體晶片η係以作用φ lla接置於該基板 之一表面，並封住該基板10之開口 100的一端，並 打線連接（Wlre bonding)之導線12穿過該開口 100， 半導體晶片11電性連接該基板10另-表面之電性連 广且於該電性連接墊13上形成覆有係為鎳 2屬保護層U，並於該半導體晶片11α及導線12上 © -丛封裝材料15，其餘之電性連接墊13另接置有—烊接 兀件16。 穿、晶^於則述結構中’該半導體晶片11藉由該導線12 墊ΐ°3*帝1/0以電性連接該基板1〇另一表面之電性連接 所， >而^長°玄導線12的長度而影響訊號傳輸速度與品 一 P且°玄半導體晶片11係接置於該基板10之開口 100 n而道亚以封裝材料15覆蓋該導線12以及半導體晶片 U’導致整體之封裝尺寸料，並且以散熱。 士何提出一種封裝基板及其製法，以克服習知 6 110642 200941681 開窗型球柵陣列式之半導體封裝結構中，整體 較高、不易散熱等問題，實 =士裝尺寸 :.·題。 周匕成局目剧業界亟待解決之課 ·'【發明内容】 馨於上述習知技術之缺失，本發明 供一種高散埶封裝吴柘月甘制、士 ΘΑ 文日的在於^ 升ml 製純好n力能，以提 升放”、、效率，進而增進接置其上之晶片效能。 •立製法”二又目的在於提供一種高散熱封裝基板及 ❺其I法，旎降低封裝基板之整體厚度。 I製η另一目的在於提供一種高散熱封裝基板及 -1法、’此降低訊號損失及增快訊號傳輸速度。200941681 IX. Description of the invention: [Technical field to which the invention pertains] / The present invention relates to a package substrate and a method of manufacturing the same, and more particularly to a high heat dissipation package substrate and a method of fabricating the same. [Prior Art] Since electronic products tend to be thin and light, the package substrate for carrying semiconductor wafers or electronic components needs to be reduced, and the evolution of semiconductor packaging technology has developed different package types, such as ball grids. Ball grid array (BGA) is an advanced semiconductor packaging technology that can accommodate more I/O connections on a package substrate of the same unit area to meet high integration. (Integration) semiconductor wafer required. Taking the window-type ball grid array (Wind〇w Ball Grid ΑπΜ, Window BGA) semiconductor package as an example, it can effectively reduce the light and thin trend of electronic products because it can effectively reduce the package size of bga package products. The window-opening ball array package is characterized in that the circuit board is opened at least through the opening of the circuit board for a semiconductor crystal to be on the surface of the circuit board, and one end of the opening is sealed and passed through The opening is such as a wire of a gold wire that electrically connects the semiconductor chip to an electrical connection port on the other surface of the circuit board. In order to improve the electrical connection between the electrical connection pads and the wires, it is usually formed on the exposed surface of the electrical connection --recording/gold (Ni/Au) layer, and can also avoid the external environment. The main body of the electrical connection is generally oxidized by a steel metal, and the electrical connection may be, for example, a wire pad of a semiconductor chip package circuit board (B〇nding 110642 5 200941681 finger), and the electrical connection pad The exposed surface is covered with a nickel/male layer. When the wire bonding operation (Wi re Bonding) is performed, the material of the same metal as the wire mat of the circuit board has a better quality. To enhance the electrical coupling between the two. σ Referring to FIG. 1 , which is a cross-sectional view of a semiconductor package structure of a conventional window type ball grid array type (7) (10) BGA, the semiconductor package structure includes a second substrate 10 and a semiconductor wafer u, wherein the substrate iQ has at least : an opening (10) penetrating the substrate 1G, and the semiconductor wafer u has a surface lh and a non-active layer llb, the active surface Ua has a plurality of electrode pads = the semiconductor wafer η is attached to the substrate by the action φ 11a a surface, and one end of the opening 100 of the substrate 10 is sealed, and a wire 12 connected by a wire bonding is passed through the opening 100. The semiconductor wafer 11 is electrically connected to the other surface of the substrate 10. The electrical connection pad 13 is formed with a protective layer U of nickel and is attached to the semiconductor wafer 11α and the wire 12, and the remaining electrical connection pads 13 are further connected to each other. Condition 16. In the structure, the semiconductor wafer 11 is electrically connected to the other surface of the substrate 1 by the wire 12, and is electrically connected to the other surface. The length of the sinusoidal wire 12 affects the signal transmission speed and the product P and the 玄 半导体 semiconductor wafer 11 is connected to the opening 100 n of the substrate 10 and the directional tape 15 covers the wire 12 and the semiconductor wafer U ′ with the encapsulation material 15 to cause the whole The package is sized and cooled. Shi He proposed a package substrate and its manufacturing method to overcome the conventional 6 110642 200941681 window type ball grid array type semiconductor package structure, the overall high, not easy to heat and other issues, the real = size: . Zhou Yucheng's eye-catching class in the industry. '[Invention] The lack of the above-mentioned conventional technology, the present invention is for a high-density package, Wu Yuyue, Gan, and Shifu. n force energy, in order to enhance the efficiency, and thus enhance the efficiency of the wafer on which it is placed. • The vertical method is also intended to provide a high heat dissipation package substrate and the I method to reduce the overall thickness of the package substrate. Another purpose of the I system is to provide a high heat dissipation package substrate and the method of reducing the signal loss and increasing the signal transmission speed.
為達上述及其他目的，本發明描4» U 板，係包括：其板# 向散熱封裝基 ^括基板本體，料有相對應之第—表面及第二 〃有貝穿該第-表面及第二表面之第一開口；第 層绩係設於該第一表面上，並具有複數第一打線 ❹口以开:，係設於該第二表面上’且封住該第-開 晶片置放區；第—防焊層，騎於該第一表面 片置放F ^層上’ 5亥第一防焊層具有第二開口以顯露該晶 1而該第—打線塾；以及第：防焊層，係設於該第 一表面及第二線路層上。 之^構中’該基板本體係為絕緣板；復包括導電 ::導電盲孔’係貫穿該基板本體，並電性連接該第一 線路層’復包括金屬保護層，係設於該第—打線塾 上0 110642 7 200941681 、依上述之結構，復包括導體層，係設於該晶片置放區 • 第開之孔土上’且遠苐一線路層復具有位於該第一 ，開口周圍之複數第二打線塾，且該第二打線塾連接該第一 ，：孔壁上之導體層，又該第-防焊層之第二開口並顯 露5亥弟一打線塾；復包括金屬保護層，係設於該導體層、 第一打線墊及第二打線墊上。 又依上述結構，該第一線路層具有複數第一焊接塾， 且該第一防焊層具有複數第—開孔，以對應顯露各該第一 ❹焊接塾，該第二線路層具有複數第二焊接墊，且該第二防 焊層具有複數第二開孔，以對應顯露各該第二焊接塾 包括金屬保護層，係設於該第一焊接塾及第二焊接塾上。 本發明復提供-種高散熱封裝基板之製法，係包括· 以共-具有相對應之第-及第二表面之基板本體，於該第 :及第二表面分別形成第一及第二金屬層；於該第一金 開口；於該基板本體中對應該置晶開口 2貝穿該苐一及第二表面之第一開口，且該第— m屬層’使該第，中之第二金屬層成為晶 m 第二金屬層經圖案化以分別形成第 :^二線路層，該第—線路層具有複數第—打線塾；於 ㈣-表面及第-線路層上形成第一防谭層，並於該第一 防焊層中形成第二開σ以顯露該晶片置放區與該第 :墊；以及於該第二表面及第二線路層上形成第 依上述之製法，該基板本體料絕緣板，· €包括於該 110642 8 200941681 基板本體形成有通孔，於該通孔中形成導電通孔，以電性 块接β玄第—及第二線路層；或於該第一金屬層形成複數 /開孔，並對應各該開孔形成貫穿該基板本體之盲孔，且該 ，盲孔未貫穿該第二金屬層，於該盲孔中形成導電盲孔，以 電性連接該第-及第二線路層；復包括金屬保護層，係設 於該第一打線勢上。 又依上述之製法，復包括形成該第一及第二線路層， 並於該晶片置放區及第—開口之孔壁上形成—導體層； ❹该第-線路層復具有位於該第一開口周圍之複數第二打 線墊’且該第二打線墊連接該第一開口之孔壁上的導體 層，又該第一防焊層之第二開口並顯露該第二打線墊丨復 =於該導體層、第-打線塾及第二打線塾上形成金屬保 瘦層。 再依★上述之製法，該第一線路層復具有複數第一谭接 該第焊層復形成複數第-開孔，以對應顯露各 Q二 ，該第二線路層復具有複數第二焊接墊，且 防焊層復形成複數第二開孔，以對應顯 =復包括金屬保護層，係設於該第一焊接塾上 本發明之高散熱封裝基板及其製法， 裝基板之第，中厚t I: ，導：長度以增加傳輸速度，且該封裝基板係： !:導體層接置半導體晶片，故可增加散熱效果，又，: 。層開口之孔壁所設導體層復可供遮蔽外 = 110642 9 200941681 以供接地（Grounding)之 進而可提升整體基板之佈 擾’並電性連接該第二打線墊 用，可減少導電通孔之數目， :線密度。 【實施方式】 說明本發明之實施方 書所揭示之内容輕易地 以下係藉由特定的具體實例 式’熟悉此技藝之人士可由本說明 瞭解本發明之其他優點與功效。 [第一實施例]In order to achieve the above and other objects, the present invention describes a 4» U-plate, comprising: a plate # directional heat-dissipating base comprising a substrate body, the corresponding first surface and the second surface having the first surface and a first opening of the second surface; the first layer is disposed on the first surface, and has a plurality of first wire openings to be opened: and is disposed on the second surface and sealing the first opening wafer a first solder mask, the first solder mask layer is placed on the F ^ layer, and the first solder resist layer has a second opening to expose the crystal 1 and the first wire bond; and the first: The solder layer is disposed on the first surface and the second circuit layer. In the structure, the substrate is an insulating plate; the composite includes a conductive: a conductive blind hole, which penetrates the substrate body, and is electrically connected to the first circuit layer, and includes a metal protective layer, which is disposed in the first In the above structure, the conductor layer is further disposed on the first and second opening layers a plurality of second wire 塾, and the second wire 塾 is connected to the first, the conductor layer on the wall of the hole, and the second opening of the first solder resist layer reveals a lap of the hexagram; the composite layer includes a metal protective layer The system is disposed on the conductor layer, the first bonding pad and the second bonding pad. According to the above structure, the first circuit layer has a plurality of first soldering pads, and the first solder resist layer has a plurality of first opening holes to correspondingly expose the first first soldering pads, the second circuit layer has a plurality of And a second soldering pad, wherein the second solder mask has a plurality of second openings, so as to correspondingly expose the second soldering pads, including a metal protective layer, disposed on the first soldering pads and the second soldering pads. The invention provides a method for manufacturing a high heat dissipation package substrate, comprising: a substrate body having a corresponding first and second surfaces, wherein the first and second metal layers are respectively formed on the first and second surfaces In the first gold opening; a first opening corresponding to the first and second surfaces of the substrate opening in the substrate body, and the first m-layer 'make the second metal of the first and second The layer becomes a crystal m. The second metal layer is patterned to form a second circuit layer, wherein the first circuit layer has a plurality of first-wire layers; and the first anti-tan layer is formed on the (four)-surface and the first circuit layer. And forming a second opening σ in the first solder resist layer to expose the wafer placement area and the first pad; and forming a method according to the above method on the second surface and the second circuit layer, the substrate body material Insulating board, · included in the 110642 8 200941681 substrate body is formed with a through hole, a conductive through hole is formed in the through hole, electrically connecting the β Xuan - and the second circuit layer; or the first metal layer Forming a plurality of openings/openings, and forming a blind hole penetrating through the substrate body corresponding to each of the openings And the blind hole does not penetrate the second metal layer, and the conductive blind hole is formed in the blind hole to electrically connect the first and second circuit layers; the metal protective layer is further included in the first wire bonding potential on. According to the above method, the first and second circuit layers are formed, and a conductor layer is formed on the wafer placement area and the first opening hole wall; and the first line layer has the first layer a plurality of second wire mats around the opening' and the second wire bonding pad is connected to the conductor layer on the hole wall of the first opening, and the second opening of the first solder resist layer reveals the second wire bonding pad A metal thin layer is formed on the conductor layer, the first wire and the second wire. According to the above method, the first circuit layer has a plurality of first slabs connected to the first solder layer to form a plurality of first-opening holes to correspondingly expose each of the Q2, and the second circuit layer has a plurality of second solder pads And the solder resist layer is formed into a plurality of second openings, corresponding to the display of the metal protective layer, and the high heat dissipation package substrate of the invention is disposed on the first soldering pad, and the method for manufacturing the substrate, the medium thickness t I: , Guide: length to increase the transmission speed, and the package substrate is: !: The conductor layer is connected to the semiconductor wafer, so the heat dissipation effect can be increased, and: The conductor layer provided on the hole wall of the layer opening is covered for shielding = 110642 9 200941681 for grounding, which can enhance the interference of the whole substrate and electrically connect the second wire pad to reduce the conductive through hole Number, line density. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The disclosure of the present invention is readily made by the following specific examples. Those skilled in the art can understand the other advantages and effects of the present invention. [First Embodiment]
娜基板及 〃如第2Α圖所示’首先，提供一具有相對應之第一及 第二表面20a’20b之基板本體2〇，於該第一及第二表面 20a，20b分別形成第一及第二金屬層21a 21b，其中該 第一及第二金屬層21a，21b係為銅箔，該基板本體2〇係 為絕緣板。 如第2B圖所示，該第一金屬層21 β經圖案化形成置 ®晶開口 210a及複數開孔21 Ob。 如第2C圖所示，於該基板本體2〇中對應該置晶開口 210a开》成貫穿該第一及第二表面20a，20b之第一開口 200 ’且該第一開口 200未貫穿該第二金屬層21b，使該 第一開口 200中之第二金屬層21b成為晶片置放區2〇c， 又於該基板本體20、第一及第二金屬層21a，21b中以機 械鑽孔形成貫穿之通孔201，並對應該開孔210b以雷射 燒融（laser ablation)形成貫穿該基板本體20之盲孔 10 110642 200941681 202，且該盲孔202未貫穿該第二金屬層21b β 如第21)圖所示，以物理沈積之濺鍍（Sputtering)或 .··化學沈積之無電鍍方式，於該第一金屬層21a上、第二金 ，屬層21b上、第一開口 2〇〇之孔壁上、通孔2〇1之孔壁上 及盲孔202之孔壁上形成導電晶種層22，該導電晶種層 22主要作為後述電鍍所需之電流傳導路徑，其可由金 屬、合金或沉積數層金屬層所構成，如選自銅、錫、鎳、 鉻、鈦及銅-鉻合金等所組群組之其中一者，或該導電晶 ©種層22係為聚乙快、聚苯胺或有機硫聚合物等導電高: 子材料；接著，於該導電晶種層22上形成光阻層23，且 該光阻層23經圖案化形成複數光阻層開口區23〇，以顯 露該導電晶種層22之部份表面。 如第2E及2E’圖所示，於該光阻層開口區23〇中之 導電晶種層22上形成-第三金屬層21c’且於該通孔2〇1 令形成導電通孔21d，並於該盲孔2〇2中形成導電盲孔 ❹：le’如第冗圖所示；或該導電通孔2id及導電盲孔… 可為第三金屬層21c所鍍滿，如第2E，圖所示； 2丑圖所示之結構作說明。 如第2F圖所示，移除該光阻層23及其 二種層22、第一及第二金屬層21a，21b，以於該;板2 之弟-表面20a形成由該第一金屬層叫、導電晶種層 及第三金屬層21c所組成之第一線路層2〗，， =，具有複數第-焊接塾2Π及第一打線塾;3;並 …基板本體20之第二表® 20b形成由該第二金屬層 110642 11 200941681 &笔BB種層2 2及第三金屬層21 c所組成之第二線路 ..層21” ’該第二線路層21，，復具有複數第二焊接墊212。 '该第一線路層21，以該導電通孔21d及/或導電盲孔2ie 電性連接該第二線路層21，，。 如第2G、2G’、及2G”圖所示，於該第一表面2〇a及 第一線路層21，上形成第一防焊層24a，並於該第一防焊 層24a中形成第二開口 24〇a以顯露該晶片置放區2〇c及 弟打線塾213，且於該第一防焊層24a形成複數第一開 鲁孔241a’以對應顯露各該第一焊接墊211;並於該第二表 面20b及第二線路層21”上形成第二防焊層24b，且於該 第二防焊層24b形成複數第二開孔241b，以對應顯露各 该第二焊接墊212;如第2G圖所示，該導電通孔2id及 導電盲孔21e中剩餘之空間係填滿該第一防焊層24&及/ 或第二防焊層24b;或者如第2G，圖所示，該導電通孔 21d’及導電盲孔21e’係鍍滿該第三金屬層21c;或者如第 ❾2G”圖所示’該導電通孔21d及導電盲孔21e之空隙中填 入係為樹脂（resin)之塞孔材料21f;之後以第2G圖所示 之結構作說明。 如弟2H圖所示，於該晶片置放區2〇c中之第二金屬 層21b、第一焊接墊211、第二焊接墊212及第一打線墊 213上形成金屬保護層25,以完成本發明之高散熱封襄基 板’其中該金屬保護層25之材料係選自銅、錫、錯、銀、 鎮、金、翻之組合及上述成份之合金。 如第21圖所示，係本發明之高散熱封裝基板之應用 110642 12 200941681 ^，其係於該晶片置放區1上接置半導體晶片％， •，亥+導體晶片26具有一作用面26a及非作用面挪，該 ^作用Φ 26a具有複數電㈣加，且該半導體晶片26以 1其非作用面26b接置於該晶片置放區2〇c上，並以導線 262電性連接該第一打線墊213上之金屬保護層μ及半 導體晶片26之電極塾261;另以封裝材料⑽包覆該第 幵’ 200半導體晶片26及導線262，俾以保護該半導 體晶片26之作用面26a及導線262。 • 如第2J至2J”圖所示，於該第一焊接墊211之金屬 保護層25上形成第一焊接元件27卜且於該第二焊接塾 212之金屬保護層25上形成第二焊接元件272，如第 圖所示·’或於該第二表面20b及第二線路層21，，上全面形 成第二防焊層24b’如第2J，圖所示；或該第一防焊層2如 不顯露該第一線路層21，，如第2J”圖所示。 [弟二實施例] 請參閱第3八至3D圖，係顯示本發明高散熱封裝基板 及其製法第二實施例製法之剖面示意圖，與前述第一實施 例大致相同，主要不同之處在於本實施例中該基板本體之 第一開口之孔壁及晶片置放區上形成第三金屬層以成為 導體層，及於該基板本體之第一表面形成第二打線墊。 如第3A圖所示，先提供係如第2C圖所示之結構，並 於該第一金屬層21a上、第二金屬層21b上、第一開口 200之孔壁上、通孔201之孔壁上及盲孔2〇2之孔壁上形 成一導電晶種層22,再於該導電晶種層22上形成光阻層 110642 13 200941681 23,且該光阻層23經圖案化形成複數光阻層開口區23〇, 以顯露部份之第一金屬層21a、部份第二金屬層21b、第 一開口 200之孔壁及晶片置放區2〇ci之導電晶種層22。 1 如第3B圖所示，復如第2E至2H圖所示之製作流程， 於形成該第-及第二線路層21，，21，，’並於該第一開口 2〇〇 之孔壁及該晶片置放區2〇c上形成第三金屬層2ic，以形 成導體層21g，並於該第一開口 2〇〇周圍之 打線塾…，且該第二打線塾214連接該第一：=: ©孔壁上之導體層21g ’又該第一防焊層24&之第二開口 240a並顯露該第二打線墊214;復於該導體層第一 焊接墊211、第二焊接墊212、第一打線墊213及第二打 線藝214上形成金屬保護層25，以完成本發明之高散熱 封裝基板。 如第3C至3C”圖所示，係本發明之高散熱封裝基板 之應用實例，其係於該晶片置放區20c之導體層21g上接 置半導體晶片26’該半導體晶片26具有一主動面⑽及 非主動面26b ’ s亥主動面26a具有複數電極墊261，且該 半導體晶片26以其非主動面26b接置於該晶片置放區 2〇c上，並以複數導線262分別電性連接該第一打線塾213 =體：片26之電極塾26卜及電性連接該第二打線 及半導體晶片26之電極墊26卜使該半導體 =與導=層叫進行接地价_叫），並以該導體層日 =放熱及遮蔽外界電磁波之干擾，以保護該半導體晶片 Π0642 14 200941681 *復於該第一焊接墊211之金屬保護層25上形成第一 焊接元件271，且於該第二焊接墊212之金屬保護層25 上形成第二焊接元件272 ,如第3C圖所示；或於該第二 表面20b及第二線路層21”上全面形成第二防焊層24b, 如第3C’圖所示；或該第一防焊層24a不顯露該第一線路 層21’，如第3C”圖所示。 如第3D圖所示，係為本發明之另一應用，其中係以 第3C”圖之結構疊接於第3C圖之結構的上方，並電性連 ❺接所成之封t豐加（Package on package)結構。 本發明復提供一種高散熱封裝基板，如第2}ί圖所 不，係包括：基板本體20，係具有相對應之第一表面2〇a 及第二表面20b，且具有貫穿該第一表面2〇a及第二表面 20b之第一開口 200;第一線路層21，’係設於該基板本 體20之第一表面2〇a’並具有複數第一打線墊213;第二 線路層21”，係設於該基板本體2〇之第二表面2〇b，且封 ❿住該第一開口 200以形成一晶片置放區2〇c;第一防焊層 24a ’係設於該第一表面2〇a及第一線路層21，上，且該 第一防焊層24a中具有第二開口 240a以顯露該晶片置放 區20c，以及第二防焊層24b，係設於該第二表面20b及 第二線路層21”上。 上述之結構中’該基板本體20係為絕緣板；該晶片 置放區20c及第一開口 200之孔壁上設有導體層21g，且 該第一線路層21’具有設於該第一開口 2〇〇周圍之複數第 一打線墊214，且該第二打線墊214連接該第一開口 2〇〇 15 110642 200941681 ；^孔壁上之導體層21g ’又該第_防焊層恤之第二開口 .240a並顯露該第二打線塾214，如第祁圖所示。 又依上述結構，復包括導電通孔21d或導電盲孔 21e ’係貝穿該基板本體2〇，並電性連接該第一及第 路層 21’，21”。 又依上述結構，該第一線路層21，具有複數第一焊接 塾211，且該第-防焊層24a具有複數第一開孔如，以 對應顯露各該第-焊接墊211;該第二線路層21”復具有 β複數第二焊接墊212’且該第二防焊層24b具有複數第二 開孔241b，以對應顯露各該第二焊接墊212。 又依上述結構，復包括於該導體層21g、第一焊接 21卜第二焊接墊212、第-打線塾213及第二打線塾214 上形成金屬保護層25，如第2H圖及第3B圖所示。 综上所述，本發明之高散熱封裝基板及其製法’係可 將一半導體晶片置於該封裝基板之第一開口中，以降低封 ❹ 裝厚度，並縮短導線長度以增加傳輸逮度，且該封譽某' 係以晶片置放區之導體層接置半導體晶片’故可^ 效果’又該壓合層開π之孔壁所設導體層復可供^ ^ 電磁波干擾’並電性連接該第二打磕 ' μ 、 7綠墊，以供接地 (Grounding)之用，可減少導電通孔之數 u 進而可提弁 整體基板之佈線密度。 7 上述實施例僅例示性說明本發明之原理及其功六 非用於限制本發明。任何熟習此項技藝之 >丈而 ., 贫 八士均可在不遠 月本發明之精神及㈣下，對上述實施例進行修飾與改 110642 16 200941681 ’應如後述之申請專利 球柵陣型式封裝結構 :變。因此，本發明之權利保護範圍 範圍所列。 /【圖式簡單說明】 第ί圖係為習用底穴置晶型 圖；And the first substrate and the second surface 20a' The second metal layer 21a 21b, wherein the first and second metal layers 21a, 21b are copper foils, and the substrate body 2 is an insulating plate. As shown in Fig. 2B, the first metal layer 21 β is patterned to form a crystal opening 210a and a plurality of openings 21 Ob. As shown in FIG. 2C, in the substrate body 2, the corresponding opening 210a is opened to penetrate the first opening 200' of the first and second surfaces 20a, 20b, and the first opening 200 does not penetrate the first opening 200 The second metal layer 21b is such that the second metal layer 21b in the first opening 200 becomes the wafer placement area 2〇c, and is formed by mechanical drilling in the substrate body 20, the first and second metal layers 21a, 21b. Through the through hole 201, and forming a blind hole 10 110642 200941681 202 through the substrate body 20 by laser ablation, and the blind hole 202 does not penetrate the second metal layer 21b β As shown in Fig. 21), the first metal layer 21a, the second gold, the genus layer 21b, and the first opening 2 are formed by sputtering of physical deposition or electroless plating. A conductive seed layer 22 is formed on the wall of the hole, on the hole wall of the through hole 2〇1, and on the hole wall of the blind hole 202. The conductive seed layer 22 is mainly used as a current conduction path required for electroplating, which may be metal. , alloying or depositing several layers of metal, such as selected from the group consisting of copper, tin, nickel, chromium, titanium, and copper-chromium One of the group of alloys or the like, or the conductive crystal layer 22 is a conductive high: sub-material such as polyethylidene, polyaniline or organic sulfur polymer; and then formed on the conductive seed layer 22. The photoresist layer 23 is patterned to form a plurality of photoresist layer opening regions 23A to expose a portion of the surface of the conductive seed layer 22. As shown in FIGS. 2E and 2E', a third metal layer 21c' is formed on the conductive seed layer 22 in the open region 23A of the photoresist layer, and a conductive via 21d is formed in the via hole 2? And forming a conductive blind via ❹: le' as shown in the redundancy diagram; or the conductive via 2id and the conductive blind via... can be plated for the third metal layer 21c, as in 2E, Figure 2; 2 ugly figure shows the structure. As shown in FIG. 2F, the photoresist layer 23 and its two layers 22, the first and second metal layers 21a, 21b are removed, so that the first surface of the board 2 is formed by the first metal layer. The first circuit layer 2 composed of the conductive seed layer and the third metal layer 21c, has a plurality of first-welding Π2Π and the first wire 塾; 3; and the second table of the substrate body 20 20b forms a second line composed of the second metal layer 110642 11 200941681 & pen BB seed layer 2 2 and third metal layer 21 c. layer 21" 'the second circuit layer 21, the complex has a plurality of The second soldering pad 212. The first circuit layer 21 is electrically connected to the second circuit layer 21 by the conductive via 21d and/or the conductive via 2ie. For example, the 2G, 2G', and 2G" a first solder resist 24a is formed on the first surface 2a and the first circuit layer 21, and a second opening 24a is formed in the first solder resist 24a to expose the wafer placement area. 2〇c和弟线线塾213, and forming a plurality of first open holes 241a' in the first solder resist layer 24a to correspondingly expose the first solder pads 211; and on the second surface 20b and the second circuit layer a second solder mask 24b is formed on the 21", and a plurality of second openings 241b are formed in the second solder resist layer 24b to correspondingly expose the second solder pads 212; as shown in FIG. 2G, the conductive vias The remaining space in the 2id and conductive blind vias 21e fills the first solder resist layer 24& and/or the second solder resist layer 24b; or as shown in FIG. 2G, the conductive via 21d' and the conductive via hole 21e' is plated with the third metal layer 21c; or as shown in FIG. 2G", the gap between the conductive via 21d and the conductive via 21e is filled with a plug material 21f which is a resin; The structure shown in Fig. 2G is explained. As shown in FIG. 2H, a metal protective layer 25 is formed on the second metal layer 21b, the first soldering pad 211, the second soldering pad 212, and the first bonding pad 213 in the wafer placement area 2〇c to complete The high heat-dissipating sealing substrate of the present invention wherein the material of the metal protective layer 25 is selected from the group consisting of copper, tin, silver, silver, town, gold, and a combination of the above components. As shown in FIG. 21, the application of the high heat dissipation package substrate of the present invention is 110642 12 200941681 ^, which is attached to the wafer placement area 1 by a semiconductor wafer %, and the HEL + conductor wafer 26 has an active surface 26a. The non-active surface Φ 26a has a plurality of electric (four) additions, and the semiconductor wafer 26 is placed on the wafer placement area 2〇c with its non-active surface 26b, and electrically connected by wires 262. a metal protection layer μ on the first bonding pad 213 and an electrode 塾 261 of the semiconductor wafer 26; the second '200 semiconductor wafer 26 and the wiring 262 are covered with a sealing material (10) to protect the active surface 26a of the semiconductor wafer 26. And wire 262. As shown in the 2J to 2J", a first soldering element 27 is formed on the metal protective layer 25 of the first solder pad 211, and a second soldering component is formed on the metal protective layer 25 of the second soldering pad 212. 272, as shown in the figure, or on the second surface 20b and the second circuit layer 21, the second solder resist layer 24b' is formed over the entire surface as shown in FIG. 2J; or the first solder resist layer 2 If the first circuit layer 21 is not revealed, as shown in FIG. 2J". [Second Embodiment] Please refer to FIGS. 3-8 to 3D, which are schematic cross-sectional views showing the manufacturing method of the high heat dissipation package substrate and the second embodiment of the method of the present invention, which are substantially the same as the first embodiment described above, and the main difference is that In the embodiment, a third metal layer is formed on the hole wall and the wafer placement area of the first opening of the substrate body to form a conductor layer, and a second wire pad is formed on the first surface of the substrate body. As shown in FIG. 3A, the structure shown in FIG. 2C is first provided, and the hole is formed on the first metal layer 21a, the second metal layer 21b, the hole wall of the first opening 200, and the through hole 201. A conductive seed layer 22 is formed on the wall of the wall and the hole of the blind hole 2〇2, and a photoresist layer 110642 13 200941681 23 is formed on the conductive seed layer 22, and the photoresist layer 23 is patterned to form a plurality of light. The barrier opening region 23 is formed to expose a portion of the first metal layer 21a, a portion of the second metal layer 21b, the hole walls of the first opening 200, and the conductive seed layer 22 of the wafer placement region 2〇ci. 1 as shown in FIG. 3B, the fabrication process shown in FIGS. 2E to 2H is performed to form the first and second circuit layers 21, 21, and 'in the hole wall of the first opening 2 And forming a third metal layer 2ic on the wafer placement area 2〇c to form a conductor layer 21g, and a wire 塾 around the first opening 2〇〇, and the second wire 塾214 is connected to the first: =: © the conductor layer 21g on the wall of the hole, and the second opening 240a of the first solder resist layer 24 & and the second wire pad 214 is exposed; the first solder pad 211 and the second solder pad 212 are added to the conductor layer A metal protective layer 25 is formed on the first bonding pad 213 and the second bonding pattern 214 to complete the high heat dissipation packaging substrate of the present invention. As shown in FIG. 3C to FIG. 3C, an application example of the high heat dissipation package substrate of the present invention is to connect a semiconductor wafer 26' to the conductor layer 21g of the wafer placement area 20c. The semiconductor wafer 26 has an active surface. (10) and the inactive surface 26b's active surface 26a has a plurality of electrode pads 261, and the semiconductor wafer 26 is placed on the wafer placement area 2〇c with its inactive surface 26b, and is electrically connected by a plurality of wires 262, respectively. Connecting the first wire 塾 213 = body: the electrode 26 of the film 26 and the electrode pad 26 electrically connected to the second wire and the semiconductor wafer 26 so that the semiconductor = and the layer = grounding price _ call) The first soldering element 271 is formed on the metal protective layer 25 of the first soldering pad 211, and the second soldering element 271 is formed on the metal protective layer 25 of the first soldering pad 211, and the second soldering element 271 is formed on the metal protective layer 25 of the first soldering pad 211. A second soldering member 272 is formed on the metal protective layer 25 of the solder pad 212, as shown in FIG. 3C; or a second solder resist layer 24b is formed on the second surface 20b and the second wiring layer 21", such as the 3C. 'Illustrated; or the first solder mask 24a does not reveal the The first circuit layer 21' is shown in Fig. 3C". As shown in Fig. 3D, it is another application of the present invention, in which the structure of the 3C" is superimposed on the structure of the 3C figure. And electrically connected to the packaged package (package on package) structure. The present invention provides a high heat dissipation package substrate, as in the second embodiment, comprising: a substrate body 20 having a corresponding first surface 2a and a second surface 20b and having a first surface therethrough a first opening 200 of the second surface 20b; the first circuit layer 21 is disposed on the first surface 2〇a' of the substrate body 20 and has a plurality of first bonding pads 213; the second wiring layer 21 a second surface 2〇b of the substrate body 2〇, and sealing the first opening 200 to form a wafer placement area 2〇c; the first solder resist layer 24a′ is disposed in the first a surface 2〇a and a first circuit layer 21, and the first solder resist layer 24a has a second opening 240a to expose the wafer placement area 20c, and a second solder resist layer 24b is disposed on the surface The two surfaces 20b and the second circuit layer 21". In the above structure, the substrate body 20 is an insulating plate; the wafer placement area 20c and the hole wall of the first opening 200 are provided with a conductor layer 21g, and the first circuit layer 21' has a first opening a plurality of first wire mats 214 around the second wire pad 214, and the second wire bonding pad 214 is connected to the first opening 2〇〇15 110642 200941681; the conductor layer 21g on the wall of the hole is the first The second opening .240a and the second line 214 are exposed, as shown in the figure. According to the above structure, the conductive via hole 21d or the conductive via hole 21e' is inserted through the substrate body 2〇 and electrically connected to the first and second via layers 21', 21". a circuit layer 21 having a plurality of first soldering pads 211, and the first solder resist layer 24a has a plurality of first openings such as to expose respective first solder pads 211; the second circuit layer 21" has a complex β The plurality of second solder pads 212' and the second solder mask 24b have a plurality of second openings 241b to correspondingly expose the second solder pads 212. According to the above structure, the metal protective layer 25 is formed on the conductor layer 21g, the first solder 21, the second solder pad 212, the first wire 213, and the second wire 214, as shown in FIG. 2H and FIG. 3B. Shown. In summary, the high heat dissipation package substrate of the present invention and the method for manufacturing the same can be used to place a semiconductor wafer in the first opening of the package substrate to reduce the thickness of the package and shorten the length of the wire to increase the transmission catch. And the affixed one is connected to the semiconductor wafer by the conductor layer of the wafer placement area, so that the effect of the conductor layer of the π-hole wall of the laminated layer is replenished by ^ ^ electromagnetic interference 'electricity Connecting the second cymbal 'μ, 7 green pad for grounding can reduce the number of conductive vias and further improve the wiring density of the entire substrate. The above-described embodiments are merely illustrative of the principles of the invention and the advantages thereof are not intended to limit the invention. Anyone who is familiar with this skill can make modifications and changes to the above-mentioned embodiments under the spirit of the invention and (4), and should apply for the patent ball grid array as described later. Type package structure: change. Therefore, the scope of the claims of the present invention is listed. / [Simple description of the drawing] The second picture is the crystal form of the conventional bottom hole;
第2Α至2J圖係為本發明 一實施例之剖面示意圖，· 之高散熱封裝基板及其製法2A to 2J are schematic cross-sectional views showing an embodiment of the present invention, a high heat dissipation package substrate and a method of manufacturing the same
第2Ε’圖係為第2Ε圖之另一結構之剖面示 第2G，及第2G”圖係為第2G圖之另-結構：剖面示意The second Ε' diagram is a cross-section showing another structure of the second figure, and the second G-Fig.
第2J’及第2J”圖係為第2 j圖之另 一結構之剖面示意 第二發r散熱封裝基板及其製法 圖 第3C’及第3C”圖係為第3(：圖之另—結構之剖面示意2J' and 2J" are the cross-sections of the other structure of the second figure. The second heat dissipation package substrate and its method of drawing 3C' and 3C" are the third (: another figure) Schematic representation of the structure
【主要元件符號說明】 ic 基板 11，26半導體晶片 11b’ 26b非作用面 12，2 6 2 導線 14’ 25金屬保護層 16 焊接元件 200第一開口 100 開口 11a，26a 作用面 111, 261電極塾 13 電性連接塾 15，2 6 3 封裝材料 20 基板本體 201 通孔 110642 17 200941681 202 盲孔 20a 第一表面 20b 第二表面 20c 晶片置放區 21， 第一線路層 21” 第二線路層 211 第一焊接墊 212 第二焊接墊 213 第一打線墊 214 第二打線墊 21a 第一金屬層 210a 置晶開口 21b 第二金屬層 210b 開孔 21c 第三金屬層 21d,21d’ 導電通孔 21 e,: 21e? 導電盲孔 21f 塞孔材料 21g 導體層 22 導電晶種層 23 光阻層 230 光阻層開口區 24a 第一防焊層 240a 第二開口 241a 第一開孔 24b 第二防焊層 241b 第二開孔 271 第一焊接元件 272 第二焊接元件 ❹ 18 110642[Main component symbol description] ic substrate 11, 26 semiconductor wafer 11b' 26b non-active surface 12, 2 6 2 wire 14' 25 metal protective layer 16 soldering element 200 first opening 100 opening 11a, 26a active surface 111, 261 electrode 13 Electrical connection 塾15, 2 6 3 Package material 20 Substrate body 201 Through hole 110642 17 200941681 202 Blind hole 20a First surface 20b Second surface 20c Wafer placement area 21, First circuit layer 21" Second circuit layer 211 First solder pad 212 second solder pad 213 first wire pad 214 second wire pad 21a first metal layer 210a crystallized opening 21b second metal layer 210b opening 21c third metal layer 21d, 21d' conductive via 21 e , 21e? Conductive blind hole 21f Plug material 21g Conductor layer 22 Conductive seed layer 23 Photoresist layer 230 Photoresist layer open area 24a First solder resist layer 240a Second opening 241a First opening 24b Second solder mask 241b second opening 271 first welding element 272 second welding element ❹ 18 110642