1357650 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種封裳基板及其製法，尤指 散熱封裝基板及其製法。 间 【先前技術】 . 由於電子產品日趨輕薄短小，故對於用於承載础1357650 IX. Description of the Invention: [Technical Field] The present invention relates to a substrate and a method for producing the same, and more particularly to a heat-dissipating package substrate and a method for fabricating the same. [Prior Art] . Because electronic products are becoming thinner and lighter, they are used for carrying
元件之封裳基板亦需隨之縮減，而半導體封ί 技：處開發出不同的㈣型態，其中如 J (油㈣町町，_，得、為一種先進的半導體封襄技 術，此在相同單位面積之封裳基板上可以容納更多輪入/ =連接端（I/〇 CQnnecti〇n)以符合高度 (Integration)之半導體晶片所需。 以開窗型球栅陣列式（Wind〇w Bau以 Window BGA)半導體封裳 ， 封裝產品之—得以期::= = 的發展趨勢。開窗型球珊陣列 ：：電專= 開設至少一貫穿該電路板 ⑽在於其電路板 於該電路板之一表面，且封“開二:半山導體:%片接置 該開口之係如金線之導線，使該半:導體晶由穿過 電路板另一表面之電性連接 、接至該 之間之㈣合，通常會在該電與導線 一鎳/金lL , r王連接墊之外露表面形成 ”、，（Au)層，此外亦可藉此避免因外界产 導致該電性連接墊本體，一 ，衣兄衫·#而 接墊，可例如為半導體曰曰 ^金屬之氧化’該電性連 ηι 〜曰片封裝電路板之打線墊(Bondl 110642 5 1357650 f工n g e小並於該電性連接墊外露之表面覆蓋有—鎮/金 【二：:後續之打線作業⑷“時，得藉 ^路板之打線塾均具有相同金屬之材質有較佳之結合 性’以提昇兩者之電性耦合。 1圖’係為習知開窗型球柵陣列式(Wind0W 、V""封$結構之剖視圖，該半導體封I結構包含 一基板10及半導體晶片11，其中該基板1〇具有至少一 貫穿該基板1G之開口跡而該半導體晶片U具有一作 1 用面，1U及非·作用面llb，該作用面iia具有複數電極塾 1〇之=半導體晶片11係以作用面lla接置於該基板 由打並封住該基板10之開口剛的—端，並藉 使；ifrwlrebonding)之導線12穿過該開口⑽， 接11電性連接該基板1G另-表面之電性連 之且於該電性連接墊13上形成覆有係為鎳/金層 2屬保護層14,並於該半導體晶片丨丨以及導線12上 1=裝材料15’其餘之電性連接㈣另接置有一痒接 二於：述結構中，該半導體晶片u #由該導線12 塾^^ 電性連接該基板10另—表面之電性連接 所 而延長s玄導線12的長度而影響訊號傳輸速度與品 貝:/該半導體晶丨11係接置於該基板10之開口 100 二亚以封裝材料15覆蓋該導線12以及半導體晶片 致整體之封|尺寸較高，並且不易散熱。 士何提出-種封I基板及其製法，以克服習知 110642 6 1357650 開窗型球栅陣列式之半導體封農結構中，整 較向、不易散熱等問題，實已成爲、 題。 」某界亟待解決之課 【發明内容】 鑒於上述習知技術之缺失， 供-種高料板及m 主要目的在於提 升散埶Μ · ”好散熱功能，以提 升放熱效率，進而增進接置其上之晶片效能。 ，本4月之又一目的在於提供一種高散熱 其製法，能降低封裝基板之整體厚度。’、、土 本發明之另-目的在於提供—種高散 其製法，能降低訊號損失及增快訊號傳輸速度 板，匕及其他目的，本發明提出-種高散熱封裝基 糸4.基板本體，係具有相對應之第 表：，且具有貫穿該第-表面及第二表面之第一二ί 一線路層’係設於該第一矣 弟 塾，·第_後& & 、 乂 ，並具有複數第一打線 二表面上，且封住該第-開 及第—Lr 防痒層，係設於該第-表面 及弟，·泉路層上，該第一防焊層且右笙—、 片置放區與該第-打線 及第口：』露該晶 二表面及第二線路層上。及第-防焊層，係設於該第 通孔二二，本體係為絕緣板;復包括導電 Γ目.&牙該基板本體，並電性連接該第一 上。 層’ <复包括金屬保護層，係設於該第一打線墊 Π 0642 7 1357650 • μ 一 、之、’°構，復包括導體層，係設於該晶片置放區 乐二之孔壁上’且該第-線路層復具有位於該第一 „ 弟一打線墊，且該第二打線墊連接該第一 開口之孔壁上之導體層， ㈣楚-““ 弟—防焊層之第二開口並顯 1' ，復包括金屬保護層，係設於該導體層、 苐一打線墊及第二打線墊上。 ^ 上述、’ σ構，该第一線路層具有複數第一焊接墊， /第ρ方焊層具有複數第一開孔，以對應顯露各該第一 3塾’該第二線路層具有複數第二焊接塾，且該第二防 、g具有複數第二開孔，以對應顯露各該第二焊接墊；復 包括金屬保㈣’係設於該第―焊㈣及第二焊接塾上。 β本發明復提供-種高散熱封裝基板之製法，係包括·· j供-具有相對應之第一及第二表面之基板本體，於該第 -及第二表面分別形成第一及第二金屬層；於該第一金 屬層形成一置晶開口；於該基板本體中對應該置晶開口 :成貫穿該第一及第二表面之第一開口，且該第一開口未 貝穿该第二金屬層，使該第—開口中之第二金屬層成為晶 片置放區；該第一及第二金屬層經圖案化以分別形成第 :及第二線路層’該第一線路層具有複數第一打線塾；於 攻第一表面及第一線路層上形成第一防焊層，並於該第一 防焊層中形成第二開口以顯露該晶片置放區與該第一打 線墊；以及於該第二表面及第二線路層上形成第二 層。 依上述之製法’該基板本體係為絕緣板；復包括於該 110642 Ϊ357650 基板本體形成有通孔，於該通孔中形成導電通孔，以電性 連接該第-及第二線路層；或於該第―金屬層形成複數 開孔，並對應各該開孔形成貫穿該基板本體之盲孔，且該 盲孔未貫穿該第二金屬層，於該盲孔中形成導電盲孔，以 電性連接該第-及第二線路層；€包括金屬保護層，係設 於該第一打線墊上。 又依上述之製法，復包括形成該第一及第二線路層， 並於該晶片置放區及第一開口之孔壁上形成一導體層； U第-線路層復具有位於該第一開口周圍之複數第二打 塾’且該第二打線塾連接該第—開口之孔壁上的導體 二又《亥f p方知層之第二開口並顯露該第二打線墊；復 =於該導體層、第一打線墊及第二打線墊上形保 蠖層。 再依上述之製法，該第一線路層復具有複數第一谭接 笛且該第一防焊層復形成複數第一開孔，以對應顯露各 该第一焊接墊，該第二線路層復具有複數第二焊接塾，且 :::防焊層復形成複數第二開孔’以對應顯露各該第二 上復包括金屬保護層，係設於該第-烊接墊及第二 本發明之高散熱封裝基板及其製法，係 片置於該封穿美拓夕楚 ^ ^ 千等奴日日 區! = ^增加傳輸速度’且該封裳基板係以晶片置放 I爲曰接置半導體晶片’故可增加散熱效果，又該壓 。曰開口之孔壁所設導體層復可供4蔽外界電磁波干 110642 9 1357650 以供接地（Grounding)之 進而可提升整體基板之佈 •擾，並電性連接該第二打線墊， 用，可減少導電通孔之數目， *線密度。 【實施方式】 以下係藉由特定的且娜杳 的具肢貫例說明本發明之實施方 式，熟悉此技藝之人士可A太甜 本5兒月書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例] 請參閱第2A至2J 其製法第一實施例製法The sealing substrate of the components also needs to be reduced, and the semiconductor sealing technology has developed different (four) types, such as J (Oil), which is an advanced semiconductor sealing technology. The same unit area of the substrate can accommodate more round/= connections (I/〇CQnnecti〇n) to meet the requirements of the semiconductor wafer. The window type ball grid array (Wind〇w) Bau uses Window BGA) semiconductor packaging, packaging products - the development trend of :: = =. Window type ball array:: electricity = open at least one through the board (10) in its circuit board on the board One surface, and the seal "open two: half-hill conductor: % piece is connected to the opening such as the wire of the gold wire, so that the half: the conductor crystal is electrically connected through the other surface of the circuit board, to the The (4) combination usually forms the "Au" layer on the exposed surface of the electric and wire-nickel/gold lL, r-wang connection pad, and can also avoid the external connection body body due to external production. , one, the brother brother shirt · # and the pad, for example, the semiconductor 曰曰 ^ metal The electric wire ηι 〜 曰 片 片 片 片 片 片 (Bondl 110642 5 1357650 f work nge small and exposed on the surface of the electrical connection pad - town / gold [two:: follow-up line work (4) "When you have to use the circuit board, you have the same combination of the same metal material to improve the electrical coupling. 1 Figure ' is a conventional window type ball grid array type (Wind0W, V" The semiconductor package I structure includes a substrate 10 and a semiconductor wafer 11, wherein the substrate 1 has at least one opening trace penetrating the substrate 1G, and the semiconductor wafer U has a surface for use, 1 U The non-active surface 11b has a plurality of electrodes =1 = = the semiconductor wafer 11 is attached to the substrate by the active surface 11a, and the end of the opening of the substrate 10 is sealed and sealed. The wire 12 of the iffwlrebonding) passes through the opening (10), and the connection 11 is electrically connected to the other surface of the substrate 1G and is electrically formed on the electrical connection pad 13 to be covered with a protective layer of nickel/gold layer. 14, and on the semiconductor wafer cassette and the wire 12 1 = loading 15' The remaining electrical connection (4) is further connected to an itch connection: in the structure, the semiconductor wafer u # is electrically connected to the other surface of the substrate 10 by the wire 12 塾 ^ ^ to extend s The length of the sinusoidal wire 12 affects the signal transmission speed and the product: / the semiconductor wafer 11 is connected to the opening 100 of the substrate 10, and the encapsulation material 15 covers the wire 12 and the semiconductor wafer High, and not easy to dissipate heat. Shi He proposed - a kind of I substrate and its manufacturing method to overcome the problems of the conventional 110642 6 1357650 window-type ball grid array type semiconductor sealing structure, the whole direction is relatively easy to dissipate heat, etc. Become a problem. Lessons to be solved in a certain field [Invention] In view of the lack of the above-mentioned prior art, the main purpose of the high-material board and m is to improve the heat dissipation function to improve the heat release efficiency and enhance the connection. The wafer performance of the above. Another purpose of this April is to provide a high heat dissipation method, which can reduce the overall thickness of the package substrate. ',, and another aspect of the invention is to provide a method for high dispersion, which can reduce The present invention proposes a high heat dissipation package base. The substrate body has a corresponding table: and has a through surface and a second surface. The first two 一 one line layer is set in the first 矣 塾, · _ _ & & & & &&;, 并, and has a plurality of first line two surface, and seal the first open and the first - The Lr anti-itch layer is disposed on the first surface and the younger, the spring road layer, the first solder mask layer and the right side, the sheet placement area and the first-line and the first mouth: The surface and the second circuit layer, and the first solder resist layer are disposed on the surface The first through hole 22, the system is an insulating plate; the composite includes a conductive eye. The substrate body is electrically connected to the first upper layer. The layer < complex includes a metal protective layer, which is disposed at the first线线Π 642 0642 7 1357650 • μ, , '° structure, complex including the conductor layer, is placed on the hole wall of the wafer placement area Le Er' and the first-line layer has the first one a wire pad, and the second wire pad is connected to the conductor layer on the hole wall of the first opening, (4) Chu - "" Brother - the second opening of the solder resist layer and display 1", including a metal protective layer, The conductor layer, the first wire pad and the second wire pad. ^ The above, 'σ structure, the first circuit layer has a plurality of first solder pads, and the /th p-square solder layer has a plurality of first openings, so as to correspondingly expose the first three turns, the second circuit layer has a plurality of The second welding rod has a plurality of second openings, so as to correspondingly expose the second welding pads; and the plurality of metal protection (four)' is disposed on the first welding (four) and the second welding crucible. The invention provides a method for manufacturing a high heat dissipation package substrate, comprising: a substrate body having a corresponding first and second surfaces, forming first and second portions on the first and second surfaces, respectively a metal layer; forming a crystal opening in the first metal layer; and correspondingly forming a crystal opening in the substrate body: a first opening penetrating the first and second surfaces, and the first opening does not penetrate the first opening a second metal layer, wherein the second metal layer in the first opening becomes a wafer placement area; the first and second metal layers are patterned to form a first: and a second circuit layer respectively; the first circuit layer has a plurality a first soldering layer is formed on the first surface and the first wiring layer, and a second opening is formed in the first solder resist layer to expose the wafer placement area and the first bonding pad; And forming a second layer on the second surface and the second circuit layer. According to the above method, the substrate is an insulating plate; the substrate is integrally formed with a through hole formed in the body of the 110642 Ϊ 357650, and a conductive via is formed in the through hole to electrically connect the first and second circuit layers; or Forming a plurality of openings in the first metal layer, and forming a blind hole penetrating through the substrate body corresponding to each of the openings, and the blind hole does not penetrate the second metal layer, and a conductive blind hole is formed in the blind hole to electrically The first and second circuit layers are connected; the metal protective layer is disposed on the first wire pad. According to the above method, the first and second circuit layers are formed, and a conductor layer is formed on the wafer placement area and the first opening; and the U-circuit layer has a first opening. a plurality of second snorings surrounding the second wire 塾 and the second wire 塾 is connected to the second opening of the wall of the first opening and revealing the second opening of the layer and revealing the second wire pad; The layer, the first wire mat and the second wire mat have a shape of a protective layer. According to the above method, the first circuit layer has a plurality of first tandem flutes, and the first solder resist layer is formed into a plurality of first openings to correspondingly expose the first solder pads, and the second circuit layer is complex a plurality of second soldering rafts, and::: the solder resist layer is formed into a plurality of second openings 'to correspondingly expose each of the second upper layers including a metal protective layer, and is disposed on the first 烊 pads and the second invention The high heat dissipation package substrate and its manufacturing method, the film is placed in the seal of the United States and the United States ^ ^ Thousand slaves day area! = ^ increase the transmission speed 'and the shelf substrate is placed on the wafer I The semiconductor wafer 'can increase the heat dissipation effect and the pressure. The conductor layer provided on the wall of the opening of the opening can be used to cover the external electromagnetic wave 110642 9 1357650 for grounding, thereby improving the cloth interference of the whole substrate and electrically connecting the second wire pad. Reduce the number of conductive vias, * line density. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific and specific examples, and those skilled in the art can easily understand other aspects of the present invention by the contents disclosed in A. Advantages and effects. [First Embodiment] Please refer to Chapters 2A to 2J for the production method of the first embodiment.
’係顯示本發明高散熱封裝基板及 之剖面示意圖。 如第2A圖所不’首先，提供一具有相對應之第一及 第二表面2Ga，2Gb之基板本體2()，於該第一及第二表面 2/a，20=分別形成第一及第二金屬層213,2化，其中，該 第及第一巫屬21a，21b係為鋼镇，該基板本體2〇係 為絕緣板。 如第2B圖所示’該第一金屬層⑴經圖案化形成置 晶開口 21 Oa及複數開孔21 〇b。 如第2C圖所示’於該基板本體2〇中對應該置晶開口 210a形成貫穿該第一及第二表面2〇a，2〇b之第一開口 200，且該第一開〇 200未貫穿該第二金屬^別，使該 第一開口 200中之第二金屬層21b成為晶片置放區2〇c， 又於該基板本體20、第一及第二金屬層2ia，2ib中以機 械鑽孔形成貫穿之通孔201，並對應該開孔2i〇b以雷射 燒融（laser ablation)形成貫穿該基板本體20之盲孔 110642 10 1357650 202且6亥目孔2〇2未貫穿該第二金屬層Mb。 -如第2D圖所示’以物理沈積之賤鑛（Sputtering)或 :.化學沈積之無電鍍方式，於該第一金屬層⑴上、第二金 .*屬j 21b上、第一開口 2〇〇之孔壁上、通孔2〇1之孔壁上 2 〇 2之孔壁上形成導電晶種層2 2，該導電晶種層 22主要作為後述電鍍所需之電流傳導路徑，其可由金 屬、合金或沉積數層金屬層所構成，如選自銅/錫、鎳·、 鉻、鈦及銅-鉻合金等所組群組之其中一者，或該導電晶 •種層22係為聚乙炔、聚苯胺或有機硫聚合物等導電高分 子材料，接著，於该導電晶種層上形成光阻層23 ,且 j光阻層23經圖案化形成複數光阻層開口區23〇，以顯 露該導電晶種層22之部份表面。 如第2E及2E’圖所示，於該光阻層開口區23〇中之 導電晶種層22上形成-第三金屬層21c，且於該通孔2〇1 令形成導電通孔21d，並於該盲孔202中形成導電盲孔 鲁21e’如第2E圖所示；或該導電通孔21d及導電盲孔 可為第三金屬層21c所鍍滿，如第2E，圖所示；之後以第 2E圖所示之結構作說明。 如第2F圖所示，移除該光阻層23及其所覆蓋之導電 晶種層22、第-及第二金屬層21a，21b，以於該^板本體 2〇之第一表面20a形成由該第一金屬層21a、導電晶種層 22及第三金屬層21c所組成之第一線路層21，，該第一^ 路層21，具有複數第一焊接墊211及第一打線墊213:並 於該基板本體20之第二表面20b形成由該第二金屬層 ]10642 1] 1357650 广:^日種層22及第三金屬層&所組成之第二 :乂，二線路層21，，復具有複數第二焊接塾212。 弟、’A路層21’以該導電 電性連接該第二線路層21 ”。Η及/…目孔叫 莖一 έΦ第2G 2G、及2G，，圖所示，於該第一表面2〇a及 μ 24 φΜ 24a ^ :一 a形成第二開口 24〇a以顯露該晶片置放區別〇及 ^線塾213’且於該第一防輝層池形成複數第—開 241a’以對應顯露各該第—焊接塾2ιι;餘該第 =〇b及第二線路層21，，上形成第二防焊層灿，且於該、 :防，層24b形成複數第二開孔241b，以對應顯露各 :第-焊接塾2⑵如第2G圖所示，該導電通孔叫及 ¥電盲孔21e中剩餘之空間係填滿該第一防焊層⑷及/ 或第二防焊層24b;或者如第2G，圖所示，該導電通孔 21d’及導電盲孔21e，係鍍滿該第三金屬層Η。或者如 2G”圖所示’該導電通孔21d及導電盲孔^之空隙令填 入係為樹脂（resin)之塞孔材料21f;之後以第％圖、 之結構作說明。 Θ 不 如第2Η圖所示，於該晶片置放區2〇c φ夕结 T 第二金屬 層21b、第一焊接墊211、第二焊接墊212 ’ 久弟一打線塾 213上形成金屬保護層2 5 ’以完成本發明之高气熱封茫美 板’其中該金屬保護層2 5之材料係選自领、姐 曰則錫、鉛、銀、 鎳、金、鉑之組合及上述成份之合金。 如第21圖所示，係本發明之高散埶封择波上 .、、衣卷板之應用 110642 12 1357650 “列，其係於該晶片置放區2〇c上 =導體晶…有一作用面26a及非;二 :26a具有複數電極墊26卜且該半導體晶片26以 2:二接置於該晶片置放區2〇c上，並以導線 ,曾^ 第一打線塾213上之金屬保護層25及半 ^肢晶片26之電極墊261;另以封裝材料263包覆該第 一開口 200、半導體晶片26及導 弟 體晶UMM26a_2^62,俾以保護該半導 伴至2J”圖所示’於該第一焊接墊211之金屬 =層25上形成第一焊接元件271，且於該第二桿接塾 212之金屬保護層25上形成第二焊接元件272，如第 圖所…戈於該苐二表面20b及第二線路層21，，上全面形 成第二防焊層24b，如第2Γ圖所示；《該第—防焊層 不顯露該第一線路層21，，如第2j”圖所示。 [第二實施例] 請參閱m 3D圖，係顯示本發明高散熱封襄基板 及其製法第二實施例製法之剖面示意圖，與前述第一實施 例大致相同’主要不同之處在於本實施例中該基板本體之 第-開口之孔壁及晶片置放區上形成第三金屬層：：為 導體t及於該基板本體之第—表面形成第二打線塾。” 如第3A圖所示，先提供係如第2C圖所示之結構，並 於該第一金制21a上、第二金屬層训上、第一開口 200之孔壁上、通孔201之孔壁上及盲孔2〇2之孔壁上形 成-導電晶種層22,再於該導電晶種層22上形成光阻層 110642 13 1357650 復於該第一焊接墊211之金屬保護層25上形成第一 焊接元件271，且於該第二焊接墊212之金屬保護層25 .上形成第二焊接元件272，如第3c圖所示；或於該第二 表面20b及第一線路層21”上全面形成第二防焊層2处， 如第3C’圖所示；或該第一防焊層24a不顯露該第一線路 層21’，如第3C”圖所示。 如第3D圖所示’係為本發明之另一應用，其中係以 第3C”圖之結構疊接於第3C圖之結構的上方，並電性連 •接所成之封裝疊加（Package on package)結構。 本發明復提供一種高散熱封裝基板，如第2}J圖所 不，係包括：基板本體20，係具有相對應之第一表面2〇a 及第二表面20b，且具有貫穿該第一表面2〇a及第二表面 20b之第一開口 200，第一線路層21’，係設於該基板本 肢20之第一表面20a’並具有複數第一打線墊213;第二 線路層21” ’係設於該基板本體20之第二表面20b，且封 鲁住§亥第一開口 2 0 0以形成一晶片置放區2 〇 c;第一防焊層 24a，係設於該第一表面2〇a及第一線路層21，上，且該 第一防焊層24a中具有第二開口 240a以顯露該晶片置放 區20c;以及第二防焊層24b，係設於該第二表面2〇b及 第二線路層21”上。 上述之結構中，該基板本體20係為絕緣板；該晶片 置放區20c及第一開口 200之孔壁上設有導體層21g，且 該第一線路層2 Γ具有設於該第一開口 2 〇 〇周圍之複數第 二打線墊214，且該第二打線墊214連接該第一開口 2〇〇 15 110642 1357650 變。因此，本發明之權利俘嘈銘囹 ^ a 保瘦靶圍，應如後述之申請專利 範圍所列。 -【圖式簡單說明】 .‘圖；帛1圖係為習用底穴置晶型球拇陣型式封褒結構 =至2】圖係為本發明之高散熱封|基板及其製法 弟一貫施例之剖面示意圖； 第2E，圖係為第2E圖之另—結構之剖面示意圖； # . WG’及第2G”圖係為第％圖之另—結構之剖面示意 圖， ^ 第2J’及第2J”圖係為第2】圖之另—結構之剖面示音 圖； … …，3A至3D圖係為本發明之高散熱封裝基板及其製法 第一貫施例之剖面示意圖；以及 第3C’及第3C”圖係為第㈣之另—結構之 音 圖。 心、 鲁【主要元件符號說明】 10 基板 100 開口 11, 26 半導體晶片 1 la, 26a 作用面 lib, 26b非作用面 111, 261 電極塾 12, 262 導線 13 電性連接塾 14, 25 金屬保護層 15, 263 封裝材料 16 焊接元件 20 基板本體 200 第一開口 201 通孔 17 Π0642 1357650 202 盲孑L 20a 第一表面 20b 第二表面 20c 晶片置放區 -21， 第一線路層 21，， 第二線路層 211 第一焊接墊 212 第二焊接墊 213 第一打線墊 214 第二打線塾 21a 第一金屬層 210a 置晶開口 21b 第二金屬層 210b 開孔 21c 第三金屬層 21d，21d’ 導電通孔 ,21e， 21e’ 導電盲孔 21f 基孔材料 21g 導體層 22 導電晶種層 23 光阻層 230 光阻層開口區 24a 第一防焊層 240a 第二開口 241a 第一開孔 24b 第二防焊層 241b 272 第二開孔 第二焊接元件 271 第一焊接元件 18 110642The high heat dissipation package substrate of the present invention is shown in cross section. As shown in FIG. 2A, firstly, a substrate body 2 (2) having corresponding first and second surfaces 2Ga, 2Gb is provided, and the first and second surfaces 2/a, 20= respectively form the first and The second metal layer 213 is formed, wherein the first and second genus 21a, 21b are steel towns, and the substrate body 2 is an insulating plate. As shown in Fig. 2B, the first metal layer (1) is patterned to form a crystal opening 21 Oa and a plurality of openings 21 〇b. As shown in FIG. 2C, a first opening 200 penetrating the first and second surfaces 2a, 2b is formed in the substrate body 2's corresponding to the crystal opening 210a, and the first opening 200 is not Through the second metal, the second metal layer 21b in the first opening 200 becomes the wafer placement area 2〇c, and the machine body 20, the first and second metal layers 2ia, 2ib are mechanically The hole is formed through the through hole 201, and the blind hole 2102b is formed by laser ablation, and the blind hole 110642 10 1357650 202 is penetrated through the substrate body 20 and the 6-hole hole 2〇2 is not penetrated. The second metal layer Mb. - as shown in Fig. 2D, by electroless deposition of Sputtering or: electroless plating, on the first metal layer (1), the second gold. * is j 21b, the first opening 2 A conductive seed layer 22 is formed on the wall of the hole of the crucible and on the wall of the hole of the through hole 2〇1, and the conductive seed layer 22 is mainly used as a current conduction path required for electroplating to be described later. a metal, an alloy, or a plurality of layers of metal, such as one selected from the group consisting of copper/tin, nickel, chromium, titanium, and copper-chromium alloy, or the conductive layer 22 is a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer, and then a photoresist layer 23 is formed on the conductive seed layer, and the j photoresist layer 23 is patterned to form a plurality of photoresist layer opening regions 23, To expose a portion of the surface of the conductive seed layer 22. As shown in FIGS. 2E and 2E', a third metal layer 21c is formed on the conductive seed layer 22 in the open region 23A of the photoresist layer, and a conductive via 21d is formed in the via hole 2? And forming a conductive blind via 21e' in the blind via 202 as shown in FIG. 2E; or the conductive via 21d and the conductive via can be filled with the third metal layer 21c, as shown in FIG. 2E; The structure shown in Fig. 2E will be described later. As shown in FIG. 2F, the photoresist layer 23 and the conductive seed layer 22 and the second and second metal layers 21a and 21b are removed to form the first surface 20a of the board body 2〇. a first circuit layer 21 composed of the first metal layer 21a, the conductive seed layer 22 and the third metal layer 21c, the first circuit layer 21 has a plurality of first solder pads 211 and a first wire pad 213 And forming a second layer of the second metal layer 10102 1] 1357650 wide and the second metal layer & the second circuit layer 20 is formed on the second surface 20b of the substrate body 20: , the complex has a plurality of second welding weirs 212. The 'A road layer 21' is connected to the second circuit layer 21 by the conductive connection. The 孔 and /... the holes are called 茎 Φ 2G 2G, and 2G, as shown in the figure, on the first surface 2 〇a and μ 24 φΜ 24a ^ : aa forms a second opening 24〇a to expose the wafer placement difference 〇 and 塾 塾 213 ′ and forms a plurality of first opening 241 a ′ in the first anti-choke layer pool to correspond The second solder mask layer is formed on the first and second solder layers 2, and the second solder mask layer 241 Correspondingly, each of the first and second solder masks (4) and/or the second solder resist 24b Or as shown in FIG. 2G, the conductive via 21d' and the conductive via 21e are plated with the third metal layer Η or as shown in FIG. 2G 'the conductive via 21d and the conductive blind hole ^ The voids are filled with a plug material 21f which is a resin; the structure of the first graph and the structure will be described later. Θ As shown in Fig. 2, a metal protective layer is formed on the wafer placement area 2〇c φ 结 T T second metal layer 21b, the first solder pad 211, and the second solder pad 212 ' 2 5 'In order to complete the high gas heat sealing of the present invention, the material of the metal protective layer 25 is selected from the group consisting of collar, sister, tin, lead, silver, nickel, gold, platinum and the above components. alloy. As shown in Fig. 21, the application of the high-density sealing wave of the present invention, and the application of the roll plate 110642 12 1357650 "column, which is attached to the wafer placement area 2〇c = conductor crystal... has a function The surface 26a and the second; 26a have a plurality of electrode pads 26 and the semiconductor wafer 26 is placed 2:2 on the wafer placement area 2〇c, and is a wire, and the metal on the first wire 213 The protective layer 25 and the electrode pad 261 of the semiconductor wafer 26; the first opening 200, the semiconductor wafer 26, and the guiding body UMM26a_2^62 are covered by the encapsulating material 263, to protect the semiconductor with the 2J" The first soldering element 271 is formed on the metal=layer 25 of the first soldering pad 211, and the second soldering component 272 is formed on the metal protective layer 25 of the second pole bonding 212, as shown in the figure... The second solder mask layer 24b is formed on the second surface 20b and the second circuit layer 21, as shown in FIG. 2; "the first solder mask does not expose the first circuit layer 21, such as [2th embodiment] [Second embodiment] Please refer to the m 3D diagram, which is a cross-sectional view showing the high heat-dissipating sealing substrate of the present invention and the manufacturing method of the second embodiment thereof. The schematic diagram is substantially the same as the first embodiment. The main difference is that a third metal layer is formed on the first opening wall and the wafer placement area of the substrate body in the embodiment: a conductor t and the substrate The first surface of the body forms a second wire. As shown in FIG. 3A, the structure shown in FIG. 2C is first provided, and the first metal 21a and the second metal layer are trained. a conductive seed layer 22 is formed on the wall of the opening 200, the hole wall of the through hole 201, and the hole wall of the blind hole 2〇2, and a photoresist layer 110642 is formed on the conductive seed layer 22. a first soldering element 271 is formed on the metal protective layer 25 of the first soldering pad 211, and a second soldering component 272 is formed on the metal protective layer 25 of the second soldering pad 212, as shown in FIG. 3c; The second surface 20b and the first circuit layer 21" are integrally formed with the second solder resist layer 2 as shown in FIG. 3C'; or the first solder resist layer 24a does not expose the first circuit layer 21', such as Figure 3C" is shown. As shown in Fig. 3D, it is another application of the present invention, in which the structure of the 3C" is superimposed on the structure of the 3C figure, and the package is electrically connected to the package (Package on The present invention further provides a high heat dissipation package substrate, as in the second embodiment, comprising: a substrate body 20 having a corresponding first surface 2a and a second surface 20b, and having a through The first surface 2A and the first opening 200 of the second surface 20b, the first circuit layer 21' is disposed on the first surface 20a' of the substrate body 20 and has a plurality of first wire pads 213; The circuit layer 21"' is disposed on the second surface 20b of the substrate body 20, and seals the first opening 200 to form a wafer placement area 2 〇c; the first solder resist 24a is provided On the first surface 2a and the first circuit layer 21, and the first solder resist 24a has a second opening 240a to expose the wafer placement area 20c; and the second solder resist 24b, On the second surface 2b and the second circuit layer 21". In the above structure, the substrate body 20 is an insulating board; a conductor layer 21g is disposed on the wall of the hole 20c and the first opening 200, and the first circuit layer 2 has a plurality of second wire pads 214 disposed around the first opening 2, and the second wire pad 214 is connected to the first opening 2〇〇15 110642 1357650. Therefore, the right captive of the present invention is as listed in the patent application scope described below. - [Simple description of the drawing] Figure 1; Figure 1 is a conventional bottom hole crystal-type ball-shaped frame type sealing structure = to 2] The figure is a high heat-sealing seal of the invention; the substrate and its manufacturing method are consistently schematic; 2E, Figure It is a cross-sectional view of the structure of the other structure of Figure 2E; # . WG' and 2G" are the cross-sectional views of the other structure of the % figure, ^ 2J' and 2J" are the 2nd figure A cross-sectional view of the structure of the other structure; the 3A to 3D diagram is a schematic cross-sectional view of the first embodiment of the high heat dissipation package substrate and the method for manufacturing the same; and the 3C' and 3C" diagrams are (4) The other - the structure of the sound map. Heart, Lu [Major component symbol description] 10 Substrate 100 opening 11, 26 semiconductor wafer 1 la, 26a active surface lib, 26b non-active surface 111, 261 electrode 塾 12, 262 wire 13 electrical connection 塾 14, 25 metal protective layer 15, 263 encapsulating material 16 soldering element 20 substrate body 200 first opening 201 through hole 17 Π 0642 1357650 202 blind 孑 L 20a first surface 20b second surface 20c wafer placement area-21, first circuit layer 21, second Circuit layer 211 first solder pad 212 second solder pad 213 first wire pad 214 second wire 塾 21a first metal layer 210a crystallized opening 21b second metal layer 210b opening 21c third metal layer 21d, 21d' conductive Hole, 21e, 21e' conductive blind hole 21f base hole material 21g conductor layer 22 conductive seed layer 23 photoresist layer 230 photoresist layer open region 24a first solder resist layer 240a second opening 241a first opening 24b second Solder layer 241b 272 second opening second soldering element 271 first soldering element 18 110642