TW201444006A - 金屬凸塊結構 - Google Patents

金屬凸塊結構 Download PDF

Info

Publication number
TW201444006A
TW201444006A TW103115992A TW103115992A TW201444006A TW 201444006 A TW201444006 A TW 201444006A TW 103115992 A TW103115992 A TW 103115992A TW 103115992 A TW103115992 A TW 103115992A TW 201444006 A TW201444006 A TW 201444006A
Authority
TW
Taiwan
Prior art keywords
metal bump
metal
layer
cap layer
adhesive layer
Prior art date
Application number
TW103115992A
Other languages
English (en)
Other versions
TWI573205B (zh
Inventor
Chiu-Shun Lin
Original Assignee
Himax Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Tech Ltd filed Critical Himax Tech Ltd
Publication of TW201444006A publication Critical patent/TW201444006A/zh
Application granted granted Critical
Publication of TWI573205B publication Critical patent/TWI573205B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • H01L2224/03614Physical or chemical etching by chemical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • H01L2224/05582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825Plating, e.g. electroplating, electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1355Shape
    • H01L2224/13551Shape being non uniform
    • H01L2224/13552Shape being non uniform comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1357Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13575Plural coating layers
    • H01L2224/1358Plural coating layers being stacked
    • H01L2224/13582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Led Device Packages (AREA)

Abstract

一種金屬凸塊結構,包含位於金屬銲墊上之護層、位於金屬銲墊上又部份位於護層上之黏著層、部份位於凹穴中並覆蓋黏著層之金屬凸塊、以及完全覆蓋金屬凸塊之帽蓋層。

Description

金屬凸塊結構
本發明大致上關於一種金屬凸塊結構及其形成的方法。特別是,本發明關於一種特用於驅動積體電路(IC)金屬凸塊結構而免於周遭之大氣環境的威脅、在鹵素或高電場之存在下也不會發生迦凡尼效應(Galvanic effect)效應,及其形成的方法。
在電子電路中,金屬凸塊用來形成兩組電路之間的電連接。為了要降低不可避免的電阻與達成最佳的效果,銅通常是金屬凸塊材料的第一選擇。
一般說來,銅是作為金屬凸塊理想的材料,因為它的化學性質不活潑,還有著極低的電阻值。然而,在一些應用場合中,作為金屬凸塊材料的銅卻遭受嚴重的損傷,這是因為在異常的情形或是極端的情況存在之下,會發生迦凡尼效應(Galvanic effect)的緣故。這樣的結果對電子電路的可靠性而言是不利的。
有鑒於此,本發明首先提出一種金屬凸塊結構,其可與異方性導電膠(ACF)一起連結使用,或用於驅動積體電路(driver IC)中。此等金屬凸塊結構,在極端環境或是異常環境下基本上不會發生迦凡尼效應(Galvanic effect)。
本發明之金屬凸塊結構,包含金屬銲墊、護層、黏著層、金屬凸塊與帽蓋層。護層位於金屬銲墊上,並定義出位於金屬銲墊上之凹穴。黏著 層位於凹穴中、位於金屬銲墊上、又部份位於護層上,黏著層又直接接觸金屬銲墊與護層。金屬凸塊部份位於凹穴中並覆蓋黏著層。帽蓋層位於金屬凸塊上並覆蓋金屬凸塊,而使得金屬凸塊不會暴露出來。
在本發明一實施方式中,金屬凸塊自行對準於黏著層。
在本發明另一實施方式中,帽蓋層自行對準於金屬凸塊。
在本發明另一實施方式中,帽蓋層、黏著層、與護層間具有一嵌穴(notch)。
在本發明另一實施方式中,金屬凸塊包含銅與金其中之一者。
在本發明另一實施方式中,帽蓋層與金屬凸塊形成合金,以防止金屬凸塊穿出帽蓋層。
在本發明另一實施方式中,帽蓋層與金屬凸塊之界面沒有合金。
在本發明另一實施方式中,當金屬凸塊由銅所組成時,帽蓋層包含錫、鎳、金、鈀其中至少一者,當金屬凸塊由金所組成時,帽蓋層包含錫、鎳、鈀其中至少一者。
在本發明另一實施方式中,在鹵素與高電場其中之至少一者存在下,不發生迦凡尼效應(Galvanic effect)效應。
在本發明另一實施方式中,金屬凸塊結構位在玻璃覆晶(chip on glass,COG)封裝結構與薄膜覆晶(chip on flex,COF)封裝結構其中一者中。
本發明再提出一種形成一種金屬凸塊結構的方法,而可以用於驅動積體電路(driver IC)中。首先,提供底材。底材包含金屬銲墊、護層、黏著層、與圖案化光阻。護層位於金屬銲墊上,並定義出位於金屬銲墊上之凹穴。黏著層位於凹穴中,覆蓋並直接接觸金屬銲墊與護層。圖案化光阻位於黏著層上,並包含有開口,此開口暴露位於凹穴中與護層上之黏著層。其次,以金屬凸塊材料填入開口中。然後,移除圖案化光阻,使得金屬凸塊材料成為位於黏著層上之金屬凸塊。再來,移除沒有被金屬凸塊材料所覆蓋之黏著 層,同時部分暴露位於下方之護層。又使得金屬凸塊熟化以調整其硬度。繼續,形成覆蓋金屬凸塊的帽蓋層。
在本發明一實施方式中,帽蓋層自行對準於金屬凸塊。
在本發明另一實施方式中,移除黏著層時,過移除(over-removed)黏著層,以形成位於帽蓋層、黏著層、與護層間之嵌穴(notch)。
在本發明另一實施方式中,金屬凸塊包含銅或是金。
在本發明另一實施方式中,形成金屬凸塊結構的方法,更包含熟化位於金屬凸塊上之帽蓋層,於是帽蓋層與金屬凸塊形成合金,用來防止金屬凸塊穿出帽蓋層。
在本發明另一實施方式中,形成帽蓋層以完全覆蓋金屬凸塊,但是不形成合金。
在本發明另一實施方式中,當金屬凸塊由銅所組成時,帽蓋層包含錫、鎳、金、鈀其中至少一者,當金屬凸塊由金所組成時,帽蓋層包含錫、鎳、鈀其中至少一者。
在本發明另一實施方式中,在鹵素與高電場其中至少一者之存在下,金屬凸塊不發生迦凡尼效應(Galvanic effect)效應。
在本發明另一實施方式中,以電鍍的方式將金屬凸塊材料填入開口中。
在本發明另一實施方式中,以無電電鍍的方式形成帽蓋層。
1‧‧‧金屬凸塊結構
9‧‧‧絕緣層
10‧‧‧底材
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
14‧‧‧光阻層
14‧‧‧光阻層’
15‧‧‧凹穴
16‧‧‧開口
20’‧‧‧金屬凸塊材料
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層
41‧‧‧合金
第1圖至第6圖繪示本發明形成金屬凸塊結構的方法。
第7圖或第7A圖繪示本發明形成金屬凸塊結構的方法。
第8圖繪示本發明形成金屬凸塊結構的方法,因為嵌穴被完全填滿所以消失不見。
第9圖、第9A圖或第10圖繪示本發明之金屬凸塊結構。
本發明首先提供一種形成金屬凸塊結構的方法,可以將驅動積體電路晶片(driver IC)與顯示器之電路進行電連接,特別適用於金屬凸塊封裝的玻璃覆晶(COG)封裝結構與薄膜覆晶(COF)封裝結構技術中。第1圖至第6圖繪示本發明形成金屬凸塊結構的方法。首先,在第一方面先說明如何將金屬凸塊形成在底材上。如第1圖所繪示,提供底材10。底材10包括金屬銲墊11、護層12與黏著層13。
絕緣層9為底材10之基礎部份,用來支撐其它之元件,例如用來支撐金屬銲墊11、護層12、黏著層13與後續圖中之圖案化光阻層。金屬銲墊11可以是一種質輕之金屬材料,例如鋁,並經過圖案化。但是,其它之金屬亦可採用,而並不僅限於鋁。
護層12即位於金屬銲墊11之上,同時還具有定義出凹穴15的圖案,使得凹穴15亦位於金屬銲墊11之上。護層12可以是一種電絕緣之材料,例如是氮化矽、氧化矽或是其組合。通常來說,凹穴15的大小會小於金屬銲墊11的大小。
黏著層13又位於凹穴15之中。此外,黏著層13還會覆蓋金屬銲墊11與護層12,使得黏著層13會直接接觸金屬銲墊11與護層12。黏著層13用來幫助後續形成之金屬凸塊材料(圖未示)牢牢地附著在凹穴15之中。黏著層13可以是一種合金層,例如鈦鎢合金層或是鈦金屬層。
黏著層13的形成方法可以是,利用濺鍍一層鈦鎢合金,與例如銅的晶種層的方法,來均勻地覆蓋底材10,例如完全地覆蓋金屬銲墊11、護層12、與凹穴15的表面。結果例示於第1圖中。形成圖案化光阻層之方式,可以參考如下所示之方式。
如第2圖所繪示,將一大片光阻層14’整體形成在黏著層13上, 並同時填滿凹穴15。光阻層14’可以是光敏性的材料,例如是有機的光敏材料。
再來,如第3圖所繪示,將光阻層14’圖案化。圖案化光阻層14的方式可以是如下所述。光阻層14形成在黏著層13上來定義出開口16。開口16用來暴露出位於凹穴15中與護層12上的黏著層13,因此,在本發明之一實施例中,開口16會稍微大於凹穴15。換句話說,開口16可以用來定義出後續所形成之金屬凸塊材料(圖未示)所位在的空間,而此空間本身即容置了凹穴15。
然後,整體的光阻層14’又會經過適當的曝光與顯影步驟,而轉換成圖案化光阻層14,而具有曝光與顯影所賦與的預定圖案。圖案是經由開口16所定義出的,其結果即繪示於第3圖所中。
接下來,如第4圖所繪示,使用金屬凸塊材料20’來填入開口16中。請注意,金屬凸塊材料20’可能僅僅只是「填入」開口16中,而沒有「填滿」開口16。此時,黏著層13即因此夾置於金屬凸塊材料20’與金屬銲墊11之間,以及夾置於金屬凸塊材料20’與護層12之間。例如,由於金屬銲墊11與黏著層13均為導電性材料,所以金屬凸塊材料20’可以經由電鍍之方式來形成。視情況需要,金屬凸塊材料20’可以使用鈀、銀、銅或是金,以尋求較佳之導電性,與越低越好之化學活性。
一但將金屬凸塊材料20’形成好了之後,就不再需要圖案化光阻層14了。於是,如第5圖所繪示,移除圖案化光阻層14,使得金屬凸塊材料20’成為各自獨立之金屬凸塊20。可以使用傳統的方式來移除圖案化光阻層14。於是,各自獨立之金屬凸塊20,就會完全位於黏著層13之上,並直接接觸黏著層13。
由於黏著層13是導電的,這會導致所有的金屬凸塊20彼此短路,所以多餘的黏著層13必須要移除。再來,如第6圖所繪示,沒有被金屬凸塊20所覆蓋的黏著層13經由蝕刻步驟來移除,又部份地暴露出下方之護層12, 使得所有的金屬凸塊20,藉由電絕緣材料,亦即護層12的隔離,成為彼此電絕緣。如此一來,所有的金屬凸塊20即自我對準於黏著層13。例如,可以使用過氧化氫來蝕刻黏著層13的鈦鎢合金。
視情況需要,蝕刻步驟之後還可以進行加熱金屬凸塊20的熟化,來調整金屬凸塊20達到所需的硬度。例如,在大於300℃或是維持超過90分鐘之退火條件。一般說來,較低的硬度需要較高的熟化溫度與較短的熟化時間,而較高的硬度需要較低的熟化溫度與較長的熟化時間,來將金屬凸塊20調整到所需的適當硬度,例如不超過130維氏硬度(Hv),較佳者不大於110維氏硬度,更佳者介於50維氏硬度至110維氏硬度之間。
此時可以注意到在第6圖中,在移除黏著層13時,在金屬凸塊20、黏著層13、與護層12之間形成了一只嵌穴30,因為蝕刻步驟不只會完全移除沒有被金屬凸塊20所覆蓋的黏著層13,蝕刻步驟也可能會更進一步移除沒有被金屬凸塊20所覆蓋的黏著層13以外其他的黏著層13,例如,夾置於金屬凸塊20、與護層12間之黏著層13。而結果是,在金屬凸塊20、黏著層13、與護層12之間便形成了一只嵌穴30,而成為本發明結構的特徵之一。在有嵌穴30存在時,金屬凸塊20會幾乎覆蓋所有的黏著層13。另外,嵌穴30則可能橫向地深入1微米(μm)-2微米左右。
由於各自獨立之金屬凸塊20,仍然可能因為暴露於周圍的大氣環境中而失之脆弱,所以需要再特意形成帽蓋層來覆蓋金屬凸塊20,使得金屬凸塊20盡量不會暴露於周圍的大氣環境中。請參考第7圖所繪示,形成帽蓋層40來幾乎完全覆蓋金屬凸塊20,或是參考如第7A圖所繪示,帽蓋層40伸入了嵌穴30,而在有嵌穴30之存在下,得到了理想的金屬凸塊結構1。
帽蓋層40可以包含多種保護性的材料。如果是銅製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、鈀其中至少一者。如果是銀製成的金屬凸塊20,帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊20,帽蓋層40 可以包含錫。帽蓋層40也可以不含鎳。不過,所形成帽蓋層40可能只會減小嵌穴30的尺寸,或是如第8圖所繪示,因為完全填滿了嵌穴30,使得嵌穴30消失不見。而且,帽蓋層40也可以完全覆蓋金屬凸塊20。
較佳者,可以經由無電極電鍍法來形成帽蓋層40,例如可以在小於4之酸鹼值、硫酸鹽之輔助下進行無電極電鍍法。由於護層12是一種電絕緣材料,所以帽蓋層40很可能只會特定而專一地形成在金屬凸塊20上。換句話說,帽蓋層40即自我對準在金屬凸塊20上。帽蓋層40可以是單層結構或是複合結構,而包含多層之帽蓋材料。在本發明的一實施例中,如第8圖所繪示,帽蓋層40完全覆蓋金屬凸塊20,但是帽蓋層40與金屬凸塊20之界面上沒有形成合金,嵌穴30也消失不見。
另外,依據無電極電鍍法的不同電鍍配方或是電鍍條件,帽蓋層40還可以有不同的厚度與其它的形狀。例如,帽蓋層40可能是合金41、內層與外層之搭配或組合。較佳者,帽蓋層40含有金,其優點在於有利於重工(re-work),又可以減低材料的成本。當帽蓋層40含鈀時,鈀層的厚度可以是0.15微米-0.4微米左右。當帽蓋層40含金時,金層的厚度可以是在2微米以下,較佳者不大於0.1微米,甚至於可以只有0.006微米而已。表1列舉電鍍帽蓋層40之可行步驟與製程參數。其中在每個步驟之後,均可以再加入純水洗滌之清潔步驟。
在本發明之一實施例中,帽蓋層40會完全包覆金屬凸塊20但又不與金屬凸塊20形成伴生之合金層,例如銅不容易與鎳或鈀形成伴生之合金層。在本發明之另一實施例中,又可以進行一熟化(curing)步驟,使得帽蓋層40與金屬凸塊20形成合金。例如,請參考第9圖或第10圖所繪示,形成在金屬凸塊20上的帽蓋層40被加熱到,例如在150℃~180℃與30~60分鐘之條件下,與金屬凸塊20形成合金41。銅與錫在不同的條件下,可以形成多種的合金,例如Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3
合金41的形成,刻意用來防止金屬凸塊20在極端的情形下可能穿過帽蓋層40。在帽蓋層40的保護下,不管有或是沒有合金41,金屬凸塊20都不會暴露於周圍的大氣環境中,所以在鹵素及/或高電場之存在下也不會發生迦凡尼效應(Galvanic effect)效應。第9A圖繪示,帽蓋層40被熟化形成合金41,但只會減小嵌穴30的尺寸。第10圖所繪示,帽蓋層40被熟化形成合金41,但使得嵌穴30消失不見。
在經過以上之步驟後,就可以得到一種金屬凸塊結構1。本發明之金屬凸塊結構1,適合玻璃覆晶(COG)封裝結構或是薄膜覆晶(COF)封裝結構,因此可以用於驅動積體電路(driver IC)中。第9圖或第10圖繪示本發明之金屬凸塊結構。本發明之金屬凸塊結構1包含金屬銲墊11、護層12、黏著層13、金屬凸塊20、帽蓋層40、與視情況需要之合金41。金屬銲墊11可以是一種質輕之金屬材料,例如鋁,並經過圖案化。但是,其它之金屬亦可採用,而並不限於鋁。
護層12即位於金屬銲墊11之上,同時還具有圖案化而定義出的凹穴15,使得凹穴15亦位於金屬銲墊11之上。護層12可以是一種電絕緣之材料,例如是氮化矽、氧化矽或是其組合。通常來說,凹穴15的大小會小於金屬銲墊11的大小。
凹穴15之中完全填有黏著層13。此外,黏著層13還位於金屬銲墊11之上,來覆蓋並直接接觸金屬銲墊11。然而,部分的黏著層13位於護層12上,來覆蓋並直接接觸護層12。黏著層13用來幫助金屬凸塊20牢牢地附著在凹穴15之中。黏著層13可以是一種合金層,例如鈦鎢合金層,或是鈦金屬層。
金屬凸塊20部份地位於凹穴15中並覆蓋黏著層13,使得黏著層13夾置於金屬凸塊20與金屬銲墊11之間,以及夾置於金屬凸塊20與護層12之間。特別是,金屬凸塊20會自我對準於黏著層13。視情況需要,金屬凸塊20的材料可以是鈀、銀、銅或是金,以尋求較佳之導電性,與越低越好之化學活性。
帽蓋層40位於金屬凸塊20上並完全覆蓋金屬凸塊20,如第7圖所繪示,而使得金屬凸塊20完全不會暴露出來。或是,如第7A圖所繪示,帽蓋層40伸入了嵌穴30中而使得金屬凸塊20幾乎完全不會暴露出來。換句話說,帽蓋層40可以自我對準在金屬凸塊20上。
特別是,如第7圖與第9圖所繪示,可以注意到本發明結構的特徵之一,在金屬凸塊20、黏著層13、與護層12之間還可能會有一只嵌穴30,使得嵌穴30可能會使得黏著層13部分暴露出來。
帽蓋層40是用來完全覆蓋金屬凸塊20,使得金屬凸塊20得以免於暴露於大氣環境中。帽蓋層40可以包含多種保護性的材料。如果是銅製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、金、鈀其中至少一者。如果是金製成的金屬凸塊20,帽蓋層40可以包含錫、鎳、鈀其中至少一者。如果是銀製成的金屬凸塊20,帽蓋層40可以包含錫。如果是鈀製成的金屬凸塊20,帽蓋層40可以包含錫。不過,請注意到較厚的帽蓋層40可能會減小嵌穴30的尺寸,如第8圖或第10圖所繪示,因為較厚的帽蓋層40可能會完全填滿了嵌穴30,或是使得嵌穴30消失不見。
由於形成在金屬凸塊20上的帽蓋層40是有緣故的,帽蓋層40 即可以自我對準在金屬凸塊20上。在本發明的一實施例中,如第7圖或第8圖所繪示,帽蓋層40只會完全包覆金屬凸塊20,但又不與金屬凸塊20形成伴生之合金層。在本發明的另一實施例中,如第9圖或第10圖所繪示,形成在金屬凸塊20上的帽蓋層40會與金屬凸塊20形成伴生之合金層41。
如果有合金41,如第9圖或第10圖所繪示,銅、錫、鎳、銀、金、鈀可能會形成多種之合金。例如,銅與錫在不同的條件下,可以形成Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3的合金。特別是,合金41的形成,刻意用來防止金屬凸塊20在極端的情形下可能穿過帽蓋層40。在帽蓋層40的保護下,不管有或是沒有合金41,金屬凸塊20都不會暴露於周圍的大氣環境中,所以在鹵素及/或高電場之存在下也不會發生迦凡尼效應(Galvanic effect)效應。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1‧‧‧金屬凸塊結構
9‧‧‧絕緣層
11‧‧‧金屬銲墊
12‧‧‧護層
13‧‧‧黏著層
20‧‧‧金屬凸塊
30‧‧‧嵌穴
40‧‧‧帽蓋層

Claims (20)

  1. 一種金屬凸塊(metal bump)結構,其用於一驅動積體電路(driver IC)中並包含:一金屬銲墊;一護層,位於該金屬銲墊上,並定義出位於該金屬銲墊上之一凹穴;一黏著層,位於該凹穴中、位於該金屬銲墊上、又部份位於該護層上,其中該黏著層直接接觸該金屬銲墊與該護層;一金屬凸塊,部份位於該凹穴中並覆蓋該黏著層;以及一帽蓋層,位於該金屬凸塊上並覆蓋該金屬凸塊,而使得該金屬凸塊不會暴露出來。
  2. 如請求項1之金屬凸塊結構,其中該金屬凸塊自行對準於該黏著層。
  3. 如請求項1之金屬凸塊結構,其中該帽蓋層自行對準於該金屬凸塊。
  4. 如請求項1之金屬凸塊結構,其中該帽蓋層、該黏著層、與該護層間具有一嵌穴(notch)。
  5. 如請求項1之金屬凸塊結構,其中該金屬凸塊包含銅與金其中一者。
  6. 如請求項1之金屬凸塊結構,其中該帽蓋層與該金屬凸塊形成一合金,以防止該金屬凸塊穿出該帽蓋層。
  7. 如請求項1之金屬凸塊結構,其中該帽蓋層與該金屬凸塊之一界面沒有合金。
  8. 如請求項5之金屬凸塊結構,其中當該金屬凸塊由銅所組成時該帽蓋層包含錫、鎳、金、鈀其中至少一者,當該金屬凸塊由金所組成時該帽蓋層包含錫、鎳、鈀其中至少一者。
  9. 如請求項1之金屬凸塊結構,在鹵素與一高電場其中至少一者之存在下不發生迦凡尼效應(Galvanic effect)效應。
  10. 如請求項1之金屬凸塊結構,位在玻璃覆晶(COG)封裝結構與薄膜覆晶(COF)封裝結構其中一者中。
  11. 一種形成一種金屬凸塊結構的方法,而用於一驅動積體電路(driver IC)中,其包含:提供一底材,其包含:一金屬銲墊;一護層,位於該金屬銲墊上,並定義出位於該金屬銲墊上之一凹穴;一黏著層,位於該凹穴中、覆蓋並直接接觸該金屬銲墊與該護層;以及一圖案化光阻,位於該黏著層上,並包含暴露位於該凹穴中與該護層上之該黏著層之一開口;以一金屬凸塊材料填入該開口中;移除該圖案化光阻,使得該金屬凸塊材料成為位於該黏著層上之一金屬凸塊;移除沒有被該金屬凸塊材料所覆蓋之該黏著層,以部分暴露位於下方之該護層,並使得該金屬凸塊熟化以調整其硬度;以及形成一帽蓋層,以覆蓋該金屬凸塊。
  12. 如請求項11形成一種金屬凸塊結構的方法,其中該帽蓋層自行對準於該金屬凸塊。
  13. 如請求項11形成一種金屬凸塊結構的方法,其中移除該黏著層時,過移除(over-removed)該黏著層,以形成位於該帽蓋層、該黏著層、與該護層間之一嵌穴(notch)。
  14. 如請求項11形成一種金屬凸塊結構的方法,其中該金屬凸塊包含銅與金其中一者。
  15. 如請求項11形成一種金屬凸塊結構的方法,更包含:熟化位於該金屬凸塊上之該帽蓋層,而與該金屬凸塊形成一合金,而防止該金屬凸塊穿出該帽蓋層。
  16. 如請求項11形成一種金屬凸塊結構的方法,其中形成該帽蓋層以完全覆蓋該金屬凸塊,而不形成合金。
  17. 如請求項15形成一種金屬凸塊結構的方法,其中當該金屬凸塊由銅所組成時該帽蓋層包含錫、鎳、金、鈀其中至少一者,當該金屬凸塊由金所組成時該帽蓋層包含錫、鎳、鈀其中至少一者。
  18. 如請求項11形成一種金屬凸塊結構的方法,其中在鹵素與一高電場其中至少一者之存在下,該金屬凸塊不發生迦凡尼效應(Galvanic effect)效應。
  19. 如請求項11形成一種金屬凸塊結構的方法,其中以電鍍將該金屬凸塊材料填入該開口中。
  20. 如請求項11形成一種金屬凸塊結構的方法,其中以無電電鍍形成該帽蓋層。
TW103115992A 2013-05-06 2014-05-05 金屬凸塊結構 TWI573205B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361820152P 2013-05-06 2013-05-06

Publications (2)

Publication Number Publication Date
TW201444006A true TW201444006A (zh) 2014-11-16
TWI573205B TWI573205B (zh) 2017-03-01

Family

ID=51841032

Family Applications (3)

Application Number Title Priority Date Filing Date
TW103113751A TWI600129B (zh) 2013-05-06 2014-04-15 玻璃覆晶接合結構
TW103115992A TWI573205B (zh) 2013-05-06 2014-05-05 金屬凸塊結構
TW103116132A TWI600130B (zh) 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW103113751A TWI600129B (zh) 2013-05-06 2014-04-15 玻璃覆晶接合結構

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW103116132A TWI600130B (zh) 2013-05-06 2014-05-06 薄膜覆晶結構、金屬凸塊結構與形成薄膜覆晶結構的方法

Country Status (4)

Country Link
US (2) US10128348B2 (zh)
KR (3) KR101611376B1 (zh)
CN (4) CN104143538B (zh)
TW (3) TWI600129B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2573137T3 (es) * 2012-09-14 2016-06-06 Atotech Deutschland Gmbh Método de metalización de sustratos de célula solar
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
CN107210241B (zh) * 2015-03-10 2019-12-31 三菱电机株式会社 功率半导体装置
KR102663140B1 (ko) * 2016-06-24 2024-05-08 삼성디스플레이 주식회사 디스플레이 장치
KR102508527B1 (ko) 2016-07-01 2023-03-09 삼성전자주식회사 필름형 반도체 패키지
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
IT201700087309A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici
IT201700087318A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10741482B2 (en) 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP7122593B2 (ja) * 2018-05-08 2022-08-22 パナソニックIpマネジメント株式会社 半導体装置の製造方法、半導体装置の製造装置、及び半導体装置
US11469194B2 (en) * 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
CN110854066A (zh) * 2019-11-28 2020-02-28 无锡微视传感科技有限公司 一种半导体电镀方法
WO2021184188A1 (zh) * 2020-03-17 2021-09-23 元锦生物科技股份有限公司 可拆式接合结构
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205099A (en) * 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
CN1679154A (zh) * 2002-05-16 2005-10-05 新加坡国立大学 晶片级无电镀铜法和凸块制备方法,以及用于半导体晶片和微芯片的渡液
US7008867B2 (en) 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JP2007531247A (ja) * 2003-07-16 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 側壁用絶縁体を有する金属バンプ及びこのような金属バンプを有するチップを製造する方法
TWI222198B (en) 2003-09-04 2004-10-11 Fupo Electronics Corp Fine pitch gold bump fabrication process and its package article
JP4718809B2 (ja) 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
KR100642765B1 (ko) 2004-09-15 2006-11-10 삼성전자주식회사 하이브리드 범프를 포함하는 미세전자소자칩, 이의패키지, 이를 포함하는 액정디스플레이장치 및 이러한미세전자소자칩의 제조방법
TWI286454B (en) * 2005-03-09 2007-09-01 Phoenix Prec Technology Corp Electrical connector structure of circuit board and method for fabricating the same
KR100801073B1 (ko) 2005-10-06 2008-02-11 삼성전자주식회사 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법
US7601566B2 (en) * 2005-10-18 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
JP2007317979A (ja) * 2006-05-29 2007-12-06 Toshiba Corp 半導体装置の製造方法
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
KR20080102545A (ko) 2007-05-21 2008-11-26 주식회사 엘지화학 Cof 실장용 2층 동박 적층판 및 그 제조 방법
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
TWI469288B (zh) 2009-06-11 2015-01-11 Chipbond Technology Corp 凸塊化晶片結構及其應用之半導體覆晶裝置
TW201044527A (en) * 2009-06-11 2010-12-16 Int Semiconductor Tech Ltd Chip architecture having film-faced metal bumps and semiconductor flip-chip device applied from the same
KR20110090332A (ko) 2010-02-03 2011-08-10 한양대학교 산학협력단 이방성 전도 필름을 이용하여 기판이 접합된 반도체 소자 및 기판 접합방법
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
KR20120139115A (ko) * 2011-06-16 2012-12-27 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US8643196B2 (en) 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
JP6035714B2 (ja) 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US20130193570A1 (en) * 2012-02-01 2013-08-01 Chipbond Technology Corporation Bumping process and structure thereof
US8501614B1 (en) * 2012-03-22 2013-08-06 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US9646951B2 (en) * 2013-12-10 2017-05-09 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor

Also Published As

Publication number Publication date
CN104143539A (zh) 2014-11-12
US9450061B2 (en) 2016-09-20
CN104143540A (zh) 2014-11-12
TW201444037A (zh) 2014-11-16
CN104143543A (zh) 2014-11-12
CN104143538A (zh) 2014-11-12
KR20140131876A (ko) 2014-11-14
US10128348B2 (en) 2018-11-13
KR101611846B1 (ko) 2016-04-12
CN104143540B (zh) 2017-05-03
KR20140131884A (ko) 2014-11-14
KR20140131871A (ko) 2014-11-14
TWI600130B (zh) 2017-09-21
TWI573205B (zh) 2017-03-01
US20140327134A1 (en) 2014-11-06
US20140327133A1 (en) 2014-11-06
TW201444042A (zh) 2014-11-16
KR101611376B1 (ko) 2016-04-11
CN104143538B (zh) 2018-01-02
TWI600129B (zh) 2017-09-21
CN104143543B (zh) 2017-10-03
CN104143539B (zh) 2018-04-10
KR101641993B1 (ko) 2016-07-22

Similar Documents

Publication Publication Date Title
TWI573205B (zh) 金屬凸塊結構
TWI229435B (en) Manufacture of semiconductor device
TWI539508B (zh) 半導體裝置之製造方法及電子裝置之製造方法
TW200428608A (en) Semiconductor device and manufacturing method thereof
CN106206505B (zh) 半导体装置以及半导体装置的制造方法
TWI690045B (zh) 構裝結構、其接合方法及用於其的線路板
JP2009177072A (ja) 半導体装置及びその製造方法
JP2002231854A (ja) 半導体装置およびその製造方法
KR102210802B1 (ko) 반도체 장치 및 그 제조 방법
US10256117B2 (en) Manufacturing method and wiring substrate with through electrode
US9929069B2 (en) Semiconductor device and manufacturing method thereof
TW200901419A (en) Packaging substrate surface structure and method for fabricating the same
JP2010092974A (ja) 半導体装置及びその製造方法、並びに電子装置
JP2005268442A (ja) 半導体装置およびその製造方法
JP2020047794A (ja) 半導体装置の製造方法
JP2009135345A (ja) 半導体装置及びその製造方法
JP4938346B2 (ja) 半導体装置およびその製造方法
TW200937599A (en) Semiconductor package substrate having fine-pitch circuitry and fabrication method thereof
JP2010135554A (ja) 半導体装置の製造方法
JP2008258552A (ja) 半導体チップ積層実装体の製造方法
JP2007067429A (ja) 半導体装置の製造方法
JP2006005220A (ja) 半導体装置の製造方法
TW200427116A (en) Package for IC and LED