CN107210241B - 功率半导体装置 - Google Patents

功率半导体装置 Download PDF

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Publication number
CN107210241B
CN107210241B CN201680009370.9A CN201680009370A CN107210241B CN 107210241 B CN107210241 B CN 107210241B CN 201680009370 A CN201680009370 A CN 201680009370A CN 107210241 B CN107210241 B CN 107210241B
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layer
power semiconductor
semiconductor device
electrode layer
semiconductor element
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CN107210241A (zh
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小川翔平
菊池正雄
藤野纯司
内田祥久
铃木裕一郎
柳本辰则
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Mitsubishi Corp
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Mitsubishi Corp
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Abstract

在功率半导体装置(100)中，关于功率半导体元件(4)的表面电极(41a)，在维氏硬度为200～350Hv的以Cu为主成分的通过非电解镀敷形成的Cu层(81)上层叠设置有比Cu层(81)柔软的维氏硬度为70～150Hv的以Cu为主成分的通过非电解镀敷形成的Cu层(82)，对Cu层(82)与Cu制的导线(6)进行导线键合。

Description

功率半导体装置
技术领域
本发明涉及为了进行功率半导体元件的表面电极与外部电极的电气布线而连接键合导线的功率半导体装置。
背景技术
以往，为了进行功率半导体装置的电气布线，进行Al导线(wire)键合，但根据高温动作化、高可靠化的要求，需要重新考虑导线的材料。因此，进行由于电容大、机械强度高而被期待提高可靠性的Cu导线键合的开发。但是，在通过与以往的使用Al导线时相同的楔焊(wedge bonding)来进行使用Cu导线的键合(bonding)的情况下，由于Cu与Al相比杨氏模量高，所以，在键合时，有可能对半导体元件造成损伤。要求能够不对半导体元件造成损伤地键合Cu导线的构造。
在专利文献1中，公开了对功率半导体元件的电极形成Ni/Pd/Au的膜来防止在导线键合时在功率半导体元件产生损伤的发明。另外，在专利文献2中，公开了通过将硬度高的W、Co、Mo、Ti、Ta的保护膜设置于元件并在其上进行Cu的成膜来兼顾接合性与损伤抑制效果的发明。
现有技术文献
专利文献1：日本特开2013－004781号公报(第0019段、图2)
专利文献2：日本特开2014－082367号公报(第0020段、图1)
发明内容
然而，在专利文献1中，虽然成膜为非电解Ni镀层/Pd/Au，但由于Ni镀层的膜应力大，所以，如果在功率半导体中使用的大面积的元件中为了使损伤抑制效果最大限度地发挥而使膜厚增大，则存在发生翘曲、剥离这样的问题。另外，由于膜应力大，所以，存在由于键合时的应力而Ni镀层膜裂开这样的问题。
另外，在专利文献2中，在功率半导体元件的电极上，为了避免在导线键合时对功率半导体元件造成损伤，进行W等的成膜，作为缓冲件而发挥功能。但是，为了进行W等金属的成膜，只能使用溅射，如果为了使损伤抑制效果增大而使膜厚增大，则存在生产率不足这样的问题。进一步地，在对该膜结构键合有Cu导线的情况下，受到由线膨胀系数之差引起的热应力的影响，存在在Cu导线中产生裂纹、在金属膜处发生剥离这样的问题。
本发明是为了解决上述问题而完成的，其目的在于，提供在用Cu导线进行键合的情况下能够抑制对半导体元件的损伤的功率半导体装置。
本发明涉及一种功率半导体装置，其特征在于，具备：功率半导体元件；第一电极层，设置于功率半导体元件上；第二电极层，设置于第一电极层上，硬度比第一电极层低，并且以Cu为主成分；以及键合导线，连接到第二电极层，并且以Cu为主成分。
根据本发明，通过将硬度低且接合性优良的层设置于电极层的最表面，即使在用Cu导线键合到功率半导体元件的情况下，也能够抑制对功率半导体元件的损伤地进行接合，能够实现可靠性优良的布线。另外，能够抑制表面电极的剥离、裂缝，能够实现生产率的提高。
附图说明
图1是示出本发明的实施方式1的功率半导体装置的结构的剖面示意图。
图2是示出本发明的实施方式1的功率半导体装置的主要部分的结构的放大剖视图。
图3是示出本发明的实施方式2的功率半导体装置的主要部分的结构的放大剖视图。
图4是示出本发明的实施方式3的功率半导体装置的主要部分的结构的放大剖视图。
图5是示出本发明的实施方式4的功率半导体装置的主要部分的结构的放大立体图。
图6是示出本发明的实施方式4的功率半导体装置的主要部分的结构的放大剖视图。
图7是示出本发明的实施方式4的功率半导体装置的主要部分的其他结构的放大俯视图。
图8是示出本发明的实施方式4的功率半导体装置的主要部分的其他结构的放大剖视图。
图9是示出本发明的实施方式5的功率半导体装置的主要部分的结构的放大剖视图。
(附图标记说明)
4功率半导体元件；6导线；7Al层；8Cu层；9绝缘层；41a表面电极；81Cu层；82Cu层；83金属层；100功率半导体装置。
具体实施方式
实施方式1.
参照附图，以下说明作为本发明的实施方式1的功率半导体装置。图1是示出本发明的实施方式1的功率半导体装置的结构的剖面示意图。
如图1所示，功率半导体装置100包括底板1、接合于底板1上的陶瓷基板2、配置于陶瓷基板2上的功率半导体元件4以及将功率半导体元件4的表面电极41a与形成于陶瓷基板2上的作为电路图案的电极层22c键合的导线6。
底板1作为散热板而使用Cu制的板。通过焊料(Sn－Ag－Cu系)3将陶瓷基板2接合到底板1上。底板1只要是热导率高的材料即可，也可以使用Al制等。另外，也可以是与绝缘基板成为一体的底基板。将焊料3设为Sn－Ag－Cu系，但只要能够将底板1与陶瓷基板2接合并确保散热性，则也可以使用Sn－Ag－Cu－Sb系焊料、加入Pb的焊料等。另外，也可以设为使用Ag、其他粒子的烧结接合、利用散热片、散热油脂(grease)的连接。
陶瓷基板2将Cu制的导体层22a、22b、22c层叠于AlN制的基体材料21的两面。陶瓷基板2的背面侧的电极层22b通过焊料3接合到底板1上，并将功率半导体元件4配置于表面侧的导体层22a。另外，陶瓷基板2上的作为电路图案的电极层22c通过导线6与功率半导体元件4的表面电极41a进行键合。基体材料21只要能够确保绝缘性，则也可以是Al2O3制、Si3N4制等。
功率半导体元件4使用Si制的IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)，背面电极41b通过Ag烧结件5管芯键合于陶瓷基板2上的导电层22a。表面电极41a用导线6通过楔焊与包括作为陶瓷基板2上的电路图案的向源极焊盘的主布线、栅极布线、向各种读出焊盘(sensing pad)的布线的全部的表面侧的电极层22c进行键合。导线6使用以Cu为主成分的直径为φ400μm的导线。
将功率半导体元件4设为IGBT，但也可以是IC(Integrated Circuit，集成电路)、晶闸管、MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)。也可以是SBD(Schottky Barrier Diode，肖特基势垒二极管)、JBS(Junction Barrier Schottky，结势垒肖特基二极管)等二极管。另外，也可以应用于功率半导体以外的半导体封装体。另外，将厚度设为100μm，但不限于此。关于功率半导体元件4的管芯键合，设为Ag烧结，但也可以是焊接。另外，也可以是使用Cu等Ag以外的材料的烧结接合。
导线6使用以Cu为主成分的直径为φ400μm的导线，但不限于此。也可以是仅将栅极布线用的导线6和向读出焊盘的布线用的导线6设为线径小的导线等，使用不同的线径。另外，也可以仅将栅极布线用的导线6设为以往的Al导线、以Al为主成分的Al合金导线。导线6的接合是设为楔焊，但也可以是球焊(ball bonding)、超声波接合。另外，关于向源极焊盘的主布线，也不限于以Cu为主成分的导线6，也可以是以Al、Ag等为主成分的纯金属、合金。进一步地，也可以将带、引线框进行超声波接合而不是导线6。
图2是示出本发明的实施方式1的功率半导体装置100的主要部分的结构的示意图，是将图1的区域A放大的剖视图。如图2所示，功率半导体元件4的表面电极41a包括Cu层8与Al层7的多个金属层。Cu层8还包括维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82以及维氏硬度为200～350Hv的硬的以Cu为主成分的通过非电解镀敷形成的Cu层81。即，该多个金属层的最表面是维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82，在其下方存在维氏硬度为200～350Hv的硬的以Cu为主成分的通过非电解镀敷形成的Cu层81。进一步地，在其下方，通过溅射来成膜有以Al为主成分的Al层7。各自的膜厚设为Al层7是0.1～5μm、Cu层81是5～20μm、Cu层82是5～20μm。导线6通过楔焊而键合到形成于表面电极41a的最表面的Cu层82。
维氏硬度的差异表现在晶体粒径上，硬度越高，则晶体粒径越小。晶体粒径的差异能够通过镀敷液中的离子浓度等来控制。硬的Cu层81的平均晶体粒径为1μm以下，柔软的Cu层82的平均晶体粒径为5μm以上。另外，通过进行镀敷后热处理，也能够控制晶体粒径。
作为镀敷的基底层，通过溅射进行Al层7的成膜，但作为镀敷的基底层，不限于Al层7，也可以是Cu层、Ni层等。另外，Cu层81与Cu层82不限于通过非电解镀敷形成，也可以通过电解镀敷、溅射形成。在通过溅射形成的情况下，也可以省略作为基底的Al层7。
以下说明这样构成的理由。表1中示出发明者们进行的Cu镀层的维氏硬度和与导线6的接合性评价结果。表1所示的超声波的输出是装置固有的值(在表中是任意单位[a.u.])，表示能够接合的超声波输出越低、则对功率半导体元件4造成的损伤越小。另外，意味着能够接合的超声波的功率的幅度越宽，则接合条件的余量越宽，能够期待成品率的提高。本实验中的膜厚全部是30μm。
[表1]
表1接合性评价结果
其结果，如表1所示，在维氏硬度为70～150Hv之间时，成为即使超声波输出是低功率、导线6也能接合而得到电气特性的结果(○)。与此相对地，在维氏硬度为160Hv以上的情况下，通过低功率进行的导线6的接合变得困难(－)，条件余量变小。另外，在高功率时，在维氏硬度为160Hv以下的情况下，成为功率半导体元件4被破坏而得不到电气特性(×)这样的结果。另一方面，如果维氏硬度超过200Hv，则能够连接导线6而得到电气特性(○)，观察到抑制损伤的效果。但是，在维氏硬度为450Hv以上的情况下，在镀层表面产生裂缝(△)。
接下来，表2以及表3是发明者们进行的Cu镀层厚度与导线6的接合性评价的结果，表2表示Cu镀层的维氏硬度为120Hv时的结果，表3示出Cu镀层的维氏硬度为250Hv时的结果。
[表2]
表2接合性评价结果
[表3]
表3接合性评价结果
其结果，在表2的Cu镀层维氏硬度为120Hv时，在镀层厚度低于20μm的情况下，除了超声波输出是30[a.u.]的情况，成为功率半导体元件4被破坏而得不到电气特性(×)这样的结果。在镀层厚度为20μm以上的情况下，连接导线6而得到电气特性(○)，得到抑制损伤的效果。但是，在高功率时，功率半导体元件4被破坏而得不到电气特性(×)。
另一方面，在表3的Cu镀层维氏硬度250Hv时，在膜厚5μm以下的情况下，无法进行导线6的接合(－)，另外，在膜厚10μm以上的情况下，也是在低功率时无法进行导线6的接合(－)，在哪一个情况下都没有破坏功率半导体元件4。在高功率时，连接导线6而得到电气特性(○)。
根据上述结果，可以认为通过将这些镀层组合，即通过层叠利用低功率的超声波输出能够接合的较柔软的以Cu为主成分的通过非电解镀敷而形成的Cu层82以及不易破坏功率半导体元件4的较硬的以Cu为主成分的通过非电解镀敷而形成的Cu层81，能够不对功率半导体元件4造成损伤地对导线6进行楔焊。另外，通过进行组合，Cu层8整体的膜厚变薄，能够得到生产率优良的镀层。如果考虑制造偏差和批量生产性，则在维氏硬度方面，在通过非电解镀敷形成的Cu层82的情况下，在70～150Hv的范围时优选，低于70Hv是Cu的硬度的下限的界限，如果超过150Hv，则难以进行利用低功率的导线6的接合。另一方面，在通过非电解镀敷形成的Cu层81的情况下，在200～350Hv的范围时优选，在低于200Hv的情况下，在高功率时功率半导体元件4被破坏而得不到电气特性，如果超过350Hv，则在Cu层81容易产生裂缝。另外，在膜厚方面，在Cu层82的情况下，在5～20μm的范围时优选，在低于5μm的情况下，功率半导体元件4被破坏而得不到电气特性，如果超过20μm，则生产率不足。在Cu层81的情况下，也是在5～20μm的范围时优选，在低于5μm的情况下，功率半导体元件4被破坏而得不到电气特性，如果超过20μm，则生产率不足。
另外，通过做成本结构，功率半导体元件4的表面电极41a与导线6的接合部变成Cu与Cu的接合，所以，能够降低线膨胀系数的不匹配，并且由于是同种金属，所以，存在不形成由扩散导致的柯肯多尔孔洞(Kirkendall void)这样的优点。而且，Cu是与Al相比杨氏模量高且线膨胀系数小的与功率半导体元件接近的金属，高强度且不易发生塑性变形，所以存在即使在发生由温度循环导致的热应变的时候等也能够抑制Cu层8的剥离的效果，能够实现可靠性优良的布线。另外，由于仅通过非电解镀敷而完成工艺，所以与溅射相比，更容易使膜厚增大。
此外，也可以使柔软的通过非电解镀敷形成的Cu层82的膜厚变厚直至能够抑制对功率半导体元件4的损伤的程度为止，做成没有硬的通过非电解镀敷形成的Cu层81的构造。在该情况下，通过非电解镀敷形成的Cu层82是以Cu为主成分的膜，所以容易氧化。如果氧化膜变厚，则有可能产生对导线6的接合性的不良影响，所以，在从Cu层82的成膜工序至Cu导线6的键合工序的期间，加入使用有机溶剂的进行防氧化膜的成膜的工序，从而能够抑制储存对导线键合性的影响。
非电解镀敷的维氏硬度能够通过变更镀敷液的添加物、处理温度来调整。另外，除测定维氏硬度以外，还能够根据观察剖面时的晶体粒径不同，容易地判别构成有不同的层。
如上所述，在本发明的实施方式1的功率半导体装置100中，在功率半导体元件4的表面电极41a中，在作为第一电极层的Al层7上的维氏硬度为200～350Hv的以Cu为主成分的通过非电解镀敷形成的Cu层81上，层叠设置比Cu层81柔软的、作为第二电极层的维氏硬度为70～150Hv的以Cu为主成分的通过非电解镀敷形成的Cu层82，对Cu层82与Cu制的导线6进行导线键合，所以，即使在用Cu导线键合到功率半导体元件的情况下，也能够抑制对功率半导体元件的损伤地进行接合，能够实现可靠性优良的布线。另外，能够抑制表面电极的剥离、裂缝，能够实现生产率的提高。
实施方式2.
在实施方式1中，构成为在功率半导体元件4的表面电极41a中，在通过非电解镀敷形成的Cu层81上层叠比Cu层81柔软的通过非电解镀敷形成的Cu层82，但在实施方式2中，说明在Cu层81与Cu层82之间设置有提高密合力的金属层的情况。
图3是示出本发明的实施方式2的功率半导体装置的主要部分的结构的放大剖视图。如图3所示，功率半导体元件4的表面电极41a在通过非电解镀敷形成的Cu层81与比Cu层81柔软的通过非电解镀敷形成的Cu层82之间以及通过非电解镀敷形成的Cu层81与Al层7之间的某一方或者双方，为了提高密合力，进行包括Au的金属层83的成膜。此外，只要能够提高密合力，则不限于Au，也可以是Pd等。关于其他结构，与实施方式1的功率半导体装置100相同，省略其说明。
此外，根据金属膜的组合，有可能形成金属化合物层，所以，也可以还形成包括Ni等的防扩散膜。另外，为了容易进行Cu层81、Cu层82的非电解镀敷的成膜，也可以预先在这些层的下方进行以Cu为主成分的0.1μm以下的晶种(seed)层的成膜。
如上所述，在本发明的实施方式2的功率半导体装置中，在功率半导体元件4的表面电极41a中，在Cu层81与比Cu层81柔软的Cu层82之间以及Cu层81与Al层7之间的某一方或者双方，进行包括Au的金属层83的成膜，所以，即使在用Cu导线键合到功率半导体元件的情况下，也不仅能够抑制对功率半导体元件的损伤，通过提高表面电极的密合力，还能够实现生产率的提高，并且，能够实现可靠性进一步优良的布线。
实施方式3.
在实施方式1中，构成为在功率半导体元件4的表面电极41a中，在通过非电解镀敷形成的Cu层81上层叠比Cu层81柔软的通过非电解镀敷形成的Cu层82，但在实施方式3中，说明柔软的Cu层的下方是硬的Ni层的情况。
图4是示出本发明的实施方式3的功率半导体装置的主要部分的结构的放大剖视图。如图4所示，关于功率半导体元件4的表面电极41a，在维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82的下方，代替Cu层81而设置有比Cu层82硬的以Ni为主成分的通过非电解镀敷形成的Ni层84。Ni层84的膜厚设为5～20μm。关于其他结构，与实施方式1的功率半导体装置100相同，省略其说明。
通过做成本结构，能够利用通过非电解镀敷形成的Ni层84来抑制对功率半导体元件4的损伤，利用通过非电解镀敷形成的Cu层82来确保接合性。另外，在Al层7与Cu层82之间进行Ni的成膜，作为防止扩散的壁垒层而发挥功能。
此外，如实施方式2所示，在本实施方式3中，也可以在通过非电解镀敷形成的Ni层84与通过非电解镀敷形成的Cu层82之间以及Ni层84与Al层7之间的某一方或者双方，按0.1μm以下进行包括Au、Pd等的用于提高密合力的金属层83的成膜。
如上所述，在本发明的实施方式3的功率半导体装置中，在功率半导体元件4的表面电极41a中，在维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82的下方，设置比Cu层82硬的以Ni为主成分的通过非电解镀敷形成的Ni层84，所以，即使在用Cu导线键合到功率半导体元件的情况下，也能够抑制对功率半导体元件的损伤地进行接合，能够实现可靠性优良的布线。另外，能够防止表面电极的剥离、裂缝，实现生产率的提高。
实施方式4.
在实施方式1中，做成将多条导线6键合到一个表面电极41a的结构，但在实施方式4中，说明设置与多条导线6分别对应的表面电极的情况。
图5是示出本发明的实施方式4的功率半导体装置中的功率半导体元件4的表面电极41a的结构的立体图，图6是图5的B－B向视剖视图。另外，图7以及图8是示出实施方式4的功率半导体装置中的功率半导体元件4的表面电极41a的其他结构的图。
如图5所示，功率半导体元件4的表面电极41a针对多条导线6分别按接合部的面积的约1.2倍的面积以椭圆形状地设置。将包括聚酰亚胺的绝缘层9配置于没有表面电极41a的区域整体。一般来说，在功率半导体元件中，为了确保绝缘性，在功率半导体元件的外周等，使用聚酰亚胺，但在本实施方式4中，在没有表面电极41a的区域整个面进行成膜。另外，如图6所示，表面电极41a与实施方式1同样地，最表面是维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82，在其下方存在维氏硬度为200～350Hv的硬的以Cu为主成分的通过非电解镀敷形成的Cu层81。进一步地，在其下方成膜有以Al为主成分的Al层7。导线6通过楔焊而键合到形成于表面电极41a的最表面的Cu层82。关于其他结构，也与实施方式1的功率半导体装置100相同，省略其说明。
通过做成本结构，针对Si制的功率半导体元件4、AlN制的陶瓷基板2等低线膨胀系数的材料与线膨胀系数大的表面电极41a的不匹配，能够使热应力分散，所以能够抑制剥落，能够提高可靠性。另外，包括聚酰亚胺的绝缘层9作为掩模而发挥功能，所以，无需追加用于格子状地配置表面电极41a的照相制版、蚀刻这样的工序，能够形成图案，生产率优良。进一步地，通过在整个面进行Al层7的成膜，防止在Cu层8与绝缘层9之间产生间隙。
此外，表面电极41a各自的大小是与导线6的接合部的面积的1～1.5倍即可，形状不限于椭圆，如图7所示，也可以是矩形(参照图7(b))。另外，此时，为了避免应力集中，也可以对于角实施R(参照图7(c))、倒角(图7(d)参照)等处理。
另外，作为绝缘层9而使用聚酰亚胺，但不限于此。只要是能够确保绝缘性的材料即可，也可以是氮化膜等。另外，做成最终残留绝缘层9的结构，但也可以是涂敷抗蚀剂而进行表面电极41a的成膜、并在成膜后去除抗蚀剂的方法。
另外，也可以以对应于各导线6的方式仅形成表面电极41a的表面侧的一部分的层。例如，在图8(a)中，示出在Al层7之上以对应于各导线6的方式仅进行Cu层8(Cu层81与Cu层82)的成膜而形成的情况，在图8(b)中，示出在Cu层81之上以对应于各导线6的方式仅进行Cu层82的成膜而形成的情况。另外，也可以在完成至Cu层8的成膜之后，以对应于各导线6的方式仅使表面电极41a的表面侧的一部分的层残留而形成。例如，在图8(c)中，示出以对应于各导线6的方式仅使Cu层8(Cu层81与Cu层82)残留而形成的情况，在图8(d)中，示出以对应于各导线6的方式仅使Cu层82残留而形成的情况。在这些情况下，Al层7需要设为0.1μm以上。
如上所述，在本发明的实施方式4的功率半导体装置中，将功率半导体元件4的表面电极41a或者表面电极41a的表面侧的一部分的层分别对应于多条导线6地设置，对表面电极41a的最表面的Cu层82与分别对应的Cu制的导线6进行导线键合，所以，即使在用Cu导线键合到功率半导体元件的情况下，也不仅能够抑制对功率半导体元件的损伤，由于能够使热应力分散，所以还能够抑制表面电极的剥落，进一步地能够实现可靠性优良的布线。另外，能够实现生产率的提高。
实施方式5.
在实施方式4中，与Al层7的形状相匹配地形成Cu层8(Cu层81与Cu层82)，但在实施方式5中，说明以Cu层8(Cu层81与Cu层82)遮盖的方式形成的情况。
图9是示出本发明的实施方式5的功率半导体装置的主要部分的结构的放大剖视图。如图9所示，在功率半导体元件4的表面电极41a中，Cu层8(Cu层81与Cu层82)在以覆盖Al层7的方式在绝缘层9上伸出1～10μm左右的状态下进行遮盖。表面电极41a与实施方式4同样地，最表面是维氏硬度为70～150Hv的柔软的以Cu为主成分的通过非电解镀敷形成的Cu层82，在其下方存在维氏硬度为200～350Hv的硬的以Cu为主成分的通过非电解镀敷形成的Cu层81。进一步地，在其下方成膜有以Al为主成分的Al层7。将非电解镀敷81镀敷在非电解镀敷82上，所以，非电解镀敷81也在绝缘层9上与非电解镀敷82相同或者更多地遮盖。关于其他结构，也与实施方式4的功率半导体装置相同，省略其说明。
如上所述，在本发明的实施方式5的功率半导体装置中，在功率半导体元件4的表面电极41a中，Cu层8(Cu层81与Cu层82)在以覆盖Al层7的方式在绝缘层9上伸出的状态下进行遮盖，所以，即使在用Cu导线键合到功率半导体元件的情况下，也能够抑制对功率半导体元件的损伤，通过使热应力分散，不仅能够抑制表面电极的剥落，由于Al不露出，所以还能够防止Al的电蚀，进一步地，能够实现可靠性优良的布线。另外，能够实现生产率的提高。
在上述各实施方式的功率半导体装置中，通过Cu制的导线6进行导线键合，所以与Al制的导线相比，成为电阻小且电流容量大的布线。因此，作为功率半导体元件4，也可以使用通过带隙比Si制大的宽带隙半导体而形成的元件。作为宽带隙半导体，例如，可列举碳化硅(SiC)、氮化镓(GaN)、金刚石等。
通过这样的宽带隙半导体形成的功率半导体元件的耐电压性高，容许电流密度也高。另外，由于耐热性也高，所以能够实现散热部件的冷却凸片的小型化、空冷化，所以能够实现功率半导体装置的进一步的小型化。
如果使功率半导体装置的小型化推进，则对于确保散热性和针对热应力的长期可靠性的要求进一步变高。针对这样的要求，本发明的功率半导体装置也发挥优良的效果。
此外，本发明能够在其发明范围内自由地组合各实施方式或者将各实施方式适当地变形、省略。

Claims (18)

1.一种功率半导体装置，其特征在于，具备：
功率半导体元件；
第一电极层，设置于所述功率半导体元件上；
第二电极层，设置于所述第一电极层上，硬度比所述第一电极层低，并且以Cu为主成分；以及
键合导线，连接到所述第二电极层，并且以Cu为主成分，
所述第一电极层的维氏硬度是200～350Hv，所述第二电极层的维氏硬度是70～150Hv。
2.根据权利要求1所述的功率半导体装置，其特征在于，
所述第一电极层是以Cu为主成分的层。
3.根据权利要求1所述的功率半导体装置，其特征在于，
所述第一电极层是基底层与通过非电解镀敷形成于所述基底层上的以Cu为主成分的层。
4.根据权利要求3所述的功率半导体装置，其特征在于，
所述第二电极层是以所述第一电极层为基底并通过非电解镀敷形成的以Cu为主成分的层。
5.根据权利要求1所述的功率半导体装置，其特征在于，
所述第一电极层仅是基底层，所述第二电极层是以所述第一电极层为基底并通过非电解镀敷形成的以Cu为主成分的层。
6.根据权利要求1所述的功率半导体装置，其特征在于，
所述第一电极层的平均晶体粒径为1μm以下。
7.根据权利要求1所述的功率半导体装置，其特征在于，
所述第二电极层的平均晶体粒径为5μm以上。
8.根据权利要求1所述的功率半导体装置，其特征在于，
所述第一电极层的膜厚是5～20μm。
9.根据权利要求1所述的功率半导体装置，其特征在于，
所述第二电极层的膜厚是5～20μm。
10.根据权利要求3所述的功率半导体装置，其特征在于，
所述第一电极层的基底层的膜厚是0.1～5μm。
11.根据权利要求10所述的功率半导体装置，其特征在于，
所述基底层由Al、Cu或者Ni形成。
12.根据权利要求1所述的功率半导体装置，其特征在于，
在所述第一电极层与所述第二电极层之间，设置有金属膜。
13.根据权利要求1所述的功率半导体装置，其特征在于，
所述键合导线设置有多条，并且至少所述第二电极层是与所述键合导线分别对应地设置有多个，
所述功率半导体元件在所述第一电极层以及所述第二电极层的外周设置有绝缘层。
14.根据权利要求13所述的功率半导体装置，其特征在于，
所述绝缘层用聚酰亚胺或者氮化膜来设置。
15.根据权利要求3所述的功率半导体装置，其特征在于，
所述键合导线设置有多条，并且至少所述第二电极层是与所述键合导线分别对应地设置有多个，
所述功率半导体元件在所述基底层的外周设置有绝缘层，
通过非电解镀敷形成于所述基底层上的以Cu为主成分的层以及所述第二电极层遮盖外周的所述绝缘层。
16.根据权利要求15所述的功率半导体装置，其特征在于，
遮盖所述绝缘层的区域的外周的宽度是1～10μm。
17.根据权利要求1所述的功率半导体装置，其特征在于，
所述功率半导体元件由宽带隙半导体材料形成。
18.根据权利要求17所述的功率半导体装置，其特征在于，
所述宽带隙半导体材料是碳化硅、氮化镓系材料以及金刚石中的任意材料。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112016001142B4 (de) * 2015-03-10 2020-01-16 Mitsubishi Electric Corporation Leistungs-Halbleitervorrichtung
CN109075089B (zh) 2016-05-18 2021-12-17 三菱电机株式会社 电力用半导体装置及其制造方法
WO2018015156A1 (en) * 2016-07-19 2018-01-25 Danfoss Silicon Power Gmbh Electrical assembly comprising a metal body arranged on a semiconductor chip and a connecting material arranged between the semiconductor chip and the metal body and connecting them
JP6698499B2 (ja) * 2016-11-15 2020-05-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2019110247A (ja) * 2017-12-19 2019-07-04 トヨタ自動車株式会社 半導体装置
US10872861B2 (en) * 2018-02-07 2020-12-22 Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan Semiconductor packages
US11538734B2 (en) * 2018-04-11 2022-12-27 Hitachi Energy Switzerland Ag Power semiconductor package with highly reliable chip topside
US11658093B2 (en) * 2018-07-12 2023-05-23 Rohm Co., Ltd. Semiconductor element with electrode having first section and second sections in contact with the first section, and semiconductor device
JPWO2020144790A1 (ja) * 2019-01-10 2021-02-18 三菱電機株式会社 電力用半導体装置
DE112021001391T5 (de) * 2020-03-04 2022-12-15 Rohm Co., Ltd. Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements
JP7267963B2 (ja) * 2020-03-11 2023-05-02 株式会社 日立パワーデバイス 半導体装置
DE112020007026T5 (de) 2020-04-06 2023-01-19 Mitsubishi Electric Corporation Halbleitereinheit und verfahren zur herstellung einer halbleitereinheit
JP7496724B2 (ja) 2020-06-25 2024-06-07 株式会社 日立パワーデバイス 半導体装置
US20230253349A1 (en) 2020-08-03 2023-08-10 Mitsubishi Electric Corporation Semiconductor device, manufacturing method thereof and power converter
CN112201628A (zh) * 2020-08-24 2021-01-08 株洲中车时代半导体有限公司 一种功率模块封装结构及其制备方法
JP2023058346A (ja) 2021-10-13 2023-04-25 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2023182429A (ja) * 2022-06-14 2023-12-26 三菱重工業株式会社 パワーモジュール用基板
WO2024009722A1 (ja) * 2022-07-05 2024-01-11 ローム株式会社 半導体装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148649A (ja) * 1986-12-12 1988-06-21 Mitsubishi Electric Corp 半導体装置の電極構造
US5235212A (en) * 1988-03-18 1993-08-10 Kabushiki Kaisha Toshiba Semiconductor device having a mechanical buffer
JPH07302811A (ja) * 1994-05-10 1995-11-14 Hitachi Ltd 大電流通電用Ａｌワイヤ及びこれを用いた半導体モジュール
CN1484857A (zh) * 2000-12-28 2004-03-24 具自行钝化铜合金之铜垫\接合\铜线
CN1957260A (zh) * 2004-05-19 2007-05-02 Jsr株式会社 片状探针及其制造方法和应用
CN101290930A (zh) * 2007-04-19 2008-10-22 英飞凌科技股份公司 包含半导体芯片叠层的半导体器件及其制造方法
CN103703560A (zh) * 2011-08-04 2014-04-02 三菱电机株式会社 半导体装置及其制造方法
JP2014082367A (ja) * 2012-10-17 2014-05-08 Nippon Micrometal Corp パワー半導体装置
CN104143539A (zh) * 2013-05-06 2014-11-12 奇景光电股份有限公司 用于驱动集成电路的金属凸块结构及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000208548A (ja) * 1999-01-11 2000-07-28 Hitachi Ltd 半導体装置
JP3790995B2 (ja) * 2004-01-22 2006-06-28 有限会社ボンドテック 接合方法及びこの方法により作成されるデバイス並びに接合装置
KR100756134B1 (ko) * 2004-04-21 2007-09-05 닛본 덴끼 가부시끼가이샤 솔더 및 그것을 사용한 실장품
US8378231B2 (en) * 2008-07-31 2013-02-19 Ibiden Co., Ltd. Semiconductor device and method for manufacturing the same
JP5326481B2 (ja) * 2008-10-14 2013-10-30 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP2013004781A (ja) 2011-06-17 2013-01-07 Sanken Electric Co Ltd 半導体装置及び半導体装置の製造方法
JP5970316B2 (ja) * 2012-09-26 2016-08-17 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE112014002135T5 (de) * 2013-04-25 2016-01-14 Fuji Electric Co., Ltd. Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung
DE112016001142B4 (de) * 2015-03-10 2020-01-16 Mitsubishi Electric Corporation Leistungs-Halbleitervorrichtung

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148649A (ja) * 1986-12-12 1988-06-21 Mitsubishi Electric Corp 半導体装置の電極構造
US5235212A (en) * 1988-03-18 1993-08-10 Kabushiki Kaisha Toshiba Semiconductor device having a mechanical buffer
JPH07302811A (ja) * 1994-05-10 1995-11-14 Hitachi Ltd 大電流通電用Ａｌワイヤ及びこれを用いた半導体モジュール
CN1484857A (zh) * 2000-12-28 2004-03-24 具自行钝化铜合金之铜垫\接合\铜线
CN1957260A (zh) * 2004-05-19 2007-05-02 Jsr株式会社 片状探针及其制造方法和应用
CN101290930A (zh) * 2007-04-19 2008-10-22 英飞凌科技股份公司 包含半导体芯片叠层的半导体器件及其制造方法
CN103703560A (zh) * 2011-08-04 2014-04-02 三菱电机株式会社 半导体装置及其制造方法
JP2014082367A (ja) * 2012-10-17 2014-05-08 Nippon Micrometal Corp パワー半導体装置
CN104143539A (zh) * 2013-05-06 2014-11-12 奇景光电股份有限公司 用于驱动集成电路的金属凸块结构及其制造方法

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