CN1484857A - 具自行钝化铜合金之铜垫\接合\铜线 - Google Patents

具自行钝化铜合金之铜垫\接合\铜线 Download PDF

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Publication number
CN1484857A
CN1484857A CNA018216528A CN01821652A CN1484857A CN 1484857 A CN1484857 A CN 1484857A CN A018216528 A CNA018216528 A CN A018216528A CN 01821652 A CN01821652 A CN 01821652A CN 1484857 A CN1484857 A CN 1484857A
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copper
packing
self
passivating
alloy
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CN1296997C (zh
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H-J
H·-J·巴斯
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种集成电路结构，其改进系包含一线接合铜垫铜线组件，其中该铜垫铜线组件特征为自行钝化、低电阻、高接合力以及改进的抗氧化与腐蚀，该铜垫铜线组件系包含一金属化线路，一衬垫，系分开该金属化线路与围绕一铜垫的一铜合金，一介电层，系围绕该衬垫，以及一铜垫，系与一铜合金线接合，该铜线组件其特征为自行钝化区域系位于一掺杂丰富接口，其中该掺杂丰富接口系位于该铜合金与该衬垫之间、该铜垫的一表面、在该铜垫与该铜合金线间之一接合的一表面、及该铜合金线的一表面。

Description

具自行钝化铜合金之铜垫\接合\铜线
发明背景：
本案系指有关于使用自行钝化铜合金以线接合铜垫与铜线。此产自于一掺杂丰富之铜合金的自行钝化层可保护铜免于腐蚀与氧化。
先前技术之描述：
在线接合的技艺中，此技艺现行的状况是使用铝垫来与传统的铝楔子或铝球相接合。然而，于一铜基金属化作用的顶部引进铝垫是昂贵且需要额外的处理步骤。
再者，倘若使用现行的铜线与铜垫之接合，则所暴露出的铜层对于腐蚀与氧化将是极度敏感的
先前技艺指向在传统过渡电镀上具有线接合的芯片连接，过渡涂附的铜垫是昂贵的，因为在拥有直接芯片贴装(DCA，direct chipattach)线接合集成电路(IC，integrated circuit)芯片的电路载体(circuit carrier)以及用以表现高量线接合(high yieldwirebonding)于拥有铜电路之载体上的线接合跨接器电路(wirebondjumper circuits)都需要有昂贵的镀料。该集成电路芯片系经加热而藉一黏着或接合之芯片贴合物而贴装于该电路载体上。一电路覆盖涂附层(covercoat)或是接合罩(solder mask)遮盖了该铜电路。在直接芯片贴装(DCA)线接合的操作中，硅芯片系被线接合于电路载体上之内接合垫片，其拥有障碍电镀不足(barrier underplatings)与贵重(noble)或是半贵重(seminoble)金属过渡电镀漆(overplatefinishes)或是表面涂附的组合。电路载体线接合应用上的常见层状表面漆冶金(layered surface finish metallurgies)系为一镍电镀不足涂层，其上系藉金、钯或是银之表面过渡电镀的涂层来覆盖。这些层状表面漆处理禁止了下层铜电路金属化作用扩散至上层板(overplate)的表面并且预防了线接合垫表面接着将发生的氧化。相当多在接合之前的垫表面氧化可在其它方面导致无能(inability)，其系发生于高产量的线接合与线接合内连结可靠性的退化等两者上。在铜垫上使用这些过渡处理已被应用于提供高产量以及高的线接合内连结的可靠性等两者之上了。
因为电镀槽化学需要珍贵的金属组件以及严谨的方法控制，这些电镀处理是昂贵的。再者，当使用电解电镀时，汇流组态(bussingconfiguration)必须被提供至需要电镀处理的所有区域。该汇流(bussing)包含较有效率的线组态并可预防在面版与电路两设计中可用载体空间的最大使用量。该电解电镀能导致较高的电路片段花费，因为多个微处理器电路组态料系被无效率地封装在面版态载体材料上，其系包含有弹性的载体材料，例如聚醯亚胺(polyimide)，聚酯(polyester)以及刚性载体材料，例如玻璃环氧组件(glass epoxycomposite)或是陶器(ceramic)，液晶聚合物(LCP，liquid crystalpolymer)。
美国5,632,438号专利揭露了一个线接合铝于铜电路化作用之直接芯片贴装(direct chip attachment)方法，其系包含：传递一集成电路芯片至一载体；以一具有柠檬酸与草酸根之添加物的液态清洗水溶液处理该该载体及所附之集成电路芯片；冲洗该芯片及所负之集成电路芯片；以及线结合于由该载体传送的铜电路化作用之上。
一用以改良深次微米集成电路封装(deep-submicron integratedcircuit packages)接合能力的方法系被揭露于美国6,110,816号专利中。此方法包含：提供一具有顶端电导层之半导体物质、覆盖在该顶端电导层上的一覆盖层以及涂附在该复盖层上的一光阻层；图案化(patterning)该光阻层以形成次微米尺寸的孔数组(array ofsubmicron size holes)；蚀刻由该覆盖层通至该顶端电导层的开口并透过该覆盖层的开口而形成一粗质表面轮廓于该顶端电导层；以及寻址一钝化膜(passivation film)于该覆盖层上，并形成线球接合(wire ball banding)之线接垫窗口(wiring pad window)。
在以铜线(Cu-wires)线接合(wirebonding)铜垫(Cu-pads)而制作集成电路的技艺领域中，接合于纯铜垫上的纯铜线提供了最佳的接合品质以及最低的电阻；然而，纯铜无法提供自行钝化的效果，也因此使得铜将处于受的腐蚀以及氧化的危险之中。相对应地，关于能够提供铜线接合于铜垫上进以提供好的接合能力以及好的接合品质，其系耦合于自我钝化的能力，以至于以此组态所生成的铜与集成电路能执行自行钝化并进而可抗腐蚀与氧化方面的需求是存在于本技艺之中的。
发明概述
本案之目的，系为提供将铜线接合至铜垫，因而提供一好的接合品质与低的电阻，其中该铜具有自行钝化的特征。
本案之另一目的，系为提供铜线接合至铜垫，因而提供一好的接合品质与低的电阻，藉铜线接合至铜垫上，并由于自行钝化铜合金的利用，而可抗腐蚀与氧化。
本案之另一目的，系为提供铜线接合至铜垫，因而提供一好的接合品质与低的电阻，经由利用铜线与铜垫  以提供铜线接合至铜垫，该铜因自行钝化铜合金的使用而抗腐蚀与氧化。
本案之另一目的，系为提供铜线接合至铜垫，其中此线为一固体的铜合金线或是一双层铜线，其具有一由铜合金组件的内芯与一纯铜的外部核心，依据将铜线接合至铜垫，以便提供好的接合力与接合品质，以由铜合金而达到自行钝化。
本案之另一目的，系为提供铜线接合至铜垫，其中铜线系为一双层与铜垫亦为一双层(铜合金种晶层+纯铜填充)，以达到自行钝化，因而抵抗腐蚀与氧化。
根据本案之构想，当铜垫与铜线的线接合利用铜合金(铜-铝、铜-镁与铜-锂)而被完成时，好的接合力与好的接合品质就被与抵抗腐蚀与氧连在一起。
简单图标说明：
第一图呈现了一个与一铜垫接合之前的铜合金线，其中该铜垫系被一铜合金围绕，该铜合金又被衬垫围绕，所有皆被设置于一介电质中。
第二图呈现了在线接合以及锻炼至一铜垫后的铜合金线，其中所形成的接合乃为一球或是楔子，且其中有一个掺杂丰富的接口层藉自行钝化而特化生成，如X’s所示。
实施内容：
一般而言，在本发明的内容中，具有铜线的铜垫线接合，系使用自行钝化之铜合金以便制成一个半导体装置或是集成电路，其系由下列处理程序制备而得：
(1)图案化一(双重)波纹结构在一介电层中以形成该接线与接合垫；
(2)沉积一金属衬垫(以物理气相沉积(PVD)、化学气相层积(CVD)、无电镀(electroless)，或是其它技艺已熟知的方法(此步骤可由使用最佳数量的铜合金而成为选择性的步骤))；
(3)沉积一铜合金成为一种晶层以做为一最终的铜填充(PVD、CVD或是其它技艺已熟知的方法)；
(4)以纯铜填充该波纹结构(电镀、CVD、无电镀、PVD或是其它技艺已熟知的方法)；
(5)预先化学机械研磨(pre-CMP)退火，其系在小于200℃的低温进行，以形成具有较大铜粒子的一低电阻铜薄膜；然而此时应防止在该铜合金中的掺杂向外散布；
(6)化学机械研磨该铜以移除过量填充的铜(Cu-overfill)，接着化学机械研磨该衬垫；
后续处理程序的四种可能主张系分述于后：
主张A：
(7)后化学机械研磨(post-CMP)退火(温度范围：250℃至450℃)以便在该铜-表面以及该铜-该衬垫之接口上形成一自行钝化掺杂丰富层(其有利于透过一逐步性的温度增加来开始抑制丘状物的生成。在掺杂丰富表层初步生成之后，该丘状物的之形成将明显地减少)；
(8)沉积介电盖层(铜扩散障碍、硅-氮化物、区块或是其它技艺已熟知的方法)。整个排除此介电扩散阻碍并继续二氧化硅沉积或是其它介电材料(例如低k材料)沉积的方法是可能的。
主张B：
(7)沉积一介电层盖层(铜扩散障碍、硅-氮化物、区块或是其它技艺已熟知的方法)；
(8)退火(温度范围：250-450℃)以便在铜-介电盖层之接口以及该铜-该衬垫之接口上形成一自行钝化掺杂丰富层。
主张C：
(7)后化学机械研磨(post-CMP)退火，其系在温度250℃至400℃内进行，当与(9)相比较时，此温度是较低的。该后盖层退火约在接近50℃时在该铜表面以及铜-衬垫之接口上形成一部分自行钝化掺杂丰富层。其有利于透过一逐步性的温度增加来开始抑制丘状物的生成。在掺杂丰富表层初步(部分)生成之后，该丘状物的之形成将明显地减少；
(8)沉积介电盖层(铜扩散障碍、硅-氮化物、区块或是其它技艺已熟知的方法)。整个排除此介电扩散阻碍并继续二氧化硅沉积或是其它介电材料(例如低k材料)沉积的方法是可能的。
(9)后盖层退火，(温度范围：300-450℃约高于(7)之后化学机械研磨退火50℃，以在该衬垫及盖层接口上形成最终自行钝化层。此具有两个退火步骤(7)以及(8)之方式在丘状物生成以及黏着方面上是有利的。
主张D：
(7)沉积介电盖层(铜扩散障碍、硅-氮化物、区块或是其它技艺已熟知的方法)。此探作程序的观点中并无退火因而并无自行钝化层的形成。
下列步骤为本发明方法的关键步骤：
(10)沉积一最终钝化层(氧化物/氮化物联合体)；
(11)沉积一聚醯亚胺或光敏感聚醯亚胺(PSPI)层(选择性的)；
(12)图案化该聚醯亚胺(或是PSPI)以及完成最终钝化(系包含在铜顶端之介电盖层)，其系藉由微光显影与蚀刻步骤来敞开该垫区域。在该垫开口的蚀刻方法中(以及过去的处理)，位于铜/盖层接口上的自行钝化层被移除以便有一个可供进行探测(probing)的干净铜表面。
(13)探测芯片；
(14)以铜合金线来线接合(楔子或是球接合)被探测的垫；以及
(15)在温度250℃至450℃之间退火接合的该芯片以便形成一自行钝化层于敞开的该铜垫表面与该铜线上。
在探测步骤(13)与接合步骤(14)之间，较长的时间消逝。为了在此期间保护铜垫，一个额外的步骤可被引入以形成自行钝化/保护层于该被探测的铜表面。在结合前的不久，此层系藉湿式清洗而被移除，以便能有一个干净的铜垫表面用以获得最佳的接合品质。
参考的部份现在以第一图表现，其描绘出在与铜垫11接合前的铜合金线10。该铜垫系被一铜合金12所围绕，其依次藉一衬垫14而与介电层13区隔。
随意地，如虚线所示，一聚醯亚胺15可被沉积在该介电层的顶部。
如第二图中所可看见的，在线结合后紧接着退火，则钝化掺杂丰富接口层16以及自行钝化铜表面17将形成，两着皆藉X’s来标示。此自行钝化系在铜合金附近，在接合球或是楔子18附近，且位在垫-线连接的接合处。此掺杂丰富的自行钝化层与丘状物无关且保护铜免于受的腐蚀、氧化并避免铜外散至周围的半导体装置地区。
在本发明之正文中，所谓的铜合金可为铜-铝、铜-镁、铜-锂以及其它已广为人知的铜合金，而来自于其它铜合金组件之非铜添加物的浓度将介于该铜合金的原子重量百分比之0.1至5％。
以铜线接于铜垫之线接合，其系使用了自行钝化铜合金，在改善接合能力进以保护铜免受腐蚀与氧化是特别重要的，其系为本发明方法所引发出之自行钝化的优点。
相对应地，具有铜线之铜垫，其系使用自行钝化铜合金，提供了可与接合在纯铜垫上之纯铜线相比较的接合品质与低电阻，并且也提供了接合于纯铜垫上之纯铜线所无法获致的自行钝化效果。换言之，此与一双层铜垫(铜合金晶种层+纯铜充填)相接合的双层铜线显现了最佳的自行钝化、低电阻以及高接合强度等等的特性。
当某些具代表性的实施例以及详情已被视为是本案所述之较佳实施例的目的时，本案得由熟习此技艺者任施匠思而为诸般修饰，然接不脱如所附申请专利范围所欲保护者。

Claims (18)

1.一种集成电路结构，其改进系包含一线接合铜垫铜线组件，其中该铜垫铜线组件特征为自行钝化、低电阻、高接合力以及改进的抗氧化与腐蚀，该铜垫铜线组件系包含：
一金属化线路；
一衬垫，系分开该金属化线路与围绕一铜垫的一铜合金；
一介电层，系围绕该衬垫；以及
一铜垫，系接合至一铜合金线，
该铜线组件其特征为自行钝化区域，系位于：
a)一掺杂丰富接口，系位于该铜合金与该衬垫之间；
b)该铜垫的一表面；
c)在该铜垫与该铜合金线间之一接合的一表面；
d)该铜合金线的一表面。
2.如申请专利范围第1项所述之结构，其中一氧化物、一氮化物或氮化物的组合之一钝化层，在大约250℃至大约450℃的一温度的退火之后，已被设置在该介电层。
3.如申请专利范围第2项所述之结构，其中在该钝化区域系在一范围内呈现，该范围系为大约0.1至大约5的该铜合金原子重量百分比。
4.如申请专利范围第3项所述之结构，其中该铜合金系选自一群组，该群组包含一铜-铝合金、一铜-镁合金及一铜-锂合金。
5.如申请专利范围笫4项所述之结构，其中该铜合金系为一铜-铝合金。
6.如申请专利范围第4项所述之结构，其中该铜合金系为一铜-镁合金。
7.如申请专利范围第4项所述之结构，其中该铜合金系为一铜-锂合金。
8.一种制备一集成电路结构之方法，其中该集成电路结构系包含具有铜线之一线接合铜垫组件，其中一自行钝化铜垫铜线，其特征为抗氧化、腐蚀与改善在一接口的黏着，该接口系在该铜垫与一金属化线路之间以及在该铜垫与连结一铜合金线之一接合之间，该方法系包含：
a)图案化一波纹结构在一介电层中以形成一接线与接合垫；
b)沉积一金属衬垫；
c)沉积一铜合金成为一种晶层以做为一最终的铜填充；
d)填充一纯铜至该波纹结构；
e)预先化学机械研磨(pre-CMP)退火，其系在小于200℃的低温进行，形成具有较大铜粒子的一低电阻铜薄膜与防止在该铜合金中的掺杂向外散布；
f)化学机械研磨该铜，以移除填充过多的该铜，以及由化学机械研磨该衬垫；
g)后化学机械研磨(post-CMP)退火，其系在大约250℃至大约450℃的一温度范围内进行，在该铜表面与该衬垫接口上形成一自行钝化掺杂丰富层；
h)沉积一聚醯亚胺层；
i)图案化该聚醯亚胺与完成该钝化，其系经由微影与蚀刻步骤，敞开该垫区域而提供一干净的该铜表面以进行探测(probing)；
j)探测一芯片；
k)以该铜合金线来线接合探测的该垫；
l)退火接合的该芯片，温度系在大约250℃至大约450℃之间以形成一自行钝化层于敞开的该铜垫表面与该铜线上。
9.如申请专利范围第8项所述之方法，其中，在步骤a)之后，步骤b)系被沉积一最适当量的铜合金而除去。
10.一种制备一集成电路结构之方法，其中该集成电路结构系包含具有铜线之一线接合铜垫组件，其中一自行钝化铜垫铜线，其特征为抗氧化、腐蚀与改善在一接口的黏着，该接口系在该铜垫与一金属化线路之间以及在该铜垫与连结一铜合金线之一接合之间，该方法系包含：
a)图案化一波纹结构在一介电层中以形成一接线与接合垫；
b)沉积一金属衬垫；
c)沉积一铜合金成为一种晶层以做为一最终的铜填充；
d)填充一纯铜至该波纹结构；
e)预先化学机械研磨(pre-CMP)退火，其系在小于200℃的低温进行，形成具有较大铜粒子的一低电阻铜薄膜与防止在该铜合金中的掺杂向外散布；
f)化学机械研磨该铜，以移除填充过多的该铜，以及由化学机械研磨该衬垫；
g)沉积一介电层盖层；
h)退火，其系在大约250℃至大约450℃的一温度范围内进行，在该铜-该介电层盖之接口与该铜-该衬垫之接口上形成一自行钝化掺杂丰富层；
i)沉积一聚醯亚胺层；
j)图案化该聚醯亚胺与完成该自行钝化，其系经由微影与蚀刻步骤，敞开该垫区域而提供一干净的该铜表面以进行探测(probing)；
k)探测一芯片；
l)以该铜合金线来线接合探测的该垫；以及
m)退火接合的该芯片，温度系在大约250℃至大约450℃之间以形成一自行钝化层于敞开的该铜垫表面与该铜线上。
11.如申请专利范围第10项所述之方法，其中，在步骤a)之后，步骤b)系被沉积一最适当量的铜合金而除去。
12.一种制备一集成电路结构之方法，其中该集成电路结构系包含具有铜线之一线接合铜垫组件，其中一自行钝化铜垫铜线，其特征为抗氧化、腐蚀与改善在一接口的黏着，该接口系在该铜垫与一金属化线路之间以及在该铜垫与连结一铜合金线之一接合之间，该方法系包含：
a)图案化一波纹结构在一介电层中以形成一接线与接合垫；
b)沉积一金属衬垫；
c)沉积一铜合金成为一种晶层以做为一最终的铜填充；
d)填充一纯铜至该波纹结构；
e)预先化学机械研磨(pre-CMP)退火，其系在小于200℃的低温进行，形成具有较大铜粒子的一低电阻铜薄膜与防止在该铜合金中的掺杂向外散布；
f)化学机械研磨该铜，以移除填充过多的该铜，以及由化学机械研磨该衬垫；
g)后化学机械研磨(post-CMP)退火，其系在大约250℃至大约450℃的一温度范围内进行，在该铜表面与该衬垫接口上形成一部分自行钝化掺杂丰富层；
h)沉积一介电层盖层；
i)于自约300度至约450度之温度后盖层退火，以于该衬垫及盖层接口上形成一最后自行钝化层；
j)沉积一聚醯亚胺层；
k)图案化该聚醯亚胺与完成该自行钝化，其系经由微影与蚀刻步骤，敞开该垫区域而提供一干净的该铜表面以进行探测(probing)；
l)探测一芯片；
m)以该铜合金线来线接合探测的该垫；
n)退火接合的该芯片，温度系在大约250℃至大约450℃之间以形成一自行钝化层于敞开的该铜垫表面与该铜线上。
13.如申请专利范围笫12项所述之方法，其中，在步骤a)之后，步骤b)系被沉积一最适当量的铜合金而除去。
14.一种制备一集成电路结构之方法，其中该集成电路结构系包含具有铜线之一线接合铜垫组件，其中一自行钝化铜垫铜线，其特征为抗氧化、腐蚀与改善在一接口的黏着，该接口系在该铜垫与一金属化线路之间以及在该铜垫与连结一铜合金线之一接合之间，该方法系包含：
a)图案化一波纹结构在一介电层中以形成一接线与接合垫；
b)沉积一金属衬垫；
c)沉积一铜合金成为一种晶层以做为一最终的铜填充；
d)填充一纯铜至该波纹结构；
e)预先化学机械研磨(pre-CMP)退火，其系在小于200℃的低温进行，形成具有较大铜粒子的一低电阻铜薄膜与防止在该铜合金中的掺杂向外散布；
f)化学机械研磨该铜，以移除填充过多的该铜，以及由化学机械研磨该衬垫；
g)后化学机械研磨(post-CMP)退火，其系在大约250℃至大约450℃的一温度范围内进行，在该铜表面与该铜衬垫接口上形成一自行钝化掺杂丰富层；
h)沉积一介电层盖层；
i)沉积一聚醯亚胺层；
j)图案化该聚醯亚胺与完成该自行钝化，其系经由微影与蚀刻步骤，敞开该垫区域而提供一干净的该铜表面以进行探测(probing)；
k)探测一芯片；
l)以该铜合金线来线接合探测的该垫；
m)退火接合的该芯片，温度系在大约250℃至大约450℃之间以形成一自行钝化层于敞开的该铜垫表面与该铜线上。
15.如申请专利范围第14项所述之方法，其中，在步骤a)之后，步骤b)系被沉积一最适当量的铜合金而除去。
16.如申请专利范围第14项所述之结构，其中该铜垫系为一铜-铝合金。
17.如申请专利范围第14项所述之结构，其中该铜线系为内芯为铜合金而外部区域为纯铜之双层线，且该铜垫系铜合金。
18.如申请专利范围第14项所述之结构，其中该铜线系为一铜-锂合金，且该铜垫系铜合金。
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