CN1770437A - 接合垫结构 - Google Patents

接合垫结构 Download PDF

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Publication number
CN1770437A
CN1770437A CNA2005100735278A CN200510073527A CN1770437A CN 1770437 A CN1770437 A CN 1770437A CN A2005100735278 A CNA2005100735278 A CN A2005100735278A CN 200510073527 A CN200510073527 A CN 200510073527A CN 1770437 A CN1770437 A CN 1770437A
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Prior art keywords
layer
joint sheet
stress
metal
metal layer
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CNA2005100735278A
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CN100517668C (zh
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黄泰钧
姚志翔
万文恺
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN1770437A publication Critical patent/CN1770437A/zh
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种接合垫结构。集成电路晶片的接合垫结构中，有一应力缓冲层介于接合垫层与最上层内连线层的金属层之间，以避免晶圆的探针测试与封装撞击对接合垫所造成的破坏。该应力缓冲层为一导电材料，其杨氏模数、硬度、强度或坚韧度大于最上层内连线层的金属层或该接合垫层的杨氏模数、硬度、强度或坚韧度。为改善粘合与接合的强度，可将应力缓冲层的底部修改为各种不同形式，如嵌于保护层的环状、网状或连锁栅格结构，在应力缓冲层中可以有多个孔洞，其由接合垫层将之填满。本发明所述接合垫结构，提供较佳的机械完整性。可避免应力造成的失效与接垫剥离的问题，而大大增加接合的可靠度。

Description

接合垫结构
技术领域
本发明主要是关于接合垫(bond pad)结构，特别是关于一具有应力缓冲层(stress-buffering layer)的接合垫结构，该缓冲层覆盖内连线金属层，以避免因晶圆电性测试(Wafer AcceptanceTest)与封装撞击的应力所造成的失效(failure)。
背景技术
接合垫是介于在半导体晶片内的集成电路与装置封装间的介面。借由打线接合、卷带自动接合(tape automated bonding)或覆晶接合技术，将接合垫连结至装置封装的集成电路粘合面上的接触垫(contact pad)。因为铜较佳的导电性和机械完整性，所以采用铜作为下一代内连线金层、接点和接合垫的材料。一种介电常数尽可能低的绝缘材料，如介电常数低于3.9的硅氧化物，已被使用在后段制程(Back-end-of-line，BEOL)的内连线技术，以避免信号干扰和传播延迟。铜是一种极易氧化的材料，并且湿气容易加深其氧化的程度，因此使用高抗氧化力的铝接合垫覆盖铜内连线的上部，可使用铝内连线技术的接合工具与制程制作铝接合垫。然而在铜金属层上沉积铝接合垫时，大部分的铝被消耗在与铜作用(生成CuAl2)。于是需要一介于铝接合垫与铜金属层间的钽氮化物作为扩散阻障层，以避免铝与铜作用。作为本发明参考的美国专利第6350667号，描述一介于钽氮化物与铜金属层间的粘合铝层，可改善接合垫金属堆叠结构的粘合。
具高电流强度的现代集成电路设计，为缩小接合垫的间距与尺寸，所需的针脚(pin)与接合垫的数目明显增加。但是伴随接合操作而来的机械应力，容易破坏尺寸较小的接合垫。在晶圆电性测试(Wafer Accept Test)时，如晶圆的探针测试(wafer probingtest)或类似的测试，探针针脚可能破坏铝接合垫柔软的表面，进而使铜金属层曝露于空气中并受到侵蚀，如此将降低金属连线的接合力。在包括晶圆測试、打线接合、覆晶封装或晶圆的探针測试的封装制程中，外力或强大机械应力可能使靠近探针针脚的金层间介电层(inter-metal dielectric，IMD)破裂。该裂缝可能延伸至包围最上层铜金层层的金层间介电层的内部，导致侵蚀和层剥离的问题，也将导致铝接合垫从最上层铜金层层剥离，而失去与金层线的连结，进而降低接合的可靠性。此外，因为铝接合垫易受机械应力破坏影响，接合垫的间距与尺寸无法进一步缩小，以致限制下一时代晶片尺寸的缩小。
发明内容
本发明的目的在提供一改良的接合垫结构，其具有应力缓冲层设置于一最上层内连线金层层与一接合垫层之间，以避免因晶圆电性测试与封装撞击的应力所造成的失效。
为达以上的目的，本发明提供一种接合垫结构，包括：
一第一金属层，形成于一集成电路基板之上；一接合垫层，位于该第一金属层之上并且电性连结于该第一金属层；及一应力缓冲层，位于该第一金属层与该接合垫层之间，其中该应力缓冲层的杨氏模数、硬度、强度或坚韧度大于该第一金属层或该接合垫层的杨氏模数、硬度、强度或坚韧度。
本发明所述的接合垫结构，该应力缓冲层包括一钨金属层。
本发明所述的接合垫结构，该第一金属层包括铜或铜基合金。
本发明所述的接合垫结构，该接合垫层包括铝或铝基合金。
本发明所述的接合垫结构，更包括一第一夹层位于该第一金属层与该应力缓冲层之间，其中该第一夹层包括氮化钽(TaN)、氮化钛(TiN)、钽(Ta)、钨化钛(TiW)、氮化钨(WN)、以上的混合物、以上的组合或以上的合金。
本发明所述的接合垫结构，更包括一第二夹层位于该接合垫层与该应力缓冲层之间，其中该第二夹层包括氮化钽(TaN)、氮化钛(TiN)、钽(Ta)、钨化钛(TiW)、氮化钨(WN)、以上的混合物、以上的组合或以上的合金。
本发明所述的接合垫结构，该集成电路基板包括至少一个介电层，该介电层的介电常数小于3.9，而该第一金属层形成于该介电层中。
本发明所述的接合垫结构，该集成电路基板包括一集成电路，而至少部分的该集成电路位于该接合垫结构之下。
本发明所述的接合垫结构，更包括：一保护层形成于该第一金属层之上，该保护层包括有一接垫孔洞，以使至少部分的该第一金属层暴露出来；其中该应力缓冲层形成于该接垫孔洞之中，该应力缓冲层是沿着该接垫孔洞的底部或侧壁而形成；其中该接合垫层形成于该应力缓冲层之上并且填满该接垫孔洞。
本发明所述的接合垫结构，更包括：一保护层形成于该第一金属层之上，该保护层包括有一图案化的第一孔洞，以使至少部分的该第一金属层暴露出来，且该保护层包括至少一个被该第一孔洞围绕的岛区；其中该应力缓冲层形成于该保护层之上并且填满该第一孔洞。
本发明所述的接合垫结构，更包括：一保护层形成于该第一金属层之上，该保护层包括有一第一孔洞，以使至少部分的该第一金属层暴露出来；其中该应力缓冲层形成于该第一孔洞之中，且该应力缓冲层包括至少一个小于该第一孔洞的第二孔洞，以使至少部分的该第一金属层暴露出来；其中而该接合垫层形成于该应力缓冲层之上并且填满该第二孔洞。
本发明所述的接合垫结构，更包括：一第二金属层，位于该第一金属层之下；多个导电中介窗插塞，位于该第一金属层与该第二金属层之间，用以电性连结该第一金属层与该第二金属层；及一钨金属层，位于该多个导电中介窗插塞与该第二金属层之间。
本发明所述的接合垫结构，更包括：一第二金属层，位于该第一金属层之下；多个导电中介窗插塞，位于该第一金属层与该第二金属层之间，用以电性连结该第一金属层与该第二金属层；及一钨金属层，位于该多个导电中介窗插塞与该第一金属层之间。
为达以上的目的，本发明提供一种接合垫结构，包括一铜基金属层，形成于一集成电路基板上；一保护层，形成于该铜基金属层之上，该保护层至少有一个第一孔洞，以使至少部分的该铜基金属层暴露出来；一应力缓冲层，形成于该铜基金属层上方的该第一孔洞中；及一铝基接合垫层，形成于该应力缓冲层之上，并且电性连结至该铜基金属层；其中该应力缓冲层的杨氏模数、硬度、强度或坚韧度大于该铜基金属层或该铝基接合垫层的杨氏模数、硬度、强度或坚韧度。
为达以上的目的，本发明提供一种接合垫结构，包括一铜基金属层，形成于一集成电路基板之上；一保护层，形成于该铜基金属层之上，该保护层至少有一个第一孔洞，以使至少部分的该铜基金属层暴露出来；一第一夹层，作为该保护层的第一孔洞的衬垫；一钨金属层，形成于该第一夹层之上并填满该第一孔洞；一第二夹层，形成于该钨金属层之上；及一铝基接合垫层，形成于该第二夹层之上，并且电性连结至该铜基金属层。
本发明所述接合垫结构，提供较佳的机械完整性。可避免因晶圆电性测试与封装撞击的应力所造成的破坏。故能避免应力造成的失效与接垫剥离的问题，而大大增加接合的可靠度。
附图说明
图1A至图1D是根据本发明的实施例，显示接合垫结构的横剖面示意图；
图2A是根据本发明的实施例，显示一金属线球(wire ball)粘合于接合垫结构的横剖面示意图；
图2B是根据本发明的实施例，显示一形成于接合垫结构上的金属凸块形成于接合垫结构之上的横剖面示意图；
图3A、图3B是根据本发明的实施例，显示一位于接合垫结构下方的电路(circuits under pad，CUP)区域的横剖面示意图；
图4A是根据本发明的实施例，显示一嵌于第一保护层的环状孔洞中的应力缓冲层的横剖面示意图；
图4B是根据本发明的实施例，显示该嵌于第一保护层的环状孔洞中的应力缓冲层底部的俯视图；
图5A是根据本发明的实施例，显示一嵌于第一保护层的连锁栅格孔洞中的应力缓冲层的横剖面示意图；
图5B、图5C是根据本发明的实施例，显示嵌于第一保护层的连锁栅格孔洞中的应力缓冲层底部的俯视图；
图6A是根据本发明的实施例，显示一嵌于应力缓冲层的孔洞中的接合垫底部的横剖面示意图；
图6B、图6C是根据本发明的实施例，显示应力缓冲层的孔洞的俯视图。
具体实施方式
本发明提供一改良的集成电路的接合垫结构。本发明的一实施例是提供一接合垫结构，其具有一应力缓冲层，设置于一最上层内连线金属层与一接合垫层之间，以避免因晶圆电性测试(如晶圆的探针测试)与封装撞击(如打线接合、覆晶封装或其它封装制程中的外力)的应力所造成的破坏。该应力缓冲层可为导电材料，而且相较于该第一金属层与该接合垫层其中之一的材料性质，该应力缓冲层的杨氏模数(Young’s modulus)、硬度、强度或坚韧度(toughness)较大。于本发明的一实施例中，一接合垫结构是提供于一具有至少一低介电常多层(介电常数大体小于3.9)的集成电路晶片上，其具有一应力缓冲层，置于一最上层内连线金属层的电极接触区与一铝基接合垫层之间。该应力缓冲层由导电材料构成，具有较佳的机械完整性，在材料的选择上为钨，因其杨氏模数大于铜与铝。为改善粘合与接合的强度，可将接合垫孔洞修改为各种不同形式，使应力缓冲层的底部成为如嵌于保护层的环状、条纹状、岛状、网状或连锁中介窗结构。在本发明的一实施例中，为求更有效使用晶片面积或缩小晶片大小，至少一部分的电路位于接合垫结构下方，被称为接合垫结构下方的电路(circuits underpad，CUP)。
本发明可使用铜基导电材料以形成第一金属层与第二金属层，其中第二金属层位于该第一金属层之下。该铜基导电材料倾向于包括大体为纯元素的铜、含难以避免的杂质的铜、或是含少量元素如钽、铟、锡、锌、镁、铬、钛、锗、锶、铂、锰、铝、锆的铜合金。铜后段内连线可使用标准镶嵌制程。虽然本发明的较佳实施例是显示铜内连线的图案，但也可使用铜以外的金属材料作为后段内连线的材料。
图1A是根据本发明的实施例，显示接合垫结构100的横剖面示意图。在一使用于内连线制造的半导体基板10的例子中，可包含一使用于半导体集成电路制造的半导体基板与形成于其上或其下的集成电路。半导体基板被定义为包括半导体材料的任何结构，其中包含但不限定：硅块(bulk silicon)、半导体晶圆、绝缘层上硅晶(silicon-on-insulator，SOI)或包括Ge、GaAs、GaP、InAs和InP的基板。此处的集成电路指的是有多个独立的电路元件的电子电路，如晶体管、二极管、电阻、电容、电感和其它主动或被动元件。
在半导体基板10上，可形成一金属层间介电层12以作为最上层金属层间介电层，而第一金属层14则形成于金属层间介电层12之中。第一金属层14包含一终端接触区，其为导电路径的一部分并有一曝露的表面作为与接合垫层26的电性连结。可用如化学机械研磨的平坦化制程处理第一金属层14，以达与金属层间介电层12相同的平坦度。第一金属层14的合适材料包括如铜、铜合金或其它铜基导电材料。金属层间介电层12的形成可以采用各种不同的技术，如旋转涂布、化学气相沉积和未来发展的沉积技术，厚度大体为1000～20000埃。金属层间介电层12材质可为二氧化硅、SiNx、SiON、含磷硅石玻璃(PSG)、硼磷硅石玻璃(BPSG)、含氟二氧化硅或其它各式介电常数小于3.9的低介电常数材料(如介电常数3.5的低介电常数材料)。根据本发明的实施例，可使用广泛的低介电常数材料，如旋转涂布的无机介电材料、旋转涂布的有机介电材料、多孔洞的介电材料、有机聚合物、有机硅石玻璃、含氟硅石玻璃(FSG)、似钻石的碳、含氢的硅酸盐类(HydrogenSilsesquioxane)系列的材料、含甲基的硅酸盐类(Methylsilsesquioxane，简称MSQ)系列的材料或多孔洞的有机系列材料。
沉积一第一保护层16，然后将之图案化以提供一接垫孔洞18，该接垫孔洞18定义其下方的第一金属层14的导电中介窗的区域。为避免集成电路晶片受到外界环境的影响，第一保护层16包含至少一种可以避免湿气接触到第一金属层14的材料，如硅氧化物或硅氮化物。第一保护层16可以是单层或多层的结构，包含四乙基氧硅烷(TOES)氧化物、硅氧化物或等离子加强硅氮化物其中任何一种。
第一保护层16代表性的厚度大体为500～200000埃。接垫孔洞18是一终端中介窗孔洞(terminal via opening)，其使用微影、光罩(masking)和干式蚀刻技术使第一金属层14的终端接触区(terminal contact region)暴露出来。
沉积接合垫层26之前，先沿着该接垫孔洞18的底部与侧墙依序沉积第一夹层20、应力缓冲层22和第二夹层24。依照接合垫结构100的材料沉积形式，第一夹层20与第二夹层24至少其中之一可以是非必须的，但应力缓冲层22则是必须的，用以覆盖其下的第一金属层14。图1A显示一种三层结构，包括第一夹层20、应力缓冲层22与第二夹层24。本发明也提供一种接合垫结构仅包含有第一夹层20或第二夹层24，如图1B、图1C所示。作为接垫孔洞18的衬垫的第一夹层20，可包括一金属扩散阻障层、一粘合层(adhesion layer)或一以上两者的组合。第一夹层20提供良好的金属扩散阻障层与导电性。第一夹层20的材料可包含但不限定耐火材料、氮化钽(TaN)、氮化钛(TiN)、钽(Ta)、钛、TiSN、TaSN、铬、钨化钛、氮化钨、以上的混合物、以上的组合、以上的合金或其它可避免铜金属层暴露于空气的材料，可以物理气相沉积、化学气相沉积、原子层沉积(atomic layerdeposition)、化学镀(无电镀)(electroless plating)、溅镀或其它相似的沉积技术形成之。第一夹层20的厚度大体为50～1500埃。
应力缓冲层22是一导电材料并具有一性质选自于下列的群组，其包括：杨氏模数(Young’s modulus)、硬度(如Minernlhardness、Brinell hardness和Vikers hardness)、强度和坚韧度(toughness)，至少大于第一金属层14与接合垫层26其中之一。例如，应力缓冲层22是一钨金属，其杨氏模数(Young’s modulus)或硬度大于铜与铝。在实验量测中，钨的杨氏模数是铜的3倍以上而钨的Vikers硬度约是铜的10倍。钨的杨氏模数是铝的5倍以上而钨的Vikers硬度约是铜的20倍。应力缓冲层22的厚度视接合垫层26的材料与厚度和接合垫的阻值要求而定。应力缓冲层22的厚度最好为500～5000埃。如图1A所示的实施例中，应力缓冲层22沿着接垫孔洞18的底部与侧墙沉积于第一夹层20之上。如图1D所示的实施例中，应力缓冲层22只沿着接垫孔洞18的底部沉积于至少一部分接垫面积之上。
沉积于应力缓冲层22上的第二夹层24可包括一金属扩散阻障层、一粘合层或一以上两者的组合。第二夹层24提供良好的金属扩散阻障层与导电性。第二夹层24也提供介于应力缓冲层22与接合垫层26间的良好的附着特性。第二夹层24可使用与第一夹层20相同的材料，如耐火材料、氮化钽(TaN)、氮化钛(TiN)、钽(Ta)、钛、TiSN、TaSN、铬、钨化钛、氮化钨、以上的混合物、以上的组合、以上的合金或其它可避免铜金属层暴露于空气的材料。可以物理气相沉积、化学气相沉积、原子层沉积(atomic layerdeposition)、化学镀(无电镀)(electroless plating)、溅镀或其它相似的沉积技术形成之。第二夹层24的厚度大体为50～1500埃。
以物理气相沉积、化学气相沉积、原子层沉积(atomic layerdeposition)、化学镀(无电镀)(electroless plating)、溅镀或其它相似的沉积技术，沉积接合垫层26于第二夹层24上，并至少填满接垫孔洞18。接合垫层26最好是铝基材料，如铝、铝铜合金、铝铜硅合金。接合垫层26的厚度大体为1000～20000埃。然后利用微影、光罩与干式蚀刻(如等离子蚀刻或活性离子蚀刻)制程将接合垫层26、第二夹层24、应力缓冲层22与第一夹层20图案化，以形成一堆叠金属接垫图案得以与其下的第一金属层14电性连结。接着进一步的制程，可选择性地将一第二保护层28形成于堆叠金属接垫图案之上，并露出接合垫层26，以利后续的封装/组装制程。
图2A是根据本发明的实施例，显示一金属线球(wire ball)粘合于接合垫结构的横剖面示意图；图2B是根据本发明的实施例，显示一形成于接合垫结构上的金属凸块34形成于接合垫结构之上的横剖面示意图，省略与图1A相同或相似的叙述。如图2A所示，为了打线接合的应用，使用热压合(thermal compression)、热超音波(thermalsonic)制程，将金属线球30粘合至接合垫层26。金属线球30的组成可以是金(选择性地使用少量铍、铜、钯、铁、银、钙、镁)、铜或银。如图2B所示，为了打线接合的应用，凸块底下金属层(Under Bump Metallurgy，UBM)结构32与金属凸块34依序形成于接合垫层26之上。凸块底下金属层结构32可有一层、两层、三层或更多层的变化，取决于金属凸块34的材质是选用金、铜、铝、铅、锡或镍基合金。凸块底下金属层结构32的材质可以用铬/铜、钛/钯、钛/钨、钛/铂、铝/镍、铬/铜/金、镍/铜、钛/铜、钛化钨/铜与镍/金，其可采用蒸镀、印刷、无电镀、溅镀等制程形成。
本发明的接合垫结构100有多点优于现有技术。将应力缓冲层22设置于接合垫层26与第一金属层14之间，其坚硬材质与导电性质可在接合垫结构100中提供较佳的机械完整性。这可避免因晶圆电性测试(如晶圆的探针测试)与封装撞击(如晶圆测试、打线接合、覆晶封装或其它封装制程中的外力)的应力所造成的破坏。故能避免应力造成的失效与接垫剥离的问题，而大大增加接合的可靠度。另外可调整接合垫层26与应力缓冲层22的厚度以达成阻值的要求。在实验量测中，500～1500埃的钨金属层与6500～7500埃的铝金属层的组合可得一约相当于4.81E-2micro-ohm的电阻，几乎与传统9000埃的铝接垫相等。
为求更有效使用晶片面积或缩小晶片大小，至少一部分的电路位于接合垫结构下方，被称为接合垫结构下方的电路(circuitsunder pad，CUP)。图3A、图3B是根据本发明的实施例，显示一位于接合垫结构下方的电路(circuits under pad，CUP)区域的横剖面示意图。以下则省略与图1A相同或相似的叙述，其中第二金属层36位于金属层间介电层12之下，并透过多个嵌于金属层间介电层12的导电中介窗插塞(via plug)38，电性连结至第一金属层14。可形成另一应力缓冲层40于第二金属层36的上部、第一金属层14的底部或其组合。另一应力缓冲层40的材料可与应力缓冲层22相同。另一应力缓冲层40是导电材料且其杨氏模数(Young’s modulus)或硬度大于该第一金属层14与第二金属层36其中之一。另一应力缓冲层40可为厚度500～5000埃的钨金属层。坚硬材质的另一应力缓冲层40在接合垫结构100中提供较佳的机械完整性以避免应力造成的失效。
为改善粘合与接合的强度，可将接合垫孔洞18修改为各种不同形式，使应力缓冲层22的底部成为嵌于第一保护层16的环状、条纹状、岛状、网状或连锁中介窗结构(interlocking-viastructure)。同样的，为了将垂直传导最佳化，可在应力缓冲层22中定义各种不同形式的孔洞，使接合垫层26的底部成为嵌于应力缓冲层22的环状、条纹状、岛状、网状或连锁中介窗结构。
图4A是根据本发明的实施例，显示一嵌于第一保护层的环状孔洞中的应力缓冲层的横剖面示意图；图4B是根据本发明的实施例，显示该嵌于第一保护层的环状孔洞中的应力缓冲层底部的俯视图，在此则省略与图1A相同或相似的叙述。相较于图1A的接垫孔洞18，图4A、图4B描述一定义于第一保护层16的环状孔洞17a，用以曝露与的对应的第一金属层14的环状接触区，也因此定义一位于第一保护层16中被环状孔洞17a包围的岛区16a。在以第一夹层20作为环状孔洞17a的衬垫后，沉积应力缓冲层22于第一夹层20之上以填满环状孔洞17a，且覆盖第一保护层16的上表面。应力缓冲层22嵌于第一保护层16的环状孔洞17a中的底部称为环状金属支撑22a，其能加强金属堆叠的接垫结构各层间的附着力，避免介面剥离的失效与介面断裂的失效。
图5A是根据本发明的实施例，显示一嵌于第一保护层的连锁栅格孔洞中的应力缓冲层的横剖面示意图；图5B、图5C是根据本发明的实施例，显示嵌于第一保护层的连锁栅格孔洞中的应力缓冲层底部的俯视图。省略与图4A、图4B相同或相似的叙述。
相较于环状孔洞17a，图5B、图5C描述一定义于第一保护层16的如栅栏或网状连锁栅格孔洞17b，用以曝露与之对应的第一金属层14的连锁栅格接触区，也因此定义一位于第一保护层16中多个被连锁栅格孔洞17b包围的岛区16a。应力缓冲层22嵌于第一保护层16的连锁栅格孔洞17b中的底部称为连锁栅格金属支撑22b，其能加强金属堆叠的接垫结构各层间的附着力。
图6A是根据本发明的实施例，显示一嵌于应力缓冲层的孔洞的接合垫底部的横剖面示意图；图6B、图6C是根据本发明的实施例，显示应力缓冲层的孔洞的俯视图。省略与图4A、图4B相同或相似的叙述。沉积接合垫层26之前，先图案化至少一个孔洞19，该孔洞19穿透第一夹层20、应力缓冲层22与第二夹层24，用以曝露与的对应的第一金属层14的接触区。再沉积接合垫层26，将小于接垫孔洞18的孔洞19填满。嵌于孔洞19中的接合垫层26的底部26a可直接接触其下的第一金属层14。孔洞19的数目、外形或大小与产品需求和与制程限制有关。例如，如图6B所示，多个分离的条状孔洞19被定义于应力缓冲层22中。如图6C所示，一个分离的孔洞19阵列被定义于应力缓冲层22中。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
半导体基板：10
金属层间介电层：12
第一金属层：14
第二金属层：36
应力缓冲层：22、40
环状金属支撑：22a
连锁栅状金属支撑：22b
第一保护层：16
第二保护层：28
接合垫结构：100
接合垫层：26
接合垫的底部：26a
接垫孔洞：18
孔洞：19
岛区：16a
环状孔洞：17a
连锁栅格孔洞：17b
第一夹层：20
第二夹层：24
金属线球：30
凸块底下金属层结构：32
金属凸块：34
中介窗插塞：38

Claims (13)

1、一种接合垫结构，所述接合垫结构包括：
一第一金属层，形成于一集成电路基板之上；
一接合垫层，位于该第一金属层之上并且电性连结于该第一金属层；及
一应力缓冲层，位于该第一金属层与该接合垫层之间，其中该应力缓冲层的杨氏模数、硬度、强度或坚韧度大于该第一金属层或该接合垫层的杨氏模数、硬度、强度或坚韧度。
2、根据权利要求1所述的接合垫结构，其特征在于：该应力缓冲层包括一钨金属层。
3、根据权利要求1所述的接合垫结构，其特征在于：该第一金属层包括铜或铜基合金。
4、根据权利要求1所述的接合垫结构，其特征在于：该接合垫层包括铝或铝基合金。
5、根据权利要求1所述的接合垫结构，其特征在于：更包括一第一夹层位于该第一金属层与该应力缓冲层之间，其中该第一夹层包括氮化钽、氮化钛、钽、钨化钛、氮化钨、以上的混合物、以上的组合或以上的合金。
6、根据权利要求1所述的接合垫结构，其特征在于：更包括一第二夹层位于该接合垫层与该应力缓冲层之间，其中该第二夹层包括氮化钽、氮化钛、钽、钨化钛、氮化钨、以上的混合物、以上的组合或以上的合金。
7、根据权利要求1所述的接合垫结构，其特征在于：该集成电路基板包括至少一个介电层，该介电层的介电常数小于3.9，而该第一金属层形成于该介电层中。
8、根据权利要求1所述的接合垫结构，其特征在于：该集成电路基板包括一集成电路，而至少部分的该集成电路位于该接合垫结构之下。
9、根据权利要求1所述的接合垫结构，其特征在于更包括：
一保护层形成于该第一金属层之上，该保护层包括有一接垫孔洞，以使至少部分的该第一金属层暴露出来；
其中该应力缓冲层形成于该接垫孔洞之中，该应力缓冲层是沿着该接垫孔洞的底部或侧壁而形成；
其中该接合垫层形成于该应力缓冲层之上并且填满该接垫孔洞。
10、根据权利要求1所述的接合垫结构，其特征在于更包括：
一保护层形成于该第一金属层之上，该保护层包括有一图案化的第一孔洞，以使至少部分的该第一金属层暴露出来，且该保护层包括至少一个被该第一孔洞围绕的岛区；
其中该应力缓冲层形成于该保护层之上并且填满该第一孔洞。
11、根据权利要求1所述的接合垫结构，其特征在于更包括：
一保护层形成于该第一金属层之上，该保护层包括有一第一孔洞，以使至少部分的该第一金属层暴露出来；
其中该应力缓冲层形成于该第一孔洞之中，且该应力缓冲层包括至少一个小于该第一孔洞的第二孔洞，以使至少部分的该第一金属层暴露出来；
其中而该接合垫层形成于该应力缓冲层之上并且填满该第二孔洞。
12、根据权利要求1所述的接合垫结构，其特征在于更包括：
一第二金属层，位于该第一金属层之下；
多个导电中介窗插塞，位于该第一金属层与该第二金属层之间，用以电性连结该第一金属层与该第二金属层；及
一钨金属层，位于该多个导电中介窗插塞与该第二金属层之间。
13、根据权利要求1所述的接合垫结构，其特征在于更包括：
一第二金属层，位于该第一金属层之下；
多个导电中介窗插塞，位于该第一金属层与该第二金属层之间，用以电性连结该第一金属层与该第二金属层；及
一钨金属层，位于该多个导电中介窗插塞与该第一金属层之间。
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