CN109994430A - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN109994430A
CN109994430A CN201811476472.9A CN201811476472A CN109994430A CN 109994430 A CN109994430 A CN 109994430A CN 201811476472 A CN201811476472 A CN 201811476472A CN 109994430 A CN109994430 A CN 109994430A
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China
Prior art keywords
layer
electrode
salient point
semiconductor element
emitter
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CN201811476472.9A
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English (en)
Inventor
黑川敦
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Publication of CN109994430A publication Critical patent/CN109994430A/zh
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Abstract

提供一种半导体元件，能够使起因于凸点与半导体层的热膨胀系数的差异而产生的热应力降低并且能够减少布线层的层数。晶体管包含设置于基板的半导体区域以及三种端子电极，至少一个端子电极具有由多个导体图案构成的分离电极构造。在具有分离电极构造的端子电极之上，配置有将多个导体图案相互电连接的凸点。在晶体管的半导体区域与凸点之间，配置有由包含高熔点金属的金属材料构成的应力缓和层。在导体图案与凸点之间，没有配置将多个导体图案相互连接的电流路径。

Description

半导体元件
技术领域
本发明涉及半导体元件。
背景技术
经由凸点将半导体元件安装于安装基板并将凸点用作散热路径的技术是公知的(专利文献1、2)。
在专利文献1所公开的半导体装置中，通过将形成于化合物半导体基板的多个单位晶体管进行并联连接而构成了异质结双极晶体管(HBT)。多个单位晶体管的发射极与凸点电连接。多个单位晶体管在第一方向上排列，凸点在第一方向上延伸而配置。
在专利文献2所公开的半导体装置中，布线层中包含的电流路径与导电性柱连接。导电性柱与HBT的发射极连接。
在先技术文献
专利文献
专利文献1：JP特开2016-103540号公报
专利文献2：美国发明专利第8314472号
发明内容
发明要解决的课题
专利文献1所公开的多个单位晶体管的每个单位晶体管具有集电极、基极以及发射极这三个端子。多个单位晶体管的集电极彼此、基极彼此、以及发射极彼此分别通过汇总布线而连接。由于为了将三个端子分别与汇总布线连接而需要使布线交叉，因此需要至少两层的布线层。
在专利文献2所公开的半导体装置中，由于导电性柱(凸点)与半导体层的热膨胀系数的差异，在半导体层产生热应力。由于该热应力，容易发生半导体装置的可靠性的下降、电气特性的偏差、电气特性的不良等。
本发明的目的在于，提供一种能够使起因于凸点与半导体层的热膨胀系数的差异而产生的热应力降低、并且能够减少布线层的层数的半导体元件。
用于解决课题的手段
本发明的第一观点的半导体元件具有：
晶体管，其包含设置于基板的半导体区域以及三种端子电极，至少一个所述端子电极具有由多个导体图案构成的分离电极构造；
凸点，其配置在具有所述分离电极构造的所述端子电极之上，并将多个所述导体图案相互电连接；和
应力缓和层，其配置在所述晶体管的半导体区域与所述凸点之间，由包含高熔点金属的金属材料构成，
在所述导体图案与所述凸点之间，没有配置将多个所述导体图案相互连接的电流路径。
通过配置应力缓和层，从而能够使在晶体管的半导体区域产生的热应力降低。由于具有分离电极构造的端子电极的多个导体图案通过凸点而相互电连接，因此不需要配置将多个导体图案相互连接的布线层。因此，能够减少布线层的层数。
本发明的第二观点的半导体元件在第一观点的半导体元件的结构的基础上，还具有如下特征：
所述应力缓和层包含从由W、Mo、Ta以及Cr构成的组中选择的至少一种高熔点金属，并且所述应力缓和层的厚度为100nm以上。
通过将应力缓和层设为这样的结构，从而能够得到使热应力降低的充分效果。
本发明的第三观点的半导体元件在第一观点的半导体元件的结构的基础上，还具有如下特征：
所述应力缓和层包含Ti作为高熔点金属，并且所述应力缓和层的厚度为300nm以上。
通过将应力缓和层设为这样的结构，从而能够得到使热应力降低的充分效果。
本发明的第四观点的半导体元件在第一观点至第三观点的任一项的半导体元件的结构的基础上，还具有如下特征：
所述应力缓和层形成为所述凸点的基底层，并且具有与所述凸点的平面形状相同的平面形状。
通过成为凸点的基底层的应力缓和层配置在凸点与半导体区域之间，从而能够使起因于凸点的热膨胀率与半导体区域的热膨胀率的差异而在半导体区域产生的热应力降低。
本发明的第五观点的半导体元件在第一观点至第三观点的任一项的半导体元件的结构的基础上，还具有如下特征：
所述应力缓和层构成具有所述分离电极构造的所述端子电极的一部分。
通过端子电极作为应力缓和层而发挥功能，从而能够使在半导体区域产生的热应力降低。
本发明的第六观点的半导体元件在第一观点至第五观点的任一项的半导体元件的结构的基础上，还具有如下特征：
所述半导体元件还具有配置在所述端子电极与所述凸点之间的一个布线层，
所述凸点以及所述导体图案与所述布线层中包含的布线不经由其他布线层而连接。
由于凸点和多个导体图案经由一层的布线层而连接，多个导体图案通过凸点而相互连接，因此不需要配置两层以上的布线层。由此，能够实现制造成本的降低。
本发明的第七观点的半导体元件在第一观点至第六观点的任一项的半导体元件的结构的基础上，还具有如下特征：
所述晶体管是包含集电极层、基极层、发射极层的双极晶体管，
三个所述端子电极包含分别与所述集电极层、所述基极层以及所述发射极层连接的集电极电极、基极电极以及发射极电极。
通过使在双极晶体管的半导体区域产生的热应力降低，从而能够抑制双极晶体管的可靠性的下降、电气特性的偏差等。
本发明的第八观点的半导体元件在第七观点的半导体元件的结构的基础上，还具有如下特征：
在俯视下，在所述凸点的内侧配置有所述发射极层。
能够使在发射极层产生的热通过凸点有效地向外部进行散热。由于在凸点与半导体区域之间配置有应力缓和层，因此即使在俯视下在凸点的内侧配置有发射极层的情况下，由于在发射极层产生的热应力被降低，因此能够抑制可靠性的下降、特性的偏差等。
本发明的第九观点的半导体元件在第一观点至第六观点的任一项的半导体元件的结构的基础上，还具有如下特征：
所述晶体管是包含划定在所述基板的表层部的活性区域的场效应晶体管，
三个所述端子电极包含分别配置于所述活性区域之上的源极电极、漏极电极以及栅极电极。
通过使在场效应晶体管的半导体区域产生的热应力降低，从而能够抑制场效应晶体管的可靠性的下降、电气特性的偏差等。
本发明的第十观点的半导体元件在第九观点的半导体元件的结构的基础上，还具有如下特征：
在俯视下，所述栅极电极与所述活性区域重叠的区域配置在所述凸点的内侧。
能够使在栅极电极与活性区域重叠的动作区域产生的热通过凸点有效地向外部进行散热。由于在凸点与半导体区域之间配置有应力缓和层，因此即使在俯视下在凸点的内侧配置有动作区域的情况下，由于在动作区域产生的热应力被降低，因此也能够抑制可靠性的下降、特性的偏差等。
发明效果
通过配置应力缓和层，能够使在晶体管的半导体区域产生的热应力降低。由于具有分离电极构造的端子电极的多个导体图案通过凸点而相互电连接，因此不需要配置将多个导体图案相互连接的布线层。因此，能够减少布线层的层数。
附图说明
图1是第一实施例的半导体元件的俯视图。
图2是图1的单点划线2-2处的剖视图。
图3是比较例的半导体元件的概略俯视图。
图4A是第一实施例的第二变形例的半导体元件的剖视图，图4B是第一实施例的第三变形例的半导体元件的剖视图。
图5是第二实施例的半导体元件的俯视图。
图6是图5的单点划线6-6处的剖视图。
图7是示出在第二实施例中以未配置作为应力缓和层而发挥功能的凸点下金属层的情况为基准时的在本征发射极层产生的热应力的最大值的变化率的图。
图8是第三实施例的半导体元件的剖视图。
图9是示出在第三实施例中以未配置应力缓和层的情况为基准时的在本征发射极层产生的热应力的最大值的变化率的图。
图10是示出在第四实施例中以未配置作为应力缓和层的发射极电极的情况为基准时的在本征发射极层产生的热应力的最大值的变化率的图。
图11是第五实施例的半导体元件的俯视图。
图12是图11的单点划线12-12处的剖视图。
图13是第五实施例的变形例的半导体元件的剖视图。
符号说明
20 基板
21 单位晶体管
23 辅助集电极层
23a 隔离区域
24 集电极层
25 基极层
26 发射极层
26A 本征发射极层
26B 发射极台面层
26C 台肩层
27、28 绝缘膜
28A 树脂膜
28B SiN膜
28C 树脂膜
30 发射极用的凸点
31 凸点下金属层
32 金属柱
33 焊料层
35 集电极用的凸点
41 应力缓和层
50 活性区域
51 基板
52 沟道层
52a 隔离区域
55、56 绝缘膜
60 动作区域
B0 基极电极
B1 第一层的基极布线
BC 基极汇总布线
C0 集电极电极
C1 第一层的集电极布线
CC 集电极汇总布线
D0 漏极电极
D1 第一层的漏极布线
E0 发射极电极
E1 第一层的发射极布线
EC 发射极汇总布线
G0 栅极电极
G1 第一层的栅极布线
S0 源极电极
S1 第一层的源极布线。
具体实施方式
[第一实施例]
参照图1、图2以及图3，对第一实施例的半导体元件进行说明。
图1是第一实施例的半导体元件的俯视图。定义如下的xyz正交坐标系，即：将半导体元件的基板的上表面设为xy面，将上表面的法线方向设为x轴的正方向。第一实施例的半导体元件包含晶体管以及与晶体管连接的布线和凸点。该晶体管包含相互并联连接的两个单位晶体管21。
两个单位晶体管21在x轴方向上排列配置。单位晶体管21的每一个包含：发射极层、基极层和集电极层、以及与它们分别连接的发射极电极E0、基极电极B0和集电极电极C0。在图1中，对发射极电极E0、基极电极B0以及集电极电极C0标注了阴影线。
各发射极电极E0具有在y轴方向上较长的长方形的平面形状。基极电极B0配置为，关于x轴方向从正侧以及负侧和关于y轴从正侧这三个方向包围各发射极电极E0。关于x轴方向在基极电极B0的两侧分别配置有集电极电极C0。配置于两个单位晶体管21的基极电极B0之间的集电极电极C0由两个单位晶体管21共用。
实施例的半导体元件包含：配置于第一层的布线层的发射极布线E1、集电极布线C1以及基极布线B1。第一层的发射极布线E1由配置为与两个发射极电极E0分别重叠的两个孤立的导体图案构成，每个导体图案与其下的发射极电极E0电连接。
第一层的集电极布线C1具有梳齿型的平面形状。第一层的集电极布线C1的梳齿部分配置为分别与集电极电极C0重叠。构成集电极电极C0的多个导体图案通过第一层的集电极布线C1而相互连接。
第一层的基极布线B1将两个单位晶体管21的各自的基极电极B0相互连接。
凸点30配置为与第一层的发射极布线E1的两个导体图案重叠。凸点30与第一层的发射极布线E1的两个导体图案电连接。构成两个单位晶体管21的发射极电极E0的两个导体图案通过凸点30而相互电连接。
图2是图1的单点划线2-2处的剖视图。在由半绝缘性的GaAs构成的基板20之上配置有辅助集电极层23。辅助集电极层23由高浓度的n型GaAs形成，其厚度例如为0.5μm。辅助集电极层23的一部分设为通过离子注入而绝缘化的隔离区域23a。辅助集电极层23由两个单位晶体管21共用。
在辅助集电极层23之上，按每个单位晶体管21依次层叠有集电极层24、基极层25以及发射极层26。集电极层24由n型GaAs形成，其厚度例如为1μm。基极层25由p型GaAs形成，其厚度例如为100nm。基极层25和集电极层24具有相同的平面形状，构成集电极台面(mesa)。
发射极层26配置在基极层25的一部分区域之上。发射极层26例如包含从基极层25侧依次配置的厚度30nm～40nm的n型InGaP层、厚度100nm的高浓度的n型GaAs层、以及厚度100nm的高浓度的n型InGaAs层。高浓度的n型InGaAs层用于与配置于其上的发射极电极E0取得欧姆接触。
集电极电极C0配置在辅助集电极层23之上，并且与辅助集电极层23欧姆连接。集电极电极C0由三个导体图案构成，三个导体图案关于x轴方向而言配置在集电极台面之间以及两个集电极台面的外侧。集电极电极C0例如通过将厚度60nm的AuGe膜、厚度10nm的Ni膜以及厚度200nm的Au膜进行层叠而形成。
基极电极B0配置在基极层25之上，并且与基极层25欧姆连接。在图2所示的剖面中，基极电极B0配置在发射极层26的两侧。基极电极B0例如通过将厚度50nm的Ti膜、厚度50nm的Pt膜、厚度200nm的Au膜进行层叠而形成。
在发射极层26之上配置有发射极电极E0。作为发射极电极E0，例如可使用厚度50nm的Ti膜。
绝缘膜27配置为覆盖单位晶体管21。作为绝缘膜27，例如可使用SiN膜与聚酰亚胺等树脂膜的层叠膜。绝缘膜27的上表面被平坦化。另外，也可以由SiN膜的单层来构成绝缘膜27。
在绝缘膜27之上，配置有第一层的发射极布线E1以及集电极布线C1。发射极布线E1经由设置于绝缘膜27的开口与发射极电极E0电连接。第一层的集电极布线C1经由设置于绝缘膜27的开口与集电极电极C0电连接。在图2所示的剖面中虽未示出，但在绝缘膜27之上，还配置有第一层的基极布线B1(图1)。基极布线B1经由设置于绝缘膜27的开口与基极电极B0电连接。
第一层的发射极布线E1、集电极布线C1以及基极布线B1例如具有厚度50nm的Ti膜和配置于其上的厚度1μm的Au膜的两层构造。
在绝缘膜27之上配置有上层的绝缘膜28，使得覆盖第一层的发射极布线E1、集电极布线C1以及基极布线B1。作为绝缘膜28，例如可使用SiN膜、或SiN膜与树脂膜的层叠膜。
在绝缘膜28之上，配置有凸点30。凸点30经由在绝缘膜28按第一层的每个发射极布线E1设置的开口而与发射极布线E1电连接。凸点30包含金属柱32以及其上的焊料层33。在凸点30之下，配置有凸点下金属层31作为基底层。
凸点下金属层31例如由Ti形成。作为金属柱32，例如可使用厚度50μm的Cu膜。作为焊料层33，例如可使用厚度30μm的Sn膜。也可以在金属柱32与焊料层33之间，配置由Ni等构成的相互扩散防止用的阻挡金属层。
接着，关于通过采用第一实施例的半导体元件的构造而得到的优异的效果，与图3所示的比较例的半导体元件进行比较来加以说明。
图3是比较例的半导体元件的概略俯视图。为了将多个单位晶体管并联连接而配置有集电极汇总布线CC、发射极汇总布线EC以及基极汇总布线BC。集电极汇总布线CC将多个集电极电极C0相互连接。发射极汇总布线EC将多个发射极电极E0相互连接。基极汇总布线BC将多个基极电极B0相互连接。为了将三种电极分别与对应的汇总布线进行连接，通常，至少不得不使两个布线交叉。例如，在图3所示的比较例中，用于将发射极电极E0与发射极汇总布线EC进行连接的布线与集电极汇总布线CC交叉。因此，为了将多个单位晶体管21并联连接，需要至少两层的布线层。
在第一实施例中，如图1所示，第一层的集电极布线C1以及基极布线B1分别担负作为集电极汇总布线以及基极汇总布线的任务。第一层的发射极布线E1按照发射极电极E0的两个导体图案的每一个导体图案进行配置，不具有作为发射极汇总布线的任务。在第一实施例中，凸点30将发射极电极E0的两个导体图案相互连接，担负作为发射极汇总布线的任务。这样，凸点30除了具有本来的作为外部连接用的端子的功能之外，还具有作为将发射极电极E0的两个导体图案相互连接的汇总布线的功能。因此，不需要设置与图3所示的集电极汇总布线CC交叉的布线。
如上所述，在第一实施例中，不必一定设置两层的布线层，因此与比较例(图3)相比能够减少布线层的层数。通过减少布线层的层数，从而能够实现制造成本的降低。
接着，对通过配置凸点下金属层31(图2)而得到的优异的效果进行说明。起因于由GaAs、InGaAs等的半导体构成的发射极层26、基极层25以及集电极层24的热膨胀率与由Cu、Sn等构成的金属柱32以及焊料层33的热膨胀率之差，在发射极层26等的半导体层产生热应力。例如，相对于GaAs的热膨胀率为大约6ppm/℃，InGaP的热膨胀率在5ppm/℃以上且6ppm/℃以下的范围内，而Cu的热膨胀率为17ppm/℃，Sn的热膨胀率为22ppm/℃。此外，一般地，安装半导体元件的印刷电路板的热膨胀率也在15ppm/℃以上且20ppm/℃以下的范围内。
用于凸点下金属层31的Ti的热膨胀率为8.6ppm/℃，接近于半导体层的热膨胀率。因此，凸点下金属层31作为缓和在半导体层产生的热应力的应力缓和层而发挥功能。
若在半导体层产生热应力所引起的变形，则在高温下的通电动作时双极晶体管的电流放大率下降。在第一实施例中，由于在半导体层产生的热应力降低，因此能够抑制电流放大率的下降。
进而，在第一实施例中，成为发热源的发射极层26等配置在凸点30的正下方。由于从发热源到凸点30的传热路径变短，因此能够确保经由凸点30的良好的散热特性。结果，能够抑制双极晶体管的温度上升所引起的高频特性的下降。
接着，对第一实施例的第一变形例进行说明。在第一实施例中在凸点下金属层31(图2)使用了Ti，但也可以使用其他的高熔点金属、包含高熔点金属的化合物、或包含高熔点金属的合金。作为高熔点金属，除了Ti之外还可举出Ta、Mo、Cr、W。作为包含高熔点金属的化合物，可举出TaN、TiN等高熔点金属的氮化物、MoSi、WSi等高熔点金属的硅化物。作为包含高熔点金属的合金，可举出TiW等。
作为凸点下金属层31，也可以采用包含对于SiN等的基底的绝缘膜28(图1)而言粘接性良好的Ti膜、和配置于其上的W等应力缓和作用高的膜的多层构造。这样，也可以将凸点下金属层31设为由多个金属膜构成的层叠构造。
接着，参照图4A以及图4B，进一步对第一实施例的第二变形例以及第三变形例进行说明。
图4A是第一实施例的第二变形例的半导体元件的剖视图。在第一实施例中，发射极电极E0和凸点30经由第一层的发射极布线E1(图2)连接。在第二变形例中，省略第一层的布线层，发射极电极E0和凸点30不经由布线层而电连接。进而，基极用的凸点以及集电极用的凸点也不经由布线层而分别与基极电极B0以及集电极电极C0电连接。
在第一变形例中，由于不需要在发射极电极E0、基极电极B0以及集电极电极C0与凸点30之间配置布线层，因此能够进一步降低制造成本。
图4B是第一实施例的第三变形例的半导体元件的剖视图。在第一实施例中，第一层的发射极布线E1经由发射极电极E0(图2)与发射极层26连接。在第三变形例中，省略发射极电极E0，第一层的发射极布线E1与发射极层26直接接触。即，第一层的发射极布线E1兼作第一实施例的发射极电极E0(图2)。
此外，也可以省略集电极电极C0，使第一层的集电极布线C1与辅助集电极层23直接欧姆接触。进而，也可以省略基极电极B0，使第一层的基极布线B1(图1)与基极层25直接欧姆接触。
接着，对第一实施例的第四变形例进行说明。
第一实施例的半导体元件中包含的HBT包含三种端子电极，即发射极电极E0、基极电极B0以及集电极电极C0。在第一实施例的半导体元件中，多个集电极电极C0通过第一层的集电极布线C1而相互电连接，多个基极电极B0通过第一层的基极布线B1而相互电连接。与此相对，构成发射极电极E0的多个导体图案通过凸点30而相互电连接，在发射极电极E0与凸点30之间的布线层中，没有配置将发射极电极E0的多个导体图案相互连接的电流路径。
在第四变形例中，构成集电极电极C0的多个导体图案通过凸点而相互连接，在集电极电极C0与凸点之间，没有配置将构成集电极电极C0的多个导体图案相互连接的电流路径。构成发射极电极E0的多个导体图案通过第一层的发射极布线E1而相互电连接。
也可以构成为通过凸点将构成基极电极B0的多个导体图案相互进行连接，并且在基极电极B0与凸点之间，不配置将构成基极电极B0的多个导体图案相互连接的电流路径。
此外，在第一实施例中，将发射极电极E0的平面形状设为了长方形，但也可以设为其他形状，例如八边形等多边形。与发射极电极E0的形状相匹配，其下的发射极层26的平面形状也可以设为八边形等多边形。
[第二实施例]
接着，参照图5、图6以及图7，对第二实施例的半导体元件进行说明。以下，对于与第一实施例的半导体元件共同的结构，省略说明。
图5是第二实施例的半导体元件的俯视图。在第一实施例中将两个单位晶体管21(图1)进行了并联连接，但在第二实施例中，通过将三个以上的多个例如十个单位晶体管21进行并联连接而构成HBT。十个单位晶体管21在x轴方向上排列配置。各单位晶体管21包含发射极电极E0、基极电极B0以及集电极电极C0。在图5中，对发射极电极E0、基极电极B0以及集电极电极C0标注了阴影线。
第一层的发射极布线E1对应于十个发射极电极E0而由十个导电图案构成。第一层的集电极布线C1将构成集电极电极C0的多个导体图案相互连接。多个第一层的基极布线B1分别与构成基极电极B0的多个导体图案连接。
在第一实施例中，关于x轴方向将基极电极B0配置于发射极电极E0的两侧，但在第二实施例中，仅在发射极电极E0的单侧(x轴的负的一侧)配置有基极电极B0。
凸点30具有在x轴方向上较长的长方形的两端连接了半圆的跑道形状。在俯视下第一层的集电极布线C1的内侧，配置有多个集电极用的凸点35，第一层的集电极布线C1与集电极用的凸点35电连接。
图6是图5的单点划线6-6处的剖视图。基板20、集电极层24以及基极层25的结构与第一实施例的这些结构相同。发射极层26与第一实施例的半导体元件的发射极层26(图2)同样地包含n型InGaP层、高浓度的n型GaAs层、以及高浓度的n型InGaAs层。
在第二实施例中，最下方的n型InGaP层配置在基极层25的上表面的整个区域之上。在n型InGaP层的一部分区域之上，配置有由n型GaAs层和n型InGaAs层构成的发射极台面层26B。n型InGaP层中的没有配置发射极台面层26B的区域耗尽化。将耗尽化的区域称为台肩(ledge)层26C。将n型InGaP层中的与发射极台面层26B重叠的区域称为本征发射极层26A。本征发射极层26A和发射极台面层26B相当于第一实施例的半导体元件的发射极层26(图2)。
在设置于台肩层26C的开口内配置有基极电极B0。发射极电极E0以及集电极电极C0的结构与第一实施例的半导体元件的发射极电极E0以及集电极电极C0(图2)的结构相同。
由SiN构成的绝缘膜27配置为覆盖单位晶体管21。在第一实施例中，绝缘膜27(图2)的上表面被平坦化，但是在第二实施例中，绝缘膜27的上表面没有被平坦化。
配置在绝缘膜27之上的第一层的发射极布线E1以及集电极布线C1分别经由设置于绝缘膜27的开口与发射极电极E0以及集电极电极C0电连接。作为第一层的发射极布线E1以及集电极布线C1，例如可使用厚度1μm的Au膜。
绝缘膜28覆盖第一层的发射极布线E1以及集电极布线C1。绝缘膜28具有将树脂膜28A、SiN膜28B以及树脂膜28C按此顺序进行层叠的三层构造。绝缘膜28的上表面被平坦化。绝缘膜28之上的凸点下金属层31以及凸点30的构造与第一实施例的半导体元件(图2)的这些的构造相同。
多个单位晶体管21的本征发射极层26A经由发射极台面层26B、发射极电极E0以及第一层的发射极布线E1，通过凸点30而相互连接。多个单位晶体管21的集电极层24经由辅助集电极层23、集电极电极C0，通过第一层的集电极布线C1而相互连接。
多个单位晶体管21的基极层25经由基极电极B0与第一层的基极布线B1(图1)连接。在图1中，示出了多个基极电极B0通过第一层的基极布线B1而相互连接的例子，但是优选在单位晶体管21各自的基极层25连接镇流电阻、高频输入用的电容器等。基极层25经由镇流电阻与偏置电路连接，并且经由电容器与高频输入用的凸点连接。另外，基极层25也可以经由电容器以及同一基板上的匹配电路与高频输入用的凸点连接。
第二实施例的半导体元件通过将发射极用的凸点30、集电极用的凸点35(图5)、高频输入用的凸点等焊接于安装基板的连接盘等，从而安装于安装基板。作为安装基板，例如可使用氧化铝等的陶瓷基板、树脂基板等。
接着，参照图7，对通过仿真求取在发射极层26产生的热应力的结果进行说明。在仿真中，将本征发射极层26A(图6)的y轴方向的尺寸(长度)设为30μm，将x轴方向的尺寸(宽度)设为4μm。取出10个本征发射极层26A(图5)中的一个并计算了热应力。凸点30(图5)设为在长度240μm、宽度75μm的长方形的短边连接了直径75μm的半圆的跑道形状。将树脂膜28A、28C各自的厚度设为1.5μm，将SiN膜28B的厚度设为0.5μm。对在使半导体元件的温度从焊料的接合温度附近的230℃下降至150℃时在本征发射极层26A产生的热应力进行了计算。
图7是示出以未配置作为应力缓和层而发挥功能的凸点下金属层31的情况为基准时的在本征发射极层26A产生的热应力的最大值的变化率的图。横轴用单位“μm”表示作为应力缓和层而发挥功能的凸点下金属层31的厚度，纵轴用单位“％”表示应力变化率。负的应力变化率意味着热应力降低。应力变化率的绝对值大意味着热应力小。对在凸点下金属层31使用了Ti、Ta、Mo、Cr、W这五种高熔点金属的情况进行了仿真。Ti、Ta、Mo、Cr、W的热膨胀率分别为8.6ppm/℃、6.3ppm/℃、5.1ppm/℃、4.9ppm/℃、4.5ppm/℃。
可知随着凸点下金属层31变厚而热应力下降。这是因为凸点下金属层31的材料的热膨胀率接近于构成半导体元件的半导体材料的热膨胀率。通过该仿真，确认了凸点下金属层31具有使热应力缓和的功能。
[第三实施例]
接着，参照图8以及图9，对第三实施例的半导体元件进行说明。以下，对于与图5、图6、图7所示的第二实施例的半导体元件共同的结构省略说明。
图8是第三实施例的半导体元件的剖视图。在第二实施例中，用作凸点30的基底层的凸点下金属层31(图6)作为应力缓和层而发挥了功能。在第三实施例中，未配置凸点下金属层31，而是在第一层的发射极布线E1之下，配置有应力缓和层41。第一层的发射极布线E1经由应力缓和层41与发射极电极E0连接。
图9是示出以未配置应力缓和层41的情况为基准时的在本征发射极层26A(图8)产生的热应力的最大值的变化率的图。横轴用单位“μm”表示应力缓和层41的厚度，纵轴用单位“％”表示应力变化率。对在应力缓和层使用了Ti、Ta、Mo、W这四种高熔点金属的情况进行了仿真。
随着应力缓和层41变厚而热应力下降，应力缓和层41具有使热应力缓和的功能这一情况得到了确认。在图8所示的例子中，将应力缓和层41配置在第一层的发射极布线E1之下，但应力缓和层41电可以配置在第一层的发射极布线E1之上或第一层的发射极布线E1的内部。
[第四实施例]
接着，参照图10，对第四实施例的半导体元件进行说明。以下，对于与图5、图6、图7所示的第二实施例的半导体元件共同的结构省略说明。
在第二实施例中，使用了厚度50nm的Ti膜作为发射极电极E0，但在第四实施例中，使构成发射极电极E0的Ti膜更厚，或者在发射极电极E0使用Ti以外的高熔点金属。此外，不配置作为应力缓和层而发挥功能的凸点下金属层31(图6)。
图10是示出以未配置作为应力缓和层而发挥功能的发射极电极E0的情况为基准时的在本征发射极层26A产生的热应力的最大值的变化率的图。横轴用单位“μm”表示发射极电极E0的厚度，纵轴用单位“％”表示应力变化率。对在发射极电极E0使用了Ti、Ta、Mo、W这四种高熔点金属的情况进行了仿真。
随着发射极电极E0变厚而热应力下降，发射极电极E0具有使热应力缓和的功能这一情况得到了确认。
[应力缓和层的厚度]
接着，对从第二实施例、第三实施例以及第四实施例的半导体元件的应力变化率的仿真结果推导出的应力缓和层的优选厚度进行说明。使凸点下金属层31(图6)、应力缓和层41(图8)以及发射极电极E0(图10)等应力缓和层都极薄而进行了HBT的寿命试验。结果，判明了在短时间内HBT劣化，难以将该HBT应用于实际使用。这是因为，本征发射极层26A等半导体层由于热应力而受到损伤。若通过配置应力缓和层而使在本征发射极层26A产生的热应力降低2％，则HBT的寿命会延长为大约35倍。该寿命处于经得住实际使用的范围。
若以不配置应力缓和层的情况下的热应力为基准时的应力变化率的绝对值为2％以上，则HBT的寿命进一步延长。但是，在应力变化率的绝对值为2％以上的范围内，寿命的延长方式是平缓的。例如，在应力变化率为-28％的情况下，HBT的寿命的延长最高为41倍。根据这些评价实验可以认为，为了实现HBT的长寿命化，优选与不配置应力缓和层的情况相比，使在本征发射极层26A产生的热应力降低2％以上。
根据图7、图9以及图10所示的仿真结果可以认为，为了实现HBT的长寿命化，通过将使用Ta、Mo、Cr或W作为高熔点金属的应力缓和层的厚度设为100nm以上，从而能够确保充分的寿命。此外，即使在使用由包含这些高熔点金属的合金或化合物构成的应力缓和层的情况下，也可以认为，通过将应力缓和层的厚度设为100nm以上，能够确保充分的寿命。
可以认为，通过将使用Ti作为高熔点金属的应力缓和层的厚度设为300nm以上，从而能够确保充分的寿命。此外，即使在使用由包含Ti的合金或化合物构成的应力缓和层的情况下，也可以认为，通过将应力缓和层的厚度设为300nm以上，能够确保充分的寿命。
在应力缓和层包含从Ta、Mo、Cr以及W中选择的一种高熔点金属和Ti的情况下，只要将应力缓和层的厚度设为100nm以上即可。例如，在应力缓和层使用TiW合金的情况下，将其厚度设为100nm以上即可，在使用TiAl合金的情况下，将其厚度设为300nm以上即可。
从电阻的观点出发，并不优选将应力缓和层设得过厚。决定HBT的性能的发射极电阻的实际使用上的值是每100μm2发射极面积为0.1Ω左右。应力缓和层的电阻值优选比该发射极电阻的实际使用上的值小一位以上。即，优选设为0.01Ω以下。用于应力缓和层的Ti、Ta、Mo、Cr、W等的电阻率大致为10-7Ωm的量级。若假定应力缓和层在与发射极面积相同程度的开口与发射极电极相接，则为了将应力缓和层的电阻设为0.01Ω以下，优选将应力缓和层的厚度设为例如10μm以下。
[第五实施例]
接着，参照图11以及图12，对第五实施例的半导体元件进行说明。以下，对于与第一实施例的半导体元件共同的结构省略说明。第一实施例的半导体元件包含双极晶体管，但第五实施例的半导体元件取代双极晶体管而包含场效应晶体管(FET)。
图11是第五实施例的半导体元件的俯视图。定义如下的xyz正交坐标系，即：将基板的上表面设为xy面，将上表面的法线方向设为z轴的正方向。在x轴方向上排列有多个单位晶体管21。通过多个单位晶体管21并联连接，从而构成了一个场效应晶体管。在图11中，示出了配置有四个单位晶体管21的例子。各单位晶体管21为MESFET。
各单位晶体管21包含栅极电极G0、源极电极S0以及漏极电极D0。在图11中，对栅极电极G0、源极电极S0以及漏极电极D0标注了阴影线。在x轴方向上较长的长方形的活性区域50与在y轴方向上较长的四个栅极电极G0的每一个交叉。多个栅极电极G0在活性区域50的外侧相互连结。例如，在图11中，左侧的两个栅极电极G0相互连结，右侧的两个栅极电极G0相互连结。所有的栅极电极G0与第一层的栅极布线G1电连接。
在栅极电极G0各自的一侧配置有漏极电极D0，在另一侧配置有源极电极S0。彼此相邻的单位晶体管21共用一个源极电极S0或一个漏极电极D0。在图11中，示出了配置有两个源极电极S0以及三个漏极电极D0的例子。
梳齿型的第一层的漏极布线D1的梳齿部分配置为分别与三个漏极电极D0重叠，并与漏极电极D0电连接。第一层的漏极布线D1的多个梳齿部分在活性区域50的外侧相互连结。
第一层的源极布线S1配置为与源极电极S0重叠。源极布线S1由与源极电极S0分别对应配置的多个导体图案构成。构成第一层的源极布线S1的多个导体图案通过凸点30而相互电连接。
活性区域50与栅极电极G0重叠的部分是在FET的动作中控制漏极电流的部分。在本说明书中，将活性区域50与栅极电极G0重叠的部分称为动作区域60。多个动作区域60配置在俯视下凸点30的内侧。
图12是图11的单点划线12-12处的剖视图。在由半绝缘性的GaAs构成的基板51之上外延生长有由n型GaAs构成的沟道层52。沟道层52的一部分区域通过离子注入技术被绝缘化而成为隔离区域52a。通过隔离区域52a来划定活性区域50。
两个源极电极S0、四个栅极电极G0以及三个漏极电极D0配置为与沟道层52相接。绝缘膜55配置为覆盖这些电极。绝缘膜55例如具有由SiN膜构成的单层构造、或由SiN膜和聚酰亚胺膜构成的两层构造。
在绝缘膜55之上配置有第一层的漏极布线D1以及源极布线S1。第一层的漏极布线D1经由设置于绝缘膜55的开口与漏极电极D0电连接。第一层的源极布线S1经由设置于绝缘膜55的开口与源极电极S0电连接。在绝缘膜55之上，还配置有第一层的栅极布线G1(图11)。第一层的漏极布线D1、源极布线S1以及栅极布线G1例如具有厚度50nm的Ti膜与配置于其上的厚度1μm的Au膜的两层构造。
在绝缘膜55之上配置有上层的绝缘膜56，使得覆盖这些第一层的布线。绝缘膜56例如具有由SiN膜构成的单层构造、或由SiN膜和聚酰亚胺膜构成的两层构造。
在绝缘膜56之上配置有凸点30。凸点30与第一实施例的半导体元件的凸点30(图2)同样地，具有由金属柱32以及焊料层33构成的两层构造。作为凸点30的基底层，配置有凸点下金属层31。凸点下金属层31与第一实施例的半导体元件的情况同样地作为应力缓和层而发挥功能。
接着，对通过采用第五实施例的半导体元件的结构而得到的优异的效果进行说明。
若在FET的正上方配置有凸点，则由于凸点材料与半导体材料的热膨胀率的差异，在FET的半导体区域容易产生热应力。若在半导体区域特别是在动作区域60产生热应力，则容易引起FET的可靠性的下降、电气特性的偏差、特性不良等。特别是对于由GaAs等的化合物半导体构成的沟道层52来说，由于在栅极电极G0的附近产生的热应力而产生压电电荷。由于该压电电荷，而发生阈值电压的变动等，特性的偏差变大。
在第五实施例中，由于凸点下金属层31作为应力缓和层而发挥功能，因此能够抑制热应力所引起的特性的偏差、特性的不良、可靠性的下降等。
进而，由于通过凸点30将构成第一层的源极布线S1的多个导体图案相互电连接，因此不需要配置用于将这些导体图案进行连接的其他布线层。因此，能够减少布线层的层数，结果，能够实现制造成本的降低。
接着，参照图13，对第五实施例的变形例的半导体元件进行说明。在第五实施例中，使用了凸点下金属层31作为应力缓和层，但在本变形例中，与第三实施例的半导体元件的应力缓和层41(图8)同样地，在第一层的源极布线S1以及漏极布线D1之下，配置应力缓和层42。使源极布线S1以及漏极布线D1延伸到栅极电极G0的正上方，使得应力缓和层42配置于动作区域60的正上方。由此，能够使在动作区域60可能产生的应力降低。在配置应力缓和层42的情况下，也可以使凸点下金属层31不具有使应力缓和的功能。因此，与第五实施例的情况相比，也可以将凸点下金属层31设得较薄。
此外，也可以与第四实施例的半导体元件的作为应力缓和层而发挥功能的发射极电极E0(图6)同样地，由高熔点金属形成栅极电极G0，使其作为应力缓和层而发挥功能。此外，也可以将栅极电极G0的一部分设为由高熔点金属构成的层。
像这样，即使在第一层的布线层或栅极电极G0的一部分配置应力缓和层，也能够与第五实施例同样地使在动作区域60产生的热应力降低。
不言而喻，上述的各实施例为例示，能够进行在不同的实施例中示出的结构的部分置换或组合。关于多个实施例的相同的结构所带来的同样的作用效果，没有按每个实施例依次提及。进而，本发明并不限定于上述的实施例。例如，对于本领域技术人员来说，能够进行各种变更、改良、组合等是显而易见的。

Claims (10)

1.一种半导体元件，具有：
晶体管，其包含设置于基板的半导体区域以及三种端子电极，至少一个所述端子电极具有由多个导体图案构成的分离电极构造；
凸点，其配置在具有所述分离电极构造的所述端子电极之上，并将多个所述导体图案相互电连接；和
应力缓和层，其配置在所述晶体管的半导体区域与所述凸点之间，由包含高熔点金属的金属材料构成，
在所述导体图案与所述凸点之间，没有配置将多个所述导体图案相互连接的电流路径。
2.根据权利要求1所述的半导体元件，其中，
所述应力缓和层包含从由W、Mo、Ta以及Cr构成的组中选择的至少一种高熔点金属，并且所述应力缓和层的厚度为100nm以上。
3.根据权利要求1所述的半导体元件，其中，
所述应力缓和层包含Ti作为高熔点金属，并且所述应力缓和层的厚度为300nm以上。
4.根据权利要求1至3中的任一项所述的半导体元件，其中，
所述应力缓和层形成为所述凸点的基底层，并且具有与所述凸点的平面形状相同的平面形状。
5.根据权利要求1至3中的任一项所述的半导体元件，其中，
所述应力缓和层构成具有所述分离电极构造的所述端子电极的一部分。
6.根据权利要求1至5中的任一项所述的半导体元件，其中，
所述半导体元件还具有配置在所述端子电极与所述凸点之间的一个布线层，
所述凸点以及所述导体图案与所述布线层中包含的布线不经由其他布线层而连接。
7.根据权利要求1至6中的任一项所述的半导体元件，其中，
所述晶体管是包含集电极层、基极层、发射极层的双极晶体管，
三个所述端子电极包含分别与所述集电极层、所述基极层以及所述发射极层连接的集电极电极、基极电极以及发射极电极。
8.根据权利要求7所述的半导体元件，其中，
在俯视下，在所述凸点的内侧配置有所述发射极层。
9.根据权利要求1至6中的任一项所述的半导体元件，其中，
所述晶体管是包含划定在所述基板的表层部的活性区域的场效应晶体管，
三个所述端子电极包含分别配置于所述活性区域之上的源极电极、漏极电极以及栅极电极。
10.根据权利要求9所述的半导体元件，其中，
在俯视下，所述栅极电极与所述活性区域重叠的区域配置在所述凸点的内侧。
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