CN105849873A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN105849873A
CN105849873A CN201480070604.1A CN201480070604A CN105849873A CN 105849873 A CN105849873 A CN 105849873A CN 201480070604 A CN201480070604 A CN 201480070604A CN 105849873 A CN105849873 A CN 105849873A
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China
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mentioned
layer
emitter layer
opening
emitter
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CN201480070604.1A
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CN105849873B (zh
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梅本康成
德田大辅
西明恒和
德矢浩章
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本发明涉及半导体装置。在具备双极晶体管BT的半导体装置中，柱状凸点(20)和与发射极层(5)电连接的第二布线(14)接触的第三开口(16)从与发射极层(5)的正上对应的位置向发射极层(5)的长边方向偏移，第三开口(16)相对于发射极层(5)，被配置成发射极层(5)的长边方向的端部与第三开口(16)的开口端几乎一致。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别是，涉及具备异质结型的双极晶体管的半导体装置。
背景技术
近年，作为构成移动终端机等功率放大器模块的晶体管，应用异质结型的双极晶体管。这种双极晶体管被称为HBT(Hetero junctionBipolar Transistor：异质结双极晶体管)。
这里，对具备那样的双极晶体管的半导体装置的一个例子进行说明。如图27、图28以及图29所示，在双极晶体管中，子集电极层102形成为与半绝缘性GaAs基板101接触，集电极层103形成为与该子集电极层102接触。基极层104形成为与集电极层103接触，发射极层105形成为与该基极层104接触。
发射极电极106形成为与发射极层105接触。基极电极107形成为与基极层104接触。集电极电极108形成为与子集电极层102接触。第一绝缘膜109形成为覆盖发射极电极106、基极电极107以及集电极电极108等。
第一布线111a、111b、111c形成为与第一绝缘膜接触。经由形成于第一绝缘膜109的第一开口110，第一布线111a与发射极电极106电连接，第一布线111b与基极电极107电连接，第一布线111c与集电极电极108电连接。第二绝缘膜112形成为覆盖第一布线111a、111b、111c。
第二布线114形成为与第二绝缘膜接触。第二布线114经由形成于第二绝缘膜112的第二开口113，与发射极电极106电连接。钝化膜115形成为覆盖第二布线114。
柱状凸点120形成为与钝化膜115接触。柱状凸点120是凸点下金属117、金属桩118以及焊锡119的层叠结构。柱状凸点120经由形成于钝化膜115的第三开口116与第二布线114电连接。第三开口116形成为双极晶体管的整体位于第三开口116的区域内。以往的双极晶体管如上述那样构成。
在具备以往的双极晶体管的半导体装置中，双极晶体管的整体配置在第三开口116的区域内，所以柱状凸点120经由发射极电极106、第一布线111a以及第二布线114位于发射极层105的正上。
由此，柱状凸点120配置在双极晶体管中成为发热源的发射极层105的正下的集电极层103等的正上，从发射极层105的正下的集电极层103等到柱状凸点120的距离几乎成为最短距离，能够减小热电阻。其结果，使在双极晶体管中产生的热量有效地散热到柱状凸点120，能够抑制双极晶体管的接合温度的上升。
此外，作为公开了作为凸点，在双极晶体管的正上配置钉头凸点的半导体装置的文献的一个例子，有日本特开2003－77930号公报(专利文献1)。
专利文献1：日本特开2003－77930号公报
如上述那样，在以往的双极晶体管中，通过在发射极层105的正上配置柱状凸点120，能够减小热电阻。然而，在该结构中，由发明者们确认在通过在高温下对双极晶体管进行通电来评价长期可靠性时产生问题。
即，判明了在发射极层等内产生起因于发射极层等(GaAs层)的热膨胀率(热膨胀系数)与柱状凸点的热膨胀率(热膨胀系数)之差的热应力，由于该热应力，双极晶体管的电流放大率在极短时间内降低。
例如，作为连接柱状凸点的结构，在将双极晶体管面朝下安装于PCB(Printed Circuit Board：印刷线路板)基板等安装基板的结构中，若在温度150℃以上的环境下流通20～50kA/cm2的电流，则双极晶体管的电流放大率在极短的时间内劣化。
具体而言，在面朝下安装的结构中，与通过通常的引线键合实现不具有柱状凸点的双极晶体管与外部的电连接的面朝上安装的结构比较，在相同的条件下进行了环境试验的情况下，可靠性寿命从1/10缩短到1/100。
发明内容
本发明是为了解决上述问题点而提出的，其目的在于提供具备能够抑制热电阻的增大，并且缓和热应力的双极晶体管的半导体装置。
本发明所涉及的半导体装置是具备异质结型的双极晶体管的半导体装置，双极晶体管具备集电极层、基极层、发射极层、发射极布线、钝化膜以及凸点。基极层形成在集电极层上。发射极层形成在基极层上。发射极布线与发射极层电连接。钝化膜被形成为覆盖发射极布线，且具有使发射极布线露出的开口。凸点在钝化膜上被形成为填埋开口，并经由发射极布线而与发射极层电连接。开口相对于发射极层配置第一配置和第二配置之间的位置，上述第一配置为俯视时发射极层与开口内的区域重合的面积的相对于发射极层的面积的重合比例小于1/2，上述第二配置为相对于上述第一配置向远离发射极层的方向偏移且发射极层的端部位于凸点与钝化膜在俯视时重合的区域。
根据本发明所涉及的半导体装置，开口相对于发射极层配置在重合比例小于1/2的第一配置与发射极层的端部位于凸点与钝化膜在俯视时重合的区域的第二配置之间的位置。由此，能够抑制热电阻的增大并且缓和热应力。
优选开口相对于发射极层配置在重合比例小于1/4的第三配置与第二配置之间的位置。
由此，能够有效地缓和热应力。
优选作为具体的配置，发射极层具有具有宽度地延伸，凸点相对于发射极层，被配置成凸点的重心俯视时位于从发射极层的重心向发射极层延伸的长边方向远离的位置。
另外，优选发射极布线被形成为覆盖发射极层的整体。
由此，能够有助于热电阻的减少。
并且，优选具备再布线，上述再布线与位于开口的发射极布线电连接且形成在钝化膜上。
由此，能够提高与再布线连接的垫片等的配置的自由度。
本发明所涉及的其它的半导体装置是具备异质结型的双极晶体管的半导体装置，双极晶体管具备集电极层、基极层、发射极层、发射极布线、再布线、绝缘膜以及凸点。基极层形成在集电极层上。发射极层形成在基极层上。发射极布线与发射极层电连接。再布线与发射极布线连接。绝缘膜被形成为覆盖再布线，且具有使发射极布线露出的开口。凸点在绝缘膜上被形成为填埋开口，并经由发射极布线而与发射极层电连接。开口相对于发射极层，配置在第一配置和第二配置之间的位置，上述第一配置为俯视时发射极层与开口内的区域重合的面积的相对于发射极层的面积的重合比例小于1/2，上述第二配置为相对于上述第一配置向远离发射极层的方向偏移且发射极层的端部位于凸点与绝缘膜在俯视时重合的区域。
根据本发明所涉及的其它的半导体装置，开口相对于发射极层，配置在重合比例小于1/2的第一配置与发射极层的端部位于凸点与绝缘膜在俯视时重合的区域的第二配置之间的位置。由此，能够抑制热电阻的增大并且缓和热应力。
优选作为凸点的具体的种类，凸点包括柱状凸点。
优选此时，柱状凸点至少包括与发射极布线连接的金属层、被形成为与金属层接触的金属桩、以及被形成为与金属桩接触的焊锡。
并且，优选具备安装双极晶体管的安装基板，凸点与安装基板连接。
由此，能够缓和起因于双极晶体管的热膨胀率与安装基板的热膨胀率之差的热应力。
附图说明
图1是本发明的实施方式1所涉及的半导体装置的俯视图。
图2是上述实施方式中，图1所示的剖面线II－II上的剖视图。
图3是上述实施方式中，图1所示的剖面线III－III上的剖视图。
图4是上述实施方式中，图1所示的剖面线IV－IV上的剖视图。
图5是表示上述实施方式中，相对于双极晶体管的柱状凸点的配置与热应力的关系的图表。
图6是示意地表示上述实施方式中，发射极层与第三开口的配置关系的第一俯视图。
图7是示意地表示上述实施方式中，发射极层与第三开口的配置关系的第二俯视图。
图8是示意地表示上述实施方式中，发射极层与第三开口的配置关系的第三俯视图。
图9是上述实施方式中，发射极层与第三开口的配置关系的第四俯视图。
图10是上述实施方式中，变形例所涉及的半导体装置的俯视图。
图11是上述实施方式中，图10所示的剖面线XI－XI上的剖视图。
图12是表示上述实施方式中，半导体装置的制造方法的一工序的剖视图。
图13是表示上述实施方式中，在图12所示的工序之后进行的工序的剖视图。
图14是表示上述实施方式中，在图13所示的工序之后进行的工序的剖视图。
图15是表示上述实施方式中，在图14所示的工序之后进行的工序的剖视图。
图16是表示上述实施方式中，在图15所示的工序之后进行的工序的剖视图。
图17是表示上述实施方式中，在图16所示的工序之后进行的工序的剖视图。
图18是表示上述实施方式中，在图17所示的工序之后进行的工序的剖视图。
图19是表示上述实施方式中，在图18所示的工序之后进行的工序的剖视图。
图20是表示上述实施方式中，在图19所示的工序之后进行的工序的剖视图。
图21是表示上述实施方式中，在图20所示的工序之后进行的工序的剖视图。
图22是表示上述实施方式中，在图21所示的工序之后进行的工序的剖视图。
图23是表示上述实施方式中，在图22所示的工序之后进行的工序的剖视图。
图24是本发明的实施方式2所涉及的半导体装置的剖视图。
图25是本发明的实施方式3所涉及的半导体装置的剖视图。
图26是本发明的实施方式4所涉及的半导体装置的剖视图。
图27是以往的半导体装置的俯视图。
图28是图27所示的剖面线XXVIII－XXVIII上的剖视图。
图29是图27所示的剖面线XXIX－XXIX上的剖视图。
具体实施方式
实施方式1
这里，对具备异质结型双极晶体管的半导体装置的第一例进行说明。
如图1、图2、图3以及图4所示，在具备双极晶体管BT的半导体装置中，子集电极层2(n型GaAs，Si浓度：5×1018cm-3，膜厚：0.6μm)形成为与半绝缘性GaAs基板1的表面接触。形成集电极层3(n型GaAs，Si浓度：5×1015cm-3，膜厚：1.0μm)形成为与子集电极层2接触。基极层4(p型GaAs，C浓度：4×1019cm-3，膜厚：100nm)形成为与集电极层3接触。
台面形状的发射极层5形成为与基极层4接触。发射极层5是从基极层4侧，依次层叠n型InxGa1－xP层(In组成比x＝0.5，Si浓度：3×1017cm-3，膜厚：30nm)、n型GaAs层(Si浓度：3×1017cm-3，膜厚：90nm)、n型GaAs接触层(Si浓度：1×1019cm-3，膜厚：50nm)、以及n型InxGa1－xAs接触层(In组成比x＝0.5，Si浓度：1×1019cm-3，膜厚：50nm)的结构。
发射极电极6形成为与发射极层5接触。集电极电极8形成为与子集电极层2接触。基极电极7形成为与基极层4接触。发射极电极6由WSi膜(Si摩尔比：0.3，膜厚：0.3μm)形成。基极电极7通过层叠Ti膜(膜厚：50nm)/Pt膜(膜厚：50nm)/Au膜(膜厚：200nm)形成。集电极电极8通过层叠AuGe膜(膜厚：60nm)/Ni膜(膜厚：10nm)/Au膜(膜厚：200nm)形成。
第一绝缘膜9(SiN，膜厚：50nm)形成为覆盖发射极电极6、基极电极7以及集电极电极8。在第一绝缘膜9形成有使发射极电极6等露出的第一开口10。经由第一开口10，与发射极电极6电连接的第一布线11a、与基极电极7电连接的第一布线11b、以及与集电极电极8电连接的第一布线11c分别形成为与第一绝缘膜9接触。第一布线11a、11b、11c例如由金膜(Au，膜厚：1μm)形成。
第二绝缘膜12(SiN，膜厚：100nm)形成为覆盖第一布线11a、11b、11c。在第二绝缘膜12形成使第一布线11a露出的第二开口13。经由第二开口13与第一布线11a电连接的第二布线14(Au，膜厚：4μm)形成为与第二绝缘膜12接触。如图1所示，第二布线14形成为覆盖包括集电极层3、基极层4以及发射极层5的双极晶体管的整体。
钝化膜15(SiN，膜厚：500nm)形成为覆盖第二布线14。在钝化膜15中的规定的区域形成使第二布线14露出的第三开口16。柱状凸点20形成为填埋该第三开口16，并且与沿第三开口16的开口端进行配置的钝化膜15接触。如图3以及图4所示，柱状凸点20是UBM(UnderBump Metal：凸点下金属)17(Ti，膜厚：150nm)、金属桩18(Cu，膜厚：50μm)以及焊锡19(Sn，膜厚：30μm)的层叠结构。此外，也可以在金属桩18与焊锡19之间，例如，形成Ni等的相互扩散防止用的阻挡金属层。
这里，对柱状凸点20、第三开口16、以及双极晶体管(发射极层5)的配置关系进行详细说明。
如图1所示，发射极层5为矩形的发射极。若将长边方向设为X方向，将与长边方向正交的方向设为Y方向，则发射极层5的Y方向的长度(宽度)设定为4μm，X方向(长边方向)的长度设定为28μm。柱状凸点20的X方向的长度PX设定为75μm，Y方向的长度PY设定为75μm～500μm左右。第三开口16的X方向的长度KX设定为55μm。并且如图3所示，第三开口16相对于发射极层5配置为发射极层5的长边方向的端部与第三开口16的开口端几乎一致。
在上述的具备双极晶体管的半导体装置中，柱状凸点20和与发射极层5电连接的第二布线14接触的第三开口16配置在从与发射极层5的正上对应的位置，向发射极层5的长边方向偏移的位置。由此，能够使作用给双极晶体管的热应力缓和。对此进行说明。
由发明者们确认热应力起因于发射极层5等(GaAs层)的热膨胀率与柱状凸点20的热膨胀率之差。通过模拟评价热应力与相对于双极晶体管BT的柱状凸点20(第三开口16)的配置的关系的图表如图5所示。横轴表示以发射极层的中心(长边方向与宽度方向的中央)为原点，沿发射极层的长边方向的位置。纵轴表示发射极层中的热应力。发射极层的长度设定为30μm。另外，将相对于发射极层的俯视时的面积的、发射极层与第三开口的俯视时的重合的面积的比例设为重合比例。
如图5所示，首先，作为比较例，在如图27等所示的以往的半导体装置那样，重合比例为100％的情况下，明确在发射极层的区域内，热应力示出几乎恒定的分布。若从该状态，使第三开口(柱状凸点)向X方向(正)偏移，逐渐减小重合比例，则明确从第三开口所在的一侧的发射极层的部分(部分A)向与第三开口所在的一侧相反的一侧的发射极层的部分(部分B)，发射极层的热应力示出逐渐减少的趋势。
即，明确若减小重合比例，则在发射极层中，朝向X方向(负)，热应力示出逐渐减少的趋势。并且，明确发射极层的部分A的热应力也减少，在重合比例为7％左右时，与比较例的情况相比，热应力大约减少12％。
根据发明者们的评价，判明了即使在发射极层与第三开口在俯视时重合，在其重合比例为比1/2(50％)低的值时，也能够使发射极层的端部的热应力减少，若重合比例是比1/4(25％)低的值，则能够更有效地减少热应力。换言之，判明了为了减少热应力，发射极层与第三开口俯视时不重合并不是必需的结构，而只要发射极层与第三开口俯视时重合面积较小即可。
这考虑是因为能够在发射极层5的正上形成未配置柱状凸点20的区域，而且，即使在发射极层5的正上配置柱状凸点20，也能够形成发射极层5等被夹在与柱状凸点20之间的钝化膜15覆盖的区域，从而能够缓和发射极层5等的热应力。
并且，明确在重合比例为0％时，与比较例的情况相比，热应力减少大约22％。根据发明者们的评价，判明了在重合比例为0％的情况下，若发射极层的端部位于柱状凸点与钝化层俯视时重合的区域，则能够减少发射极层的应力。换言之，判明了为了减少热应力，发射极层与柱状凸点在俯视时不重合并不是必需的结构，而通过在发射极层5与柱状凸点20之间夹入钝化膜15能够减少热应力。
即，考虑通过在发射极层5等与柱状凸点20俯视时重合的区域夹入钝化膜，能够缓和发射极层5等的热应力。
然而，通过使第三开口(柱状凸点)从发射极层5向X方向(正)偏移，虽然能够使热应力减少，但另一方面从发射极层5等到柱状凸点20的距离变长，使在发射极层5的正下的集电极层3等产生的热量传导到柱状凸点20时的热电阻增大。因此，对热电阻进行研究。
在发射极层与柱状凸点俯视时不重合的配置中，使在发射极层5的正下的集电极层3等产生的热量传导到柱状凸点20时的热电阻急剧地增大。例如，若发射极层的长边方向的端部与第三开口的端部的距离为18μm，则热电阻急剧地增大到以往的情况的大约2.6倍。并且，若距离比18μm长，则热电阻迅速地与距离的增量成比例以上地增大。
另一方面，在重合比例比1/2(50％)低的情况下，由于从发射极层5的正下的集电极层3等到柱状凸点20的第三开口16的端部的距离变短，所以避免其间的热电阻的增大。例如，在发射极层与第三开口的重合比例为7％左右时，热电阻停留在以往的情况下的1.5倍左右，成为比较缓慢的增大。
另外，在本实施方式1中，作为柱状凸点20电连接的布线示出了第二布线14，但该第二布线14的膜厚为4μm，所以与将厚度1μm的第一布线11a作为电连接的布线使用相比，该区域的部分的热电阻较小，有利于使整个热电阻减少。
发明者们研究了该热应力与热电阻两个参数的结果，得到以下那样的知识。首先，如图6所示，将发射极层5与第三开口16的重合比例为1/2(50％)的配置设为配置A，如图7所示，将重合比例为1/4(25％)的配置设为配置B。另外，如图8所示，将重合比例为0，发射极层的长边方向的端部与第三开口的开口端一致的配置设为配置C。而且，如图9所示，将重合比例为0，发射极层5的长边方向的端部位于柱状凸点20与钝化膜15俯视时重合的区域的配置设为配置D。
这样一来，发明者们发现为了抑制热电阻的增大并且使热应力缓和，期望第三开口16相对于发射极层5，配置在配置A与配置D之间的位置，为了更有效地减少热应力，期望第三开口16相对于发射极层5，配置在配置B与配置D之间的位置。
上述的图1～图4所示的双极晶体管与配置C对应。另外，重合比例为7％的情况下的双极晶体管如图10以及图11所示。图10以及图11所示的双极晶体管除了重合比例不同以外，与图1～图4所示的双极晶体管相同，所以在同一部件附加同一附图标记并且不重复其说明。
在上述的双极晶体管中，通过缓和发射极层5等的热应力，在通过在高温下进行通电来评价长期可靠性时，能够防止双极晶体管的电流放大率在短时间降低，能够使具备双极晶体管的半导体装置的可靠性提高。
另外，第三开口16配置在从与发射极层5的正上对应的位置向发射极层5的长边方向偏移的位置，从而双极晶体管的专有面积与比较例的情况相比增大。在上述的半导体装置中，通过确定相对于发射极层5使第三开口16配置的范围，能够将专有面积的增大抑制到需要最小限度。
接下来，作为具备双极晶体管的半导体装置的制造方法，对图1等所示的半导体装置的制造方法的一个例子进行说明。
首先，在半绝缘性GaAs基板的表面上，分别通过有机金属气相生长法(MOCVD：Metal Organic Chemical Vapor Deposition：金属有机化合物化学气相沉积)法等外延生长法形成成为子集电极层、集电极层、基极层、发射极层等的规定的层。
如图12所示，在半绝缘性GaAs基板1上，形成成为子集电极层的n型GaAs层2a(Si浓度：5×1018cm-3，膜厚：0.6μm)。成为集电极层的n型GaAs层3a(Si浓度：5×1016cm-3，膜厚：1.0μm)形成为与n型GaAs层2a接触。成为基极层的p型GaAs层4a(C浓度：4×1019cm-3，膜厚：50nm)形成为与n型GaAs层3a接触。
接下来，成为发射极层的外延层5a形成为与p型GaAs层4a接触。作为外延层5a，依次层叠n型InxGa1－xP层(In组成比x＝0.5，Si浓度：3×1017cm-3，膜厚：30nm)、n型GaAs层(Si浓度：3×1017cm-3，膜厚：90nm)、n型GaAs接触层(Si浓度：1×1019cm-3，膜厚：50nm)、以及n型InxGa1－xAs接触层(In组成比x＝0.5，Si浓度：1×1019cm-3，膜厚：50nm)。
接下来，使用高频溅射法在外延层5a上的整个面堆积钨硅化物(WSi)膜(Si摩尔比：0.3，膜厚：0.3μm)。接下来，通过实施规定的光刻处理、和通过规定的气体的干式蚀刻处理，如图13所示，形成发射极电极6。
接下来，通过实施规定的光刻处理、和通过规定的药液的湿式蚀刻处理，如图14所示，发射极层5图案化为所希望的形状。接下来，将基极电极7形成为与p型GaAs层4a接触。接下来，通过实施规定的光刻处理、和通过规定的药液的湿式蚀刻处理，如图15所示，形成基极层4以及集电极层3。
接下来，将集电极电极8(参照图2)形成为与子集电极层2接触。接下来，通过实施规定的光刻处理、和通过规定的药液的湿式蚀刻处理，子集电极层2图案化为所希望的形状。
接下来，例如，将由氮化硅膜构成的第一绝缘膜9(参照图16)覆盖发射极电极6等。接下来，通过实施规定的光刻处理、和规定的干式蚀刻处理，如图16所示，在第一绝缘膜9形成使发射极电极6露出的第一开口10、和使基极电极7露出的开口。
接下来，将成为第一布线的金膜(未图示)形成为填埋第一开口10等。接下来，通过实施规定的光刻处理、和规定的蚀刻处理，如图17所示，形成与发射极电极6电连接的第一布线11a以及与基极电极7电连接的第一布线11b等。
接下来，例如，将由氮化硅膜构成的第二绝缘膜12(参照图18)形成为覆盖第一布线11a、11b等。接下来，通过实施规定的光刻处理、和规定的干式蚀刻处理，如图18所示，在第二绝缘膜12形成使第一布线11a露出的第二开口13。
接下来，将成为第二布线的金膜(未图示)形成为填埋第二开口13。接下来，通过实施规定的光刻处理、和规定的蚀刻处理，如图19所示，形成与第一布线11a电连接的第二布线14。如图1所示，第二布线14形成为覆盖包括发射极层的双极晶体管的整体。
接下来，例如，将由氮化硅膜构成的钝化膜(未图示)形成为覆盖第二布线14。接下来，通过实施规定的光刻处理、和规定的蚀刻处理，如图20所示，形成使第二布线14露出的第三开口16。如图20以及图1所示，第三开口16相对于发射极层5，形成为发射极层5的长边方向的端部与第三开口16的开口端几乎一致。
接下来，如图21所示，形成成为UBM的钛(Ti)膜17a。接下来，如图22所示，在规定的区域，层叠由铜(Cu)膜构成的金属桩18和焊锡19，以便与钛膜17a接触。接下来，通过除去露出的钛膜17a，如图23所示，形成由UBM17、金属桩18以及焊锡19的层叠结构构成的柱状凸点20。如图1所示，柱状凸点20形成填埋第三开口16，并且沿第三开口16的开口端，覆盖钝化膜15。由此，形成具备双极晶体管BT的半导体装置的主要部分。
在上述的半导体装置的制造方法中，成为发射极层5与第三开口16俯视时重合的重合比例为0，发射极层5的长边方向的端部与第三开口16的开口端几乎一致的配置(配置C)。由此，如已经说明的那样，能够抑制热电阻的增大并且有效地缓和热应力，能够使具备双极晶体管的半导体装置的可靠性提高。另外，能够将双极晶体管的专有面积抑制到需要最小限度。
实施方式2
这里，作为具备异质结型的双极晶体管的半导体装置的第二例，对形成再布线的半导体装置进行说明。
如图24所示，例如，将由聚酰亚胺膜等构成的第三绝缘膜21(膜厚：10μm)形成为覆盖钝化膜15。在该第三绝缘膜21以及钝化膜15，形成使第二布线14露出的第三开口16。第三开口16相对于发射极层5，配置为发射极层5的长边方向的端部与第三开口16的开口端几乎一致(配置C)。
作为再布线形成由铜(Cu)膜构成的第三布线23(膜厚：5μm)，以便与在该第三开口16的底露出的第二布线14接触，并且与沿第三开口16的开口端进行配置的第三绝缘膜21接触。另外，与第三绝缘膜21接触地，形成使第三布线23露出的由聚酰亚胺膜构成的第四绝缘膜22(膜厚：3μm)。柱状凸点20形成为与第三布线23接触，并且与第四绝缘膜22接触。
此外，其以外的构成与在实施方式1中说明的图1～图4所示的半导体装置相同，所以对同一部件附加同一符号，除了需要的情况之外不重复其说明。
在上述的半导体装置中，配置为发射极层5与第三开口16的重合比例为0，发射极层5的长边方向的端部与第三开口16的开口端一致(配置C)。由此，如在实施方式1中说明的那样，能够抑制热电阻的增大并且有效地缓和热应力。
另外，在形成作为再布线的第三布线23的双极晶体管中，在第二布线14与柱状凸点20之间，除了钝化膜15之外，还夹有第三绝缘膜21和第四绝缘膜22。由此，能够进一步有效地缓和热应力，在通过在高温下进行通电来评价长期可靠性时，能够避免寿命(电流放大率)劣化。
另外，第二布线14形成为覆盖发射极层5的整体也能够有助于热电阻的减少。
另外，通过在形成钝化膜15之后，形成第三布线23，能够提高与第三布线23电连接的垫片等的配置的自由度。即，能够在电阻、电容元件等其它的元件上配置凸点，所以能够减小芯片尺寸。另外，若使再布线的膜厚足够厚，则能够形成具有较高的Q值的低损耗的螺旋电感，能够使MMIC(Monolithic Microwave Integrated Circuit：单片微波集成电路)的性能提高。
此外，在上述的半导体装置中，例举发射极层5的长边方向的端部与第三开口16的开口端一致的配置C进行了说明。作为发射极层5与第三开口16的配置关系并不限定于配置C，为了抑制热电阻的增大并且缓和热应力，第三开口16相对于发射极层5，配置在配置A与配置D之间的位置即可，为了更有效地减少热应力，第三开口16相对于发射极层5，配置在配置B与配置D之间的位置即可。
实施方式3
这里，作为具备异质结型的双极晶体管的半导体装置的第三例，对实施方式2的变形例进行说明。
如图25所示，例如，将由聚酰亚胺膜等构成的第三绝缘膜21(膜厚：10μm)形成为覆盖钝化膜15。在该第三绝缘膜21以及钝化膜15形成使由铜(Cu)膜构成的第二布线14(膜厚：5μm)露出的第三开口16。
然后，作为再布线的第三布线23形成为与在第三开口16的底露出的第二布线14接触，并且与沿第三开口16的开口端进行配置的第三绝缘膜21接触。第三布线23经由位于发射极层5的正上的第二布线14的部分、第一布线11a的部分以及发射极电极6，以短距离与发射极层5电连接。
另外，例如，将由聚酰亚胺膜构成的第四绝缘膜22(膜厚：3μm)与第三绝缘膜21接触。在该第四绝缘膜22形成使第三布线23露出的第四开口24。柱状凸点20形成为与第三布线23接触，并且与第四绝缘膜22接触。第四开口24相对于发射极层5，配置为发射极层5的长边方向的端部与第四开口24的开口端几乎一致。
此外，其以外的构成与在实施方式1中说明的图1～图4所示的半导体装置相同，所以对同一部件附加同一符号，并在除了需要的情况下之外不重复其说明。
在上述的半导体装置中，配置为发射极层5与第四开口24的重合比例为0，发射极层5的长边方向的端部与第四开口24的开口端一致(配置C)。由此，如在实施方式1中说明的那样，能够抑制热电阻的增大并且有效地缓和热应力。
另外，在形成了作为再布线的第三布线23的双极晶体管中，在第二布线14与柱状凸点20之间，除了钝化膜15之外，还夹有第三绝缘膜21和第四绝缘膜22。由此，能够进一步有效地缓和热应力，在通过在高温下进行通电来评价长期可靠性时，能够避免寿命(电流放大率)劣化。
另外，与实施方式2的情况相比，在柱状凸点20与第三布线23接触的面与发射极层5之间，新夹有膜厚10μm的第三绝缘膜21。由此，与实施方式2的情况相比，能够进一步有效地缓和热应力。
并且，将第二布线14形成为覆盖发射极层5的整体也能够有助于热电阻的减少。
另外，通过在形成钝化膜15之后，形成第三布线23，能够提高与第三布线23电连接的垫片等的配置的自由度，特别是，能够在电阻、电容元件上配置垫片，所以能够缩小芯片尺寸。另外，若增大再布线的厚度，则能够形成具有较高的Q值的电感。
此外，在上述的半导体装置中，例举发射极层5的长边方向的端部与第四开口24的开口端一致的配置C进行了说明。作为发射极层5与第四开口24的配置关系并不限定于配置C，为了抑制热电阻的增大并且缓和热应力，第四开口24相对于发射极层5，配置在配置A与配置D之间的位置即可，为了更有效地减少热应力，第四开口24相对于发射极层5，配置在配置B与配置D之间的位置即可。
实施方式4
这里，对将形成了双极晶体管的基板安装在安装基板的半导体装置进行说明。
如图26所示，与发射极层5电连接的柱状凸点20与安装基板25连接。作为安装基板25，例如，应用氧化铝、陶瓷、PCB等。在安装基板25的表面配置有连接柱状凸点20的薄膜的金属布线26。包括发射极层5的双极晶体管与图1等所示的双极晶体管相同。
在双极晶体管安装于安装基板25的半导体装置中，假定起因于发射极层5等的热膨胀率与安装基板25的热膨胀率之差的热应力经由柱状凸点20在发射极层5等产生。
在上述的包括安装基板的半导体装置中，配置为发射极层5与第三开口16的重合比例为0，发射极层5的长边方向的端部与第三开口16的开口端一致(配置C)。由此，与在实施方式1中说明的相同，能够抑制热电阻的增大，并且有效地缓和起因于发射极层5等的热膨胀率与安装基板25的热膨胀率之差的热应力。
此外，在上述的半导体装置中，例举发射极层5的长边方向的端部与第三开口16的开口端一致的配置C进行了说明，但为了抑制热电阻的增大并且缓和热应力，第三开口16相对于发射极层5，配置在配置A与配置D之间的位置即可，为了进一步有效地减少热应力，第三开口16相对于发射极层5，配置在配置B与配置D之间的位置即可。
另外，在上述的各实施方式中，例举具备一个双极晶体管的半导体装置进行了说明，但也可以是在半绝缘性GaAs基板形成了多个双极晶体管的半导体装置。另外，作为凸点，例举柱状凸点进行了说明，但除了柱状凸点之外，例如，也可以是焊锡凸点、钉头凸点。
并且，在上述的各实施方式所涉及的双极晶体管中，例举发射极层5由InGaP层形成，基极层4由GaAs层形成的情况进行了说明。作为发射极层以及基极层的材料的组合(发射极层/基极层)，并不限定于InGaP层/GaAs层，例如，也可以是应用了AlGaAs层/GaAs层、InP层/InGaAs层、InGaP层/GaAsSb层、InGaP层/InGaAsN层、Si层/SiGe层、AlGaN层/GaN层等材料的异质结型的双极晶体管。
另外，在上述的各实施方式中，例举发射极层5的平面形状为矩形的情况进行了说明，但发射极层的平面形状也可以是圆形、椭圆形、六角形、或者八角形等。另外，在上述的各实施方式中，对第三开口16向发射极层5的长边方向的一方向偏移的情况进行了说明，但也可以是向相反的方向偏移的情况。
这次公开的实施方式是例示的实施方式而并不限定于此。本发明并不由上述说明的范围，而由权利要求书示出，包括与权利要求书均等的意味以及范围内的全部的变更。
本发明有效地利用于具备双极晶体管的半导体装置。
附图标记的说明：BT…异质结双极晶体管，1…半绝缘性GaAs基板，2…子集电极层，3…集电极层，4…基极层，5…发射极层，6…发射极电极，7…基极电极，8…集电极电极，9…第一绝缘膜，10…第一开口，11a…第一布线，11b…第一布线，11c…第一布线，12…第二绝缘膜，13…第二开口，14…第二布线，15…钝化膜，16…第三开口，17…UBM，18…金属桩，19…焊锡，20…柱状凸点，21…第三绝缘膜，22…第四绝缘膜，23…第三布线，24…第四开口，25…安装基板，26…金属布线，2a…n型GaAs层，3a…n型GaAs层，4a…p型GaAs层，5a…发射极外延层，7a…金属层。

Claims (9)

1.一种半导体装置，是具备异质结型的双极晶体管的半导体装置，
上述双极晶体管具备：
集电极层；
基极层，形成在上述集电极层上；
发射极层，形成在上述基极层上；
发射极布线，与上述发射极层电连接；
钝化膜，被形成为覆盖上述发射极布线，且具有使上述发射极布线露出的开口；以及
凸点，在上述钝化膜上被形成为填埋上述开口，并经由上述发射极布线而与上述发射极层电连接，
上述开口相对于上述发射极层配置在第一配置和第二配置之间的位置，上述第一配置为俯视时上述发射极层与上述开口内的区域重合的面积的相对于上述发射极层的面积的重合比例小于1/2，上述第二配置为相对于上述第一配置向远离上述发射极层的方向偏移且上述发射极层的端部位于上述凸点与上述钝化膜在俯视时重合的区域。
2.根据权利要求1所述的半导体装置，其中，
上述开口相对于上述发射极层配置在上述重合比例小于1/4的第三配置与上述第二配置之间的位置。
3.根据权利要求1或者2所述的半导体装置，其中，
上述发射极层具有宽度地延伸，
上述凸点相对于上述发射极层，被配置成上述凸点的重心在俯视时位于从上述发射极层的重心向上述发射极层延伸的长边方向远离的位置。
4.根据权利要求1～3中任一项所述的半导体装置，其中，
上述发射极布线被形成为覆盖上述发射极层的整体。
5.根据权利要求1～4中任一项所述的半导体装置，其中，
具备再布线，上述再布线与位于上述开口的上述发射极布线电连接且形成在上述钝化膜上。
6.一种半导体装置，是具备异质结型的双极晶体管的半导体装置，
上述双极晶体管具备：
集电极层；
基极层，形成在上述集电极层上；
发射极层，形成在上述基极层上；
发射极布线，与上述发射极层电连接；
再布线，与上述发射极布线连接；
绝缘膜，被形成为覆盖上述再布线，且具有使上述发射极布线露出的开口；以及
凸点，在上述绝缘膜上被形成为填埋上述开口，并经由上述发射极布线而与上述发射极层电连接，
上述开口相对于上述发射极层，配置在第一配置和第二配置之间的位置，上述第一配置为俯视时上述发射极层与上述开口内的区域重合的面积的相对于上述发射极层的面积的重合比例小于1/2，上述第二配置为相对于上述第一配置向远离上述发射极层的方向偏移且上述发射极层的端部位于上述凸点与上述绝缘膜在俯视时重合的区域。
7.根据权利要求1～6中任一项所述的半导体装置，其中，
上述凸点包括柱状凸点。
8.根据权利要求7所述的半导体装置，其中，
上述柱状凸点至少包括：
金属层，与上述发射极布线连接；
金属桩，被形成为与上述金属层接触；以及
焊锡，被形成为与上述金属桩接触。
9.根据权利要求1～8中任一项所述的半导体装置，其中，
具备安装上述双极晶体管的安装基板，
上述凸点与上述安装基板连接。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887911A (zh) * 2017-12-06 2019-06-14 株式会社村田制作所 半导体装置
CN109994430A (zh) * 2017-12-06 2019-07-09 株式会社村田制作所 半导体元件
CN110197849A (zh) * 2018-02-27 2019-09-03 株式会社村田制作所 半导体装置
CN110998807A (zh) * 2017-08-01 2020-04-10 株式会社村田制作所 半导体装置
CN111223920A (zh) * 2018-11-26 2020-06-02 株式会社村田制作所 半导体装置
CN111490022A (zh) * 2019-01-28 2020-08-04 株式会社村田制作所 半导体元件

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105849873B (zh) 2014-01-10 2019-01-11 株式会社村田制作所 半导体装置
JP2019075536A (ja) * 2017-10-11 2019-05-16 株式会社村田製作所 パワーアンプモジュール
US10734310B2 (en) 2017-12-06 2020-08-04 Murata Manufacturing Co., Ltd. Semiconductor apparatus
US10622465B2 (en) 2017-12-20 2020-04-14 Qualcomm Incorporated Heterojunction bipolar transistor (HBT)
TWI754997B (zh) * 2019-07-31 2022-02-11 日商村田製作所股份有限公司 半導體裝置及高頻模組
US11601102B2 (en) 2020-02-05 2023-03-07 Murata Manufacturing Co., Ltd. Power amplifier circuit and semiconductor device
JP2021197474A (ja) 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置
KR20220056309A (ko) * 2020-10-27 2022-05-06 삼성전자주식회사 반도체 패키지
JP2022091566A (ja) * 2020-12-09 2022-06-21 株式会社村田製作所 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864169A (en) * 1994-07-20 1999-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including plated heat sink and airbridge for heat dissipation
JPH11265895A (ja) * 1999-02-01 1999-09-28 Sharp Corp 半導体装置
US20040023463A1 (en) * 1999-08-19 2004-02-05 Sharp Kabushiki Kaisha Heterojunction bipolar transistor and method for fabricating the same
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2913077B2 (ja) * 1992-09-18 1999-06-28 シャープ株式会社 半導体装置
JPH0945692A (ja) * 1995-07-27 1997-02-14 Sharp Corp 縦型構造トランジスタ及びその製造方法、並びに半導体装置
US6051871A (en) * 1998-06-30 2000-04-18 The Whitaker Corporation Heterojunction bipolar transistor having improved heat dissipation
JP4303903B2 (ja) 2001-09-05 2009-07-29 株式会社東芝 半導体装置及びその製造方法
JP2005327805A (ja) * 2004-05-12 2005-11-24 Renesas Technology Corp 半導体装置およびその製造方法
JP2008004779A (ja) * 2006-06-23 2008-01-10 Matsushita Electric Ind Co Ltd 窒化物半導体バイポーラトランジスタ及び窒化物半導体バイポーラトランジスタの製造方法
JP2008227116A (ja) * 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置およびその製造方法
KR20100061608A (ko) * 2008-11-29 2010-06-08 한국전자통신연구원 이종 접합 바이폴라 트랜지스터 및 그 형성 방법
US8377788B2 (en) * 2010-11-15 2013-02-19 National Semiconductor Corporation SiGe heterojunction bipolar transistor and method of forming a SiGe heterojunction bipolar transistor
TWI540722B (zh) * 2013-04-17 2016-07-01 Win Semiconductors Corp 異質接面雙極電晶體佈局結構
CN105849873B (zh) * 2014-01-10 2019-01-11 株式会社村田制作所 半导体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864169A (en) * 1994-07-20 1999-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including plated heat sink and airbridge for heat dissipation
JPH11265895A (ja) * 1999-02-01 1999-09-28 Sharp Corp 半導体装置
US20040023463A1 (en) * 1999-08-19 2004-02-05 Sharp Kabushiki Kaisha Heterojunction bipolar transistor and method for fabricating the same
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110998807A (zh) * 2017-08-01 2020-04-10 株式会社村田制作所 半导体装置
CN110998807B (zh) * 2017-08-01 2023-12-01 株式会社村田制作所 半导体装置
CN109887911A (zh) * 2017-12-06 2019-06-14 株式会社村田制作所 半导体装置
CN109994430A (zh) * 2017-12-06 2019-07-09 株式会社村田制作所 半导体元件
CN109887911B (zh) * 2017-12-06 2023-08-25 株式会社村田制作所 半导体装置
CN110197849A (zh) * 2018-02-27 2019-09-03 株式会社村田制作所 半导体装置
CN111223920A (zh) * 2018-11-26 2020-06-02 株式会社村田制作所 半导体装置
CN111223920B (zh) * 2018-11-26 2024-01-09 株式会社村田制作所 半导体装置
CN111490022A (zh) * 2019-01-28 2020-08-04 株式会社村田制作所 半导体元件
CN111490022B (zh) * 2019-01-28 2023-09-22 株式会社村田制作所 半导体元件

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