CN111490022A - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN111490022A
CN111490022A CN202010066304.3A CN202010066304A CN111490022A CN 111490022 A CN111490022 A CN 111490022A CN 202010066304 A CN202010066304 A CN 202010066304A CN 111490022 A CN111490022 A CN 111490022A
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China
Prior art keywords
layer
metal layer
opening
emitter
film
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CN202010066304.3A
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CN111490022B (zh
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黑川敦
小林一也
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本发明提供能够在安装于外部基板时，抑制电连接不良的产生的半导体元件。半导体元件具有：半导体基板；设置在半导体基板上的集电极层；设置在集电极层上的基极层；设置在基极层上的发射极层；与发射极层电连接的发射极布线；设置在发射极布线上的上部金属层；覆盖发射极布线以及上部金属层并且至少在与集电极层重叠的区域中设置有第一开口的第一保护膜；以及经由第一开口与发射极布线电连接的下部凸块金属层，且下部凸块金属层的俯视时的面积大于第一开口的面积的凸块，第一保护膜的端部包围第一开口、且设置在上部金属层上。

Description

半导体元件
技术领域
本发明涉及半导体元件。
背景技术
在专利文献1中记载了具备异质结型的双极晶体管的半导体装置。半导体装置具有双极晶体管的发射极层、发射极布线、保护层以及带焊料的凸块。发射极布线与发射极层连接，保护层形成为覆盖发射极布线。在保护层的、与发射极层重叠的部分设置开口。凸块的下部凸块金属层(UBM，Under Bump Metal)设置在保护层上，并经由开口与发射极布线电连接。在专利文献1中公开了通过设置下部凸块金属层和保护层紧贴的区域能够抑制水分的侵入的构造。
专利文献1：国际公开第2015/104967号
然而，在专利文献1的半导体装置中，通过安装时的热处理等熔化焊料，焊料有时侵入到金属柱与下部凸块金属层的界面。沿着形成于保护膜的开口端的台阶部设置下部凸块金属层。因此，下部凸块金属层有时在开口端形成空隙或薄层部。侵入到下部凸块金属层的界面的焊料有可能通过形成在下部凸块金属层的空隙、薄层部侵入至发射极布线。其结果半导体装置的可靠性有可能降低。
发明内容
本发明的目的在于提供能够抑制焊料侵入到晶体管而提高可靠性的半导体元件。
本发明的一个方面的半导体元件具有：半导体基板；集电极层，设置在上述半导体基板上，基极层，设置在上述集电极层上；发射极层，设置在上述基极层上；发射极布线，与上述发射极层电连接；上部金属层，设置在上述发射极布线上；第一保护膜，覆盖上述发射极布线以及上述上部金属层，并且至少在与上述集电极层重叠的区域中设置有第一开口；以及凸块，包括经由上述第一开口与上述发射极布线电连接的下部凸块金属层，且上述下部凸块金属层的俯视时的面积大于上述第一开口的面积，上述第一保护膜的端部包围上述第一开口，并且设置在上述上部金属层上。
在该结构中，至少在与上述第一保护膜的端部重叠的区域中设置有上部金属层。因此，在第一保护膜和发射极布线的台阶部中，即使在下部凸块金属层中形成了空隙或薄层部分的情况下，也能够通过上部金属层抑制焊料侵入到晶体管。其结果是能够提高半导体元件的可靠性。
根据本发明的半导体元件，能够抑制焊料侵入到晶体管而提高可靠性。
附图说明
图1是第一实施方式所涉及的半导体元件的俯视图。
图2是图1的II－II’剖视图。
图3是图1的III－III’剖视图。
图4是第二实施方式所涉及的半导体元件的俯视图。
图5是图4的V－V’剖视图。
图6是第二实施方式的变形例所涉及的半导体元件的剖视图。
图7是第三实施方式所涉及的半导体元件的剖视图。
附图标记的说明
1…半导体基板；2…子集电极层；2b…隔离区域；3…集电极层；3e、15e、17e、22e…端部；4…基极层；5…发射极层；6…发射极电极；7…基极电极；8…集电极电极；9…第一绝缘膜；10…第一绝缘膜开口；11a、11b、11c…第一布线；12…第二绝缘膜；13…第二绝缘膜开口；14…第二布线(发射极布线)；14t…上部金属层；15…第一保护膜；16…第一开口；17…下部凸块金属层；17s…空隙；17t…界面；18…金属柱；19…焊料；20柱凸块；21…第二开口；22…第二保护膜；23…第三开口；100、100A、100B、100C…半导体元件；A…区域；BT…双极晶体管
具体实施方式
以下，基于附图，详细地对本发明的半导体元件的实施方式进行说明。此外，并不是通过该实施方式限定本发明。各实施方式是例示的，当然能够进行不同的实施方式所示的结构的部分的置换或者组合。在第二实施方式以后，省略对与第一实施方式共用的事项的描述，仅对不同点进行说明。特别对同样的结构带来的同样的作用效果，不再对每个实施方式逐个提及。
(第一实施方式)
图1是第一实施方式所涉及的半导体元件的俯视图。图2是图1的II－II’剖视图。图3是图1的III－III’剖视图。
如图1所示，半导体元件100具有双极晶体管BT、第二布线14、上部金属层14t、第一保护膜15以及柱凸块20。双极晶体管BT是异质结型的双极晶体管(HBT：HeterojunctionBipolar Transistor)。
在以下的说明中，将与半导体基板1(参照图2)的表面平行的面内的一个方向设为第一方向Dx。另外，将与半导体基板1的表面平行的面内与第一方向Dx正交的方向设为第二方向Dy。另外，将与第一方向Dx以及第二方向Dy的各个正交的方向设为第三方向Dz。此外，并不限于此，第二方向Dy也可以相对于第一方向Dx以90°以外的角度交叉。第三方向Dz也可以相对于第一方向Dx以及第二方向Dy以90°以外的角度交叉。在本说明书中，俯视表示从第三方向Dz观察时的位置关系。
双极晶体管BT包括子集电极层2、集电极层3、基极层4、发射极层5、发射极电极6、基极电极7以及集电极电极8。在子集电极层2上设置有集电极层3、基极层4以及发射极层5。集电极层3、基极层4以及发射极层5分别是矩形，长边方向沿着第一方向Dx设置。另外，在第二方向Dy上，集电极层3、基极层4以及发射极层5设置在两个集电极电极8之间。
如图2以及图3所示，对于半导体元件100而言，在半导体基板1上依次层叠子集电极层2、集电极层3、基极层4、发射极层5、发射极电极6、第一布线11a、第二布线14(发射极布线)、上部金属层14t。第一保护膜15覆盖第二布线14以及上部金属层14t，并且至少在与集电极层3层叠的区域中设置有第一开口16。柱凸块20设置在第一保护膜15上，并经由第一开口16与第二布线14以及上部金属层14t电连接。
更具体而言，半导体基板1例如是半绝缘性GaAs(砷化镓)基板。子集电极层2设置在半导体基板1上。子集电极层2是高浓度n型GaAs层，厚度例如是0.5μm左右。集电极层3设置在子集电极层2上。集电极层3是n型GaAs层，厚度例如是1μm左右。基极层4设置在集电极层3上。基极层4是p型GaAs层，厚度例如是100nm左右。
发射极层5设置在基极层4上。发射极层5从基极层4侧起包括本征发射极层、和设置在其上部的发射极台面层。本征发射极层是n型InGaP(磷化铟镓)层，厚度例如是30nm以上且40nm以下。发射极台面层由高浓度n型GaAs层和高浓度n型InGaAs层形成。高浓度n型GaAs层和高浓度n型InGaAs层的厚度分别例如是100nm左右。设置发射极台面层的高浓度n型InGaAs层，以用于进行与发射极电极6的欧姆接触。
如图2所示，集电极电极8与子集电极层2接触，并设置在子集电极层2上。集电极电极8例如具有由AuGe(金锗)膜、Ni(镍)膜、Au(金)膜依次层叠而成的层叠膜。AuGe膜的膜厚例如是60nm。Ni膜的膜厚例如是10nm。Au膜的膜厚例如是200nm。
基极电极7与基极层4接触，并设置在基极层4上。基极电极7是由Ti膜、Pt膜、Au膜依次层叠而成的层叠膜。Ti膜的膜厚例如是50nm。Pt膜的膜厚例如是50nm。Au膜的膜厚例如的200nm。
发射极电极6与发射极层5的发射极台面层，并设置在发射极台面层上。发射极电极6是Ti(钛)膜。Ti膜的膜厚例如是50nm。
此外，在半导体基板1上，与子集电极层2相邻地设置有隔离区域2b。隔离区域2b通过离子注入技术被绝缘化。通过隔离区域2b使元件间(多个双极晶体管BT间)绝缘。
第一绝缘膜9覆盖发射极电极6、基极电极7以及集电极电极8，子并设置在集电极层2以及隔离区域2b上。第一绝缘膜9例如是SiN(氮化硅)层。第一绝缘膜9可以是单层，或者，可以层叠多个氮化物层或者氧化物层。第一绝缘膜9也可以具有SiN层和树脂层的层叠构造。
在第一绝缘膜9上设置第一布线11a、11b、11c。此外，在图2中未图示第一布线11b，在图3中未图示第一布线11c。在第一绝缘膜9设置有第一绝缘膜开口10，第一布线11a经由第一绝缘膜开口10与发射极电极6连接。同样地，第一布线11b、11c分别经由设置在第一绝缘膜9的开口与基极电极7、集电极电极8分别连接。
第一布线11a、11b、11c例如是Ti膜/Au膜。Ti膜的膜厚约是10nm以上且50nm以下左右。Au膜的膜厚约是1μm以上且2μm以下左右。此外，“/”表示层叠构造。例如，Ti/Au表示在Ti上层叠Au的构造。
第二绝缘膜12覆盖多个第一布线11a、11b、11c，并设置在第一绝缘膜9上。第二绝缘膜12使用与第一绝缘膜9相同的材料。第二绝缘膜12例如可以SiN层的单层膜，或者可以具有SiN层和树脂层的层叠构造。在第二绝缘膜12上，在与第一布线11a重叠的部分设置有第二绝缘膜开口13。
第二布线14设置在第二绝缘膜12上，并经由第二绝缘膜开口13与第一布线11a连接。第二布线14经由第一布线11a与发射极层5电连接。第二布线14例如是Ti膜/Au膜。Ti膜的膜厚约是10nm以上且50nm以下左右。Au膜的膜厚约是2μm以上且4μm以下左右。第二布线14形成为覆盖包括集电极层3、基极层4以及发射极层5的整个双极晶体管BT。
上部金属层14t设置在第二布线14上。上部金属层14t形成为覆盖整个第二布线14，即，覆盖包括集电极层3、基极层4以及发射极层5的整个双极晶体管BT。上部金属层14t包含W(钨)、Ti(钛)、Mo(钼)、Ta(钽)、Ni(镍)、Cr(铬)的金属的任意一种以上。上部金属层14t也可以是包含上述的金属的任意一种以上的化合物，或者包含上述的金属的任意一种以上的合金。上部金属层14t的厚度例如是50nm以上且2μm以下左右。
作为上部金属层14t的具体例，是以W、Ti、Mo、Ta、Ni、Cr中的任意一种为主成分的单层膜、TiW等合金、TiSi、WSi、TaSi等珪化物、TaN、WN、TiN等氮化物。另外，也可以设为这些金属的层叠，还可以是Ni/TiW等的层叠构造。
第一保护膜15被设置为覆盖第二布线14以及上部金属层14t。换言之，上部金属层14t在与半导体基板1垂直的方向(第三方向Dz)上设置于第二布线14与第一保护膜15之间。第一保护膜15例如是包含SiN或者SiON(氮氧化硅)的至少一个以上的无机绝缘膜。
在第一保护膜15的、至少与集电极层3重叠的区域设置第一开口16。上部金属层14t在第一开口16的内侧从第一保护膜15露出。换言之，第一保护膜15的端部15e包围第一开口16、且设置在上部金属层14t上。在本实施方式中，上部金属层14t遍及与第一保护膜15重叠的区域以及与整个第一开口16重叠的区域而连续设置。但是，上部金属层14t只要至少设置在包括第一开口16的开口端(第一保护膜15的端部15e)的区域中即可。
柱凸块20形成为填埋第一开口16，并且与沿着第一开口16的开口端位于的第一保护膜15接触。如图2以及图3所示，柱凸块20具有下部凸块金属层17(UBM，Under BumpMetal)、金属柱18以及焊料19的层叠构造。下部凸块金属层17在第一开口16与上部金属层14t接触，并经上部金属层14t与第二布线14连接。另外，下部凸块金属层17在第一开口16的外周与第一保护膜15的上表面以及端部15e接触。
下部凸块金属层17例如是Ti或者TiW，膜厚是50nm以上且200nm以下左右。金属柱18例如是Cu，膜厚是10μm以上且50μm以下左右。焊料19例如是Sn或者Sn与Ag的合金，膜厚是10μm以上且30μm以下左右。
如图1所示，第一保护膜15的第一开口16的面积大于双极晶体管BT的集电极层3的面积。即，集电极层3、基极层4、发射极层5位于被第一保护膜15的端部15e围起的区域。第一开口16的第一方向Dx的宽度Wa大于集电极层3的第一方向Dx的宽度Wc。第一开口16的第二方向Dy的宽度Wb大于集电极层3的第二方向Dy的宽度Wd。第一开口16的第一方向Dx的宽度Wa是在第一方向Dx上面对面的第一保护膜15的端部15e的距离。第一开口16的第二方向Dy的宽度Wb是在第二方向Dy上面对面的第一保护膜15的端部15e的距离。
柱凸块20的俯视时的面积大于第一开口16的面积。更具体而言，下部凸块金属层17的俯视时的面积大于第一开口16的面积。即，柱凸块20的端部，更具体而言，下部凸块金属层17的端部17e位于第一保护膜15上。
即，如图2以及图3所示，在半导体元件100的剖面结构中，在不与第一开口16重叠的区域中，在第三方向Dz上按照第二布线14、上部金属层14t、下部凸块金属层17的顺序层叠。另外，在第一开口16的外侧的区域中，在第三方向Dz上按照第二布线14、上部金属层14t、第一保护膜15、下部凸块金属层17的顺序层叠。
在安装半导体元件100时，存在温度因热处理而上升的情况、多余的焊料熔化的情况。熔融的焊料在金属柱18的侧面传递，有可能侵入到金属柱18与下部凸块金属层17的界面17t(参照图2、图3)。此处，柱凸块20的下部凸块金属层17沿着第一保护膜15的上表面、端部15e以及第二布线14的上表面设置，起因于由第一保护膜15和第二布线14形成的阶梯差，有时在第一开口16的端部形成空隙17s或薄层部(短接)。
根据本实施方式的半导体元件100，至少在与第一开口16的开口端(端部15e)重叠的区域中，在第二布线14与下部凸块金属层17之间设置有上部金属层14t。因此，即使在焊料从界面17t侵入到下部凸块金属层17的空隙17s等的情况下，也能够抑制焊料侵入到第二布线14。其结果抑制焊料在第二布线14中扩散并到达发射极层5，从而半导体元件100能够抑制双极晶体管BT的破损或可靠性的降低。
另外，由于能够抑制焊料到达第二布线14，所以能够抑制在第二布线14中产生焊料所包含的Sn、Ag等金属材料的电迁移。特别是在功率较大的区域中所使用的功率晶体管等中，能够良好以抑制电迁移的产生。如以上那样，半导体元件100能够抑制焊料侵入到双极晶体管BT，而提高可靠性。
另外，在第一开口16的外周，下部凸块金属层17设置在第一保护膜15上，例如由Ti或者TiW形成的下部凸块金属层17、以及由SiN或者SiON形成的第一保护膜15具有良好的紧贴性。通过形成下部凸块金属层17和第一保护膜15紧贴的区域A，半导体元件100能够抑制水分侵入双极晶体管BT。
(第二实施方式)
图4是第二实施方式所涉及的半导体元件的俯视图。图5是图4的V－V’剖视图。在第二实施方式中，与上述第一实施方式不同，对在上部金属层14t设置第二开口21的结构进行说明。
如图4以及图5所示，在上部金属层14t中，在第一保护膜15的与第一开口16重叠的区域设置有第二开口21。如图4所示，第二开口21的俯视时的面积大于集电极层3的面积且小于第一开口16的面积。上部金属层14t的端部14te包围第二开口21，并在俯视时，位于第一保护膜15的端部15e与集电极层3的端部3e之间。
即，第二开口21的第一方向Dx的宽度We大于集电极层3的第一方向Dx的宽度Wc且小于第一开口16的第一方向Dx的宽度Wa。另外，第二开口21的第二方向Dy的宽度Wf大于集电极层3的第二方向Dy的宽度Wd且小于第一开口16的第二方向Dy的宽度Wb。
如图5所示，在设置有第二开口21的区域中，第二布线14从上部金属层14t露出。下部凸块金属层17形成为填埋第一开口16以及第二开口21，并且与第一保护膜15的端部15e以及上部金属层14t的端部14te接触。下部凸块金属层17经由第一开口16以及第二开口21直接与第二布线14连接。
优选上部金属层14t的未被第一保护膜15覆盖的部分的长度，换句话说，第一方向Dx上的第一保护膜15的端部15e与上部金属层14t的端部14te之间的距离是第一保护膜15的厚度以上。这样，上部金属层14t至少从与第一保护膜15的端部15e重叠的部分向第一开口16的内侧延伸，并位于由第一保护膜15的阶梯差引起的下部凸块金属层17的空隙17s等之下。由此，上部金属层14t能够有效地抑制焊料的侵入。
另外，优选上部金属层14t设置于不与集电极层3的端部3e重叠的位置。由此，由于在第一开口16的中央部，下部凸块金属层17直接与第二布线14连接，所以能够减少第二布线14与下部凸块金属层17的接触电阻。换言之，能够提高上部金属层14t所使用的材料的自由度。换句话说，即使作为上部金属层14t而使用了电阻值较大的材料、在半导体元件100A的制造工序中表面容易氧化的材料的情况下，也能够减少第二布线14与下部凸块金属层17的接触电阻。
(变形例)
图6是第二实施方式所涉及的变形例的半导体元件的剖视图。如图6所示，在变形例所涉及的半导体元件100B中，上部金属层14t能够应用第一金属层14ta和第二金属层14tb的层叠构造。第一金属层14ta遍及与第一保护膜15重叠的区域以及第一开口16而连续设置。第一金属层14ta例如是Ni膜。第二金属层14tb设置在第一金属层14ta上。第二金属层14tb是TiW膜或者Ti膜。在本变形例中，仅在第二金属层14tb设置第二开口21。换句话说，上部金属层14t在第一开口16的外周可以是Ni/TiW或者Ni/Ti的层叠构造，在第一开口16的中央部中可以是Ni膜的单层膜构造。
据此，半导体元件100B能够通过第一金属层14ta抑制焊料侵入第一开口16的中央部的与集电极层3的台阶部重叠的区域中的下部凸块金属层17的空隙17s等。另外，由于在区域A中，第二金属层14tb的TiW膜或者Ti膜和第一保护膜15接触，所以与Ni膜单层的情况相比，能够提高第二金属层14tb和第一保护膜15的紧贴性。其结果半导体元件100B能够抑制水分的侵入，耐湿性提高。
(第三实施方式)
图7是第三实施方式所涉及的半导体元件的剖视图。在第三实施方式中，与上述第二实施方式不同，对在第一保护膜15上设置第二保护膜22的结构进行说明。
如图7所示，在第三实施方式的半导体元件100C中，在第二保护膜22中，在与第一开口16以及第二开口21重叠的区域中设置有第三开口23。下部凸块金属层17形成为填埋第一开口16、第二开口21以及第三开口23，并且与沿着每个开口端设置的上部金属层14t的端部14te、第一保护膜15的端部15e以及第二保护膜22的端部22e接触。下部凸块金属层17经由第一开口16、第二开口21以及第三开口23直接与第二布线14连接。
第三开口23的俯视时的面积大于第一开口16以及第二开口21的俯视时的面积。换言之，第二保护膜22的端部22e位于第一保护膜15上。另外，柱凸块20的俯视时的面积大于第三开口23的俯视时的面积。柱凸块20的端部，更具体而言，下部凸块金属层17的端部17e位于第二保护膜22上。
第二保护膜22例如由聚酰亚胺等树脂材料形成。第二保护膜22与由无机绝缘材料形成的第一保护膜15相比容易使水分通过。即使在该情况下，也在第二保护膜22的端部22e的内侧的区域中设置有下部凸块金属层17和第一保护膜15紧贴的区域A。区域A设置在第一开口16的外侧。由此，即使半导体元件100C是设置有第二保护膜22的结构，也能够抑制水分的侵入，耐湿性提高。
另外，由于在第二保护膜22上设置有下部凸块金属层17的端部17e，所以第二保护膜22能够缓和柱凸块20以及双极晶体管BT中产生的应力。由此，半导体元件100C提高对机械应力的耐性。
此外，第三实施方式的结构也能够应用于上述的第一实施方式以及变形例所示的半导体元件100、100B。
另外，在上述的各实施方式中，列举具备一个双极晶体管BT的半导体元件的例子进行了说明，但也可以是在半导体基板1上形成有多个双极晶体管BT的半导体元件。另外，作为凸块，列举柱凸块20的例子进行了说明，但除了柱凸块20之外，例如也可以是焊料凸块、螺柱凸块。
另外，上述的各实施方式所示的、各结构的材料、厚度、尺寸等只是例示，可以适当地变更。例如，上部金属层14t可以根据半导体元件100的安装工序的热处理条件、使用环境等的焊料侵入风险而较厚地形成，也可以层叠多个金属层。子集电极层2、集电极层3、基极层4、发射极层5、各种布线的材料、厚度也可以适当地变更。另外，列举发射极层5的平面形状为矩形的情况的例子进行了说明，但发射极层5的平面形状也可以是圆形、椭圆形、六边形或者八边形等。
此外，上述的实施方式是为了容易理解本发明的，并不是用于限定性地解释本发明。本发明在不脱离其主旨的情况下可以变更/改进，并且本发明也包括其等同方案。

Claims (8)

1.一种半导体元件，具有：
半导体基板；
集电极层，设置在上述半导体基板上，
基极层，设置在上述集电极层上；
发射极层，设置在上述基极层上；
发射极布线，与上述发射极层电连接；
上部金属层，设置在上述发射极布线上；
第一保护膜，覆盖上述发射极布线以及上述上部金属层，并且至少在与上述集电极层重叠的区域设置有第一开口；以及
凸块，包括经由上述第一开口与上述发射极布线电连接的下部凸块金属层，且上述下部凸块金属层的俯视时的面积大于上述第一开口的面积，
上述第一保护膜的端部包围上述第一开口，并且设置在上述上部金属层上。
2.根据权利要求1所述的半导体元件，其中，
上述上部金属层遍及与上述第一保护膜重叠的区域以及与上述第一开口重叠的区域而设置，
上述下部凸块金属层经由上述上部金属层与上述发射极布线连接。
3.根据权利要求1所述的半导体元件，其中，
在上述上部金属层的与上述第一开口重叠的区域具有第二开口，
上述下部凸块金属层经由上述第一开口以及上述第二开口直接与上述发射极布线连接。
4.根据权利要求3所述的半导体元件，其中，
上述上部金属层的端部包围上述第二开口，并在俯视时，位于上述第一保护膜的端部与上述集电极层的端部之间。
5.根据权利要求1～4中的任意一项所述的半导体元件，其中，
在上述第一开口的外侧的区域，上述下部凸块金属层与上述第一保护膜的上表面接触。
6.根据权利要求1～5中的任意一项所述的半导体元件，其中，
上述半导体元件具有设置在上述第一保护膜上的第二保护膜。
7.根据权利要求1～6中的任意一项所述的半导体元件，其中，
上述上部金属层具有包含钨、钛、钼、钽、镍、铬的金属中的任意一种以上的金属、包含上述金属的任意一种以上的化合物、或者包含上述金属的任意一种以上的合金中的任意一个。
8.根据权利要求1～7中的任意一项所述的半导体元件，其中，
上述第一保护膜是包含氮化硅或者氮氧化硅中的至少一个以上的无机绝缘膜。
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