CN101685810B - 用于半导体组件封装的夹片及半导体封装结构和封装方法 - Google Patents

用于半导体组件封装的夹片及半导体封装结构和封装方法 Download PDF

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CN101685810B
CN101685810B CN2009101759988A CN200910175998A CN101685810B CN 101685810 B CN101685810 B CN 101685810B CN 2009101759988 A CN2009101759988 A CN 2009101759988A CN 200910175998 A CN200910175998 A CN 200910175998A CN 101685810 B CN101685810 B CN 101685810B
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intermediate plate
semiconductor
conductive finger
semiconductor subassembly
finger structure
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CN101685810A (zh
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石磊
赵良
刘凯
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Chongqing Wanguo Semiconductor Technology Co ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种半导体组件封装的夹片，其包含有一包含有窗口阵列与至少一导电指状结构的金属薄片。每一该导电指状结构具有一第一末端与一第二末端。在窗口之一处，第一末端是电性连接至金属薄板。在第二末端处，每一导电指状结构是提供电性连接至半导体组件的上半导体区域或者是引线框架。

Description

用于半导体组件封装的夹片及半导体封装结构和封装方法
技术领域
本发明涉及一种半导体芯片封装，特别涉及一种在芯片封装中使用源极夹片，从而在兼具降低扩散电阻与增强热耗散的方式下提供电性接触。 
在半导体组件封装上，金属夹片经常是用于在半导体芯片与嵌设该芯片的框架之间提供电性连接。大部分的电流夹片是非暴露式夹片。某些夹片为了有较佳的热耗散采取暴露设计，但是有限制。举例来说，美国专利号6624522公开一种金属氧化物半导体(MOS)栅极组件晶片，其源极侧覆盖一钝化层，如光敏液态环氧树脂、氮化硅层或相似者。晶片是由自旋或者屏蔽涂布或者其它方式沉积液态环氧树脂于晶片表面上。随后进行干燥并且对已涂布的晶片依照一般显影技术进行图案化，并在钝化层上形成开口，以产生若干个分隔开且暴露出下方源极金属的表面区域，以及用以暴露出位于晶片上的芯片的下方栅极电极的相似开口。钝化层是不仅是钝态层并且更是电镀抵抗层(假如有需要的话)，也作为焊锡掩膜，标示并形成焊锡的区域。 
随后进行晶片切割或者以其它方式裁切为独立芯片。独立芯片随后向下放置于源极侧，并且一U字型或者杯状部分镀金的夹片是利用导电胶或者焊锡连接至芯片的可焊锡的漏极侧，或者键合漏极夹片至芯片的底部漏极电极。漏极夹片的管脚的底部是与芯片的源极侧表面(其是接触处凸出物的顶面)共平面。随后，在模铸承载盘内芯片的外表面进行模铸。模铸后，对组件进行测试、激光标记然后切割为独立组件。然而，此组件与标准的导线框架管脚并不兼容。 
美国专利号6777800公开一种包含有直立功率MOSFET的半导体芯片封装，其底表面设置有一栅极区域与一源极区域，顶表面设置有一漏极区域。栅极引线电性连接至栅极区域，源极引线电性连接至源极区域。漏极夹片电性连接至漏极区域。一非传导模铸材料将此半导体芯片封围(encapsulation)， 其中该漏极夹片的表面是暴露于此非传导模铸材料外。然而，这样的半导体芯片封装需要倒装制程(flip-chip process)。 
美国专利公开号20080087992公开一种具有桥式板状内部互连结构(bridged plate interconnection)的半导体封装。这个封装结构利用一桥式源极板状内部互连结构，其具有一桥式部、设于桥式部两侧的山谷部、设置在山谷部和桥式部两侧的平面部，以及倚赖于平面部之一的连接部。桥式部是设置在高于山谷部分的平面上，平面部分所在的平面是位于桥式部份所在平面与山谷部份所在平面的中间。在封围过程中，键合材料流经桥式部份的下方并且提供机械强度给该桥式源级板状内部互连结构。桥式部份的顶端可能暴露于模铸复合物外，然而暴露的区域是少的，仅允许少量热耗散路径。 
美国专利申请案号12/130663(Attorney Docket No.ANO-014/US)公开一种顶面暴露的桥式夹片，其包含有两个或以上个分隔开的导电指状结构(electrically conductive fingers)，其由一个或更多个电性传导桥来彼此电性连接。至少一指状结构的第一末端是用以与引线框架电性接触。半导体组件封装包含有沿着半导体组件与引线框架的夹片。此半导体组件可分别在顶表面与底表面具有第一与半导体区域。夹片可电性连接至桥式处的半导体区域顶面，并电性连接至位于至少一指状结构的第一末端上的引线框架。然而，这个夹片具有少量的暴露区域，其仅允许少量的热耗散途径。 
因此开发具有有效热耗散以及与半导体组件低电阻连接的半导体组件封装是令人渴求的。并且，开发与一般标准的半导体管脚兼容的封装结构是需要的。进一步，使半导体组件封装结构具有坚固耐用的应力释放结构与能弹性化的使用不同尺寸的半导体组件也是让人向往的。 
发明内容
本发明的主要目的在提供一种具有窗口阵列的顶部暴露式夹片，其具有有效的热耗散途径且能与一般标准的半导体管脚兼容。 
本发明的另一目的在提供一种具有窗口阵列的顶部暴露式夹片，其使半导体组件封装结构具有坚固耐用的应力释放结构与能弹性化的使用不同尺寸的半导体组件。 
本发明提出一种半导体组件封装的夹片，其包含有一具有窗口阵列的金 属薄板；至少一导电指状结构，每一个导电指状结构具有第一末端与第二末端，其中在窗口之一处，第一末端电性连接至金属薄板；其中每一导电指状结构在第二末端处是用以提供电性连接至半导体组件的上半导体区域或者引线框架。 
以下由具体实施例详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。 
附图说明
图1A是依据本发明的一个具体实施例的具有顶部暴露式夹片的半导体组件封装的透视图； 
图1B是利用模铸化合物封围图1A所示的组件封装的透视图； 
图1C是图1A的组件封装的透视图； 
图1D是图1A的组件封装的侧视图； 
图2A是依据本发明的另一具体实施例的具有顶部暴露式夹片的半导体组件封装的透视图； 
图2B是利用模铸化合物封围图2A所示的组件封装的透视图； 
图2C是图2A的组件封装的透视图； 
图2D是图2A的组件封装的侧视图； 
图2E是依据本发明的另一具体实施例的导电夹片的透视图； 
图3A-3D是依据本发明的具体实施例的用于导电夹片的各种窗口形状的俯视图。 
具体实施方式
图1A至图1D是依据本发明的具体实施例的半导体组件封装100的示意图。在图1A与图1C所显示的范例中，组件封装100包含有一熔接的引线框架102与一半导体组件104，该半导体组件104的顶表面与底表面具有接触区域。此接触区域是由金属暴露区域或其它电性传导材料所形成，该其它电性传导材料与位于半导体组件104内的对应的半导体组件结构电性连接。由实施例的方式，但并不以此为限，半导体组件104可以是直立式金属氧化物半导体(MOS)组件，其具有一顶面源极接触区S、一顶面栅极接触区G与 一底面漏极接触区D。在图1A至1D所示的范例中，半导体组件104是位于引线框架102上方，底面漏极接触区D面对且与引线框架102的主要部分电性接触。由范例所示的方式，但并不以此为限，引线框架102可以是被熔接的或者没有被熔接的。 
依据本发明的具体实施例，半导体组件封装100包含有单一阶梯状夹片106，其包含有两个分隔开的金属薄板108与110，且金属薄板108与110各自具有窗口阵列111与113。由范例所示的方式，但并不以此为限，金属薄板108与110可以是铜、钢、铝、镍、钛或其它基于这些金属的合金所制成，举例来说42-镍铁(42％镍)合金，或者伴随有其它成分的铜合金、钢合金、铝与镍与钛合金。此处所使用的金属是指一种具有热与电传导的材料，并且是可延展的可塑的。在金属薄板108上，每一导电指状结构112包含有第一末端与第二末端，并且导电指状结构112是形成来与半导体组件104的源级接触区域S在导电指状结构112的第二末端上形成电性接触。每一导电指状结构112的第一末端是在每一个对应的窗口111处电性连接至金属薄板108。这样的结构提供若干彼此分隔的电性平行路径。一个或更多个导电指状结构114是由分隔开的金属薄板110所形成，以提供半导体组件104的栅极接触区域G与引线框架102的栅极引线107之间的电性接触。每一导电指状结构114包含有在窗口113处电性连接至金属薄板110的第一末端，以及用以与半导体组件104的栅极接触区域G形成电性接触的第二末端。例如使用焊锡或者导电胶117的方式，在导电指状结构112、114与接触区域S、G间建立电性与机械接触。 
由范例所示的方式，但并不以此为限，每一导电指状结构112、114的第二末端可以是近似V的形状，由V底部提供电性接触至位于组件104顶面上的源极衬垫(pad)和栅极衬垫。导电指状结构112的第二末端也可以是其它形状，例如是提供电性连接至源极的U形。“V”形将描述为一般反转的拱形形状，其包含有U形与其它同等形状，但并不以此为限。夹片也包含有导电指状结构115与116，其形成于金属薄片108、110的最近边缘，分别与引线框架102的熔接的源极引线109与栅极引线107电性接触，以减少夹片键合过程中的位移。通过例如使用焊锡或者导电胶117来建立介于导电指状结构115、116与引线109、107之间的电性与机械接触。导电指状结构115、116 的第二末端与引线框架102的接触比导电指状结构112、114与半导体芯片104之间的接触陡，以减少夹片键合过程中的非期望位移。 
导电指状结构可以是利用单一步骤或者两步骤的冲模制程来制得。导电指状结构可以由形成有窗口的相同金属薄板制成。在这个具体实施例中，导电指状结构112、115的阵列可以是由形成有窗口111的金属薄板108冲模而成，而导电指状结构114、116是由形成有窗口113的金属薄板110冲模形成。 
由实施例的方式，但不以此为限，半导体组件104可以是金属氧化物半导体(MOS)组件，其具有一顶面源极与顶面栅极，与一底面漏极。在这样的范例中，夹片106的金属薄板108与110一般是分别指源极夹片与漏极夹片。夹片106在指状结构112处电性连接至组件104的顶面源极。每一个V型的底部是平坦的，以易于电性连接指状结构112与组件104的顶面源极。本发明的源极夹片108可以使用独立的栅极夹片110。在另一具体实施例中，栅极夹片110可以使用一般的打线键合或者一般夹片来取代。由实施例的方式，但不以此为限，夹片106也可与其它型态的半导体组件一起使用，特别是直立式半导体组件，例如双极结型晶体管(BJT)、绝缘栅极双极晶体管(IGBT)与二极管。 
如图1B所示，半导体组件封装100可以利用模铸化合物118进行封围并且留下金属薄板108、110的顶面，以暴露出来。这暴露出的区域是大的且能够提供有效的热耗散。由实施例的方式，但不以此为限，模铸化合物118可以是环氧树脂。 
硅与金属之间的热扩散不协调可能会引起应力，甚至是裂痕。假如两者间具有大的单一接触区域，则问题将会更严重。此时可以采用如同半导体组件100所实行的方式，将接触区域碎裂为若干较小片段作为解决的方式。夹片106通过导电指状结构112、114、115与116所提供的多个接触点来提供介于夹片106与MOS组件104之间的应力释放结构。因为导电指状结构112、114、115与116给予模铸化合物118许多在不同角度的锚状物的特色，也增加封装的机械强度。如同图1D所示，当处在垂直力量下，可以由水平移动来释放应力。 
在夹片106中，若干个电性接触区域减少扩散热阻。扩散热阻是指在导体内电流扩散所产生的电阻，起因于电流从导体接触点的侧向移动。分布多 个平行传导路径来引导贯穿半导体组件104的顶面上的接触衬垫的通道电流来减低扩散电阻。假如接触点是紧密串接在一起或者假如接触点在数量上是较少时，如在美国专利申请案公开号20080087992所示的源极夹片结构，图1A至1D所示的夹片型态能具有较低的电阻。 
本发明的另一优点是能够与一般半导体封装的管脚与印刷管脚(footprints)相兼容。因此，本发明可以使用在现行的装置上，而无须改变电路板或者周遭组件的设计。 
本领域内的技术人员可以轻易装配半导体组件封装100。举例来说，半导体组件104可以嵌设于引线框架102上。夹片106随后可以依附到半导体组件104上和引线框架102上。可以额外加入模铸化合物118来封围大部分的半导体组件封装100。夹片106的顶面暴露于模铸化合物118外，以使热容易散逸。 
图2A至2D是本发明的另一具体实施例的半导体组件封装的示意图。半导体组件封装200基本上包含有先前所述且描绘在图1A至1D内的半导体组件封装100的所有组成组件，除了源极夹片包含有可容纳较厚的封装的双阶梯状指状结构。 
如图2A与2C所示，组件封装200包含有一熔接引线框架102与一半导体组件104，例如具有一顶面源极S、顶面栅极G与底面漏极D且设置在引线框架102顶面上的MOS组件，其底面漏极D与引线框架102的主要部分接触。由实施例的方式，但不以此为限，引线框架102可以是被熔接的或是无被熔接的。 
依据本发明的具体实施例，半导体组件封装200包含有夹片206，其包含有两个分隔开且分别具有窗口阵列211和213的金属薄板208与210。在金属薄板208上，皆具有第一末端与第二末端的导电指状结构212的阵列是在第二末端处的半导体组件104的顶面源极上形成电性接触。每一导电指状结构212的第一末端是在每一对应窗口211处电性连接至金属薄板208。这样的结构提供多个平行电性路径，其彼此间是分隔开的。在金属薄板210上，包含有第一末端与第二末端的导电指状结构214在第二末端处与半导体组件104的顶面栅极形成电性接触。每一导电指状结构214的第一末端是在对应窗口213处与金属薄板210电性连接。由实施例的方式，但不以此为限，导 电指状结构212与214的第二末端可以是近似V的形状，由V型底部提供电性接触至位于组件104顶面上的源极衬垫(pad)和栅极衬垫。导电指状结构212、214也可以是其它形状，例如是提供电性连接至源极的U形。“V”形将描述为一般反转的拱形形状，其包含有U形与其它同等形状，但并不以此为限。 
导电指状结构215与216分别形成在金属薄板208与210上，分别与引线框架102的熔接源极引线109和栅极引线107形成明显(sharp)的电性接触，来减少夹片键合时的位移。 
导电指状结构可以是利用单一步骤或者两步骤的冲模制程来制得。导电指状结构可以由形成有窗口的相同金属薄板制成，例如金属薄板208与210。在此具体实施例中，导电指状结构212、215的阵列是由形成有窗口211的金属薄板208冲模形成，导电指状结构214与216是由形成有窗口213的金属薄板210冲模形成。 
进一步，导电指状结构212、214、215与216的形状是考虑到金属薄板208至半导体组件104的表面距离。在这个实施例中，如图2C与2D所示，导电指状结构212、214、215与216是双阶梯状，例如楼梯形状，以提供更多应力释放能力，减少应力释放过程的水平移动，与封装顶表面至芯片表面间较高的距离。在这个范例中，是利用垂直移动来进行应力释放。在另一具体实施例中，导电指状结构212可以是螺旋形，例如图2E所示。为了形成螺旋形状，螺旋图案可以先于金属薄板208上裁切，随后再冲模形成。 
如图2B所示，半导体组件封装200可以利用模铸化合物进行封围并且留下金属薄板208与210的顶面。由实施例的方式，但不以此为限，模铸化合物218可以是环氧树脂。 
如图2D所示，当承受一垂直力量时，应力可以由垂直位移来进行释放。 
夹片106与206基本上可以是与半导体组件封装相同的尺寸。夹片106与206一般的尺寸是由大约次毫米(sub-millimeter)至几分米。举例来说，夹片的尺寸在长度与宽度上是由大约0.5mm至大约5cm。长度与宽度可以是不同的。 
由实施例的方式，但不以此为限，图3A至3C是描述在图1A至1D与图2A至2D中所示窗口111、113与211、213的俯视图。对应的导电指状结 构可具有对应的形状。图3D显示图2E的螺旋形状导电指状结构实施例的图案的俯视图。 
虽然，以上的描述是本发明的具体实施例的整体描述，但是也可使用其它的选择、修改与同等物。因此，本发明的范畴不应当决定于上述的描述，而是决定于权利要求书，伴随着所有等效范畴。进一步，可与其它技术特征结合。附属权利要求不能解释为功能性的限制，除非已明确指出是手段或方法。 
以上所述者，仅为本发明的较佳实施例而已，并非用来限定本发明实施的范围。故即凡依本发明的权利要求所述的特征及精神所为的均等变化或修饰，均应包括于本发明的范围内。 

Claims (26)

1.一种用于半导体组件封装的夹片，其包含有：
一金属薄板，其包含有窗口阵列；
至少一导电指状结构，每一导电指状结构具有第一末端与第二末端，其中，在窗口处，第一末端电性连接至金属薄板；
其中每一该导电指状结构在第二末端处是用来提供电性连接到半导体组件上的半导体区域或者引线框架。
2.如权利要求1所述的夹片，其特征在于，该导电指状结构是单一阶梯状。
3.如权利要求1所述的夹片，其特征在于，该导电指状结构是双阶梯状。
4.如权利要求1所述的夹片，其特征在于，该导电指状结构是螺旋形状。
5.如权利要求1所述的夹片，其特征在于，该至少一导电指状结构包含有第二末端是近似V形的至少一指状结构，其近似V形的底部与该半导体区域的顶部形成电性连接。
6.如权利要求1所述的夹片，其特征在于，该至少一导电指状结构更包含有第二末端与一引线框架形成电性连接的至少一指状结构。
7.如权利要求1所述的夹片，其特征在于，该金属薄板的材料是选自于包含有铜、钢、铝、镍、钛所构成的群组或者结合有其它成分的铜合金、钢合金、铝合金、镍合金、钛合金。
8.如权利要求1所述的夹片，其特征在于，在邻接窗口间该导电指状结构提供若干个彼此间是利用间隙分隔开的平行电性路径。
9.如权利要求1所述的夹片，其特征在于，该夹片的尺寸是介于0.5mm与5cm之间。
10.如权利要求1所述的夹片，其特征在于，该导电指状结构是由该金属薄板冲模形成。
11.一种半导体封装结构，其包含有：
一引线框架，其包含有一个主要部分与至少一个引线；
一半导体组件，其包含有至少一个位于顶面的第一接触区域；以及
一夹片，其包含有：
一金属薄板，其包含有一窗口阵列；
若干个导电指状结构，每一个导电指状结构包含有第一末端与第二末端，其中，在每个窗口处，该第一末端电性连接至该金属薄板；
其中在该若干个导电指状结构的第一设置处的第二末端处，该夹片电性连接至该半导体组件的第一接触区域；
其中该夹片电性连接该第一接触区域至该引线框架；以及
该半导体组件的底面面向该引线框架的主要部分设置。
12.如权利要求11所述的半导体封装结构，其特征在于，该若干个导电指状结构的该第一设置处的第二末端是近似V形，其中每一个近似V形的底部与该第一接触区域电性连接。
13.如权利要求11所述的半导体封装结构，其特征在于，在该若干个导电指状结构的第二设置处，该夹片电性连接至该引线框架。
14.如权利要求11所述的半导体封装结构，其特征在于，该导电指状结构是单一阶梯状。
15.如权利要求11所述的半导体封装结构，其特征在于，该导电指状结构是双阶梯状。 
16.如权利要求11所述的半导体封装结构，其特征在于，该导电指状结构是螺旋形状。
17.如权利要求11所述的半导体封装结构，其特征在于，该半导体组件是利用一模铸化合物进行封围，其中该夹片的顶表面是自该模铸化合物暴露出。
18.如权利要求11所述的半导体封装结构，其特征在于，该半导体组件是金属氧化物半导体MOS组件，其中该MOS组件的表面上更包含有一栅极区域。
19.如权利要求18所述的半导体封装结构，其特征在于，该半导体组件封装更包含有一栅极夹片，其包含有：
一第二金属薄板，其包含有一个窗口阵列；
至少一个传导栅极指状结构，每一个该栅极指状结构包含有第一末端与第二末端，其中在每一个窗口处，该第一末端电性连接至该第二金属薄板；
其中在至少一个栅极指状结构的第二末端处，该栅极夹片电性连接至该半导体组件的栅极接触区域；
其中在至少另一个栅极指状结构的第二末端，该栅极夹片电性连接至一个栅极引线。
20.如权利要求11所述的半导体封装结构，其特征在于，该夹片能与一般标准尺寸的半导体组件一起使用。
21.如权利要求11所述的半导体封装结构，其特征在于，该夹片提供多个平行且穿过该半导体组件的该第一接触区域的电性与热传路径。
22.如权利要求11所述的半导体封装结构，其特征在于，该半导体组件是一直立式半导体组件，其中该半导体组件的底面更包含有一个第二接触区 域，其有传导力的依附于该引线框架的主要部分上。
23.一种形成半导体组件封装的方法，其包含有：
(a)、依附一半导体组件到一引线框架上，该半导体组件的顶面上具有第一接触区域，因此该半导体组件的底侧倚靠在该引线框架的主要部分上；
(b)、依附一夹片到该半导体组件与该引线框架上，其中，该夹片包含有：
一金属薄板，其包含有窗口阵列；
若干个导电指状结构，每一个导电指状结构包含有第一末端与第二末端，其中在每个窗口处，该第一末端电性连接至该金属薄板；
其中，在该导电指状结构的该第二末端，该夹片电性连接至该半导体组件的第一接触区域；以及
(c)、利用一模铸化合物封围该半导体组件与部分该引线框架与夹片，因此该夹片的该顶面是穿过该模铸化合物暴露出。
24.如权利要求23所述的方法，其特征在于，该半导体组件是一直立式金属氧化物半导体场效应晶体管，其中该金属氧化物半导体场效应晶体管进一步包含有位于顶侧的栅极接触区域；以及
其中该方法在步骤(b)和(c)之间，进一步包含有：
(d)、将该金属氧化物半导体场效应晶体管的栅极接触区域连接至该引线框架的栅极引线。
25.如权利要求23所述的方法，其特征在于，该导电指状结构是由金属薄片冲模而成。
26.如权利要求23所述的方法，其特征在于，该半导体组件是一直立式半导体组件，且步骤(b)进一步包含将该直立式半导体组件的底面有传导力的依附于该引线框架的主要部分上。 
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8486757B2 (en) 2009-11-25 2013-07-16 Infineon Technologies Ag Semiconductor device and method of packaging a semiconductor device with a clip
DE102010042382A1 (de) * 2010-10-13 2012-04-19 Robert Bosch Gmbh Kontaktelement und Verwendung eines Kontaktelements in einem elektronischen Bauteil
US8436429B2 (en) * 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method
US8987879B2 (en) * 2011-07-06 2015-03-24 Infineon Technologies Ag Semiconductor device including a contact clip having protrusions and manufacturing thereof
DE102012216280A1 (de) * 2012-09-13 2014-04-10 Robert Bosch Gmbh Kontaktbrücke und Anordnung mit Bauelement, Leiterstrukturträger und Kontaktbrücke
US9496214B2 (en) 2013-05-22 2016-11-15 Toyota Motor Engineering & Manufacturing North American, Inc. Power electronics devices having thermal stress reduction elements
TWI552390B (zh) * 2014-01-29 2016-10-01 一詮精密工業股份有限公司 發光二極體料帶的製造方法
TWI560845B (en) * 2014-12-04 2016-12-01 Alpha & Omega Semiconductor Method of manufacturing a semiconductor package having a small gate clip and clip frame
DE102015218369A1 (de) 2015-09-24 2017-03-30 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Leiterrahmenmoduls und Leiterrahmenmodul
US9496208B1 (en) * 2016-02-25 2016-11-15 Texas Instruments Incorporated Semiconductor device having compliant and crack-arresting interconnect structure
US10128170B2 (en) * 2017-01-09 2018-11-13 Silanna Asia Pte Ltd Conductive clip connection arrangements for semiconductor packages
JP6417462B2 (ja) * 2017-11-02 2018-11-07 ローム株式会社 半導体装置
DE102018130147A1 (de) 2018-11-28 2020-05-28 Infineon Technologies Ag Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung
WO2022138318A1 (ja) * 2020-12-23 2022-06-30 ローム株式会社 半導体装置の製造方法および半導体装置
CN113675149B (zh) * 2021-08-09 2024-04-02 泰兴市龙腾电子有限公司 一种具有应力释放结构的引线框架及封装料片
JP2024035665A (ja) * 2022-09-02 2024-03-14 株式会社東芝 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763941A (en) * 1995-10-24 1998-06-09 Tessera, Inc. Connection component with releasable leads
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
JP3614030B2 (ja) * 1999-04-02 2005-01-26 株式会社村田製作所 マザー基板，子基板およびそれを用いた電子部品ならびにその製造方法
EP1258040A4 (en) * 2000-02-10 2009-07-01 Int Rectifier Corp VERTICAL-CONDUCTING PROTUBERANCE CHIP WITH CONTACT PLOTS ON ONE SURFACE
JP3551114B2 (ja) * 2000-02-25 2004-08-04 日本電気株式会社 半導体装置の実装構造およびその方法
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6355502B1 (en) * 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6646329B2 (en) * 2001-05-15 2003-11-11 Fairchild Semiconductor, Inc. Power chip scale package
JP3868777B2 (ja) * 2001-09-11 2007-01-17 株式会社東芝 半導体装置
US6784540B2 (en) * 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
JP2006049101A (ja) * 2004-08-05 2006-02-16 Molex Japan Co Ltd シート状コネクタとその製造方法
JP4566678B2 (ja) * 2004-10-04 2010-10-20 日立オートモティブシステムズ株式会社 パワーモジュール
US7898092B2 (en) * 2007-11-21 2011-03-01 Alpha & Omega Semiconductor, Stacked-die package for battery power management
US20060145312A1 (en) * 2005-01-05 2006-07-06 Kai Liu Dual flat non-leaded semiconductor package
US7612439B2 (en) * 2005-12-22 2009-11-03 Alpha And Omega Semiconductor Limited Semiconductor package having improved thermal performance
US7511361B2 (en) * 2005-01-05 2009-03-31 Xiaotian Zhang DFN semiconductor package having reduced electrical resistance
US7394151B2 (en) * 2005-02-15 2008-07-01 Alpha & Omega Semiconductor Limited Semiconductor package with plated connection
US20070057368A1 (en) * 2005-09-13 2007-03-15 Yueh-Se Ho Semiconductor package having plate interconnections
US7622796B2 (en) * 2005-09-13 2009-11-24 Alpha And Omega Semiconductor Limited Semiconductor package having a bridged plate interconnection
US7683464B2 (en) * 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US8288200B2 (en) * 2005-11-30 2012-10-16 Diodes Inc. Semiconductor devices with conductive clips
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
JP2008227131A (ja) * 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置及びその製造方法
US7585750B2 (en) * 2007-05-04 2009-09-08 Stats Chippac, Ltd. Semiconductor package having through-hole via on saw streets formed with partial saw
US20090057869A1 (en) * 2007-08-31 2009-03-05 Alpha & Omega Semiconductor, Ltd. Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion
US8426960B2 (en) * 2007-12-21 2013-04-23 Alpha & Omega Semiconductor, Inc. Wafer level chip scale packaging
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US8680658B2 (en) * 2008-05-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Conductive clip for semiconductor device package
US7776658B2 (en) * 2008-08-07 2010-08-17 Alpha And Omega Semiconductor, Inc. Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
US8354740B2 (en) * 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
US8222078B2 (en) * 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
US8154108B2 (en) * 2010-03-29 2012-04-10 Alpha And Omega Semiconductor Incorporated Dual-leadframe multi-chip package and method of manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip

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