CN115527971A - 半导体装置以及功率放大器模块 - Google Patents

半导体装置以及功率放大器模块 Download PDF

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Publication number
CN115527971A
CN115527971A CN202211178366.9A CN202211178366A CN115527971A CN 115527971 A CN115527971 A CN 115527971A CN 202211178366 A CN202211178366 A CN 202211178366A CN 115527971 A CN115527971 A CN 115527971A
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metal film
semiconductor device
film
metal
bonding pad
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CN202211178366.9A
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大部功
梅本康成
柴田雅博
那仓健一
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Publication of CN115527971A publication Critical patent/CN115527971A/zh
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    • H03—ELECTRONIC CIRCUITRY
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Abstract

本发明提供一种在使用了包含化合物半导体的基板的半导体装置中能够抑制芯片面积的增大的半导体装置以及使用了该半导体装置的功率放大器模块。在包含化合物半导体的基板上形成电路元件。在电路元件上，接合焊盘被配置为与电路元件至少局部重叠。接合焊盘包含第1金属膜以及形成于第1金属膜上的第2金属膜。第2金属膜的金属材料比第1金属膜的金属材料硬。

Description

半导体装置以及功率放大器模块
本申请是申请日为2018年03月27日、申请号为201810261605.4、发明名称为“半导体装置以及功率放大器模块”的发明专利申请的分案申请。
技术领域
本发明涉及半导体装置以及功率放大器模块。
背景技术
在下述的专利文献1以及专利文献2中，公开了使用异质结双极晶体管(HBT)的高频放大模块用的半导体装置。在该半导体装置设置有HBT 保护用的保护电路。保护电路在静电等的过电压被施加于HBT的情况下，防止HBT的破坏。保护电路具有将多个二极管串联连接的电路结构，被连接于HBT的集电极与发射极之间。
在下述的专利文献3中，公开了在布线或者有源元件上形成有电极焊盘的半导体装置。用于在接合时保护布线或者有源元件的突起电极形成于电极焊盘(接合焊盘)的表面上。突起电极在将电极焊盘的表面上的Al 置换为可与Ni产生置换反应的Zn之后，通过在电极焊盘的表面对NiP进行非电解镀而形成。记载了除了NiP，也可以使用能进行非电解镀的Cu 系金属。
在先技术文献
专利文献
专利文献1：JP特开2005-236259号公报
专利文献2：国际公开第2001/018865号
专利文献3：特开2000-164623号公报
在专利文献1以及专利文献2中公开的半导体装置中，必须将用于配置构成保护电路的多个二极管的区域确保在半导体基板上。因此，芯片面积变大。芯片面积的增大使得化合物半导体装置的低成本化的实现变得困难。
如专利文献3中公开的半导体装置那样，通过在布线或者有源元件上配置接合焊盘(bonding pad)，能够抑制芯片面积的增大。在硅系半导体工艺中，对布线、接合焊盘使用了Al，但在化合物半导体工艺中，通常对布线、接合焊盘不使用A1。因此，难以将专利文献3中公开的技术直接应用于化合物半导体工艺。
发明内容
本发明的目的在于，提供一种在使用了包含化合物半导体的基板的半导体装置中，能够抑制芯片面积的增大的半导体装置。本发明的另一目的在于，提供一种使用了该半导体装置的功率放大器模块。
基于本发明的第1观点的半导体装置具有：
电路元件，形成在包含化合物半导体的基板上；和
接合焊盘，在所述电路元件上，被配置为与所述电路元件至少局部重叠，
所述接合焊盘包含第1金属膜以及形成于所述第1金属膜上的第2金属膜，所述第2金属膜的金属材料的杨氏模量比所述第1金属膜的金属材料的杨氏模量大。
由于电路元件与接合焊盘被配置为局部重叠，因此不需要确保用于配置接合焊盘的专用区域。由此，能够抑制芯片面积的增大。通过第2金属膜作为应力分散板而发挥作用，能够使接合时在电路元件产生的应力分散，抑制电路元件的破损。
基于本发明的第2观点的半导体装置除了基于第1观点的半导体装置的结构，还具有以下特征：所述接合焊盘进一步包含形成于所述第2金属膜上的第3金属膜，所述第3金属膜由与所述第1金属膜相同的金属材料形成。
作为第3金属膜，能够使用与接合线的接触电阻低的金属材料。与接合线直接接合于第2金属膜的情况相比，能够降低接合焊盘与接合线的接触电阻。
基于本发明的第3观点的半导体装置除了基于第2观点的半导体装置的结构，还具有以下特征：所述第1金属膜以及所述第3金属膜由Au形成，所述第2金属膜具有包含至少1种金属材料的层，所述至少1种金属材料是从包含Cu、Ni以及Mo的群选出的。
作为形成于化合物半导体基板上的多个电路元件的连接用的布线，能够使用一般被利用的Au。由于Cu、Ni以及Mo比Au硬，因此第2金属膜作为应力分散板而发挥作用。
基于本发明的第4观点的半导体装置除了基于第3观点的半导体装置的结构，还具有以下特征：所述第2金属膜具有包含至少2种金属材料的 2层，所述至少2种金属材料是从包含Cu、Ni以及Mo的群选出的。
通过将多个金属材料组合，作为第2金属膜的整体，也能够提高硬度、电阻率等选择的自由度。
基于本发明的第5至第7观点的半导体装置除了基于第2至第4观点的半导体装置的结构，还具有以下特征：
在所述第1金属膜上进一步具有保护膜，
所述保护膜具有在俯视情况下被配置于所述第1金属膜的内侧的开口，
所述第2金属膜以及所述第3金属膜在俯视情况下被配置于所述开口的内侧。
接合时施加于第2金属膜以及第3金属膜的载荷不被传递到保护膜。因此，接合时保护膜难以损伤。
基于本发明的第8至第10观点的半导体装置除了基于第5至第7观点的半导体装置的结构，进一步具有第4金属膜，所述第4金属膜覆盖所述开口的内侧的所述第1金属膜的上表面之中未被所述第2金属膜覆盖的区域、所述第2金属膜的侧面以及所述第3金属膜的侧面和上表面，并且由与所述第1金属膜相同的金属材料形成。
由于包含不同种类金属的第2金属膜与第3金属膜的接合界面被第4 金属膜覆盖，因此能够抑制不同种类金属接触腐蚀的产生。
基于本发明的第11至第13观点的半导体装置除了基于第1至第3观点的半导体装置的结构，还具有以下特征：
所述基板的化合物半导体具有闪锌矿型结晶构造，所述基板的上表面是从(100)面起的偏离角为4°以下的面，
所述电路元件是从包含异质结双极晶体管、场效应晶体管、二极管、电容器以及电阻元件的群选出的1个元件。
在将形成于具有闪锌矿型结晶构造的化合物半导体基板上的异质结双极晶体管、场效应晶体管、二极管、电容器以及电阻元件等的电路元件与接合焊盘重叠配置的结构中，能够抑制这些电路元件的损伤。
基于本发明的第14以及第15观点的半导体装置除了基于第11以及第12观点的半导体装置的结构，还具有以下特征：
所述电路元件具有包含从所述基板外延生长的半导体层的台面构造，所述台面构造的上表面的平面形状是包含与[01-1]方向平行的边和与 [011]方向平行的边的长方形或者正方形，与[011]方向平行的边比与 [01-1]方向平行的边短。
若使用包含与[01-1]方向平行的边和与[011]方向平行的边的长方形或者正方形的蚀刻掩模，通过湿式蚀刻来对半导体层进行各向异性蚀刻，则从与[011]方向平行的边起进行侧面蚀刻，形成檐状的部分。这里，所谓“各向异性蚀刻”，是指利用了基于结晶面的蚀刻速度的不同的蚀刻。该檐状的部分通过接合时产生的应力而容易破损。由于与[011] 方向平行的边比与[01-1]方向平行的边短，因此形成檐状的部分的区域变窄。因此，能够抑制接合时的破损。
基于本发明的第16以及第17观点的半导体装置除了基于第11以及第12观点的半导体装置的结构，还具有以下特征：所述电路元件具有包含从所述基板外延生长的半导体层的台面构造，所述台面构造的上表面的平面形状是包含与[001]方向平行的边以及与[010]方向平行的边的多边形。
若使用包含与[001]方向平行的边和与[010]方向平行的边的多边形的蚀刻掩模，通过湿式蚀刻来对半导体层进行各向异性蚀刻，则与这些边对应地形成几乎垂直竖立的侧面。由于未形成檐状的部分，因此能够抑制接合时的破损。
基于本发明的第18以及第19观点的半导体装置除了基于第16以及第17观点的半导体装置的结构，还具有以下特征：所述台面构造的上表面的平面形状是还包含与[01-1]方向平行的边的平行六边形。
与平行于[01-1]方向的边对应的侧面缓慢倾斜。由于未形成檐状的部分，因此能够抑制接合时的破损。
基于本发明的第20观点的功率放大器模块具有：
半导体装置，所述半导体装置包含：具有形成于包含化合物半导体的基板上的异质结双极晶体管的功率放大电路、与所述异质结双极晶体管的发射极-集电极间连接的保护电路、以及作为所述功率放大电路的输出端子的接合焊盘，构成所述功率放大电路以及所述保护电路的至少1个电路元件与所述接合焊盘被配置为局部重叠，所述接合焊盘包含第1金属膜和第 2金属膜的至少2层，所述第2金属膜的金属材料的杨氏模量比所述第1 金属膜的金属材料的杨氏模量大；
印刷布线基板，安装所述半导体装置；和
接合线，与所述接合焊盘接合，将所述接合焊盘与所述印刷布线基板的布线连接。
由于至少一个电路元件与接合焊盘被局部重叠地配置，因此不需要确保用于配置接合焊盘的专用区域。由此，能够抑制半导体装置的芯片面积的增大。通过第2金属膜作为应力分散板而发挥作用，能够使接合时在电路元件产生的应力分散，抑制电路元件的破损。
由于电路元件与接合焊盘被局部重叠地配置，因此不需要确保用于配置接合焊盘的专用区域。由此，能够抑制芯片面积的增大。通过第2金属膜作为应力分散板而发挥作用，能够使接合时在电路元件产生的应力分散，抑制电路元件的破损。
附图说明
图1A是基于第1实施例的半导体装置的一部分的俯视图，图1B以及图1C分别是图1A的单点划线1B-1B以及单点划线1C-1C处的剖视图。
图2是包含基于第1实施例的半导体装置的功率放大器模块的等效电路图。
图3A以及图3B是基于第1实施例的半导体装置的接合焊盘的引线接合前以及引线接合中的示意性的剖视图，图3C以及图3D是基于比较例的半导体装置的接合焊盘的引线接合前以及引线接合中的示意性的剖视图。
图4是表示各种金属的维氏硬度、杨氏模量以及电阻率的图表。
图5是基于第2实施例的半导体装置的剖视图。
图6是基于第3实施例的半导体装置的剖视图。
图7A以及图7B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图8A以及图8B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图9A以及图9B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图10A以及图10B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图11A以及图11B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图12A以及图12B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图13A以及图13B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图14A以及图14B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图15A以及图15B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图16A以及图16B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图17A以及图17B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图18A以及图18B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图19A以及图19B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图20A以及图20B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图21A以及图21B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图22A以及图22B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图23A以及图23B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图24A以及图24B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图25A以及图25B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图26A以及图26B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图27A以及图27B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图28A以及图28B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图29A以及图29B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图30A以及图30B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图31A以及图31B是基于第3实施例的半导体装置的制造中途阶段的剖视图。
图32A是基于第4实施例的半导体装置的剖视图，图32B以及图32C 分别是基于第4实施例的变形例的半导体装置的剖视图。
图33A是在上表面为(100)面的GaAs基板通过各向异性蚀刻而形成的正八边形的台面的俯视图，图33B、图33C、图33D以及图33E分别是图33A的单点划线33B-33B、33C-33C、33D-33D以及33E-33E处的剖视图。
图34A是基于第5实施例的半导体装置的1个二极管的俯视图，图 34B以及图34C分别是图34A的单点划线34B-34B以及单点划线34C-34C 处的剖视图。
图35A是基于第6实施例的半导体装置的1个二极管的俯视图，图 35B以及图35C分别是图35A的单点划线35B-35B以及单点划线35C-35C 处的剖视图。
图36A是基于第7实施例的半导体装置的1个二极管的俯视图，图 36B是图36A的单点划线36B-36B处的剖视图。
图37是基于第8实施例的功率放大器模块的剖视图。
-符号说明-
40 基板
41 异质结双极晶体管(HBT)
42 保护电路
43、44 通孔
45 背面电极
47 二极管
70 集电极电极
71 基极电极
72 发射极电极
73、74 通孔用连接焊盘
80 阴极电极
81 阳极电极
83 檐状的部分
101 缓冲层
102 子集电极层
103 集电极层
104 基极层
105 发射极层
106、107 接触层
108 元件分离区域
109 层间绝缘膜
110 开口
111 布线
112、113 层间绝缘膜
120 接合焊盘用的第1金属膜
121 保护膜
122 接合焊盘用的开口
127 镀覆用的种子电极层
130 接合焊盘用的第2金属膜
130A 下侧金属膜
130B 上侧金属膜
131 接合焊盘用的第3金属膜
132 接合焊盘用的第4金属膜
140 接合焊盘
143 基于比较例的半导体装置的接合焊盘
150 发射极区域
160 抗蚀剂膜
161 开口
163 抗蚀剂膜
164 开口
166 蜡
167 蓝宝石基板
170 抗蚀剂膜
171、172 开口
200 印刷布线基板
201、202 下垫板
203、204 接合焊盘
221 导电性粘接剂
225 接合线
230 硅半导体芯片
231 导电性粘接剂
232 接合焊盘
235 接合线
240 密封用固化树脂
500 半导体装置
501 信号输入用的接合焊盘
502 初级的HBT
503、504 偏置电路
505 接合线
506 金属球
510 毛细管
511 表示向第3金属膜施加的应力的分布的曲线
512 表示向保护电路施加的应力的分布的曲线
520 输入匹配电路
521 输入端子
522 信号输出用的接合焊盘
523 接合线
540 输出匹配电路
541 信号输入用的接合焊盘
542 输出端子。
具体实施方式
[第1实施例]
参照图1A至图4的附图，对基于第1实施例的半导体装置进行说明。图1A是基于第1实施例的半导体装置的一部分的俯视图。在包含半绝缘性的GaAs的基板40上，形成异质结双极晶体管(HBT)41、保护电路 42等的电路元件。多个接合焊盘140被配置为与构成保护电路42的电路元件局部重叠。
图1B是图1A的单点划线1B-1B处的剖视图。在基板40上依次层叠缓冲层101、子集电极层102、集电极层103、基极层104、发射极层105、接触层106、107。缓冲层101由非掺杂的GaAs形成，子集电极层102以及集电极层103由n型的GaAs形成。基极层104由p型的GaAs形成。发射极层105由n型的InGaP形成。接触层106、107分别由n型的GaAs 以及n型的InGaAs形成。
通过向缓冲层101以及子集电极层102的一部分的区域注入硼(B)，来形成元件分离区域108。包含子集电极层102、集电极层103、基极层 104以及发射极层105的HBT41形成在基板40上。在子集电极层102上形成集电极电极70，集电极电极70与子集电极层102欧姆连接。形成在发射极层105上的基极电极71贯通发射极层105并与基极层104欧姆连接。形成在接触层107上的发射极电极72与接触层107欧姆连接。
在HBT41的侧向的元件分离区域108上，形成通孔用连接焊盘73。在基板40的整个区域形成层间绝缘膜109，以使得覆盖HBT41、通孔用连接焊盘73。对层间绝缘膜109例如使用氮化硅(SiN)。在层间绝缘膜 109的规定的位置、例如配置有集电极电极70、基极电极71、发射极电极 72、通孔用连接焊盘73的位置形成多个接触孔。
形成在层间绝缘膜109上的布线111将发射极电极72和通孔用连接焊盘73连接。进一步地，其他多个布线111连接于集电极电极70、基极电极71。
在基板40的整个区域形成层间绝缘膜112以使得覆盖布线111，在其上方进一步形成上侧的层间绝缘膜113。对层间绝缘膜112例如使用SiN，对上侧的层间绝缘膜113使用聚酰亚胺。在层间绝缘膜113上形成保护膜 121。对保护膜121例如使用SiN。
从基板40的背面向通孔用连接焊盘73形成通孔43。形成于基板40 的背面的背面电极45通过通孔43内而与通孔用连接焊盘73连接。
图1C是图1A的单点划线1C-1C处的剖视图。在基板40上，形成利用了集电极层103与基极层104的pn结的多个二极管47。通过将多个二极管47串联连接来构成保护电路42(图1A)。
形成于二极管47的各自的子集电极层102上的阴极电极80与子集电极层102欧姆连接。形成于二极管47的各自的发射极层105上的阳极电极81贯通发射极层105而与基极层104欧姆连接。在1个二极管47的侧向的元件分离区域108上形成通孔用连接焊盘74。
在基板40的整个区域形成层间绝缘膜109，以使得覆盖二极管47以及通孔用连接焊盘74。在层间绝缘膜109的规定的位置、例如配置有阴极电极80、阳极电极81、通孔用连接焊盘74的位置，形成接触孔。通过形成于层间绝缘膜109上的多个布线111将多个二极管47的阴极电极80和阳极电极81连接，从而将多个二极管47串联连接。其他布线111将包含多个二极管47的串联电路的端部的阴极电极80和通孔用连接焊盘74连接。包含多个二极管47的串联电路的端部的阳极电极81通过其他布线111 而与HBT41(图1B)的集电极电极70连接。
在基板40的整个区域形成层间绝缘膜112以使得覆盖布线111。在层间绝缘膜112上形成接合焊盘用的第1金属膜120。第1金属膜120被配置于与多个二极管47部分重叠的位置。
在第1金属膜120以及层间绝缘膜112上形成保护膜121。在保护膜 121形成接合用的多个开口122。该多个开口122被配置于俯视情况下第1 金属膜120的内侧、并且与多个二极管47部分重叠的位置。
形成镀覆用的种子电极层127以使得覆盖开口122的底面以及侧面。种子电极层127扩展到保护膜121的上表面的包围开口122的边框状的区域。在种子电极层127上依次层叠接合焊盘用的第2金属膜130以及第3 金属膜131。由第1金属膜120、第2金属膜130以及第3金属膜131构成接合焊盘140。
第2金属膜130的金属材料比第1金属膜120的金属材料硬。金属材料的硬度例如能够由维氏硬度、杨氏模量等定义。第3金属膜131由与第 1金属膜120相同的金属材料形成。例如，第1金属膜120以及第3金属膜131由金(Au)形成，第2金属膜130由铜(Cu)形成。
形成从基板40的背面达到至通孔用连接焊盘74的通孔44。形成于基板40的背面的背面电极45通过通孔44内而与通孔用连接焊盘74连接。
图2是包含基于第1实施例的半导体装置的功率放大器模块的等效电路图。该功率放大器模块包含：输入匹配电路520、半导体装置500以及输出匹配电路540。
半导体装置500包含构成功率放大电路的初级的HBT502以及输出级的HBT41。输入信号被输入到信号输入用的接合焊盘501。输入信号被输入到初级的HBT502的基极电极。初级的HBT502的输出被输入到输出级的HBT41的基极电极71(图1B)。
偏置电路503、504分别向初级的HBT502以及输出级的HBT41提供偏置电流。在输出级的HBT41的集电极-发射极之间连接保护电路42。保护电路42包含串联连接的多个、例如10个二极管47。输出级的HBT41 的集电极与作为输出端子的多个接合焊盘140连接。
向输入匹配电路520的输入端子521输入高频信号。输入匹配电路520 的信号输出用的接合焊盘522通过接合线523而与半导体装置500的信号输入用的接合焊盘501连接。
半导体装置500的信号输出用的多个接合焊盘140分别通过多个接合线505而与输出匹配电路540的信号输入用的多个接合焊盘541连接。被输入到输入匹配电路520的输入端子521的高频信号经由输入匹配电路 520，被半导体装置500放大，经由输出匹配电路540而被输出到输出端子542。
[第1实施例的效果]
接下来，对第1实施例的优良效果进行说明。
在第1实施例中，保护电路42(图1A)具有保护HBT41(图1B) 使其免于静电破坏、过电压破坏、负载变动破坏的功能。此外，在第1实施例中，由于该保护电路42(图1A)与接合焊盘140被部分重叠地配置，因此不需要确保用于配置接合焊盘140的专用的区域。由此，能够抑制芯片面积的增大。
接下来，参照从图3A至图3D的附图，对第1实施例的其他效果进行说明。图3A以及图3B是基于第1实施例的半导体装置的接合焊盘140 的引线接合前以及引线接合中的示意性的剖视图。
在毛细管510支承接合线505。作为接合线505，例如使用金(Au) 线。在接合线505的前端形成金属球506。若将毛细管510向接合焊盘140 按压并施加热量或者超声波，则接合焊盘140的第3金属膜131以及金属球506变形并且两者接合。在第3金属膜131，沿着金属球506的外周产生相对较大的应力。通过曲线511来表示向第3金属膜131施加的应力的分布。
在第3金属膜131产生的应力经由相对较硬的第2金属膜130而被传递到保护电路42。通过第2金属膜130作为应力分散板而发挥作用，从而在比第2金属膜130更靠下方的保护电路42产生的应力的分布变得比在第3金属膜131产生的应力的分布平缓。通过曲线512来表示在保护电路 42产生的应力的分布。
图3C以及图3D是基于比较例的半导体装置的接合焊盘143的引线接合前以及引线接合中的示意性的剖视图。在比较例中，接合焊盘143由包含与第1金属膜120以及第3金属膜131(图3A、图3B)相同的金属材料的单一的金属膜形成。由于接合焊盘143比第2金属膜130(图3A、图3B)柔软，因此使应力分散的功能较弱。因此，如曲线512所示，沿着金属球506的外周，在保护电路42产生较大的应力。在产生较大的应力的位置，在构成保护电路42的电路元件容易产生损伤。
在第1实施例中，由于接合焊盘140的第2金属膜130作为应力分散板而发挥作用，因此在接合时，在保护电路42难以产生损伤。进一步地，由于作为第3金属膜131，使用比第2金属膜130柔软的金属材料，因此能够确保接合线505与接合焊盘140的良好的电连接。
从得到稳定的接触界面的观点出发，优选对第1金属膜120使用与其方的布线111(图1B、图1C)相同的金属材料。在由化合物半导体形成电路元件的情况下，一般对布线111使用Au。因此，优选对第1金属膜 120使用Au。
接下来，参照图4，说明对于接合焊盘140的第2金属膜130优选的金属材料。第2金属膜130为了提高作为应力分散板的效果，优选使用比第1金属膜120硬的金属材料。这里，所谓“硬”，是指维氏硬度高、或者杨氏模量大。进一步地，从第2金属膜130构成接合焊盘140的一部分的观点出发，优选使用电阻率较低的金属材料。
图4是表示各种金属的维氏硬度、杨氏模量以及电阻率的图表。图4 所示出的维氏硬度是在全部金属中以相同的试验力测定得出的值。
在对第1金属膜120使用Au的情况下，优选对第2金属膜130使用维氏硬度或者杨氏模量比金(Au)高的金属材料。作为一个例子，优选对第2金属膜130使用具有比30HV高的维氏硬度的金属材料或者具有比 90GPa大的杨氏模量的金属材料。作为维氏硬度或者杨氏模量比Au高并且电阻率并不明显高的金属材料，举例：铜(Cu)、镍(Ni)、钼(Mo)。优选对第2金属膜130使用Cu、Ni或者Mo。
在接合焊盘140对于使应力分散而足够厚的情况下，插入较硬的第2 金属膜130(图1C)的效果较低。在接合焊盘140的厚度为10μm以下的情况下，可得到插入第2金属膜130的显著的效果。
[第1实施例的变形例]
在第1实施例中，接合焊盘140(图1A)与构成保护电路42的二极管47(图1C)局部重叠。此外，也可以设为接合焊盘140与HBT41(图 1A、图lB)重叠的构成。在基板40(图1B、图1C)上，如图2所示那样形成电容器、电阻元件等的电路元件。也可以设为将接合焊盘140与这些电路元件局部重叠的构成。也可能在包含化合物半导体的基板40上，形成HBT以外的有源元件、例如高电子迁移率晶体管(HEMT)、MES 型场效应晶体管(MESFET)等的场效应晶体管。也可以设为将接合焊盘 140与使用了化合物半导体的这些有源元件局部重叠的构成。
在图1A中，表示了接合焊盘140的个数是3个的例子，但接合焊盘 140的个数并不局限于3个。配置1个以上的接合焊盘140即可。在图2 中，表示了输出级的HBT41是1个的例子，但一般由并联连接的多个HBT 构成输出级。
也可以在包含Cu的第2金属膜130(图1C)与包含Au的第3金属膜131(图1C)的界面，配置扩散防止膜。作为扩散防止膜，能够使用 TiW、Ni等。
在第1实施例中，作为基板40，使用了GaAs基板，但也可以使用其他的化合物半导体基板。例如，也可以作为基板40，使用InP基板。
在第1实施例中，作为一个例子，将第1金属膜120与第2金属膜130 设为相同的厚度，但优选使第2金属膜130的厚度为第1金属膜120的厚度以上。通过使第2金属膜130较厚，能够提高第2金属膜130的作为应力分散板的功能。
[第2实施例]
接下来，参照图5，对基于第2实施例的半导体装置进行说明。以下，针对与基于第1实施例的半导体装置的构成共通的构成，省略说明。
图5是基于第2实施例的半导体装置的剖视图。在第1实施例中，如图1C所示，接合焊盘140的第2金属膜130以及第3金属膜131扩展到开口122的边缘的外侧，其外周部分与保护膜121重叠。与此相对地，在第2实施例中，第2金属膜130以及第3金属膜131在俯视情况下被配置于开口122的内侧。即，第2金属膜130以及第3金属膜131与保护膜121 不重叠。另外，种子电极层127也在俯视情况下被配置于开口122的内侧。
在第2实施例中，即使在接合时向接合焊盘140的第2金属膜130以及第3金属膜131施加载荷，也不向保护膜121施加载荷。因此，能够减少接合时向保护膜121施加的机械应力。其结果，能够抑制向保护膜121 的裂缝的产生。
[第3实施例]
接下来，参照图6，对基于第3实施例的半导体装置进行说明。以下，针对与基于第2实施例的半导体装置的构成共通的构成，省略说明。
图6是基于第3实施例的半导体装置的剖视图。在第2实施例中，是包含接合焊盘140的种子电极层127、第2金属膜130以及第3金属膜131 (图5)的多层构造的侧面以及上表面露出的状态。在第3实施例中，包含种子电极层127、第2金属膜130以及第3金属膜131的多层构造的侧面以及上表面被第4金属膜132覆盖。第4金属膜132进一步覆盖开口122 内的第1金属膜120的上表面之中未形成种子电极层127的区域。对第4 金属膜132例如使用与第3金属膜131相同的金属材料。
在第3实施例中，第2金属膜130与第3金属膜131的不同种类金属的接触面不露出。因此，特别是能够抑制高湿度环境下的不同种类金属接触腐蚀。
接下来，参照图7A、图7B至图30A、图30B的附图，对基于第3 实施例的半导体装置的制造方法进行说明。基于第3实施例的半导体装置的制造方法也能够应用于基于第1实施例以及第2实施例的半导体装置的制造。
图7A、图7B至图30A、图30B的附图是基于第3实施例的半导体装置的制造中途阶段的剖视图。图7A、图7B至图30A、图30B的附图之中，在末尾附上A的附图对应于图1A的单点划线1B-1B处的剖视图，在末尾附上B的附图对应于图1A的单点划线1C-1C处的剖视图。
如图7A以及图7B所示，在包含半绝缘性的GaAs的基板40上，使缓冲层101、子集电极层102、集电极层103、基极层104、发射极层105、接触层106、107依次外延生长。对这些半导体层的形成，例如能够使用有机金属气相外延(MOVPE)法。基板40的上表面是从(100)面起的偏离角为4°以下的面。
接下来，对从缓冲层101到接触层107的各半导体层的材料、掺杂浓度以及膜厚的一个例子进行说明。缓冲层101由非掺杂的GaAs形成，其膜厚为0.1μm。子集电极层102由n型GaAs形成，作为n型掺杂剂的Si 的掺杂浓度为5×1018cm-3，膜厚为0.6μm。集电极层103由n型GaAs形成， Si的掺杂浓度为1×1016cm-3，膜厚为1.0μm。基极层104由p型GaAs形成，作为p型掺杂剂的C的掺杂浓度为5×1019cm-3，膜厚为96nm。发射极层105由n型InGaP形成，InP的摩尔比为0.48，Si的掺杂浓度为 4×1017cm-3，膜厚为35nm。接触层106由n型GaAs形成，Si的掺杂浓度为5×1018cm-3，膜厚为50nm。上侧的接触层107由n型InGaAs形成，InAs 的摩尔比为0.5，Si的掺杂浓度为1×1019cm-3，膜厚为50nm。
如图8A所示，在接触层107的规定的区域上形成发射极电极72。在图8B所示的剖面，未配置发射极电极72。发射极电极72具有从基板40 侧起依次层叠厚度10nm的Mo膜、厚度5nm的Ti膜、厚度30nm的Pt 膜以及厚度200nm的Au膜的4层构造。发射极电极72能够通过蒸镀以及剥离法来形成。
如图9A所示，通过将接触层107、106加工为规定的形状，形成发射极区域150。在发射极区域150上配置发射极电极72。在图9B所示的剖面，接触层107、106被除去，发射极层105露出。接触层107、106的加工中，能够应用光刻以及湿式蚀刻。对该湿式蚀刻，例如能够使用将磷酸、双氧水以及水混合而成的蚀刻液。作为一个例子，能够使用将浓度85重量％的磷酸、浓度35重量％的双氧水和水以体积比1：2：40的比例进行混合而成的蚀刻液。该蚀刻液具有不实质地蚀刻包含InGaP的发射极层 105而选择性地蚀刻包含GaAs的接触层107、106的选择性。
如图10A所示，在发射极区域150的两侧形成基极电极71。基极电极71在应用光刻、蒸镀以及剥离法在发射极层105上形成金属膜之后，通过进行烧结，贯通发射极层105并与基极层104欧姆连接。用于形成基极电极71的金属膜包含从基板40侧起依次被层叠的厚度30nm的Pt膜、厚度50nm的Ti膜、厚度50nm的Pt膜以及厚度200nm的Au膜。
如图10B所示，与基极电极71(图10A)的形成同时地，形成多个阳极电极81。阳极电极81也贯通发射极层105并与基极层104欧姆连接。
如图11A以及图11B所示，通过光刻以及湿式蚀刻来除去发射极层 105的不必要的部分。由此，基极层104露出。作为蚀刻液，例如能够使用盐酸。盐酸具有不实质地蚀刻包含GaAs的基极层104而选择性地蚀刻包含InGaP的发射极层105的选择性。
如图12A以及图12B所示，使用对发射极层105进行蚀刻时的蚀刻掩模，除去基极层104以及集电极层103的不必要的部分。由此，子集电极层102露出。对基极层104以及集电极层103的蚀刻，能够使用与对接触层107、106(图9A、图9B)的蚀刻使用的蚀刻液相同的蚀刻液。蚀刻的停止通过进行时间控制来进行。
如图13A以及图13B所示，形成用于确保元件间的电绝缘的元件分离区域108。元件分离区域108例如能够通过向子集电极层102以及缓冲层101离子注入硼而形成。
如图14A以及图14B所示，与在HBT41(图1B)的子集电极层102 上形成集电极电极70同时地，在二极管47(图1B)的子集电极层102上形成阴极电极80。进一步地，在元件分离区域108上形成通孔用连接焊盘 73、74。对集电极电极70、阴极电极80以及通孔用连接焊盘73、74的形成能够应用光刻、蒸镀以及剥离法。集电极电极70、阴极电极80以及通孔用连接焊盘73、74包含从基板40侧起依次被层叠的厚度60nm的AuGe 膜、厚度10nm的Ni膜以及厚度200nm的Au膜。
如图15A以及图15B所示，使层间绝缘膜109堆积于基板40的整个区域，以使得覆盖HBT41、二极管47、通孔用连接焊盘73、74。层间绝缘膜109例如由SiN形成，厚度为100nm。对于层间绝缘膜109的堆积，例如能够应用化学气相生长(CVD)法。
如图16A以及图16B所示，在层间绝缘膜109的规定的位置形成多个开口110。多个开口110分别在俯视情况下被配置于集电极电极70、基极电极71、发射极电极72、阴极电极80、阳极电极81以及通孔用连接焊盘73、74的内侧，使这些部分的上表面的一部分的区域露出。对于开口 110的形成，能够应用光刻以及干式蚀刻。
如图17A以及图17B所示，在层间绝缘膜109上形成多个布线111。布线111例如由Au形成，其厚度为1μm。对于布线111的形成，能够应用光刻、蒸镀以及剥离法。一个布线111将发射极电极72与通孔用连接焊盘73连接。另一个布线将1个二极管47的阴极电极80与通孔用连接焊盘74连接。另一个布线111将二极管47的阳极电极81与和其相邻的二极管47的阴极电极80连接。进一步地，在基极电极71以及集电极电极70也分别连接布线111。
如图18A所示，在基板40的整个区域形成层间绝缘膜112，以使得覆盖布线111。层间绝缘膜112例如由SiN形成。进一步地，在层间绝缘膜112上形成层间绝缘膜113。层间绝缘膜113例如通过涂敷聚酰亚胺并形成厚度1.8μm的聚酰亚胺膜后，进行表面的平坦化而形成。然后，除去配置接合焊盘140(图1A、图6)的区域的层间绝缘膜113。在图18B所示的剖面，层间绝缘膜113被除去，包含SiN的层间绝缘膜112露出。
如图19B所示，在层间绝缘膜112上形成第1金属膜120。第1金属膜120配置为与多个二极管47局部重叠。在图19A所示的剖面内，不形成第1金属膜120。第1金属膜120例如由Au形成，其厚度为2μm。对于第1金属膜120的形成，例如能够应用光刻、蒸镀以及剥离法。与第1 金属膜120的形成同时地，在基板40的其他区域形成第2层的布线。
在基板40的整个区域形成包含SiN的保护膜121，以使得覆盖图19B 所示的第1金属膜120。在图19A所示的剖面，在层间绝缘膜113上形成保护膜121。保护膜121的厚度例如为500nm。对于保护膜121的形成，例如能够应用CVD法。
在保护膜121上形成抗蚀剂膜160，在应形成接合焊盘140(图1A、图6)的区域形成开口161。
如图20A以及图20B所示，通过将抗蚀剂膜160作为蚀刻掩模来对保护膜121进行蚀刻，从而在保护膜121形成开口122。第1金属膜120 在开口122的内侧露出。对于保护膜121的蚀刻，例如能够应用干式蚀刻。在保护膜121形成开口122后，除去抗蚀剂膜160。
如图21A以及图21B所示，在基板40的整个区域形成镀覆用的种子电极层127，以使得覆盖保护膜121的上表面、开口122的侧面以及底面。种子电极层127例如包含厚度0.1μm的TiW膜和厚度0.1μm的Cu膜的2 层。对于种子电极层127的形成，例如能够应用溅射法。
如图22A以及图22B所示，在种子电极层127上形成抗蚀剂膜163。通过光刻，在应形成第2金属膜130以及第3金属膜131(图6)的区域形成开口164。在开口164内，种子电极层127露出。
如图23A以及图23B所示，在开口164内的种子电极层127上，通过电解镀来使第2金属膜130以及第3金属膜131依次堆积。第2金属膜 130例如由Cu形成，其厚度为2μm。第3金属膜131例如由Au形成，其厚度为1μm。第3金属膜131的上表面比抗蚀剂膜163的上表面低。在形成第2金属膜130以及第3金属膜131之后，除去抗蚀剂膜163。
如图24A以及图24B所示，对未形成第2金属膜130的区域的露出的种子电极层127进行蚀刻除去。保护膜121在图24A的剖面露出，在图 24B的剖面，第1金属膜120在保护膜121以及形成于保护膜121的开口 122内露出。
如图25B所示，在包含种子电极层127、第2金属膜130以及第3金属膜131的层叠构造的侧面和上表面、以及在开口122内露出的第1金属膜120的上表面，形成第4金属膜132。对于第4金属膜132的形成，例如能够应用非电解镀。第4金属膜132例如由Au形成，其厚度为0.1μm。在图25A以及图25B所示的保护膜121的上表面不堆积Au。
如图26A以及图26B所示，使基板40的表侧的面(形成有保护膜121 的面)与蓝宝石基板167对置，隔着蜡166而将基板40与蓝宝石基板167 粘贴。
如图27A以及图27B所示，通过从背侧对基板40进行研削，使其薄层化到厚度75μm。
如图28A以及图28B所示，在被薄层化的基板40的背侧的表面形成抗蚀剂膜170。通过光刻，在抗蚀剂膜170形成开口171、172。开口171、 172分别形成于与通孔用连接焊盘73、74对应的位置。
如图29A以及图29B所示，将抗蚀剂膜170作为蚀刻掩模，对基板 40以及元件分离区域108进行蚀刻。由此，形成贯通基板40以及元件分离区域108的通孔43、44，在其底面，分别露出通孔用连接焊盘73、74。对于基板40以及元件分离区域108的蚀刻，能够应用各向异性干式蚀刻。在通孔用连接焊盘73、74露出后，除去抗蚀剂膜170。
如图30A以及图30B所示，在基板40的被侧的表面以及通孔43、44 的侧面以及底面形成背面电极45。背面电极45能够通过利用非电解镀来使钯堆积之后，利用电解镀来使Au堆积而形成。背面电极45的厚度为 4μm。在形成背面电极45之后，从基板40取下蜡166以及蓝宝石基板167。
如图31A以及图31B所示，接合焊盘140的表层的第4金属膜132 以及保护膜121露出。然后，通过进行切割等来按照每个芯片进行分离，从而半导体装置完成。
[第4实施例]
接下来，参照图32A，对基于第4实施例的半导体装置进行说明。以下，针对与参照图1A至图4的附图而说明的第1实施例共通的构成，省略说明。
图32A是基于第4实施例的半导体装置的剖视图。在第1实施例中，构成接合焊盘140的第2金属膜130(图1C)由包含比第1金属膜120硬的金属材料的单层构成。在第4实施例中，第2金属膜130具有包含不同的金属材料的下侧金属膜130A以及上侧金属膜130B的2层构造。下侧金属膜130A以及上侧金属膜130B均由比第1金属膜120硬的金属材料形成。
例如，作为下侧金属膜130A以及上侧金属膜130B，优选使用从Cu、 Ni、Mo这3种金属选出的2种金属。
接下来，参照图32B以及图32C，对基于第4实施例的变形例的半导体装置进行说明。
图32B以及图32C分别是基于第4实施例的变形例的半导体装置的剖视图。在图32B所示的变形例中，与基于第2实施例的半导体装置的接合焊盘140(图5)同样地，第2金属膜130以及第3金属膜131被配置于在保护膜121设置的开口122的内侧。在图32C所示的变形例中，与基于第3实施例的半导体装置的接合焊盘140(图6)同样地，包含第2金属膜130以及第3金属膜131的层叠构造、以及该层叠构造的周围的第1金属膜120的上表面被第4金属膜132覆盖。在图32B以及图32C所示的变形例中，第2金属膜130也包含下侧金属膜130A和上侧金属膜130B这2 层。
在第4实施例以及第4实施例的变形例中，能够将第2金属膜130作为整体来设为所希望的硬度，并且将多个材料组合以使得抑制电阻率的增加。其结果，可提供一种可靠性更高的半导体装置。
[第5实施例]
接下来，参照图33A至图34C的附图，对基于第5实施例的半导体装置进行说明。以下，针对与第1实施例至第4实施例的各实施例共通的构成，省略说明。在第1实施例至第4实施例的各实施例中，未限定基板 40(图1B、图1C等)的上表面的面指数、二极管47(图1C等)的各半导体层的图案的平面形状以及取向。在第5实施例中，基板40的上表面的面指数被确定，半导体层的图案的平面形状以及优选的取向被限定。
首先，参照图33A至图33E的附图，对基于湿式蚀刻的各向异性蚀刻特性进行说明。
图33A是在上表面为(100)面的GaAs基板通过各向异性蚀刻而形成的正八边形的台面的俯视图。正八边形的1个边与[011]方向平行。图33B、图33C、图33D以及图33E分别是图33A的单点划线33B-33B、单点划线33C-33C、单点划线33D-33D以及单点划线33E-33E处的剖视图。作为进行各向异性蚀刻的蚀刻液，能够使用弱酸性或者弱碱性的蚀刻液。
在图33B所示的剖面，在朝向[01-1]方向的侧面以及朝向其相反方向的侧面容易形成出现了(111)A面的反台面状的部分。例如，台面构造的上层部分为反台面状，下层部分为正台面状。在反台面状的部分，形成在横向突出的檐状的部分。这里，对米勒指数的各要素付与的负号表示对该要素付与了上横线。在图33C所示的剖面，在朝向[0-1-1]方向的侧面以及朝向其相反方向的侧面容易出现(111)B面，侧面为平缓的斜面。在图33D以及图33E所示的剖面，朝向[00-1]方向的侧面以及朝向其相反方向的侧面、朝向[0-10]方向的侧面以及朝向其相反方向的侧面为几乎垂直竖立的形状。
图33B至图33E的各图中所示的各向异性蚀刻特性与对在上表面为 (100)面的GaAs基板上外延生长的化合物半导体进行各向异性蚀刻时的特性相同。此外，除了GaAs基板，对在具有闪锌矿型结晶构造的化合物半导体基板以及其上外延生长的化合物半导体层进行各向异性蚀刻的情况下，也可得到相同的特性。
图34A是基于第5实施例的半导体装置的1个二极管47的俯视图。图34B以及图34C分别是图34A的单点划线34B-34B以及单点划线 34C-34C处的剖视图。基板40的上表面的面指数为(100)。另外，也可以使用上表面是从(100)面起的偏离角为4°以下的结晶面的基板。
在由元件分离区域108包围的子集电极层102上，层叠集电极层103、基极层104以及发射极层105。俯视情况下，发射极层105被配置于集电极层103的内侧。形成于子集电极层102上的阴极电极80将集电极层103 从[011]方向、[0-11]方向以及[0-1-1]方向这三个方向包围。形成于发射极层105上的阳极电极81贯通发射极层105并与基极层104欧姆连接。
多个二极管47(图1C)与[01-1]方向平行地排列。该排列方向相当于包含GaAs的基板40的容易裂开方向。换言之，多个二极管47在与容易裂开方向平行的方向上排列。
发射极层105、基极层104以及集电极层103通过使用相同的蚀刻掩模来进行各向异性蚀刻而被图案化(参照图11B以及图12B)。该蚀刻掩模的平面形状是长方形，长边与[01-1]方向平行，短边与[011]方向平行。
如图34B所示，在相对于[0-1-1]方向垂直的剖面，包含集电极层 103、基极层104以及发射极层105的台面的上层部分为反台面状，形成檐状的部分83。图34A所示的发射极层105相当于上表面的外周线。
如图34C所示，在相对于[0-11]方向垂直的剖面，包含集电极层103、基极层104以及发射极层105的台面为正台面状，形成平缓的斜面。图34A 所示的集电极层103表示底面的外周线。
接下来，对第5实施例的优良效果进行说明。若在接合时对二极管47 施加载荷，则在檐状的部分83容易产生破损。在第5实施例中，发射极层105的外周线(图34A)之中，与形成檐状的部分83的[011]方向平行的边比与形成平缓的斜面的[01-1]方向平行的边短。这样，形成檐状的部分83的区域被限定于较窄的范围。因此，难以产生基于接合时的载荷的破损。
在图34A至图34C的附图中，表示了阳极电极81贯通发射极层105 并与基极层104欧姆连接的例子，但也可以除去发射极层105而将阳极电极81直接形成于基极层104上。在该情况下，由基极层104和集电极层 103的上层部分形成檐状的部分83。
为了提高抑制檐状的部分83的破损的效果，优选使配置有阳极电极 81的台面状部分的上表面的短边的长度为长边的长度的1/2以下。
[第6实施例]
接下来，参照图35A至图35C的附图，对基于第6实施例的半导体装置进行说明。以下，针对与基于第5实施例的半导体装置共通的构成，省略说明。
图35A是基于第6实施例的半导体装置的1个二极管47的俯视图。图35B以及图35C分别是图35A的单点划线35B-35B以及单点划线 35C-35C处的剖视图。在第5实施例中，发射极层105以及集电极层103 (图34A)的平面形状为长方形。在第6实施例中，发射极层105以及集电极层103的平面形状为包含与[01-1]方向平行的边、与[001]方向平行的边以及与[010]方向平行的边的多边形，例如平行六边形。
如图35B所示，在相对于与[01-1]方向平行的边垂直交叉的剖面，包含集电极层103、基极层104以及发射极层105的台面的形状与图34C 所示的第5实施例的剖面同样地，为正台面状。如图35A所示，集电极层 103的底面比发射极层105的底面更向[011]方向以及[0-1-1]方向扩展。
如图35C所示，在与平行于[010]方向的边交叉的剖面，包含集电极层103、基极层104以及发射极层105的台面的侧面为垂直竖立的形状。在与平行于[001]方向的边交叉的剖面也相同。
在第6实施例中，在包含二极管47的集电极层103、基极层104以及发射极层105的台面不形成檐状的部分。因此，可得到难以产生基于接合时的载荷的破损的效果。
[第7实施例]
接下来，参照图36A以及图36B，对基于第7实施例的半导体装置进行说明。以下，针对与基于第6实施例的半导体装置共通的构成，省略说明。
图36A是基于第7实施例的半导体装置的1个二极管47的俯视图。在第6实施例中，发射极层105的平面形状为平行六边形(图35A)，但在第7实施例中，是具有与[010]方向平行的边以及与[001]方向平行的边的正方形。
图36B是图36A的单点划线36B-36B中的剖视图。在与平行于[010] 方向的边交叉的剖面，包含集电极层103、基极层104以及发射极层105 的台面的侧面为垂直竖直的形状。在与平行于[001]方向的边交叉的剖面也相同。
如上述那样，在第7实施例中，包含集电极层103、基极层104以及发射极层105的台面的全部侧面为垂直竖直的形状，不形成檐状的部分。由此，可得到难以产生基于接合时的载荷的破损的效果。
[第8实施例]
接下来，参照图37来对基于第8实施例的功率放大器模块进行说明。该功率放大器模块搭载了基于从上述的第1实施例至第7实施例的任意一个实施例的半导体装置。
图37是基于第8实施例的功率放大器模块的剖视图。在印刷布线基板200安装有半导体装置500、硅半导体芯片230以及其他多个表面安装型元件。对于半导体装置500，使用基于第1实施例至第7实施例的任意一个实施例的半导体装置。在硅半导体芯片230例如形成CMOS电路。
半导体装置500的背面电极45经由导电性粘接剂221而被固定于印刷布线基板200的下垫板201并且被电连接。硅半导体芯片230经由导电性粘接剂231而被固定于印刷布线基板200的下垫板202。在下垫板201、 202的最表面形成Au膜。作为导电性粘接剂221、231，例如能够使用以使银(Ag)微粒子分散的环氧树脂为主成分的粘接剂。另外，除了环氧树脂，也可以使用丙烯酸树脂、双马来酰亚胺树脂、丁二烯树脂、硅酮树脂或者将这些树脂而成的混合树脂。
半导体装置500的多个接合焊盘140与印刷布线基板200的接合焊盘 203通过多个接合线225而被连接。作为接合线225，例如能够使用直径 20μm的Au线。接合线225使用引线接合器来与接合焊盘140、203接合。
硅半导体芯片230的多个接合焊盘232分别通过多个接合线235来与印刷布线基板200的多个接合焊盘204连接。
半导体装置500、硅半导体芯片230、其他表面安装型元件、接合线 225、235被密封用固化树脂240密封。
在第8实施例中，作为半导体装置500，使用基于第1实施例至第7 实施例的任意一个实施例的半导体装置，因此能够实现半导体装置500的小型化。进一步地，能够抑制接合时的半导体装置500的损伤。由此，提供一种可靠性高的功率放大器模块。
上述的各实施例是示例，当然可以进行不同实施例中所示的结构的局部置换或者组合。针对基于多个实施例的相同结构的相同的作用效果，不按照每个实施例来依次提及。进一步地，本发明并不局限于上述的实施例。本领域的技术人员应当清楚，例如能够进行各种变更、改进、组合等。

Claims (8)

1.一种半导体装置，具有：
电路元件，形成在包含化合物半导体的基板上；和
接合焊盘，在所述电路元件上，被配置为与所述电路元件至少局部重叠，
所述接合焊盘包含第1金属膜、形成于所述第1金属膜上的第2金属膜以及形成于所述第2金属膜上的第3金属膜，
所述第2金属膜的金属材料的杨氏模量比所述第1金属膜的金属材料的杨氏模量大，且所述第2金属膜的厚度为所述第1金属膜的厚度以上，
所述第3金属膜由与所述第1金属膜相同的金属材料形成，
在所述第1金属膜上进一步具有保护膜，所述保护膜具有在俯视情况下被配置于所述第1金属膜的内侧的开口，所述第2金属膜以及所述第3金属膜在俯视情况下被配置于所述开口的内侧，
所述半导体装置进一步具有第4金属膜，所述第4金属膜覆盖所述开口的内侧的所述第1金属膜的上表面之中未被所述第2金属膜覆盖的区域、所述第2金属膜的侧面以及所述第3金属膜的侧面和上表面，并且由与所述第1金属膜相同的金属材料形成。
2.根据权利要求1所述的半导体装置，其中，
所述第1金属膜以及所述第3金属膜由Au形成，
所述第2金属膜具有包含至少1种金属材料的层，所述至少1种金属材料是从包含Cu、Ni以及Mo的群选出的。
3.根据权利要求2所述的半导体装置，其中，
所述第2金属膜具有包含至少2种金属材料的2层，所述至少2种金属材料是从包含Cu、Ni以及Mo的群选出的。
4.根据权利要求1至3中任一项所述的半导体装置，其中，
所述基板的化合物半导体具有闪锌矿型结晶构造，所述基板的上表面是从(100)面起的偏离角为4°以下的面，
所述电路元件是从包含异质结双极晶体管、场效应晶体管、二极管、电容器以及电阻元件的群选出的1个元件。
5.根据权利要求4所述的半导体装置，其中，
所述电路元件具有包含从所述基板外延生长的半导体层的台面构造，所述台面构造的上表面的平面形状是包含与[01-1]方向平行的边和与[011]方向平行的边的长方形或者正方形，与[011]方向平行的边比与[01-1]方向平行的边短。
6.根据权利要求4所述的半导体装置，其中，
所述电路元件具有包含从所述基板外延生长的半导体层的台面构造，所述台面构造的上表面的平面形状是包含与[001]方向平行的边以及与[010]方向平行的边的多边形。
7.根据权利要求6所述的半导体装置，其中，
所述台面构造的上表面的平面形状是还包含与[01-1]方向平行的边的平行六边形。
8.一种功率放大器模块，具有：
半导体装置，所述半导体装置包含：具有形成于包含化合物半导体的基板上的异质结双极晶体管的功率放大电路、连接在所述异质结双极晶体管的发射极-集电极间的保护电路、以及作为所述功率放大电路的输出端子的接合焊盘，构成所述功率放大电路以及所述保护电路的至少1个电路元件与所述接合焊盘被配置为局部重叠，所述接合焊盘包含第1金属膜、形成于所述第1金属膜上的第2金属膜以及形成于所述第2金属膜上的第3金属膜，所述第2金属膜的金属材料的杨氏模量比所述第1金属膜的金属材料的杨氏模量大，且所述第2金属膜的厚度为所述第1金属膜的厚度以上，所述第3金属膜由与所述第1金属膜相同的金属材料形成，在所述第1金属膜上进一步具有保护膜，所述保护膜具有在俯视情况下被配置于所述第1金属膜的内侧的开口，所述第2金属膜以及所述第3金属膜在俯视情况下被配置于所述开口的内侧，所述半导体装置进一步具有第4金属膜，所述第4金属膜覆盖所述开口的内侧的所述第1金属膜的上表面之中未被所述第2金属膜覆盖的区域、所述第2金属膜的侧面以及所述第3金属膜的侧面和上表面，并且由与所述第1金属膜相同的金属材料形成；
印刷布线基板，安装所述半导体装置；和
接合线，与所述接合焊盘接合，将所述接合焊盘与所述印刷布线基板的布线连接。
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