JP3398609B2 - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP3398609B2 JP3398609B2 JP33863998A JP33863998A JP3398609B2 JP 3398609 B2 JP3398609 B2 JP 3398609B2 JP 33863998 A JP33863998 A JP 33863998A JP 33863998 A JP33863998 A JP 33863998A JP 3398609 B2 JP3398609 B2 JP 3398609B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- electrode pad
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 54
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 11
- 238000007772 electroless plating Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- GEHJYWRUCIMESM-UHFFFAOYSA-L sodium sulfite Chemical compound [Na+].[Na+].[O-]S([O-])=O GEHJYWRUCIMESM-UHFFFAOYSA-L 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005844 autocatalytic reaction Methods 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 1
- 235000010265 sodium sulphite Nutrition 0.000 description 1
Classifications
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- Engineering & Computer Science (AREA)
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- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
るもので、更に詳しくは、エリアパッド方式の半導体装
置に関するものである。
子上に形成し、電極パッドのみに専有される領域を無く
すことによって、チップサイズの縮小化を図ったエリア
パッド方式のチップが実用化されつつある。この半導体
チップの電極パッド部分は図5に示すように、半導体基
板21上に絶縁膜22、1層目配線及び能動素子23、
層間絶縁膜24、電極パッド25及び開口部を有する保
護膜26がこの順に形成される構造となっている。この
場合、電極パッド25直下に層間絶縁膜24を介して配
線及び能動素子23が形成されているために、ワイヤー
ボンディング時に配線及び能動素子23へのダメージや
層間絶縁膜24のクラックが発生する。
439号公報には図4に示すように層間絶縁膜をプラズ
マ窒化膜31と気相成長酸化膜32と不純物を含んだ気
相成長酸化膜33の3層にすることにより、カバレッジ
が良く、ワイヤーボンディングにも十分耐え得る強度を
持つ構造が開示されている。尚、図4及び図5におい
て、21は半導体基板、22は酸化膜、23は配線及び
能動素子、24は層間絶縁膜、25は電極パッド、26
は保護膜、31はプラズマ窒化膜、32は気相成長酸化
膜、33は不純物を含んだ気相成長酸化膜、34は電極
パッドと密着性の高い絶縁膜を示す。
たTCP品においても、テープキャリアのインアーリー
ドとのボンディング時に電極パッド下にダメージが入
り、パッド剥がれが生じる。
については、特開平8−264541号公報等により開
示されているが、電極パッドの下に、層間絶縁膜を介し
て配線あるいは能動素子が存在する構造は開示されてい
ない。
対策を行った場合、ウエハ製造工程の大幅な変更が必要
となり、製造工程が複雑となる。多種多様のデバイスに
適用するにはそれぞれのプロセス毎に層間膜の変更が必
要となるが、層間膜の変更はデバイスの品質や特性への
影響もあり、容易に変更は困難である。
出来上がりの質の管理は困難であり、管理を行う場合に
は、ウエハを破壊して断面を確認する必要があり、コス
トの増加の要因となる。また、層間膜や電極パッドの密
着性を測定することは困難であり、何らかのトラブルが
発生した場合でも、実際にアセンブリを行うまで発覚せ
ず、そのまま市場に流れてトラブルを生じる恐れもあ
る。
基板上に配線又は能動素子が形成され、層間絶縁膜を介
して該配線又は能動素子上に電極パッドが形成されてい
る半導体装置において、上記電極パッド表面上に、外部
端子とのボンディング時の上記配線又は能動素子の保護
のための突起電極を形成し、該突起電極がNi,Cu,
Cu合金又はNi合金からなり、突起電極の高さが0.
5μm以上10μm以下であることを特徴とするもので
ある。
なる群のうちのすくなくとも1つの材質からなる表面膜
を有することが好ましい。
成領域内のみに形成されていることが好ましい。
μm以下であることが好ましい。 本発明の半導体装置
は、他の局面では、基板上に配線又は能動素子が形成さ
れ、層間絶縁膜を介して該配線又は能動素子上に電極パ
ッドが形成されている半導体装置であって、電極パッド
表面上に、外部端子とのボンディング時における配線又
は能動素子の保護のための突起電極を形成し、上記突起
電極が、NiPからなり、該突起電極の高さが、0.5
μm以上10μm以下である。
発明を詳細に説明する。
構造を示す断面図であり、1は半導体基板、2は酸化
膜、3は配線及び能動素子、4は層間絶縁膜、5は電極
パッド、6は保護膜、7はNiP層(突起電極)、8は
Au層(表面膜)を示す。
膜2、1層目配線及び能動素子3、層間絶縁膜4、電極
パッド5及び開口部を有する保護膜6がこの順に形成さ
れ、開口部に、高さ5μmの突起電極としてのNiP層
(P含有量は7〜11%)7と厚さ1μmの突起電極の
表面を保護するための表面膜としてのAu層8がこの順
に形成されている。また、NiP層7及びAu層8を無
電解メッキ方式によって形成した。ワイヤーボンディン
グやインナーリードボンディング時の衝撃に対抗するに
は、NiP層の高さは0.5μm以上必要であり、Ni
P層形成時間を短縮するために、10μm以下が好まし
い。尚、NiP層の他に、Ni、Cu、Ni合金、Cu
合金を用いても同様である。
めに、Au層8の厚さは0.05μm以上であればよ
く、また、Snとの共晶接合に使用する場合でも2μm
あれば十分であるため、Au層の形成時間短縮を併せ
て、Au層の厚さは0.05μm以上、且つ2μm以下
が好ましい。尚、Au層の他に、PtやAg等の貴金属
を用いても同様である。
法を以下に説明する。
出した電極パッド5表面上のAlをNiと置換反応が可
能なZnに置換させる。次に、メッキ液中に浸液し、N
iP層7を保護膜6から5μmになるまで、無電解メッ
キにて形成する。この無電解メッキによるNiPの析出
が選択性がある。
n層がNiと置換反応を起こしてNi層が形成され、続
いて自己触媒作用により、Ni層の表面上で無電解メッ
キ反応が進行する。よって、メッキ用のレジストパター
ンを形成する必要はなく、また、無電解メッキであるの
で、ウエハ表面にメッキ用の導電膜を形成する必要もな
い。
酸ニッケル及び次亜リン酸ナトリウムを主成分とした一
般的なものである。
る。まず、置換Auメッキ液を用いて、NiP層7表面
上のNiをAuと置換させる。この反応は置換反応であ
り、形成できるAu層8の厚さは、0.1μm以下であ
るが、Au層8の形成がNi表面の保護を目的とするの
であれば、十分である。更に、Au層8の厚さが1μm
になるまで無電解Auメッキを行う。無電解Auメッキ
液には、亜硫酸Auナトリウムを主成分としたものを用
いる。
を覆っており、且つ、電極パッド5形成領域からはみ出
ない構造とした。この構造により、Au層8によって保
護されたNiP層7が保護開口部を覆うため、電極パッ
ド5を腐食等から保護する効果がある。また、NiP層
7を電極パッド5からはみ出さない構造とすることによ
り、応力を緩和することができ、パッド剥がれや下地半
導体基板のえぐれを防止することができる。
びその下地の強度を測定することができるため、密着性
の管理を行うことができる。
面図である。半導体チップは半導体基板1上に絶縁膜
2、1層目配線及び能動素子3、層間絶縁膜4、電極パ
ッド5及び開口部を有する保護膜6がこの順に形成さ
れ、開口部にNiP層(P含有量は7〜11%)7とA
u層8がこの順に形成されている。
バイスホールを有する絶縁性フィルム上に導体パターン
が接着剤を介して接着形成され、上記デバイスホールに
は上記導体パターンと一体に形成される導体パターンが
延長突出しており、導体リード9にはSnメッキが施さ
れている。
ャリアとの間の接合を電極パッド5上のAu層8と導体
リード9のSn層を熱圧着することにより、Au−Sn
共晶を形成して行っている。
し、電極パッド及び下地の様子を確認したが、荷重が1
電極当たり50g重、温度が560℃の条件でもダメー
ジが発生していなかった。Auのみで形成された突起電
極に同じ条件を適用した場合、電極パッド及び下地に確
実にダメージが入ることが確認されている。
クモールドパッケージや基板(プリント基板やセラミッ
ク基板)(図示せず)に実装した時の実装部の断面図で
ある。このように、突起電極上にワイヤー10をボンデ
ィングした場合も、TCPと同様に、電極パッド5及び
下地にワイヤーボンディングによるダメージが入らない
効果を得ることができる。本発明では、硬い突起電極を
Ni系金属で形成した例を示したが、他に無電解メッキ
方式で形成できる硬質突起電極材料としてCu系金属で
も同様なものが形成可能である。
用いることにより、電極パッド上にワイヤーボンディン
グやインナーリードボンディングを行っても、突起電極
がワイヤーボンディングやインナーリードボンディング
時の衝撃に対抗するため、電極パッドやその下の層間絶
縁膜、配線層及び能動素子へのダメージが生じず、アセ
ンブリでの歩留まりの向上及び接続の信頼性の向上が可
能となる。電極パッド上の保護膜開口部に硬い突起電極
を形成することにより、横方向の剪断強度(シェア強
度)測定や密着強度検査が可能なり、アセンブリ前に密
着性の確認が可能となる。従来は突起電極がないので、
パッドやパッド下部分の密着強度を測定する引っ掛かり
がなく、測定することが物理的に不可能であった。突起
電極を形成することにより、シェア強度測定用ツール等
を引っかけて測定することが可能となる。
びAu層からなる表面膜を形成することにより、突起電
極の表面酸化を防止し、且つ、Au層はSnとの共晶接
合に使用しても問題を生じない。
i合金層やAg層、Pt層及びAu層は、無電解メッキ
法により形成することが可能であるから、電解メッキ方
式による複雑な工程を必要としない。
形成することによって、突起電極からの応力による電極
パッドの剥がれや下地の半導体基板の抉れを防止でき
る。
断面図である。
パッド断面構造を示す断面図である。
パッケージや基板(プリント基板やセラミック基板)に
実装した時のパッド断面構造を示す断面図である。
断面図である。
断面図である。
Claims (5)
- 【請求項1】 基板上に配線又は能動素子が形成され、 層間絶縁膜を介して該配線又は能動素子上に電極パッド
が形成されている半導体装置において、前 記電極パッド表面上に、外部端子とのボンディング時
における前記配線又は能動素子の保護のための突起電極
を形成し、 前記突起電極が、Ni,Cu,Cu合金又はNi合金か
らなり、 前記突起電極の高さが、0.5μm以上10μm以下で
ある、 半導体装置。 - 【請求項2】 前記突起電極が、Au,PtおよびAg
からなる群のうちの少なくとも1つの材質からなる表面
膜を有する、請求項1に記載の半導体装置。 - 【請求項3】 前記突起電極が、前記電極パッド形成領
域内のみに形成されている、請求項1または請求項2に
記載の半導体装置。 - 【請求項4】 前記表面膜の厚さが、0.05μm以上
2μm以下である、請求項2に記載の半導体装置。 - 【請求項5】 基板上に配線又は能動素子が形成され、 層間絶縁膜を介して該配線又は能動素子上に電極パッド
が形成されている半導体装置において、 前記電極パッド表面上に、外部端子とのボンディング時
における前記配線又は能動素子の保護のための突起電極
を形成し、 前記突起電極が、NiPからなり、 前記突起電極の高さが、0.5μm以上10μm以下で
ある、 半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33863998A JP3398609B2 (ja) | 1998-11-30 | 1998-11-30 | 半導体装置 |
EP99309158A EP1006576B1 (en) | 1998-11-30 | 1999-11-17 | Semiconductor device |
TW088120029A TW440962B (en) | 1998-11-30 | 1999-11-17 | Semiconductor device |
DE69912565T DE69912565T2 (de) | 1998-11-30 | 1999-11-17 | Halbleiteranordnung |
KR1019990052984A KR100356770B1 (ko) | 1998-11-30 | 1999-11-26 | 반도체장치 |
US09/449,864 US20020056901A1 (en) | 1998-11-30 | 1999-11-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33863998A JP3398609B2 (ja) | 1998-11-30 | 1998-11-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000164623A JP2000164623A (ja) | 2000-06-16 |
JP3398609B2 true JP3398609B2 (ja) | 2003-04-21 |
Family
ID=18320076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33863998A Expired - Lifetime JP3398609B2 (ja) | 1998-11-30 | 1998-11-30 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20020056901A1 (ja) |
EP (1) | EP1006576B1 (ja) |
JP (1) | JP3398609B2 (ja) |
KR (1) | KR100356770B1 (ja) |
DE (1) | DE69912565T2 (ja) |
TW (1) | TW440962B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8330255B2 (en) | 2006-10-19 | 2012-12-11 | Panasonic Corporation | Semiconductor chip |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3405697B2 (ja) | 1999-09-20 | 2003-05-12 | ローム株式会社 | 半導体チップ |
KR100385165B1 (ko) * | 2000-09-25 | 2003-05-22 | 삼성테크윈 주식회사 | 반도체 패키지와 이의 제조방법 |
EP2273542A3 (en) | 2001-12-14 | 2011-10-26 | STMicroelectronics S.r.l. | Semiconductor electronic device and method of manufacturing thereof |
JP3727272B2 (ja) | 2002-01-15 | 2005-12-14 | 沖電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2003229517A (ja) * | 2002-01-31 | 2003-08-15 | Fujitsu Hitachi Plasma Display Ltd | 半導体チップ実装基板及びフラットディスプレイ |
KR20030094692A (ko) * | 2002-06-07 | 2003-12-18 | 삼성테크윈 주식회사 | 무전해 솔더범프 형성방법 |
JPWO2004059722A1 (ja) * | 2002-12-24 | 2006-05-11 | 株式会社デンソー | 半導体式センサおよび半導体装置のめっき方法 |
WO2004105133A1 (en) * | 2003-05-26 | 2004-12-02 | Axalto Sa | Wire bonding on in-line connection pads |
JP2005116632A (ja) * | 2003-10-03 | 2005-04-28 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
JP4661122B2 (ja) * | 2004-05-18 | 2011-03-30 | ソニー株式会社 | 部品実装配線基板および配線基板への部品の実装方法 |
JP4604641B2 (ja) * | 2004-10-18 | 2011-01-05 | 株式会社デンソー | 半導体装置 |
DE102005028951B4 (de) | 2005-06-22 | 2018-05-30 | Infineon Technologies Ag | Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung |
DE102005033469B4 (de) * | 2005-07-18 | 2019-05-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleitermoduls |
DE102006052202B3 (de) * | 2006-11-06 | 2008-02-21 | Infineon Technologies Ag | Halbleiterbauelement sowie Verfahren zur Herstellung eines Halbleiterbauelements |
KR20100033467A (ko) * | 2007-03-15 | 2010-03-30 | 레르 리키드 쏘시에떼 아노님 뿌르 레드 에렉스뿔라따시옹 데 프로세데 조르즈 클로드 | 평판 디스플레이 제조를 위한 구리 상호접속 |
US8293587B2 (en) | 2007-10-11 | 2012-10-23 | International Business Machines Corporation | Multilayer pillar for reduced stress interconnect and method of making same |
JP4806468B2 (ja) * | 2008-02-29 | 2011-11-02 | 三洋電機株式会社 | 半導体モジュール |
JP4588091B2 (ja) | 2008-02-29 | 2010-11-24 | 三洋電機株式会社 | 半導体モジュールの製造方法 |
JP2009246218A (ja) | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
JP5331610B2 (ja) | 2008-12-03 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP2010141112A (ja) * | 2008-12-11 | 2010-06-24 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
US20120261812A1 (en) * | 2011-04-14 | 2012-10-18 | Topacio Roden R | Semiconductor chip with patterned underbump metallization |
JP2012160739A (ja) * | 2012-03-14 | 2012-08-23 | Renesas Electronics Corp | 半導体装置 |
JP2013229491A (ja) * | 2012-04-26 | 2013-11-07 | Kyocera Corp | 電極構造、半導体素子、半導体装置、サーマルヘッドおよびサーマルプリンタ |
US9576923B2 (en) | 2014-04-01 | 2017-02-21 | Ati Technologies Ulc | Semiconductor chip with patterned underbump metallization and polymer film |
GB2557614A (en) | 2016-12-12 | 2018-06-27 | Infineon Technologies Austria Ag | Semiconductor device, electronic component and method |
JP2018186144A (ja) | 2017-04-25 | 2018-11-22 | 株式会社村田製作所 | 半導体装置及びパワーアンプモジュール |
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JPS528785A (en) * | 1975-07-10 | 1977-01-22 | Citizen Watch Co Ltd | Semiconductor device electrode structure |
JPH0214527A (ja) * | 1988-11-11 | 1990-01-18 | Seiko Epson Corp | Mos型半導体装置 |
JPH02296336A (ja) * | 1989-05-10 | 1990-12-06 | Seiko Epson Corp | 半導体回路バンプの製造方法 |
DE69330603T2 (de) * | 1993-09-30 | 2002-07-04 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | Verfahren zur Metallisierung und Verbindung bei der Herstellung von Leistungshalbleiterbauelementen |
-
1998
- 1998-11-30 JP JP33863998A patent/JP3398609B2/ja not_active Expired - Lifetime
-
1999
- 1999-11-17 DE DE69912565T patent/DE69912565T2/de not_active Expired - Lifetime
- 1999-11-17 TW TW088120029A patent/TW440962B/zh not_active IP Right Cessation
- 1999-11-17 EP EP99309158A patent/EP1006576B1/en not_active Expired - Lifetime
- 1999-11-26 KR KR1019990052984A patent/KR100356770B1/ko not_active IP Right Cessation
- 1999-11-29 US US09/449,864 patent/US20020056901A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8330255B2 (en) | 2006-10-19 | 2012-12-11 | Panasonic Corporation | Semiconductor chip |
Also Published As
Publication number | Publication date |
---|---|
EP1006576B1 (en) | 2003-11-05 |
TW440962B (en) | 2001-06-16 |
DE69912565D1 (de) | 2003-12-11 |
EP1006576A1 (en) | 2000-06-07 |
US20020056901A1 (en) | 2002-05-16 |
KR100356770B1 (ko) | 2002-10-19 |
JP2000164623A (ja) | 2000-06-16 |
DE69912565T2 (de) | 2004-09-16 |
KR20000035730A (ko) | 2000-06-26 |
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