DE69912565D1 - Halbleiteranordnung - Google Patents

Halbleiteranordnung

Info

Publication number
DE69912565D1
DE69912565D1 DE69912565T DE69912565T DE69912565D1 DE 69912565 D1 DE69912565 D1 DE 69912565D1 DE 69912565 T DE69912565 T DE 69912565T DE 69912565 T DE69912565 T DE 69912565T DE 69912565 D1 DE69912565 D1 DE 69912565D1
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DE
Germany
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69912565T
Other languages
English (en)
Other versions
DE69912565T2 (de
Inventor
Atsushi Ono
Yasunori Chikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69912565D1 publication Critical patent/DE69912565D1/de
Application granted granted Critical
Publication of DE69912565T2 publication Critical patent/DE69912565T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69912565T 1998-11-30 1999-11-17 Halbleiteranordnung Expired - Lifetime DE69912565T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP33863998A JP3398609B2 (ja) 1998-11-30 1998-11-30 半導体装置
JP33863998 1998-11-30

Publications (2)

Publication Number Publication Date
DE69912565D1 true DE69912565D1 (de) 2003-12-11
DE69912565T2 DE69912565T2 (de) 2004-09-16

Family

ID=18320076

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69912565T Expired - Lifetime DE69912565T2 (de) 1998-11-30 1999-11-17 Halbleiteranordnung

Country Status (6)

Country Link
US (1) US20020056901A1 (de)
EP (1) EP1006576B1 (de)
JP (1) JP3398609B2 (de)
KR (1) KR100356770B1 (de)
DE (1) DE69912565T2 (de)
TW (1) TW440962B (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3405697B2 (ja) 1999-09-20 2003-05-12 ローム株式会社 半導体チップ
KR100385165B1 (ko) * 2000-09-25 2003-05-22 삼성테크윈 주식회사 반도체 패키지와 이의 제조방법
EP2273542A3 (de) 2001-12-14 2011-10-26 STMicroelectronics S.r.l. Elektronische Halbleitervorrichtung und Verfahren zu deren Herstellung
JP3727272B2 (ja) 2002-01-15 2005-12-14 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2003229517A (ja) * 2002-01-31 2003-08-15 Fujitsu Hitachi Plasma Display Ltd 半導体チップ実装基板及びフラットディスプレイ
KR20030094692A (ko) * 2002-06-07 2003-12-18 삼성테크윈 주식회사 무전해 솔더범프 형성방법
JPWO2004059722A1 (ja) * 2002-12-24 2006-05-11 株式会社デンソー 半導体式センサおよび半導体装置のめっき方法
WO2004105133A1 (en) * 2003-05-26 2004-12-02 Axalto Sa Wire bonding on in-line connection pads
JP2005116632A (ja) * 2003-10-03 2005-04-28 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP4661122B2 (ja) * 2004-05-18 2011-03-30 ソニー株式会社 部品実装配線基板および配線基板への部品の実装方法
JP4604641B2 (ja) * 2004-10-18 2011-01-05 株式会社デンソー 半導体装置
DE102005028951B4 (de) 2005-06-22 2018-05-30 Infineon Technologies Ag Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung
DE102005033469B4 (de) * 2005-07-18 2019-05-09 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleitermoduls
JP2008124437A (ja) 2006-10-19 2008-05-29 Matsushita Electric Ind Co Ltd 半導体ウェハ、その製造方法、および半導体チップの製造方法
DE102006052202B3 (de) * 2006-11-06 2008-02-21 Infineon Technologies Ag Halbleiterbauelement sowie Verfahren zur Herstellung eines Halbleiterbauelements
KR20100033467A (ko) * 2007-03-15 2010-03-30 레르 리키드 쏘시에떼 아노님 뿌르 레드 에렉스뿔라따시옹 데 프로세데 조르즈 클로드 평판 디스플레이 제조를 위한 구리 상호접속
US8293587B2 (en) 2007-10-11 2012-10-23 International Business Machines Corporation Multilayer pillar for reduced stress interconnect and method of making same
JP4806468B2 (ja) * 2008-02-29 2011-11-02 三洋電機株式会社 半導体モジュール
JP4588091B2 (ja) 2008-02-29 2010-11-24 三洋電機株式会社 半導体モジュールの製造方法
JP2009246218A (ja) 2008-03-31 2009-10-22 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP5331610B2 (ja) 2008-12-03 2013-10-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP2010141112A (ja) * 2008-12-11 2010-06-24 Sharp Corp 半導体装置および半導体装置の製造方法
US20120261812A1 (en) * 2011-04-14 2012-10-18 Topacio Roden R Semiconductor chip with patterned underbump metallization
JP2012160739A (ja) * 2012-03-14 2012-08-23 Renesas Electronics Corp 半導体装置
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JP3398609B2 (ja) 2003-04-21
TW440962B (en) 2001-06-16
EP1006576A1 (de) 2000-06-07
US20020056901A1 (en) 2002-05-16
KR100356770B1 (ko) 2002-10-19
JP2000164623A (ja) 2000-06-16
DE69912565T2 (de) 2004-09-16
KR20000035730A (ko) 2000-06-26

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