DE69617391D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69617391D1
DE69617391D1 DE69617391T DE69617391T DE69617391D1 DE 69617391 D1 DE69617391 D1 DE 69617391D1 DE 69617391 T DE69617391 T DE 69617391T DE 69617391 T DE69617391 T DE 69617391T DE 69617391 D1 DE69617391 D1 DE 69617391D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69617391T
Other languages
English (en)
Other versions
DE69617391T2 (de
Inventor
Yasuo Suminaga
Koji Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69617391D1 publication Critical patent/DE69617391D1/de
Publication of DE69617391T2 publication Critical patent/DE69617391T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/126—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
DE69617391T 1996-03-22 1996-07-03 Halbleiterspeicheranordnung Expired - Lifetime DE69617391T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06687796A JP3380107B2 (ja) 1996-03-22 1996-03-22 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69617391D1 true DE69617391D1 (de) 2002-01-10
DE69617391T2 DE69617391T2 (de) 2002-07-11

Family

ID=13328553

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69617391T Expired - Lifetime DE69617391T2 (de) 1996-03-22 1996-07-03 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (2) US5726929A (de)
EP (1) EP0797214B1 (de)
JP (1) JP3380107B2 (de)
KR (1) KR100214814B1 (de)
DE (1) DE69617391T2 (de)
TW (1) TW399214B (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0172378B1 (ko) * 1995-12-30 1999-03-30 김광호 불휘발성 반도체 메모리소자
JP3211745B2 (ja) * 1997-09-18 2001-09-25 日本電気株式会社 半導体記憶装置
JP3638211B2 (ja) * 1998-06-17 2005-04-13 株式会社 沖マイクロデザイン データ書き込み回路
DE69830050D1 (de) 1998-07-29 2005-06-09 Macronix Int Co Ltd Verfahren und integrierter Schaltkreis für eine Mehrwert-Speicherzelle
US6278649B1 (en) 2000-06-30 2001-08-21 Macronix International Co., Ltd. Bank selection structures for a memory array, including a flat cell ROM array
US6492930B2 (en) * 2000-08-14 2002-12-10 Intersil Americas Inc. Reduced propagation delay current mode cascaded analog-to-digital converter and threshold bit cell therefor
US6301172B1 (en) * 2001-02-27 2001-10-09 Micron Technology, Inc. Gate voltage testkey for isolation transistor
KR100416599B1 (ko) * 2001-05-31 2004-02-05 삼성전자주식회사 집적도와 독출동작 속도를 향상시키고 전력소모를감소시킬 수 있는 메탈 프로그래머블 롬의 메모리셀 구조
JP4072127B2 (ja) 2002-02-20 2008-04-09 株式会社ルネサステクノロジ 半導体集積回路
US6563735B1 (en) * 2002-04-04 2003-05-13 Macronix International Co., Ltd. NOR-structured semiconductor memory device
JP2004158119A (ja) * 2002-11-06 2004-06-03 Sharp Corp 不揮発性半導体記憶装置
JP4278140B2 (ja) 2003-09-03 2009-06-10 シャープ株式会社 半導体記憶装置
US6980456B2 (en) * 2004-03-08 2005-12-27 Macronix International Co., Ltd. Memory with low and fixed pre-charge loading
NZ555325A (en) * 2004-10-27 2009-07-31 Daiichi Sankyo Co Ltd Benzene compound having 2 or more substituents
FR2881565B1 (fr) * 2005-02-03 2007-08-24 Atmel Corp Circuits de selection de ligne binaire pour memoires non volatiles
US7508713B2 (en) * 2007-03-29 2009-03-24 Sandisk Corporation Method of compensating variations along a word line in a non-volatile memory
US7577031B2 (en) * 2007-03-29 2009-08-18 Sandisk Corporation Non-volatile memory with compensation for variations along a word line
JP4504397B2 (ja) * 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
US7643367B2 (en) * 2007-08-15 2010-01-05 Oki Semiconductor Co., Ltd. Semiconductor memory device
JP2009301691A (ja) * 2008-06-17 2009-12-24 Renesas Technology Corp 不揮発性半導体記憶装置
WO2015182100A1 (ja) 2014-05-26 2015-12-03 パナソニックＩｐマネジメント株式会社 半導体記憶装置
WO2020104890A1 (ja) * 2018-11-22 2020-05-28 株式会社半導体エネルギー研究所 半導体装置および電池パック
CN112802523B (zh) * 2019-11-14 2024-07-19 力旺电子股份有限公司 只读式存储单元及其相关的存储单元阵列

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0752758B2 (ja) * 1988-03-28 1995-06-05 シャープ株式会社 半導体読出し専用メモリ
JPH02252194A (ja) * 1989-03-25 1990-10-09 Sony Corp 半導体メモリ装置
JP2565213B2 (ja) * 1989-10-27 1996-12-18 ソニー株式会社 読み出し専用メモリ装置
US5467300A (en) * 1990-06-14 1995-11-14 Creative Integrated Systems, Inc. Grounded memory core for Roms, Eproms, and EEpproms having an address decoder, and sense amplifier
JP2624569B2 (ja) * 1990-10-22 1997-06-25 シャープ株式会社 読出し専用メモリ
JPH04311900A (ja) * 1991-04-10 1992-11-04 Sharp Corp 半導体読み出し専用メモリ
JP2863661B2 (ja) * 1991-12-16 1999-03-03 株式会社東芝 読出専用メモリ
JPH05283654A (ja) * 1992-04-03 1993-10-29 Toshiba Corp マスクｒｏｍとその製造方法
JP2845414B2 (ja) * 1992-09-18 1999-01-13 シャープ株式会社 半導体読み出し専用メモリ
JPH06318683A (ja) * 1993-05-01 1994-11-15 Toshiba Corp 半導体記憶装置及びその製造方法
JPH07230696A (ja) * 1993-12-21 1995-08-29 Toshiba Corp 半導体記憶装置
US5557124A (en) * 1994-03-11 1996-09-17 Waferscale Integration, Inc. Flash EEPROM and EPROM arrays with select transistors within the bit line pitch

Also Published As

Publication number Publication date
EP0797214A3 (de) 1999-03-31
KR970067340A (ko) 1997-10-13
KR100214814B1 (ko) 1999-08-02
DE69617391T2 (de) 2002-07-11
JP3380107B2 (ja) 2003-02-24
EP0797214A2 (de) 1997-09-24
US5812440A (en) 1998-09-22
EP0797214B1 (de) 2001-11-28
JPH09259594A (ja) 1997-10-03
US5726929A (en) 1998-03-10
TW399214B (en) 2000-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition