DE69422901D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69422901D1
DE69422901D1 DE69422901T DE69422901T DE69422901D1 DE 69422901 D1 DE69422901 D1 DE 69422901D1 DE 69422901 T DE69422901 T DE 69422901T DE 69422901 T DE69422901 T DE 69422901T DE 69422901 D1 DE69422901 D1 DE 69422901D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69422901T
Other languages
English (en)
Other versions
DE69422901T2 (de
Inventor
Tetsuji Nakakuma
Tatsumi Sumi
Hiroshige Hirano
George Nakane
Nobuyuki Moriwaki
Toshio Mukunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69422901D1 publication Critical patent/DE69422901D1/de
Application granted granted Critical
Publication of DE69422901T2 publication Critical patent/DE69422901T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2273Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
DE69422901T 1994-02-15 1994-11-07 Halbleiterspeicheranordnung Expired - Fee Related DE69422901T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01826894A JP3191549B2 (ja) 1994-02-15 1994-02-15 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69422901D1 true DE69422901D1 (de) 2000-03-09
DE69422901T2 DE69422901T2 (de) 2000-07-27

Family

ID=11966916

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69422901T Expired - Fee Related DE69422901T2 (de) 1994-02-15 1994-11-07 Halbleiterspeicheranordnung

Country Status (7)

Country Link
US (1) US5515312A (de)
EP (1) EP0667620B1 (de)
JP (1) JP3191549B2 (de)
KR (1) KR100199786B1 (de)
CN (1) CN1096680C (de)
DE (1) DE69422901T2 (de)
TW (1) TW248603B (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953316B2 (ja) * 1994-08-12 1999-09-27 日本電気株式会社 不揮発性強誘電体メモリ
US5798964A (en) * 1994-08-29 1998-08-25 Toshiba Corporation FRAM, FRAM card, and card system using the same
JP3186485B2 (ja) * 1995-01-04 2001-07-11 日本電気株式会社 強誘電体メモリ装置およびその動作制御方法
JP2748873B2 (ja) * 1995-01-04 1998-05-13 日本電気株式会社 強誘電体メモリ装置およびその動作制御方法
JPH08194679A (ja) * 1995-01-19 1996-07-30 Texas Instr Japan Ltd ディジタル信号処理方法及び装置並びにメモリセル読出し方法
US5764561A (en) * 1995-11-16 1998-06-09 Rohm Co., Ltd. Ferroelectric memory devices and method of using ferroelectric capacitors
US6330178B1 (en) 1996-02-28 2001-12-11 Hitachi, Ltd. Ferroelectric memory device
WO1997032311A1 (fr) * 1996-02-28 1997-09-04 Hitachi, Ltd. Memoire ferroelectrique
JPH09288891A (ja) * 1996-04-19 1997-11-04 Matsushita Electron Corp 半導体メモリ装置
KR100295568B1 (ko) * 1997-02-03 2001-09-07 니시무로 타이죠 반도체 장치 및 그의 제조방법
US5911081A (en) * 1997-05-05 1999-06-08 Sun Microsystems, Inc. Method and apparatus for selectively inhibiting power shutdowns based upon the number of power shutdowns that an electrical device has been experienced
US6294439B1 (en) 1997-07-23 2001-09-25 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US5880989A (en) * 1997-11-14 1999-03-09 Ramtron International Corporation Sensing methodology for a 1T/1C ferroelectric memory
US20050122765A1 (en) * 1997-11-14 2005-06-09 Allen Judith E. Reference cell configuration for a 1T/1C ferroelectric memory
US5978251A (en) * 1997-11-14 1999-11-02 Ramtron International Corporation Plate line driver circuit for a 1T/1C ferroelectric memory
US6002634A (en) * 1997-11-14 1999-12-14 Ramtron International Corporation Sense amplifier latch driver circuit for a 1T/1C ferroelectric memory
US5892728A (en) * 1997-11-14 1999-04-06 Ramtron International Corporation Column decoder configuration for a 1T/1C ferroelectric memory
US5986919A (en) * 1997-11-14 1999-11-16 Ramtron International Corporation Reference cell configuration for a 1T/1C ferroelectric memory
US5956266A (en) * 1997-11-14 1999-09-21 Ramtron International Corporation Reference cell for a 1T/1C ferroelectric memory
US6028783A (en) 1997-11-14 2000-02-22 Ramtron International Corporation Memory cell configuration for a 1T/1C ferroelectric memory
US5969980A (en) * 1997-11-14 1999-10-19 Ramtron International Corporation Sense amplifier configuration for a 1T/1C ferroelectric memory
US5995406A (en) * 1997-11-14 1999-11-30 Ramtron International Corporation Plate line segmentation in a 1T/1C ferroelectric memory
KR100282045B1 (ko) * 1998-08-07 2001-03-02 윤종용 강유전체 커패시터를 구비한 불 휘발성 다이나믹 랜덤 엑세스메모리
JP3780713B2 (ja) * 1998-08-25 2006-05-31 富士通株式会社 強誘電体メモリ、強誘電体メモリの製造方法及び強誘電体メモリの試験方法
US6545902B2 (en) 1998-08-28 2003-04-08 Hitachi, Ltd. Ferroelectric memory device
KR100308188B1 (ko) * 1999-04-27 2001-10-29 윤종용 안정된 감지 마진을 가지는 강유전체 랜덤 액세스 메모리
JP2001035817A (ja) 1999-07-22 2001-02-09 Toshiba Corp ウェーハの分割方法及び半導体装置の製造方法
KR100816689B1 (ko) * 2001-12-29 2008-03-27 주식회사 하이닉스반도체 강유전체 메모리 셀어레이
US7972632B2 (en) 2003-02-28 2011-07-05 Unigen Pharmaceuticals, Inc. Identification of Free-B-Ring flavonoids as potent COX-2 inhibitors
EP1631304A4 (de) 2003-04-04 2007-03-21 Unigen Pharmaceuticals Inc Formulierung von dualen cycloxygenase (cox) und lipoxygenase (lox) hemmern für die hautpflege von säugetieren
WO2005091301A1 (ja) * 2004-03-24 2005-09-29 Fujitsu Limited 強誘電体メモリ
JP2010102793A (ja) * 2008-10-24 2010-05-06 Toshiba Corp 半導体記憶装置
KR102059884B1 (ko) * 2012-02-16 2019-12-27 제노 세미컨덕터, 인크. 두개의 트랜지스터로 구성된 메모리셀과 그 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59162695A (ja) * 1983-03-07 1984-09-13 Nec Corp 記憶装置
US4873664A (en) * 1987-02-12 1989-10-10 Ramtron Corporation Self restoring ferroelectric memory
JPH04141897A (ja) * 1990-10-01 1992-05-15 Hitachi Ltd Eeprom装置
US5345414A (en) * 1992-01-27 1994-09-06 Rohm Co., Ltd. Semiconductor memory device having ferroelectric film
US5381379A (en) * 1992-12-03 1995-01-10 Sharp Kabushiki Kaisha Non-volatile dynamic random access memory device; a page store device and a page recall device used in the same; and a page store method and a page recall method

Also Published As

Publication number Publication date
EP0667620B1 (de) 2000-02-02
KR950025778A (ko) 1995-09-18
EP0667620A2 (de) 1995-08-16
CN1096680C (zh) 2002-12-18
KR100199786B1 (ko) 1999-06-15
DE69422901T2 (de) 2000-07-27
CN1115099A (zh) 1996-01-17
JP3191549B2 (ja) 2001-07-23
JPH07226087A (ja) 1995-08-22
US5515312A (en) 1996-05-07
TW248603B (en) 1995-06-01
EP0667620A3 (de) 1996-02-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee