CN111223920A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN111223920A
CN111223920A CN201911154165.3A CN201911154165A CN111223920A CN 111223920 A CN111223920 A CN 111223920A CN 201911154165 A CN201911154165 A CN 201911154165A CN 111223920 A CN111223920 A CN 111223920A
Authority
CN
China
Prior art keywords
opening
bump
emitter
disposed
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911154165.3A
Other languages
English (en)
Other versions
CN111223920B (zh
Inventor
黑川敦
姬田高志
小林一也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN111223920A publication Critical patent/CN111223920A/zh
Application granted granted Critical
Publication of CN111223920B publication Critical patent/CN111223920B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13051—Heterojunction bipolar transistor [HBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

本发明提供一种能够抑制由凸块上的焊料引起的晶体管的劣化、破坏的半导体装置。在基板上配置有双极晶体管。在基板上配置有绝缘膜，以覆盖双极晶体管。在该绝缘膜上配置有通过设置于绝缘膜的第一开口与双极晶体管的发射极层电连接的发射极布线。在发射极布线上配置有保护膜。在保护膜上，配置有通过设置于保护膜的第二开口与发射极布线电连接的凸块。在俯视时，第二开口包含于凸块的内侧并且第一开口的外侧的区域。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
作为移动电话等移动体通信机的电力放大器的放大元件使用异质结双极晶体管(HBT)。作为将包含HBT的半导体晶片安装于模块基板的方法，使用倒装芯片键合。在下述的专利文献1中公开的半导体装置中，在多个HBT的发射极上设置有凸块。凸块成为将在HBT中产生的热量释放到模块基板的散热路径。
专利文献1：日本特开2016－103540号公报
为了将HBT的发射极电极与发射极布线连接，在配置于两者之间的绝缘膜设置有第一开口。进一步，为了将发射极布线与凸块连接，在配置于两者之间的保护膜设置有第二开口。在专利文献1中公开的半导体装置中，在俯视时第一开口与第二开口部分重叠。
凸块通常包含由高熔点金属等构成的凸块下金属层、金属柱、以及焊料层这3层。在倒装芯片键合工序中，有熔融的焊料侵入凸块下金属层与金属柱的界面，并到达第一开口的正上方的情况。另外，有由于第一开口的边缘的阶梯差，而在凸块下金属层产生裂纹的情况。到达第一开口的正上方的焊料通过该裂纹到达HBT的发射极。其结果，有导致HBT的劣化、破坏的情况。
发明内容
本发明的目的在于提供一种能够抑制由凸块上的焊料引起的晶体管的劣化、破坏的半导体装置。
根据本发明的一个观点，提供一种半导体装置，具有：
基板；
双极晶体管，包含层叠在上述基板上的集电极层、基极层、以及发射极层；
绝缘膜，配置在上述基板上以覆盖上述双极晶体管；
发射极布线，配置在上述绝缘膜上，通过设置于上述绝缘膜的第一开口与上述发射极层电连接；
保护膜，配置在上述发射极布线上；以及
凸块，配置在上述保护膜上，通过设置于上述保护膜的第二开口与上述发射极布线电连接，
在俯视时上述第二开口包含在上述凸块的内侧并且上述第一开口的外侧的区域。
由于在俯视时，第二开口配置于第一开口的外侧，所以即使侵入凸块内的焊料通过由第二开口的边缘引起的裂纹，也难以到达第一开口。因此，能够抑制由凸块上的焊料引起的晶体管的劣化、破坏。
附图说明
图1是表示第一实施例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。
图2是图1的点划线2－2上的剖视图。
图3是表示比较例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。
图4是图3的点划线4－4上的剖视图。
图5是第二实施例的半导体装置的剖视图。
图6是第二实施例的半导体装置的制造中途阶段中的剖视图。
图7是第二实施例的半导体装置的制造中途阶段中的剖视图。
图8是第二实施例的半导体装置的制造中途阶段中的剖视图。
图9是第二实施例的半导体装置的制造中途阶段中的剖视图。
图10是第二实施例的半导体装置的制造中途阶段中的剖视图。
图11是第二实施例的半导体装置的制造中途阶段中的剖视图。
图12A以及图12B分别表示第三实施例及其变形例的半导体装置的第一开口、第二开口、以及凸块在平面上的位置关系的图。
图13是表示第四实施例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。
图14是图13的点划线14－14上的剖视图。
具体实施方式
[第一实施例]
参照图1和图2，对第一实施例的半导体装置进行说明。
图1是表示第一实施例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。将多个例如四个HBT20排列于一列(在图1中为横向)来配置。在本说明书中，将排列多个HBT20的方向称为“排列方向”。
HBT20的每一个的发射极、基极、以及集电极分别与发射极电极21、基极电极22、以及集电极电极23电连接。发射极电极21具有在与HBT20的排列方向正交的方向上较长的几乎长方形的平面形状。在俯视时，基极电极22以朝向与排列方向正交的方向开口的U字形状包围发射极电极21。关于排列方向在基极电极22的两侧分别配置有集电极电极23。配置于相互相邻的2个HBT20之间的集电极电极23被2个HBT20共享。
在覆盖HBT20的绝缘膜上与发射极电极21对应地设置有第一开口31。在图1中，对第一开口31标注阴影。在俯视时，第一开口31内含于发射极电极21。发射极电极21通过第一开口31与发射极布线电连接。在覆盖发射极布线的保护膜设置有第二开口32。在图1中对第二开口32标注比第一开口31淡的阴影。在俯视时，第二开口32配置于不与第一开口31重叠的位置，并具有在排列方向上较长的平面形状。
凸块40被配置为在俯视时内含HBT20以及第二开口32。凸块40通过第二开口32与其下方的发射极布线电连接。换言之，在俯视时，第二开口32包含于凸块40的内侧并且第一开口31的外侧的区域。
图2是图1的点划线2－2上的剖视图。在由GaAs等化合物半导体构成的基板50上配置有子集电极层51。通过离子注入子集电极层51中的部分区域被绝缘化，而被划分为被赋予导电性的元件形成区域51a和被绝缘化的元件分离区域51b。
在子集电极层51的元件形成区域51a的部分区域上配置有HBT20。HBT20包含由n型的集电极层52、p型的基极层53、以及n型的发射极层54构成的台面状部分。在发射极层54上配置有发射极电极21，发射极电极21与发射极层54欧姆连接。在基极层53上配置有基极电极22，基极电极22与基极层53欧姆连接。在元件形成区域51a上配置有集电极电极23(图1)，集电极电极23经由元件形成区域51a与集电极层52欧姆连接。
绝缘膜70覆盖子集电极层51、集电极层52、基极层53、发射极层54、发射极电极21、以及基极电极22。在绝缘膜70设置有第一开口31。在俯视时，第一开口31内含于发射极电极21。在绝缘膜70上配置有发射极布线61。发射极布线61通过第一开口31与发射极电极21电连接。发射极布线61例如使用金(Au)。
保护膜74覆盖发射极布线61。在保护膜74设置有第二开口32。第二开口32设置于HBT20的未配置有台面状部分的区域。
在保护膜74上，配置有凸块40。凸块40包含从基板50侧开始依次层叠的凸块下金属层41、金属柱42、以及焊料层43。凸块下金属层41使用Ti、TiW等高熔点金属。金属柱42例如使用铜(Cu)。焊料层43使用包含锡(Sn)的焊料。具有这样的层叠结构的凸块40被称为Cu柱形凸块。
接下来，将第一实施例的优异的效果与图3以及图4所示的比较例对比来进行说明。
图3是表示比较例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。在第一实施例中，第二开口32被配置为不与第一开口31重叠，但在比较例中，第二开口32与第一开口31重叠。例如，在俯视时第一开口31配置于第二开口32的内侧。在图3中，对第一开口31标注相对较浓的阴影，并对第二开口标注相对较淡的阴影。
图4是图3的点划线4－4上的剖视图。第一开口31配置于第二开口32的内侧。
接下来，对图3以及图4所示的比较例的课题进行说明。若在倒装芯片键合时焊料层43熔融，则熔融的多余的焊料沿着金属柱42的侧面到达凸块下金属层41与金属柱42的界面。到达界面的焊料如图4中箭头所示，沿着凸块下金属层41与金属柱42的界面侵入凸块40的内部。
有由于第一开口31的边缘的阶梯差而凸块下金属层41产生裂纹等的情况。若侵入到凸块40的内侧的焊料到达该裂纹，则会通过裂纹到达发射极布线61。若焊料到达发射极布线61，则焊料中的Sn与发射极布线61的Au发生反应并且Sn在发射极布线61内扩散。若Sn扩散到发射极电极21以及发射极层54，则产生HBT20的劣化、破坏。Sn的扩散不仅在倒装芯片键合时产生，也可能因在HBT20的动作中发射极布线61、发射极电极21的温度上升而产生。
在第一实施例中，如在图2中用箭头所示，即使焊料沿着凸块下金属层41与金属柱42的界面侵入到第一开口31的正上方，也能够通过配置于凸块下金属层41与发射极布线61之间的保护膜74抑制焊料向发射极布线61的焊料的侵入。
另外，若焊料到达第二开口32，则有焊料通过由于第二开口32的边缘的阶梯差而在凸块下金属层41产生的裂纹，侵入发射极布线61的情况。然而，由于在俯视时，第二开口32配置于不与作为发热源的发射极层54及其正下方的基极层53、集电极层52重叠的位置，所以HBT20的动作中第二开口32的正下方的发射极布线61难以达到高温。因此，可抑制侵入发射极布线61的Sn的电迁移的进展、Sn与Au的反应。因此，在第一实施例中，可获得难以产生由焊料的侵入引起的HBT20的劣化、破坏这样的优异的效果。进一步，由于难以产生由Sn与Au的反应引起的发射极布线61的高电阻化，所以能够抑制HBT20的电气特性的降低。特别是，通过将第一实施例的结构应用于以较大的功率动作的功率晶体管，可获得显著的效果。
进一步，在第一实施例中，由于第二开口32配置于不与HBT20的台面状部分重叠的位置，所以在配置有第二开口32的区域，保护膜74的基底的平坦性较高。其结果，也可获得难以在凸块下金属层41产生裂纹的效果。
另外，在第一实施例中，在俯视时第一开口31配置于凸块40的内侧。因此，能够提高通过从HBT20经由第一开口31到达凸块40的热路径的散热效果。
[第二实施例]
接下来，参照图5～图11的附图，对第二实施例的半导体装置进行说明。以下，对于与第一实施例的半导体装置(图1、图2)共用的结构省略说明。
图5是第二实施例的半导体装置的剖视图。在第一实施例中，发射极布线61(图2)通过第一开口31与发射极电极21直接连接。与此相对，在第二实施例中，在发射极布线61的下方配置有第一层发射极布线60，第一层发射极布线60通过第一开口31与发射极电极21连接。在绝缘膜70以及第一层发射极布线60上配置有绝缘膜71。在该绝缘膜71上配置有第二层发射极布线61。第二层发射极布线61通过设置于绝缘膜71的第三开口33与第一层发射极布线60连接。该第三开口33配置为在俯视时与第一开口31几乎重叠。
在第二实施例中，凸块40通过第二开口32、第三开口33、以及第一开口31与发射极电极21电连接。在绝缘膜70上配置有基极布线62。基极布线62通过设置于绝缘膜70的开口与基极电极22连接。发射极电极21、基极电极22、集电极电极23、第一开口31、第二开口32、以及凸块40在平面上的位置关系与第一实施例(图1)的它们的位置关系相同。
接下来，参照图6～图11的附图对第二实施例的半导体装置的制造方法进行说明。图6～图11的附图是第二实施例的半导体装置的制造中途阶段的剖视图。以下说明的各构成要素的材料、尺寸、掺杂浓度等是一个例子。
如图6所示，在使用一般的半导体工序并由半绝缘性的GaAs构成的基板50上形成子集电极层51、HBT20、发射极电极21、以及基极电极22。子集电极层51的元件形成区域51a由高浓度的n型GaAs形成，其厚度为0.5μm。元件分离区域51b通过进行用于对GaAs赋予绝缘性的离子注入来形成。
HBT20的集电极层52由n型GaAs形成，其厚度为1μm。基极层53由p型GaAs形成，其厚度为100nm。发射极层54包含与基极层53相接的厚度为30nm以上40nm以下的n型InGaP层、和配置于其上的发射极台面层。
基极电极22与基极层53电连接。
发射极台面层包含厚度为100nm的高浓度的n型GaAs层和配置于其上的厚度为100nm的高浓度的n型InGaAs层。发射极台面层是用于取得与其上的发射极电极21欧姆接触的层。
发射极电极21由Ti形成，其厚度为50nm。基极电极22由自下而上依次层叠的Ti膜、Pt膜、Au膜这3层构成。虽然在图6的剖面未出现，但在子集电极层51的元件形成区域51a上配置有集电极电极。集电极电极由自下而上依次层叠的AuGe膜、Ni膜、Au膜这3层构成。
将绝缘膜70形成为覆盖子集电极层51、集电极层52、基极层53、发射极层54、发射极电极21、以及基极电极22。绝缘膜70使用SiN。之后，在绝缘膜70形成使发射极电极21露出的第一开口31、以及使基极电极22露出的开口。
如图7所示，在第一开口31内露出的发射极电极21上形成第一层发射极布线60，并在露出的基极电极22上形成基极布线62。此外，与发射极布线60以及基极布线62同时也形成集电极布线。在俯视时，基极布线62延伸到基极层53的外侧。发射极布线60以及基极布线62由厚度为10nm以上50nm以下的Ti膜、和形成于其上的厚度为1μm以上2μm以下的Au膜这2层构成。
将绝缘膜71形成为覆盖绝缘膜70、发射极布线60、以及基极布线62。绝缘膜71使用SiN。在绝缘膜71形成使发射极布线60露出的第三开口33。
如图8所示，在第三开口33内露出的发射极布线60以及绝缘膜71上形成第二层发射极布线61。发射极布线61由厚度为10nm以上50nm以下的Ti膜、以及配置于其上的厚度为2μm以上4μm以下的Au膜这2层构成。
将保护膜74形成为覆盖发射极布线61。保护膜74使用由SiN构成的单层膜、或者SiN膜和树脂膜的双层结构的膜。在保护膜74形成第二开口32。在第二开口32内发射极布线61露出。
如图9所示，将凸块下金属层41形成为覆盖保护膜74、以及第二开口32内的发射极布线61。凸块下金属层41使用Ti等高熔点金属，其厚度为50nm以上100nm以下。在凸块下金属层41上，在应形成凸块40(图5)的区域形成具有开口81的抗蚀剂膜80。在开口81内凸块下金属层41露出。
如图10所示，在开口81内露出的凸块下金属层41上，通过电镀法堆积金属柱42以及焊料层43。金属柱42使用铜(Cu)，其厚度为30μm以上50μm以下。焊料层43使用锡(Sn)或者SnAg合金，其厚度为10μm以上30μm以下。也可以在金属柱42与焊料层43之间，配置用于防止相互扩散的由Ni等构成的阻挡金属层。在形成焊料层43之后，除去抗蚀剂膜80。
如图11所示，除去被抗蚀剂膜80(图10)覆盖的区域的凸块下金属层41。在金属柱42的正下方剩余凸块下金属层41。通过进行回流焊处理，使焊料层43熔融，之后使其固化从而获得图5所示的半导体装置。
接下来，对第二实施例的优异的效果进行说明。在图5所示的第二实施例中，在俯视时第一开口31与第二开口32不重叠，在第一开口31内的发射极电极21与凸块下金属层41之间配置有保护膜74。因此，与第一实施例相同，可获得难以产生由焊料的侵入引起的HBT20的劣化、破坏这样的优异的效果。进一步，由于在配置有第二开口32的区域，保护膜74的基底的平坦性较高，所以与第一实施例相同，也可获得凸块下金属层41难以产生裂纹的效果。
为了提高抑制焊料侵入发射极电极21的效果，优选在俯视时，将保护膜74配置于第一开口31的内侧的整个区域。
[第三实施例]
接下来，参照图12A对第三实施例的半导体装置进行说明。以下，对于与第一实施例的半导体装置共用的结构省略说明。
图12A是表示第三实施例的半导体装置的第一开口31、第二开口32、以及凸块40在平面上的位置关系的图。在第一实施例中，如图1所示，关于与HBT20的排列方向正交的方向，将第一开口31和第二开口32配置于不同的位置，且第二开口32具有在排列方向上较长的平面形状。与此相对，在第三实施例中，第二开口32配置于相互相邻的第一开口31之间。关于与HBT20的排列方向正交的方向，第二开口32的尺寸比第一开口31的尺寸大。
接下来，对第三实施例的优异的效果进行说明。
在第三实施例中，由于在俯视时第一开口31与第二开口32不重叠，所以与第一实施例相同，可获得难以产生由焊料的侵入引起的HBT20的劣化、破坏这样的优异的效果。
接下来，参照图12B对第三实施例的变形例的半导体装置进行说明。
图12B是表示第三实施例的变形例的半导体装置的第一开口31、第二开口32、以及凸块40在平面上的位置关系的图。在第三实施例中，关于与HBT20的排列方向正交的方向，第二开口32的尺寸比第一开口31的尺寸小。因此，从凸块40的边缘到第二开口32的最短距离比第三实施例(图12A)的情况长。另外，从凸块40的边缘到第二开口32的最短距离比从凸块40的边缘到第一开口31的最短距离长。
像这样，由于第二开口32远离凸块40的边缘，所以从凸块40的边缘侵入的焊料难以到达第二开口32。其结果，难以产生由焊料的侵入引起的HBT20的劣化、破坏这样的效果提高。
[第四实施例]
接下来，参照图13和图14，对第四实施例的半导体装置进行说明。以下，对于与第一实施例以及第二实施例的半导体装置(图1、图2、图5)共用的结构省略说明。
图13是表示第四实施例的半导体装置的各电极、凸块、以及设置于绝缘膜的开口在平面上的位置关系的图。图14是图13的点划线14－14上的剖视图。在第一实施例以及第二实施例中，第一开口31与第二开口32在俯视时不重叠。在第四实施例中，在俯视时在一个凸块40的内部配置有多个第二开口32，部分第二开口32内含于第一开口31。剩余的第二开口32在俯视时配置在凸块40的内侧并且比第一开口31靠外侧的区域。
接下来，对第四实施例的优异的效果进行说明。在第四实施例中，第一开口31与第二开口32部分重叠，但第二开口32内含于第一开口31。在第一开口31的边缘与凸块下金属层41之间配置有保护膜74。因此，如在图14中用箭头所示，即使沿着凸块下金属层41与金属柱42的界面侵入凸块40内的焊料到达第一开口31的边缘的正上方，焊料也会被保护膜74遮挡而到达不了发射极电极21。因此，与图4所示的比较例相比，可获得难以产生由焊料的侵入引起的HBT20的劣化、破坏这样的效果。
若侵入凸块40内的焊料到达内含于第一开口31的第二开口32，则焊料经由凸块下金属层41的裂纹等到达发射极电极21的危险性升高。为了使焊料难以到达发射极电极21，优选将从凸块40的边缘到内含于第一开口31的第二开口32的最短距离设为从凸块40的边缘到第一开口31的最短距离的1.5倍以上。
进一步，在第四实施例中，形成从HBT20通过第一开口31内的第二开口32到达凸块40的散热路径。因此，第四实施例的半导体装置与第一实施例、第二实施例、以及第三实施例的半导体装置相比，在散热的观点上有利。
上述的各实施例是例示，当然能够进行在不同的实施例中示出的结构的部分置换或者组合。例如，上述实施例的半导体装置包含有HBT20，但也可以代替HBT20而包含通常的双极晶体管。另外，在上述实施例中示出了设置于由化合物半导体构成的基板的双极晶体管的例子，但对于硅基板上的双极晶体管，也能够应用上述实施例所记载的技术思想。另外，作为凸块结构例示出了包含金属柱的结构，但也可以采用不设置金属柱，而由凸块下金属层和配置于其上的焊料层构成的凸块结构。
对于由多个实施例的相同的结构带来的相同的作用效果没有在每个实施例中依次提及。进一步，本发明并不被限制于上述的实施例。例如，能够进行各种变更、改进、组合等对本领域技术人员来说是显而易见的。
附图标记说明
20…异质结双极晶体管(HBT)；21…发射极电极；22…基极电极；23…集电极电极；31…第一开口；32…第二开口；33…第三开口；40…凸块；41…凸块下金属层；42…金属柱；43…焊料层；50…基板；51…子集电极层；51a…元件形成区域；51b…元件分离区域；52…集电极层；53…基极层；54…发射极层；60…第一层发射极布线；61…发射极布线；62…基极布线；70、71…绝缘膜；74…保护膜；80…抗蚀剂膜；81…开口。

Claims (6)

1.一种半导体装置，具有：
基板；
双极晶体管，包含层叠在上述基板上的集电极层、基极层、以及发射极层；
绝缘膜，配置在上述基板上以覆盖上述双极晶体管；
发射极布线，配置在上述绝缘膜上，该发射极布线通过设置于上述绝缘膜的第一开口与上述发射极层电连接；
保护膜，配置在上述发射极布线上；以及
凸块，配置在上述保护膜上，该凸块通过设置于上述保护膜的第二开口与上述发射极布线电连接，
在俯视时，上述第二开口包含在上述凸块的内侧并且上述第一开口的外侧的区域。
2.根据权利要求1所述的半导体装置，其中，
在俯视时，在上述第一开口的内侧的整个区域配置上述保护膜。
3.根据权利要求1或2所述的半导体装置，其中，
在俯视时，从上述凸块的边缘到上述第二开口的最短距离比从上述凸块的边缘到上述第一开口的最短距离长。
4.根据权利要求1～3中任一项所述的半导体装置，其中，
上述双极晶体管包含形成在上述基板上的台面状部分，在俯视时，至少一个上述第二开口配置于上述台面状部分的外侧。
5.根据权利要求1～4中任一项所述的半导体装置，其中，
在俯视时，上述第一开口配置在上述凸块的内侧。
6.根据权利要求1～5中任一项所述的半导体装置，其中，
在俯视时，在上述保护膜设置有内含于上述第一开口的其它第二开口。
CN201911154165.3A 2018-11-26 2019-11-22 半导体装置 Active CN111223920B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-220103 2018-11-26
JP2018220103A JP2020088153A (ja) 2018-11-26 2018-11-26 半導体装置

Publications (2)

Publication Number Publication Date
CN111223920A true CN111223920A (zh) 2020-06-02
CN111223920B CN111223920B (zh) 2024-01-09

Family

ID=70770949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911154165.3A Active CN111223920B (zh) 2018-11-26 2019-11-22 半导体装置

Country Status (3)

Country Link
US (1) US10777667B2 (zh)
JP (1) JP2020088153A (zh)
CN (1) CN111223920B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809035A (zh) * 2020-06-16 2021-12-17 株式会社村田制作所 半导体装置
CN113809035B (zh) * 2020-06-16 2024-06-04 株式会社村田制作所 半导体装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI685969B (zh) * 2018-11-27 2020-02-21 立積電子股份有限公司 雙載子電晶體
JP2020120080A (ja) * 2019-01-28 2020-08-06 株式会社村田製作所 半導体素子
US11177374B1 (en) * 2020-08-11 2021-11-16 Win Semiconductors Corp. Heterojunction bipolar transistor and method for forming the same
WO2023132233A1 (ja) * 2022-01-07 2023-07-13 株式会社村田製作所 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290624A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体集積回路装置の製造方法
JPH07153772A (ja) * 1993-11-30 1995-06-16 Sony Corp バイポーラトランジスタ及びその製造方法
CN1474459A (zh) * 2002-08-09 2004-02-11 ������������ʽ���� 具有高度结构可靠性和低寄生电容的半导体器件
JP2004335890A (ja) * 2003-05-09 2004-11-25 Sumitomo Electric Ind Ltd 半導体装置およびその製造方法
JP2007073611A (ja) * 2005-09-05 2007-03-22 Renesas Technology Corp 電子装置およびその製造方法
CN105849873A (zh) * 2014-01-10 2016-08-10 株式会社村田制作所 半导体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6071009B2 (ja) 2014-11-27 2017-02-01 株式会社村田製作所 化合物半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290624A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体集積回路装置の製造方法
JPH07153772A (ja) * 1993-11-30 1995-06-16 Sony Corp バイポーラトランジスタ及びその製造方法
CN1474459A (zh) * 2002-08-09 2004-02-11 ������������ʽ���� 具有高度结构可靠性和低寄生电容的半导体器件
JP2004335890A (ja) * 2003-05-09 2004-11-25 Sumitomo Electric Ind Ltd 半導体装置およびその製造方法
JP2007073611A (ja) * 2005-09-05 2007-03-22 Renesas Technology Corp 電子装置およびその製造方法
CN105849873A (zh) * 2014-01-10 2016-08-10 株式会社村田制作所 半导体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809035A (zh) * 2020-06-16 2021-12-17 株式会社村田制作所 半导体装置
CN113809035B (zh) * 2020-06-16 2024-06-04 株式会社村田制作所 半导体装置

Also Published As

Publication number Publication date
US20200168725A1 (en) 2020-05-28
JP2020088153A (ja) 2020-06-04
US10777667B2 (en) 2020-09-15
CN111223920B (zh) 2024-01-09

Similar Documents

Publication Publication Date Title
CN111223920B (zh) 半导体装置
JP3272242B2 (ja) 半導体装置
JP5004800B2 (ja) 炭化ケイ素デバイス用のはんだ付け可能上部金属
TWI557801B (zh) Semiconductor device
US9196560B2 (en) Semiconductor device having a locally reinforced metallization structure and method for manufacturing thereof
CN101685810B (zh) 用于半导体组件封装的夹片及半导体封装结构和封装方法
US8026576B2 (en) Wiring board
US20080099926A1 (en) Semiconductor device
CN111341738B (zh) 半导体装置
TWI671825B (zh) 半導體晶片、半導體晶片之構裝方法及構裝有半導體晶片之模組
JPH07193070A (ja) 化合物半導体装置
CN111490022B (zh) 半导体元件
CN110998807B (zh) 半导体装置
KR100620926B1 (ko) 집적형 쇼트키 배리어 다이오드 및 그 제조 방법
JP6579653B2 (ja) 半導体装置および半導体装置の製造方法
CN113809036A (zh) 半导体装置
US20240047398A1 (en) Semiconductor device
US20230215840A1 (en) Semiconductor device
US20230369278A1 (en) Semiconductor device
TW202335298A (zh) 半導體裝置
CN117954314A (zh) 半导体封装结构及其制造方法
JP2008041784A (ja) 保護素子及びこの保護素子を備えた半導体装置並びに半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant