CN102629568A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN102629568A
CN102629568A CN2012100264937A CN201210026493A CN102629568A CN 102629568 A CN102629568 A CN 102629568A CN 2012100264937 A CN2012100264937 A CN 2012100264937A CN 201210026493 A CN201210026493 A CN 201210026493A CN 102629568 A CN102629568 A CN 102629568A
Authority
CN
China
Prior art keywords
metal film
mentioned
young
modulus
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100264937A
Other languages
English (en)
Other versions
CN102629568B (zh
Inventor
山本祐广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN102629568A publication Critical patent/CN102629568A/zh
Application granted granted Critical
Publication of CN102629568B publication Critical patent/CN102629568B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供半导体装置，其能够更好地防止焊盘下面的绝缘膜产生裂缝。作为解决手段，半导体装置具有三层结构的焊盘，该三层结构的焊盘由第1金属膜、第2金属膜和第3金属膜构成，第2金属膜具有比第1金属膜和第3金属膜的杨氏模量高的杨氏模量。

Description

半导体装置
技术领域
本发明涉及具有焊盘的半导体装置。
背景技术
首先说明具有焊盘的现有半导体装置。半导体装置中设有焊盘，焊盘用于向半导体集成电路提供电源电压或接地电位，还用于进行与外部的数据收发。图5是示出现有的具有焊盘的半导体装置的焊盘附近的剖面示意图。
在设置于半导体衬底50表面的绝缘膜53上设有第1金属膜51。在第1金属膜51上直接设有第2金属膜52。保护膜54覆盖第2金属膜52上方，在焊盘上具有开口部。保护膜54在保护膜54的开口部外的部分中覆盖第2金属膜52。因此，将保护膜54的开口部定义为用作焊盘的区域。
这里，关于作为第1金属膜51和第2金属膜的物理特性的杨氏模量(ャング率)，第1金属膜51的杨氏模量高于第2金属膜52的杨氏模量。如果采取这种结构，由于杨氏模量较高的第1金属膜51被设置成焊盘的下层，因此焊盘周边对于由线接合(wire bonding)的冲击所产生的应力的耐性得到提高(例如参见专利文献1)。
【专利文献1】日本特开2009-027098号公报
然而，在现有的技术中，根据线接合的冲击所产生的应力大小，有时第2金属膜52和第2金属膜51都会产生变形，绝缘膜53产生裂缝，从而成为问题。
发明内容
本发明是鉴于上述问题而完成的，其课题在于提供能够进一步防止焊盘下面的绝缘膜产生裂缝的半导体装置。
本发明为了解决上述课题，提供一种半导体装置，其具有焊盘，其特征在于，该半导体装置具有：设置于绝缘膜上的第1金属膜，该绝缘膜设置于半导体衬底上；设置于上述第1金属膜上的第2金属膜；设置于上述第2金属膜上的第3金属膜；以及保护膜，其在上述第3金属膜上具有开口部，在上述开口部以外的部分覆盖上述第1金属膜、上述第2金属膜和上述第3金属膜，上述第2金属膜的杨氏模量大于上述第1金属膜的杨氏模量和上述第3金属膜的杨氏模量。
在本发明中使用由第1金属膜、第2金属膜和第3金属膜构成的三层结构的焊盘，第2金属膜具有比第1金属膜和第3金属膜的杨氏模量高的杨氏模量。由此，能够防止焊盘下面的绝缘膜产生裂缝。
附图说明
图1是示出本发明的半导体装置的实施例的剖面示意图。
图2是示出线接合导致的膜变形的剖面示意图。
图3是示出作为变形例1的实施例的半导体装置的剖面示意图。
图4是示出作为变形例2的实施例的半导体装置的剖面示意图。
图5是示出现有的半导体装置的剖面示意图。
标号说明
10半导体衬底；11第1金属膜；12第2金属膜；13第3金属膜；14绝缘膜；15保护膜。
具体实施方式
下面参照附图说明本发明的实施方式。
首先说明具有焊盘的半导体装置的结构。图1是示出本发明涉及的半导体装置的实施例的剖面示意图。
在设置于半导体衬底10表面的绝缘膜14上设有第1金属膜11。第2金属膜12设置于第1金属膜11上。第3金属膜13设置于第2金属膜12上。在第3金属膜13和绝缘膜14上设有具备开口部的保护膜15。保护膜15的开口部定义了焊盘的区域。在保护膜15的开口部以外的部分，覆盖第1金属膜11、第2金属膜12和第3金属膜13。开口部的大小决定了可用作焊盘的区域，其小于第1金属膜11、第2金属膜12和第3金属膜13。此处，第1金属膜11和第3金属膜13例如可以由铝形成，第2金属膜可以由铜或钨形成。铝的杨氏模量为70GPa左右，铜的杨氏模量为120GPa左右，钨的杨氏模量为400GPa左右。在采取这种结构的情况下，第2金属膜12的杨氏模量比第1金属膜11和第3金属膜13的杨氏模量高。
接着，说明对焊盘实施线接合时的构成焊盘的膜的变形。图2是示出线接合导致的膜变形的剖面示意图。
在对焊盘实施线接合之前，如图2(A)所示，第1金属膜11和第2金属膜12和第3金属膜大致平行且水平重叠。
对焊盘实施线接合时，如图2(B)所示，杨氏模量较低的第3金属膜13由于线接合的冲击所产生的应力而以冲击点为中心发生大幅变形(附图进行了夸张描述，仅为示意)。此时，由于第2金属膜12的杨氏模量高于第3金属膜13的杨氏模量，因此第3金属膜13的变形导致的应力主要在平面方向分散而不是在第2金属膜12的垂直方向分散。因而第2金属膜12会以线接合的冲击点为中心发生稍大的变形，然而，是大致均匀地发生变形。而且，该第2金属膜12的变形导致的应力被杨氏模量较低的第1金属膜11吸收。因此，第1金属膜11的底面、即第1金属膜11与绝缘膜14的接合面几乎不会变形，因此线接合的冲击几乎不会对绝缘膜14造成影响。其结果，能更有效防止绝缘膜14产生裂缝。
这样，当采用具备第1金属膜11、第2金属膜12、第3金属膜13的三层结构的焊盘时，能防止焊盘下面的绝缘膜14产生裂缝，其中，该第2金属膜12具备比第1金属膜11和第3金属膜13的杨氏模量高的杨氏模量。
并且，在上述说明中，焊盘的最下面的层为第1金属膜，然而即便不是金属，只要是杨氏模量较小的物质就可以使用，例如可以使用聚酰亚胺树脂的膜。聚酰亚胺树脂的杨氏模量为3.5GPa左右，具有较小的值。而且，聚酰亚胺树脂通常与半导体装置的亲和性较好，被广泛使用。
【变形例1】
图3是示出变形例1的实施例的剖面示意图。在图1所示的实施例中，第1金属膜11设置于绝缘膜14上，但如图3所示，也可以将第1金属膜11嵌入绝缘膜14。而且，将第2金属膜12设置于该第1金属膜11上。此时，绝缘膜14具有槽，第1金属膜11嵌入于该槽中。该槽的底面形成为大致平面状。在该结构中，由于不形成台阶，因此第1金属膜能够形成得较厚。由此第2金属膜12的应力导致的变形更容易被第1金属膜11吸收。
【变形例2】
图4是示出变形例2的实施例的剖面示意图。其与图3的结构大致相同，而不同之处在于，绝缘膜14的槽的底面在图3中形成为大致平面状，而如图4所示，形成为向下凸的曲面或大致球面的一部分。即，可以将第1金属膜11的底面形成为向下凸的曲面或大致球面的一部分。由此，能够防止应力集中于第1金属膜11的底面中的角部，因此第2金属膜12的应力导致的变形更容易被第1金属膜11吸收。

Claims (7)

1.一种半导体装置，其具有焊盘，
该半导体装置具有：
半导体衬底；
设置于上述半导体衬底的表面的绝缘膜；
设置于上述绝缘膜上的第1金属膜；
设置于上述第1金属膜上的第2金属膜；
设置于上述第2金属膜上的第3金属膜；以及
保护膜，其在上述第3金属膜上具有开口部，在上述开口部以外的部分覆盖上述第1金属膜、上述第2金属膜和上述第3金属膜，
上述第2金属膜的杨氏模量大于上述第1金属膜的杨氏模量和上述第3金属膜的杨氏模量。
2.一种半导体装置，其具有焊盘，
该半导体装置具有：
半导体衬底；
设置于上述半导体衬底的表面的绝缘膜；
第1金属膜，其嵌入配置于设置在上述绝缘膜的表面的槽中；
设置于上述第1金属膜上的第2金属膜；
设置于上述第2金属膜上的第3金属膜；以及
保护膜，其在上述第3金属膜上具有开口部，在上述开口部以外的部分覆盖上述第1金属膜、上述第2金属膜和上述第3金属膜，
上述第2金属膜的杨氏模量大于上述第1金属膜的杨氏模量和上述第3金属膜的杨氏模量。
3.根据权利要求2所述的半导体装置，其中，
上述槽的底面形成为大致平面状。
4.根据权利要求2所述的半导体装置，其中，
上述槽的底面形成为向下凸的曲面、或大致球面的一部分。
5.根据权利要求1或2所述的半导体装置，其中，
上述第1金属膜和上述第3金属膜由铝形成。
6.根据权利要求1或2所述的半导体装置，其中，
上述第2金属膜由铜形成。
7.根据权利要求1或2所述的半导体装置，其中，
上述第2金属膜由钨形成。
CN201210026493.7A 2011-02-07 2012-02-07 半导体装置 Expired - Fee Related CN102629568B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011024241A JP5677115B2 (ja) 2011-02-07 2011-02-07 半導体装置
JP2011-024241 2011-02-07

Publications (2)

Publication Number Publication Date
CN102629568A true CN102629568A (zh) 2012-08-08
CN102629568B CN102629568B (zh) 2016-05-04

Family

ID=46587796

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210026493.7A Expired - Fee Related CN102629568B (zh) 2011-02-07 2012-02-07 半导体装置

Country Status (5)

Country Link
US (1) US20120199977A1 (zh)
JP (1) JP5677115B2 (zh)
KR (1) KR101903188B1 (zh)
CN (1) CN102629568B (zh)
TW (1) TW201304011A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915399A (zh) * 2013-01-07 2014-07-09 株式会社电装 半导体器件
US11621678B2 (en) 2017-04-25 2023-04-04 Murata Manufacturing Co., Ltd. Semiconductor device and power amplifier module

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016143804A (ja) * 2015-02-03 2016-08-08 トヨタ自動車株式会社 半導体装置
JP2017224753A (ja) * 2016-06-16 2017-12-21 セイコーエプソン株式会社 半導体装置及びその製造方法
JP6897141B2 (ja) 2017-02-15 2021-06-30 株式会社デンソー 半導体装置とその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330928A (ja) * 1996-06-13 1997-12-22 Toshiba Corp 配線層の形成方法
CN1574338A (zh) * 2003-06-24 2005-02-02 株式会社瑞萨科技 半导体器件
CN1770437A (zh) * 2004-11-02 2006-05-10 台湾积体电路制造股份有限公司 接合垫结构
CN1957455A (zh) * 2004-03-23 2007-05-02 德克萨斯仪器股份有限公司 在铜金属化集成电路之上具有保护性防护层可焊金属接头的接触点的结构和方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6960836B2 (en) * 2003-09-30 2005-11-01 Agere Systems, Inc. Reinforced bond pad
US7656045B2 (en) * 2006-02-23 2010-02-02 Freescale Semiconductor, Inc. Cap layer for an aluminum copper bond pad
TWI316295B (en) * 2006-05-17 2009-10-21 Au Optronics Corp Thin film transistor
JP2009016619A (ja) * 2007-07-05 2009-01-22 Denso Corp 半導体装置及びその製造方法
US8178980B2 (en) * 2008-02-05 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure
US8030780B2 (en) * 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US8202741B2 (en) * 2009-03-04 2012-06-19 Koninklijke Philips Electronics N.V. Method of bonding a semiconductor device using a compliant bonding structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330928A (ja) * 1996-06-13 1997-12-22 Toshiba Corp 配線層の形成方法
CN1574338A (zh) * 2003-06-24 2005-02-02 株式会社瑞萨科技 半导体器件
CN1957455A (zh) * 2004-03-23 2007-05-02 德克萨斯仪器股份有限公司 在铜金属化集成电路之上具有保护性防护层可焊金属接头的接触点的结构和方法
CN1770437A (zh) * 2004-11-02 2006-05-10 台湾积体电路制造股份有限公司 接合垫结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915399A (zh) * 2013-01-07 2014-07-09 株式会社电装 半导体器件
CN103915399B (zh) * 2013-01-07 2017-10-17 株式会社电装 半导体器件
US11621678B2 (en) 2017-04-25 2023-04-04 Murata Manufacturing Co., Ltd. Semiconductor device and power amplifier module

Also Published As

Publication number Publication date
CN102629568B (zh) 2016-05-04
TW201304011A (zh) 2013-01-16
JP5677115B2 (ja) 2015-02-25
JP2012164825A (ja) 2012-08-30
KR101903188B1 (ko) 2018-10-01
KR20120090827A (ko) 2012-08-17
US20120199977A1 (en) 2012-08-09

Similar Documents

Publication Publication Date Title
JP5635661B1 (ja) イメージセンサの２段階封止方法
US10186538B2 (en) Sensor package structure
US7589408B2 (en) Stackable semiconductor package
US8421242B2 (en) Semiconductor package
CN204732405U (zh) 集成电路芯片的堆叠和电子装置
WO2008153043A1 (ja) 半導体発光装置
TW201401460A (zh) 感測器陣列封裝
CN102629568A (zh) 半导体装置
US10236313B2 (en) Sensor package structure
CN102760816A (zh) 发光二极管封装结构及其制造方法
US10692917B2 (en) Sensor package structure
US9607960B1 (en) Bonding structure and flexible device
US20170073221A1 (en) Semiconductor device package and method of manufacturing the same
US8524529B2 (en) Brace for wire bond
US20180233642A1 (en) Light-emitting device and manufacturing method of light-emitting device
JP2019102568A (ja) 半導体装置およびその製造方法
US20070241272A1 (en) Image sensor package structure and method for manufacturing the same
US9196598B1 (en) Semiconductor device having power distribution using bond wires
US9029996B2 (en) Bonding and electrically coupling components
US20080067334A1 (en) Image sensor package structure and method for manufacturing the same
CN204441273U (zh) 半导体器件以及半导体封装体
US9905515B2 (en) Integrated circuit stress releasing structure
KR101688077B1 (ko) 반도체 패키지 구조물 및 그 제작 방법
US7402839B2 (en) Image sensor package structure
CN103972194A (zh) 一种封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160405

Address after: Chiba County, Japan

Applicant after: SEIKO INSTR INC

Address before: Chiba County, Japan

Applicant before: Seiko Instruments Inc.

C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: EPPs Lingke Co. Ltd.

Address before: Chiba County, Japan

Patentee before: SEIKO INSTR INC

CP01 Change in the name or title of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160504

Termination date: 20210207

CF01 Termination of patent right due to non-payment of annual fee