CN107403779B - 接合垫结构 - Google Patents

接合垫结构 Download PDF

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Publication number
CN107403779B
CN107403779B CN201710357144.6A CN201710357144A CN107403779B CN 107403779 B CN107403779 B CN 107403779B CN 201710357144 A CN201710357144 A CN 201710357144A CN 107403779 B CN107403779 B CN 107403779B
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layer
over
oxide layer
oxide
structures
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CN107403779A (zh
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O.黑尔蒙德
P.伊尔西格勒
S.施密特
M.赛德-施密特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种接合垫结构包括覆于衬底上面的第一氧化物层。多个粘合结构被形成在第一氧化物层上方。第二氧化物层被形成在所述多个粘合结构和第一氧化物层上方。形成在第二氧化物层的表面区域内的多个接触器开口中的每个接触器开口包括一侧或多侧并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方对准。在表面区域内形成阻挡层，该阻挡层在第二氧化物层上方并且在所述多个接触器开口内并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方。金属层被形成在阻挡层上方。

Description

接合垫结构
技术领域
本申请涉及一种接合垫结构，具体地讲，涉及一种包括多个粘合结构的接合垫结构。
背景技术
半导体制造商持续地工作以提高功率装置(诸如，双扩散金属氧化物半导体(DMOS)和绝缘栅双极晶体管(IGBT)装置)的性能和可靠性。关心的领域之一是功率装置管芯的接合垫的粘合失效。接合垫位于管芯的顶表面上，并且包括形成在管芯的厚氧化物或场氧化物区域上方的金属层。接合垫被导线接合到封装引线框架的内引线以形成接合垫和封装引线框架之间的电接触器。
已被用于解决粘合失效问题的一个方案是形成位于金属层和场氧化物之间的一层多晶硅。多晶硅层在金属层和场氧化物之间提供化学兼容界面，由此提高粘合力。多晶硅层吸收外部热机械应力，并且针对沿相对于金属层表面的垂直方向的应力提高耐久性。然而，场氧化物可能具有在形成期间引起的缺陷，所述缺陷是随机分布在整个场氧化物中的局部减薄的区域。功率装置通常在高电压电平(诸如250 V至远高于1000 V)操作。当高电压电平在操作期间被施加于接合垫金属层时使多晶硅层与这些缺陷区域直接接触能够导致高电流或短路状况，所述高电流或短路状况将会破坏功率装置。在接合垫所需的相对大的表面区域上方使用多晶硅的粘合力和应力吸收益处可能由以下因素抵消：局部减薄缺陷的随机分布；以及，发生高电流状况的增加的可能性，所述高电流状况能够破坏功率装置。
另一方案是直接在场氧化物上方形成金属层。诸如铝的金属对硅和氧化硅(诸如，SiO2)具有良好的粘合力。为了避免硅扩散到铝中，硅必须被添加到铝层。因为将硅添加到铝金属层能够导致诸如硅晶粒生长的问题，所以另一方案是在铝金属层和SiO2场氧化物之间使用扩散阻挡层。扩散阻挡层(诸如，钛(Ti)、氮化钛(TiN)或钛钨(TiW))有效地防止硅扩散到铝金属层中。然而，由Ti/TiN或TiW形成的阻挡层趋向于对SiO2具有较差的粘合力。由于接合垫金属和阻挡层所需的SiO2场氧化物的相对大的区域以及用于形成接合垫的材料层的不同热膨胀性质，沿平行于接合垫表面的方向的横向应力能够导致接合垫材料层从SiO2场氧化物的剥离或分离。
发明内容
根据接合垫结构的实施例，接合垫结构包括：第一氧化物层，覆于衬底上面。多个粘合结构被形成在第一氧化物层上方。第二氧化物层被形成在所述多个粘合结构和第一氧化物层上方。形成在第二氧化物层的表面区域内的多个接触器开口中的每个接触器开口包括一侧或多侧并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方对准。阻挡层被形成在表面区域内，该阻挡层在第二氧化物层上方并且在所述多个接触器开口内并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方。金属层被形成在阻挡层上方。
根据接合垫结构的实施例，接合垫结构包括：多个凹槽，布置在覆于衬底上面的氧化物层的表面区域内。所述多个凹槽中的每个凹槽包括一侧或多侧和底部，所述底部位于氧化物层的表面下方的一定深度。粘合层被形成在所述多个凹槽的底部上方并且具有小于所述深度的厚度。阻挡层被形成在所述表面区域上方并且在所述多个凹槽内并且在粘合层上方。金属层被形成在阻挡层上方。
根据形成接合垫结构的方法的实施例，所述方法包括：在衬底上方形成第一氧化物层。所述方法包括：在第一氧化物层上方形成多个粘合结构。所述方法包括：在所述多个粘合结构和第一氧化物层上方形成第二氧化物层。所述方法包括：在第二氧化物层的表面区域内形成多个接触器开口。所述多个接触器开口中的每个接触器开口包括一侧或多侧并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方对准。所述方法包括：在表面区域内形成阻挡层，该阻挡层在第二氧化物上方并且在所述多个接触器开口内并且在所述多个粘合结构中的对应粘合结构的顶表面的至少一部分上方。所述方法包括：在阻挡层上方形成金属层。
本领域技术人员将会在阅读下面的详细描述时并且在观看附图时意识到另外的特征和优点。
附图说明
附图的元件未必相对于彼此按照比例绘制。相同标号指定对应的类似部分。各种图示的实施例的特征能够被组合，除非它们彼此排斥。在附图中描绘实施例并且在下面的描述中详述实施例。
图1图示接合垫结构的实施例的剖视图。
图2图示包括接合垫结构的功率装置的实施例的局部剖视图。
图3图示接合垫结构的实施例的剖视图。
图4图示接合垫结构的实施例的顶视图。
图5A-5D分别图示氧化物层内的粘合结构的实施例的顶视图。
图6图示用于形成接合垫结构的方法的实施例的流程图。
具体实施方式
图1以100图示接合垫结构的实施例的剖视图。接合垫结构100的顶视图在图4中被图示为虚线，所述虚线引用图1。在图示的实施例中，接合垫结构100被形成在衬底102上方。在一个实施例中，衬底102是硅(Si)衬底。在其它实施例中，衬底102能够由其它合适的材料形成，所述其它合适的材料包括但不限于硅锗(SiGe)、绝缘体上硅(SOI)、碳化硅(SiC)和砷化镓(GaAs)。在图示的实施例中，第一氧化物层103被形成在衬底102上方。在一个实施例中，氧化物层103由二氧化硅(SiO2)形成。在其它实施例中，氧化物层103能够由其它合适的材料和工艺形成，所述其它合适的材料和工艺包括但不限于硅酸乙酯(TEOS)氧化物、氮化硅(Si3N4)、碳化硅(SiC)、氮氧化硅(SiON)、硼磷硅酸盐玻璃(BPSG)以及这些材料的任何组合或衍生物。
在图示的实施例中，多个粘合结构116被形成在第一氧化物层103上方。在一个实施例中，粘合结构116由多晶硅形成。在其它实施例中，粘合结构116能够由其它合适的材料形成。在图示的实施例中，粘合结构116具有以138图示的宽度和以118图示的厚度。以110图示与氧化物层103接触的粘合结构116的底表面。所述多个粘合结构116中的每个粘合结构116与所述多个粘合结构116中的相邻粘合结构116沿第一方向130分隔开距离142。在其它实施例中，所述多个粘合结构116中的每个粘合结构116与所述多个粘合结构116中的相邻粘合结构116沿两个或更多方向分隔开一定距离(也参见图4)。
在图示的实施例中，第二氧化物层104被形成在粘合结构116和第一氧化物层103上方。在一个实施例中，第二氧化物层104由SiO2形成。在其它实施例中，氧化物层104能够由其它合适的材料和工艺形成，所述其它合适的材料和工艺包括但不限于TEOS氧化物、Si3N4、SiC、SiON、BPSG以及这些材料的任何组合或衍生物。在图示的实施例中，多个接触器开口106被形成在第二氧化物层104的表面区域136内。表面区域136在图1中被定义为沿第一方向130在虚线136a和虚线136b之间的距离。每个接触器开口106包括一侧或多侧108(以108a和108b图示)，并且在对应粘合结构116的顶表面140的至少一部分上方对准，如图1中所图示。每个接触器开口106具有在氧化物层104的表面114下方的深度112。
在图示的实施例中，阻挡层120被形成在表面区域136内。在一个实施例中，阻挡层120是共形阻挡层120。在图示的实施例中，阻挡层120被形成在第二氧化物层104的表面114上方，并且被形成在所述多个接触器开口106内并且在对应粘合结构116的顶表面140的至少一部分上方。阻挡层120能够由如下任何合适的材料或合适的材料的任何组合形成：包括但不限于钛(Ti)、氮化钛(TiN)、钨(W)、钛钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化钛硅(TiSiN)、氮化钽硅(TaSiN)、氮化钨(WN)、铌(Nb)、钼(Mo)、氮化钼(MoN)、铬(Cr)、钴(Co)、镍(Ni)、钯(Pd)和铂(Pt)。在其它实施例中，可使用其它合适的材料或合适的材料的组合。在其它实施例中，阻挡层120包括两层或更多层的合适的材料。例如，在一个实施例中，阻挡层120由Ti和TiN形成，并且是Ti/TiN阻挡层。
在图示的实施例中，金属层122被形成在阻挡层120上方。在一个实施例中，金属层122是共形金属层122。在一个实施例中，金属层122是用于附连接合线的垫金属。金属层122能够由如下任何合适的材料或材料的合金形成：包括但不限于铝(Al)、金(Au)、银(Ag)、铜(Cu)、钨(W)、铬(Cr)、钛(Ti)、铂(Pt)或钯(Pd)。在其它实施例中，金属层122能够由其它合适的材料或材料的组合形成。
在图示的实施例中，金属层122具有结构化的表面128，结构化的表面128与氧化物层104的表面114上的所述多个接触器开口106一致。通过表面区域132和表面区域134之间的金属层122的表面水平的变化，在图1中图示结构化的表面128。表面区域132具有以132a图示的边缘。表面区域134具有以134a图示的边缘。表面区域132位于所述多个接触器开口106中的相邻接触器开口106之间，并且表面区域134位于所述多个接触器开口106中的每个接触器开口106上方和/或位于所述多个接触器开口106中的每个接触器开口106内。虽然金属层122在图1中被图示为具有位于表面114上方的表面区域134，但在其它实施例中，表面区域134能够位于第二氧化物104的表面114下方。在各种实施例中，表面区域134是位于氧化物层104的表面114上方还是下方能够部分地取决于如宽度124和深度112所指示的所述多个接触器开口106的尺寸。所述多个接触器开口106中的相邻接触器开口106之间的间隔由间隔126指示。在图示的实施例中，对于图1中图示的接触器开口106和粘合结构142而言，接触器开口106的高度112、宽度124和间隔126以及粘合结构142的高度118、宽度138和间隔142是相同的。在其它实施例中，高度112、宽度124、间隔126、高度118、宽度138和间隔142中的一个或多个能够在接触器开口106和粘合结构142中的任一者或二者中的不同接触器开口106和粘合结构142之间变化。例如，在一个实施例中，对于所述多个接触器开口106和对应粘合结构106中的每一个，高度112和高度118是相同的，而对于所述多个接触器开口106和对应粘合结构116中的不同接触器开口106和粘合结构116，宽度124、间隔126、宽度138和间隔142能够变化。
在图示的实施例中，粘合结构116沿相对于金属层122的表面的垂直方向在金属层122和氧化物103之间提供极好的粘合。间隔142在相邻粘合结构116之间引入间隙，由此减少粘合结构116的底部110和氧化物103之间的接触面积的总量。减少接触面积减少了氧化物103内的随机缺陷引起接合垫结构100的电流诱导失效的可能性。
在图示的实施例中，金属层122的结构化的表面128产生于表面区域132和表面区域134之间的金属层122的表面水平的变化。这种变化位于相邻表面区域132和134的相邻边缘132a和134a之间，并且用于释放沿相对于金属层122的表面的横向或平行方向在阻挡层120和氧化物层104之间的应力。由于引入由表面区域132和表面区域134之间的过渡引起的应力破坏边缘，金属层122的结构化的表面128将横向应力限制于相邻接触器开口106之间的距离126。例如产生于金属层122、阻挡层120和氧化物层104的不同热膨胀系数的负载诱导或应力诱导趋势被以受控方式抑制以提高接合垫可靠性，并且减少接合垫结构100由于热或机械应力而失效的可能性。
图2以200图示包括接合垫结构202和功率装置208的功率装置的实施例的局部剖视图。在各种实施例中，功率装置208能够是功率MOSFET(诸如，双扩散金属氧化物半导体(DMOS)装置)、绝缘栅双极晶体管(IGBT)装置或其它合适的类型的功率装置。图2图示位于衬底102上方的功率装置208的部分。在各种实施例中，诸如功率MOSFET和IGBT的功率装置在衬底102上方具有类似的横截面，并且包括形成在栅极氧化物214上方的栅极216、氧化物204、阻挡层220和金属层222。在示例性实施例中，功率装置208是IGBT，并且金属层222是发射极接触金属层。在另一示例性实施例中，功率装置208是功率MOSFET，并且金属层222是源极接触金属层。在其它实施例中，金属层222能够形成功率装置208的其它合适的类型的金属接触层。
在图示的实施例中，接合垫结构202包括粘合结构116并且功率装置208包括栅极216。在一个实施例中，粘合结构116和栅极216两者都由多晶硅形成。在一个实施例中，粘合结构116和栅极216两者都由多晶硅形成，并且由同一多晶硅层形成。在一个实施例中，粘合结构116和栅极216两者都由多晶硅形成，并且被定义在同一光刻掩模内。在这个实施例中，光刻掩模包括用于定义栅极216的第一特征集和用于定义粘合结构116的第二特征集。在一个实施例中，在光刻掩模的产生期间由图案发生器自动地定义第二特征集，所述第二特征集定义粘合结构116。在一个实施例中，接合垫结构202是栅极接合垫，并且粘合结构116和栅极216由同一多晶硅层形成。在其它实施例中，能够使用不同半导体工艺步骤来形成粘合结构116和栅极216。
在图示的实施例中，在210和212处的虚线图示接合垫结构202和功率装置208之间的氧化物104和/或氧化物204的边界。在一个实施例中，接合垫结构202的氧化物104和功率装置208的氧化物204由同一氧化物层形成。在一个实施例中，接合垫结构202的氧化物104和功率装置208的氧化物204被定义在同一光刻掩模内。在这个实施例中，光刻掩模包括用于定义氧化物204的第一特征集和用于定义氧化物104的第二特征集。在一个实施例中，在光刻掩模的产生期间由图案发生器自动地定义第二特征集，所述第二特征集定义氧化物104。在其它实施例中，能够使用不同半导体处理步骤来形成氧化物104和氧化物204。
图3以300图示接合垫结构的实施例的剖视图。接合垫结构300的顶视图在图4中被图示为虚线，所述虚线引用图3。在图示的实施例中，氧化物层304被形成在衬底102上方。在一个实施例中，氧化物层304由SiO2形成。在其它实施例中，氧化物层304能够由其它合适的材料和工艺形成，所述其它合适的材料和工艺包括但不限于TEOS氧化物、Si3N4、SiC、SiON和BPSG。在其它实施例中，可使用其它合适的材料或合适的材料的组合。在图示的实施例中，多个凹槽306被布置在氧化物层304的表面区域136内。所述多个凹槽306中的每个凹槽306与所述多个凹槽306中的相邻凹槽306沿第一方向130分隔开。所述多个凹槽306中的每个凹槽306包括一侧或多侧308 (以308a和308b图示)和底部310。底部310位于氧化物层304的表面314下方的深度312。
在图示的实施例中，粘合层316被形成在所述多个凹槽306的底部310上方。在一个实施例中，粘合层316由多晶硅形成。在其它实施例中，粘合层316能够由其它合适的材料形成。在图示的实施例中，粘合层316具有小于深度312的厚度318。在其它实施例中，粘合层316能够具有大于深度312的厚度。在其它实施例中，粘合层316能够被形成在氧化物层304的一部分表面314上方或形成在氧化物层304的整个表面314上方。
在图示的实施例中，阻挡层120被形成在表面区域136上方并且在所述多个凹槽306内并且在粘合层316上方。在一个实施例中，阻挡层120是共形阻挡层120。在图示的实施例中，阻挡层120能够由如下任何合适的材料或合适的材料的任何组合形成：包括但不限于Ti、TiN、W、TiW、Ta、TaN、TiSiN、TaSiN、WN、Nb、Mo、MoN、Cr、Co、Ni、Pd和Pt。在其它实施例中，可使用其它合适的材料或合适的材料的组合。在其它实施例中，阻挡层120包括两层或更多层的合适的材料。例如，在一个实施例中，阻挡层120由Ti和TiN形成，并且是Ti/TiN阻挡层。
在图示的实施例中，金属层122被形成在阻挡层120上方。在一个实施例中，金属层122是共形金属层122。在一个实施例中，金属层122是用于附连接合线的垫金属。金属层122能够由如下任何合适的材料或材料的合金形成：包括但不限于Al、Au、Ag、Cu、W、Cr、Ti、Pt和Pd。在其它实施例中，金属层122能够由其它合适的材料形成。
在图示的实施例中，金属层122具有结构化的表面128，结构化的表面128与氧化物层304的表面314上的所述多个凹槽306一致。通过表面区域132和表面区域134之间的金属层122的表面水平的变化，在图3中图示结构化的表面128。表面区域132位于所述多个凹槽306中的相邻凹槽306之间，并且表面区域134位于所述多个凹槽306中的每个凹槽306上方或位于所述多个凹槽306中的每个凹槽306内。虽然金属层122被图示为具有位于表面314上方的表面区域134，但在其它实施例中，表面区域134能够位于表面314下方。
在图示的实施例中，以126指示所述多个凹槽306中的相邻凹槽306之间的间隔。每个凹槽306具有高度312和宽度124。在图3中图示的实施例中，宽度124等于粘合层316的宽度338。在其它实施例中，粘合层316的宽度338能够小于宽度124。在图示的实施例中，对于图3中图示的凹槽306和粘合结构142而言，凹槽306的高度312、宽度124和间隔126以及粘合层316的厚度318和宽度338是相同的。
在其它实施例中，高度312、宽度124、间隔126、厚度318和宽度338中的一个或多个能够在凹槽306和粘合层316中的不同凹槽306和粘合层316之间变化。例如，在一个实施例中，对于凹槽306和对应粘合层316中的每一个，高度312和厚度318是相同的，而对于所述多个凹槽306和对应粘合结构316中的不同凹槽306和粘合结构316，宽度124和间隔126能够变化。
图4以400图示接合垫结构的实施例的顶视图。图4中图示的顶视图是图1中图示的接合垫100和图3中图示的接合垫300的顶视图。接合垫400包括金属层122，金属层122包括表面区域132和表面区域134。表面区域132具有以132a图示的边缘，并且表面区域134具有以134a图示的边缘。参照图4和图1，氧化物层404对应于氧化物层104，结构406对应于接触器开口106，宽度438a对应于宽度138，并且粘合结构416对应于粘合结构116。参照图4和图3，氧化物层404对应于氧化物层304，结构406对应于凹槽306，宽度438a对应于宽度338，并且粘合结构416对应于粘合层316。
在图4中图示的实施例中，表面区域的面积等于金属层122的表面面积。沿第一方向130在虚线136a和虚线136b之间测量第一距离(例如，136a-136b)。沿第二方向430在虚线436a和虚线436b之间测量第二距离(例如，436a-436b)。接合垫400的表面区域的面积等于第一距离(136a-136b)和第二距离(436a-436b)的乘积。
在图4中图示的实施例中，粘合结构416和氧化物层103(参照图1)之间或者粘合结构416和氧化物层304内的凹槽306的底部310(参照图3)之间的底表面接触面积等于宽度438a和宽度438b的乘积。将宽度438a乘以宽度438b提供粘合结构416的面积。图4包括多个粘合结构416，粘合结构416沿第一方向130和第二方向430与相邻粘合结构416分隔开一定距离。第一方向130和第二方向430平行于表面区域。图4图示在接合垫400的表面区域的面积内的20个粘合结构416。所述20个粘合结构416的总底表面接触面积等于宽度438a和宽度438b的乘积乘以20。
在图示的实施例中，粘合结构416沿相对于金属层122的表面132的垂直方向为接合垫结构400的金属层122提供极好的粘合。减少粘合结构416的总底部接触表面面积减少了随机缺陷引起接合垫结构400的电流诱导失效的可能性。由于每个结构406的表面区域132和134的边缘132a和134a导致的结构化的表面128用于将沿平行于表面132的方向的横向应力限制在相邻结构406之间。在接合垫400的表面区域内增加结构406的数量增加了横向应力减小的益处。
对于图示的实施例，通过实验数据确定：接合垫400的表面区域的面积与粘合结构416的总底部接触表面面积的最佳比例在大约3到大约1000的范围内。在另一实施例中，接合垫400的表面区域的面积与粘合结构416的总底部接触表面面积的最佳比例在4到625的范围内。在其它实施例中，接合垫400的表面区域的面积与粘合结构416的总底部接触表面面积的最佳比例能够具有其它合适的范围、最大值或最小值。
在一个示例性实施例中，当每个粘合结构416的底表面接触面积是4μm2时(例如，当宽度438a是2μm并且宽度438b是2μm时)，图4中图示的20个粘合结构416的总底部接触表面面积是80μm2。当第一距离(136a-136b)是250μm并且第二距离(436a-436b)是200μm时，接合垫400的表面区域是50,000μm2。接合垫400的表面区域的面积与粘合结构416的总底部接触表面面积之比等于625。625的比例落在如以上所讨论的大约3到大约1000的最佳比例范围内。
在其它实施例中，从图1中图示的接合垫100的剖视图或从图3中图示的接合垫300的剖视图，能够确定接合垫400的表面区域的面积与粘合结构416的总底部接触表面面积之比。在图4中以408图示相邻结构406之间的间距。
参照图1，间距406对应于宽度138与在相邻粘合结构116之间的间隔142之和，并且宽度438a对应于宽度138。在一个示例性实施例中，宽度138与间隔142之和是50μm并且宽度138是2μm。假定图4中图示的相对尺寸(例如，宽度438a等于宽度438b，并且间距408在第一方向130和第二方向430两者上都是相同的)，一个粘合结构116的表面区域等于宽度138与间隔142 (50μm)之和乘以50μm，并且粘合结构116的底部110的底部接触表面面积等于宽度138 (2μm)乘以2μm。所述比例等于2500μm2除以4μm2，即625。625的比例落在如以上所讨论的大约3到大约1000的最佳比例范围内。
参照图3，间距406对应于宽度124与在位于凹槽306的底部310上方的相邻粘合层316之间的间隔126之和，并且宽度438a对应于宽度124。在一个示例性实施例中，宽度124与间隔126之和是50μm并且宽度124是2μm。假定图4中图示的相对尺寸(例如，宽度438a等于宽度438b，并且间距408在第一方向130和第二方向430两者上都是相同的)，一个粘合层316的表面区域等于宽度124与间隔126 (50μm)之和乘以50μm，并且在粘合层316的底部310的底部接触表面面积等于宽度124 (2μm)乘以2μm。所述比例等于2500μm2除以4μm2，即625。625的比例落在如以上所讨论的大约3到大约1000的最佳比例范围内。
图5A-5D分别图示氧化物层内的粘合结构516的实施例的顶视图。图5A-5D中的粘合结构516对应于粘合结构116、粘合层316和粘合结构416的实施例。氧化物层504对应于氧化物层104、氧化物层304和氧化物层404的实施例。图5A将粘合结构516图示为沟槽结构。图5B将粘合结构516图示为交叉结构。图5C将粘合结构516图示为圆形结构。图5D将粘合结构516图示为弧形结构。在其它实施例中，粘合结构516能够具有任何合适的形状或尺寸。
图6图示用于形成接合垫结构100的方法的实施例的流程图。以600图示所述方法。在602，第一氧化物层103被形成在衬底102上方。在604，多个粘合结构116被形成在第一氧化物层103上方。在一个实施例中，所述多个粘合结构116包括多晶硅。在其它实施例中，粘合结构116能够由其它合适的材料或材料的组合形成。在一个实施例中，在第一氧化物层103上方形成所述多个粘合结构116包括所述多个粘合结构116中的每个粘合结构116沿平行于表面区域136的一个或多个方向与所述多个粘合结构116中的相邻粘合结构116分隔开一定距离142。在一个实施例中，形成所述多个粘合结构116包括将所述多个粘合结构116形成为具有在大约3到大约1000的范围内的、表面区域的面积与所述多个粘合结构116的面积之比。在图4中图示的实施例中，接合垫400的表面区域的面积等于第一距离(136a-136b)和第二距离(436a-436b)的乘积。在一个实施例中，在第一氧化物层103上方形成所述多个粘合结构116包括在覆于衬底102上面的栅极氧化物204上方形成一个或多个装置栅极216。在一个实施例中，装置栅极216和粘合结构116由同一多晶硅层形成。在606，第二氧化物层104被形成在所述多个粘合结构116和第一氧化物层103上方。在一个实施例中，在所述多个粘合结构116和第一氧化物层103上方形成第二氧化物层104包括在一个或多个装置栅极204上方形成装置氧化物204。在一个实施例中，装置氧化物204和第二氧化物104由同一氧化物层形成。在608，多个接触器开口106被形成在第二氧化物层104的表面区域136内。接触器开口106中的每个接触器开口包括一侧或多侧108 (以108a和108b图示)，并且在对应粘合结构116的顶表面140的至少一部分上方对准。在610，阻挡层120被形成在表面区域136内。在一个实施例中，阻挡层120是共形阻挡层120。在图示的实施例中，阻挡层120被形成在第二氧化物层104上方并且在所述多个接触器开口106内并且在所述多个粘合结构116中的对应粘合结构116的顶表面140的至少一部分上方。在各种实施例中，阻挡层120能够由如下任何合适的材料或合适的材料的任何组合形成：包括但不限于Ti、TiN、W、TiW、Ta、TaN、TiSiN、TaSiN、WN、Nb、Mo、MoN、Cr、Co、Ni、Pd、Pt以及这些材料的任何组合或衍生物。在其它实施例中，可使用其它合适的材料或合适的材料的组合。在其它实施例中，阻挡层120包括两层或更多层的合适的材料。例如，在一个实施例中，阻挡层120由Ti和TiN形成，并且是Ti/TiN阻挡层。在612，金属层122被形成在阻挡层120上方。在一个实施例中，金属层122是共形金属层122。在图示的实施例中，金属层122能够由如下任何合适的材料或材料的合金形成：包括但不限于Al、Au、Ag、Cu、W、Cr、Ti、Pt、Pd以及这些材料的任何组合或衍生物。在其它实施例中，金属层122能够由其它合适的材料或材料的组合形成。
空间相对术语(诸如，“在…下面”、“在...下方”、“下”、“在...上方”、“上”等)为了容易描述而被使用以解释一个元件相对于第二元件的定位。这些术语旨在包括除了与附图中描述的那些方位不同的方位之外的所述装置的不同方位。另外，诸如“第一”、“第二”等的术语也被用于描述各种元件、区域、片段等，并且也不旨在是限制性的。相同的术语在整个描述中始终表示相同的元件。
如这里所使用，术语“具有”、“含有”、“包含”、“包括”等是开放式术语，所述开放式术语指示陈述的元件或特征的存在，但不排除另外的元件或特征。冠词“一”、“一个”和“该”旨在包括复数以及单数，除非上下文清楚地另外指示。
考虑到变化和应用的以上范围，应该理解，本发明不由前面的描述限制，也不由附图限制。作为替代，本发明仅由所附的权利要求及其法定等同物限制。

Claims (16)

1.一种接合垫结构，包括：
第一氧化物层，覆于衬底上面；
至少三个粘合结构，形成在第一氧化物层上方，其中至少三个粘合结构的每一个与至少三个粘合结构的相邻粘合结构在至少第一方向和第二方向上间隔开，其中所述第一方向和所述第二方向与所述第一氧化物层的表面区域平行，且其中所述至少三个粘合结构包括多晶硅；
第二氧化物层，形成在所述至少三个粘合结构和第一氧化物层上方，其中形成在第二氧化物层的表面区域内的至少三个接触器开口中的每个接触器开口包括一侧或多侧并且在所述至少三个粘合结构中的对应粘合结构的顶表面的至少一部分上方对准；
阻挡层，形成在所述第二氧化物层的所述表面区域内并且在第二氧化物层上方并且在所述至少三个接触器开口内，其中所述阻挡层在所述至少三个粘合结构中的对应粘合结构的顶表面的所述至少一部分和所述第二氧化物层的所述表面区域上方形成并且与所述至少一部分和所述第二氧化物层的所述表面区域共形；以及
共形金属层，形成在阻挡层上方并具有结构化的表面，其中所述结构化的表面与所述至少三个接触器开口共形并包括在至少三个接触器开口的相邻接触器开口之间的阻挡层上方的共形金属层的表面水平，该表面水平大于在阻挡层上方并在所述至少三个接触器开口内的共形金属层的表面水平。
2.如权利要求1所述的接合垫结构，其中所述阻挡层包括从由下面的材料组成的一组材料选择的材料：Ti、TiN、W、TiW、Ta、TaN、TiSiN、TaSiN、WN、Nb、Mo、MoN、Cr、Co、Ni、Pd、Pt以及这些材料的任何组合或衍生物。
3.如权利要求1所述的接合垫结构，其中所述金属层包括从由下面的材料组成的一组材料选择的材料：Al、Au、Ag、Cu、W、Cr、Ti、Pt、Pd以及这些材料的任何组合或衍生物。
4.如权利要求1所述的接合垫结构，其中所述表面区域的面积与所述至少三个粘合结构的总面积之比在3到1000的范围内。
5.如权利要求1所述的接合垫结构，还包括：
一个或多个装置栅极，每个装置栅极被形成在覆于衬底上面的栅极氧化物上方，其中所述一个或多个装置栅极和所述至少三个粘合结构由同一多晶硅层形成。
6.如权利要求5所述的接合垫结构，其中所述一个或多个装置栅极和所述至少三个粘合结构由同一多晶硅层形成，其中所述一个或多个装置栅极中的每个包括形成在其上方的装置氧化物，并且其中装置氧化物和第二氧化物由同一氧化物层形成。
7.一种接合垫结构，包括：
至少三个凹槽，布置在覆于衬底上面的氧化物层的表面区域内，所述至少三个凹槽中的每个凹槽包括一侧或多侧和底部，所述底部位于氧化物层的表面下方的一定深度，其中所述至少三个凹槽的每一个与至少三个凹槽的相邻凹槽在至少第一方向和第二方向上间隔开，其中所述第一方向和所述第二方向与所述氧化物层的表面区域平行；
粘合层，形成在所述至少三个凹槽的底部上方并且具有小于所述深度的厚度，其中所述粘合层包括多晶硅；
阻挡层，形成在所述表面区域上方并且在所述至少三个凹槽内，其中所述阻挡层在所述粘合层和所述氧化物层的所述表面区域上方形成并与所述粘合层和所述氧化物层的所述表面区域共形；和
共形金属层，形成在阻挡层上方并具有结构化的表面，其中所述结构化的表面与所述至少三个凹槽共形并包括在至少三个凹槽的相邻凹槽之间的阻挡层上方的共形金属层的表面水平，该表面水平大于在阻挡层上方并在所述至少三个凹槽内的共形金属层的表面水平。
8.如权利要求7所述的接合垫结构，其中所述阻挡层包括从由下面的材料组成的一组材料选择的材料：Ti、TiN、W、TiW、Ta、TaN、TiSiN、TaSiN、WN、Nb、Mo、MoN、Cr、Co、Ni、Pd、Pt以及这些材料的任何组合或衍生物。
9.如权利要求7所述的接合垫结构，其中所述金属层包括从由下面的材料组成的一组材料选择的材料：Al、Au、Ag、Cu、W、Cr、Ti、Pt、Pd以及这些材料的任何组合或衍生物。
10.如权利要求7所述的接合垫结构，其中所述表面区域的面积与所述至少三个凹槽的底部上方的粘合层的总面积之比在3到1000的范围内。
11.一种形成接合垫结构的方法，包括：
在衬底上方形成第一氧化物层；
在第一氧化物层上方形成至少三个粘合结构，其中所述至少三个粘合结构的每一个与至少三个粘合结构的相邻粘合结构在至少第一方向和第二方向上间隔开，其中所述第一方向和所述第二方向与所述第一氧化物层的表面区域平行，且其中所述至少三个粘合结构包括多晶硅；
在所述至少三个粘合结构和第一氧化物层上方形成第二氧化物层，
在第二氧化物层的表面区域内形成至少三个接触器开口，其中所述至少三个接触器开口中的每个接触器开口包括一侧或多侧并且在所述至少三个粘合结构中的对应粘合结构的顶表面的至少一部分上方对准；
在所述表面区域内并且在第二氧化物层上方并且在所述至少三个接触器开口内形成阻挡层，其中所述阻挡层在所述至少三个粘合结构中的所述对应粘合结构的顶表面的所述至少一部分和所述第二氧化物层的所述表面区域上方形成并与所述至少一部分和所述第二氧化物层的所述表面区域共形；以及
在阻挡层上方形成具有结构化表面的共形金属层，其中所述结构化的表面与所述至少三个接触器开口共形并包括在至少三个接触器开口的相邻接触器开口之间的阻挡层上方的共形金属层的表面水平，该表面水平大于在阻挡层上方并在所述至少三个接触器开口内的共形金属层的表面水平。
12.如权利要求11所述的方法，其中所述阻挡层包括从由下面的材料组成的一组材料选择的材料：Ti、TiN、W、TiW、Ta、TaN、TiSiN、TaSiN、WN、Nb、Mo、MoN、Cr、Co、Ni、Pd、Pt以及这些材料的任何组合或衍生物。
13.如权利要求11所述的方法，其中所述金属层包括从由下面的材料组成的一组材料选择的材料：Al、Au、Ag、Cu、W、Cr、Ti、Pt、Pd以及这些材料的任何组合或衍生物。
14.如权利要求11所述的方法，其中所述表面区域的面积与所述至少三个粘合结构的总面积之比在3到1000的范围内。
15.如权利要求11所述的方法，其中在第一氧化物层上方形成所述至少三个粘合结构包括：
在覆于衬底上面的栅极氧化物上方形成一个或多个装置栅极，其中所述一个或多个装置栅极和所述至少三个粘合结构由同一多晶硅层形成。
16.如权利要求15所述的方法，其中在所述至少三个粘合结构和第一氧化物层上方形成第二氧化物层包括：
在所述一个或多个装置栅极上方形成装置氧化物，其中装置氧化物和第二氧化物由同一氧化物层形成。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7367580B2 (ja) * 2020-03-23 2023-10-24 三菱電機株式会社 半導体装置
US11495516B2 (en) * 2020-11-20 2022-11-08 Nanya Technology Corporation Semiconductor device with thermal release layer and method for fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734200A (en) * 1994-09-30 1998-03-31 United Microelectronics Corporation Polycide bonding pad structure
CN1770437A (zh) * 2004-11-02 2006-05-10 台湾积体电路制造股份有限公司 接合垫结构
US9230885B2 (en) * 2010-09-30 2016-01-05 Infineon Technologies Ag Semiconductor structure and method for making same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US6054340A (en) * 1997-06-06 2000-04-25 Motorola, Inc. Method for forming a cavity capable of accessing deep fuse structures and device containing the same
US6284655B1 (en) * 1998-09-03 2001-09-04 Micron Technology, Inc. Method for producing low carbon/oxygen conductive layers
TW426980B (en) * 1999-01-23 2001-03-21 Lucent Technologies Inc Wire bonding to copper
US7388289B1 (en) * 1999-09-02 2008-06-17 Micron Technology, Inc. Local multilayered metallization
US6803302B2 (en) * 1999-11-22 2004-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a mechanically robust pad interface
US6683380B2 (en) * 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
KR100403619B1 (ko) * 2001-02-21 2003-10-30 삼성전자주식회사 열적/기계적 스트레스에 저항성이 강한 반도체 소자의 본드패드 및 그 형성방법
US20030166334A1 (en) * 2002-02-14 2003-09-04 Ming-Yu Lin Bond pad and process for fabricating the same
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US6998335B2 (en) * 2003-12-13 2006-02-14 Chartered Semiconductor Manufacturing, Ltd Structure and method for fabricating a bond pad structure
US7307005B2 (en) * 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7335587B2 (en) * 2005-06-30 2008-02-26 Intel Corporation Post polish anneal of atomic layer deposition barrier layers
US8188590B2 (en) * 2006-03-30 2012-05-29 Stats Chippac Ltd. Integrated circuit package system with post-passivation interconnection and integration
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US8563336B2 (en) * 2008-12-23 2013-10-22 International Business Machines Corporation Method for forming thin film resistor and terminal bond pad simultaneously
US8034685B1 (en) * 2010-04-30 2011-10-11 Semiconductor Component Industries, Llc Semiconductor component and method of manufacture
US8836116B2 (en) * 2010-10-21 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates
US8444255B2 (en) * 2011-05-18 2013-05-21 Hewlett-Packard Development Company, L.P. Power distribution in a thermal ink jet printhead
US9201124B2 (en) * 2011-07-14 2015-12-01 National Semiconductor Corporation Die-sized atomic magnetometer and method of forming the magnetometer
US20130075907A1 (en) * 2011-09-23 2013-03-28 Broadcom Corporation Interconnection Between Integrated Circuit and Package
US9613926B2 (en) * 2014-12-26 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer to wafer bonding process and structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734200A (en) * 1994-09-30 1998-03-31 United Microelectronics Corporation Polycide bonding pad structure
CN1770437A (zh) * 2004-11-02 2006-05-10 台湾积体电路制造股份有限公司 接合垫结构
US9230885B2 (en) * 2010-09-30 2016-01-05 Infineon Technologies Ag Semiconductor structure and method for making same

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