JP4701264B2 - 半導体装置、および半導体装置の製造方法 - Google Patents
半導体装置、および半導体装置の製造方法 Download PDFInfo
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Description
前記ボンディングパッドの下面にバリアメタルを介して形成され、同一層内で複数の層間絶縁膜を介して離間して設けられている上部Cu層と、
前記上部Cu層と比べて前記ボンディングパッド下におけるCu層の面積が小さく、前記上部Cu層より前記半導体基板側に形成された下部Cu層と、を有し、
前記上部Cu層と前記下部Cu層とが、前記ボンディングパッドの下において、電気的に絶縁されていることを特徴とする。
前記各Cu層は、前記層間絶縁膜中にCuが埋設されたビアプラグを介して接続されていることとしてもよい。
ビアプラグ、および前記第nCu層のCu層パターンが第1の材料よりなる絶縁膜に埋設されていることとしてもよい。
前記内部回路およびボンディングパッドと電気的に接続された補助Cu配線を有することとしてもよい。
上記のように構成される本発明では、Cuは外部から加えられた力を跳ね返そうとする性質である弾性が酸化膜より大きいため、ボンディングパッド下に、耐衝撃層として、上部Cu層、および上部Cu層と同等以下のCu面積率を有する下部Cu層を設けることで、プロービングおよびボンディング時の衝撃に対する耐性が向上する。
本発明の半導体装置の構成について説明する。
本実施例は、内部回路に接続された補助Cu配線を設け、補助Cu配線にボンディングパッドを接続したことを特徴とする。
本実施例は、第2実施例で示したボンディングパッドを複数配置した場合の一例を示すものである。本実施例の構成について、以下に説明する。
本実施例では、下部Cu層の層間絶縁膜として、SiO2膜の代わりに、第1の材料に比べて比誘電率の低い材料を有する第3の絶縁膜としてSiOC膜を用いたことを特徴とする。以下に、本実施例の構成について説明する。
12、22、32、42、44、52、62、328、330 SiO2膜
13、23、33、43 Stopper−SiCN膜
14、24、34、310、314、318、322、326 積層絶縁膜
15、25、35、45 Cap−SiCN膜
100 上部Cu層
110 上部第1Cu層
120 上部第2Cu層
122 上部第2Cu配線
125 補助Cu配線
130 ボンディングパッド
132 外側パッド
134 内側パッド
140 ビアプラグ
150 ビアホール
200 下部Cu層
210、410 下部第1Cu層
212 下部第1Cu配線
220、412 下部第2Cu層
222 下部第2Cu配線
312、316、320、324 SiOC膜
414 下部第3Cu層
416 下部第4Cu層
600 スクライブ線
700 Cu配線
710 Cu最上層パッド
720 バリアメタル
730 最上層Al配線
735 ボンディング部分
740 パッシベーション絶縁膜
750 層間絶縁膜
Claims (19)
- 半導体基板上にボンディングパッドを有する半導体装置であって、
前記ボンディングパッドの下面にバリアメタルを介して形成され、同一層内で複数の層間絶縁膜を介して離間して設けられている上部Cu層と、
前記上部Cu層と比べて前記ボンディングパッド下におけるCu層の面積が小さく、前記上部Cu層より前記半導体基板側に形成された下部Cu層と、を有し、
前記上部Cu層と前記下部Cu層とが、前記ボンディングパッドの下において、電気的に絶縁されている半導体装置。 - 請求項1に記載の半導体装置であって、
前記ボンディングパッド下における上部Cu層と下部Cu層との間に、Cuが形成されていない層間絶縁膜が設けられている半導体装置。 - 請求項2に記載の半導体装置であって、
前記層間絶縁膜が、下部Cu層に用いられる層間絶縁膜よりも硬質である半導体装置。 - 請求項2に記載の半導体装置であって、
前記層間絶縁膜が、下部Cu層に用いられる層間絶縁膜よりも比誘電率が高い半導体装置。 - 請求項1乃至4のいずれかに記載の半導体装置であって、
前記上部Cu層が複数層からなる半導体装置。 - 請求項5に記載の半導体装置であって、
各Cu層の層間には層間絶縁膜が設けられ、
前記各Cu層は、前記層間絶縁膜中にCuが埋設されたビアプラグを介して接続されている半導体装置。 - 請求項5または6に記載の半導体装置であって、
前記複数層の上部Cu層として、半導体基板側からボンディングパッド側に第1Cu層、第2Cu層、…、および第nCu層(nは2以上の自然数)が順に設けられている場合、
ビアプラグ、および前記第nCu層のCu層パターンが第1の材料よりなる絶縁膜に埋設されている半導体装置。 - 請求項1乃至7のいずれかに記載の半導体装置であって、
前記下部Cu層が複数層からなる半導体装置。 - 請求項8に記載の半導体装置であって、
前記複数層の下部Cu層の各Cu層間に第1の材料よりなる絶縁膜が介在する半導体装置。 - 請求項8または9に記載の半導体装置であって、
前記複数層の下部Cu層の各Cu層において同一層に形成されたCu層パターン間に、第1の材料に比べて比誘電率が低い材料を有する第2の材料よりなる絶縁膜が介在する半導体装置。 - 請求項10に記載の半導体装置であって、
第2の材料が第1の材料よりも軟質である半導体装置。 - 請求項10または11に記載の半導体装置であって、
第2の材料よりなる絶縁膜は、SiOC膜、SiC膜、SiOF膜、ポーラスSiO2膜、ポーラスSiOC膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含む半導体装置。 - 請求項8乃至12のいずれかに記載の半導体装置であって、
複数層の前記下部Cu層の各Cu層間に、第1の材料に比べて比誘電率が低い材料を有する第3の材料よりなる絶縁膜が介在する半導体装置。 - 請求項13に記載の半導体装置であって、
第3の材料が第1の材料よりも軟質である半導体装置。 - 請求項13または14に記載の半導体装置であって、
第3の材料よりなる絶縁膜は、SiOC膜、SiC膜、SiOF膜、ポーラスSiO2膜、ポーラスSiOC膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含む半導体装置。 - 請求項1乃至15のいずれかに記載の半導体装置であって、
バリアメタルがTiNおよびTaNのうちいずれか一方を含む半導体装置。 - 請求項1乃至16のいずれかに記載の半導体装置であって、
前記半導体装置に内部回路を備え、
前記内部回路およびボンディングパッドと電気的に接続された補助Cu配線を有する半導体装置。 - 請求項1乃至17のいずれかに記載の半導体装置の製造方法であって、
前記上部Cu層および前記下部Cu層をダマシン法により形成する半導体装置の製造方法。 - 請求項5に記載の半導体装置の製造方法であって、
第nCu層および該第nCu層に接触するビアプラグをデュアルダマシン法により形成することを特徴とする半導体装置の製造方法。
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