CN107527821A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN107527821A
CN107527821A CN201710303451.6A CN201710303451A CN107527821A CN 107527821 A CN107527821 A CN 107527821A CN 201710303451 A CN201710303451 A CN 201710303451A CN 107527821 A CN107527821 A CN 107527821A
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pad
semiconductor device
insulating barrier
metal level
thickness
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CN201710303451.6A
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CN107527821B (zh
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吉泽隆彦
渡边邦雄
白泽立基
作田孝
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供半导体装置及其制造方法，该半导体装置的制造方法能够使焊盘的机械强度比以往提高而抑制裂纹的产生。该半导体装置的制造方法具有如下工序：形成由第1金属层构成的第1焊盘；在第1焊盘上形成绝缘层；通过去除第1焊盘的至少一部分区域上的绝缘层，在绝缘层设置开口部；以使第2焊盘具有比绝缘层的膜厚小的膜厚的方式，在绝缘层的开口部形成由第2金属层构成的第2焊盘；以及在第2焊盘上形成由第3金属层构成的第3焊盘。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法等。
背景技术
作为在构成半导体装置的半导体芯片上形成的金属布线的材料，一般情况下，使用铝(Al)或其合金。在半导体芯片中，金属布线的一部分区域构成为了进行电源供给或信号传送而与外部电连接的焊盘(端子)。例如，在具有多层布线构造的半导体芯片的情况下，形成在层间绝缘膜上的最上层的金属布线的一部分区域构成焊盘。
而且，半导体芯片的焊盘与半导体封装件或者印刷基板等的端子或者电极通过引线接合而电连接。以往，在引线接合中使用金(Au)线，但近年来，也使用铜(Cu)线。但是，铜线与金线或铝焊盘相比，具有高硬度，在引线接合时，有时焊盘的强度不足而无法耐受机械的应力，焊盘或层间绝缘膜产生裂纹。
作为关联的技术，在专利文献1中公开了防止半导体装置的接合焊盘被水分等腐蚀的技术。该半导体装置具有：金属布线图案，其包含在半导体衬底上隔着绝缘膜而设置的接合焊盘；绝缘保护膜，其覆盖金属布线图案；以及接合线，其与接合焊盘接合，其中，该半导体装置的特征在于，绝缘保护膜由有机树脂膜构成并且覆盖除了与接合引线接合的部分之外的接合焊盘的露出面。
但是，在专利文献1中，包含在半导体衬底上隔着绝缘膜而设置的接合焊盘在内的金属布线图案也是单层的。因此，尤其在使用铜接合线的情况下，当将接合线与接合焊盘接合时，可能在接合焊盘或绝缘膜上产生裂纹。
专利文献1：日本特开平7-94639号公报(摘要、权利要求1、图1)
发明内容
本发明的几个方式涉及提供能够使焊盘的机械强度比以往提高从而抑制裂纹的产生的半导体装置及其制造方法。此外，本发明的其他的几个方式涉及不对通常的半导体装置的制造方法追加新的工序而制造那样的半导体装置的技术。
本发明的第1方式的半导体装置的制造方法具有如下工序：工序(a)，形成由第1金属层构成的第1焊盘；工序(b)，在第1焊盘上形成绝缘层；工序(c)，通过去除第1焊盘的至少一部分区域上的绝缘层，在绝缘层设置开口部；工序(d)，以使第2焊盘具有比绝缘层的膜厚小的膜厚的方式，在绝缘层的开口部形成由第2金属层构成的第2焊盘；以及工序(e)，在第2焊盘上形成由第3金属层构成的第3焊盘。
根据本发明的第1方式，由于通过包含第1～第3焊盘的多个金属板构成多层构造的焊盘，因此，能够使焊盘的机械强度比以往提高而抑制裂纹的产生。此外，由于以使第2焊盘具有比绝缘层的膜厚小的膜厚的方式形成第2焊盘，因此，无需对第2焊盘进行研磨而使其变薄。而且，通过与形成金属布线或者栓塞同时地形成第1以及第2焊盘，无需对通常的半导体装置的制造方法追加新的工序，就能够制造那样的半导体装置。
这里，可以是，工序(c)包含：在绝缘层设置具有比开口部的开口直径小的开口直径的通孔，工序(d)包含：以使第2金属层具有比绝缘层的膜厚大的膜厚的方式在绝缘层的通孔形成第2金属层。由此，能够在向通孔内填充足够的量的金属而形成栓塞的同时，在开口部形成第2焊盘。
在该情况下，可以是，工序(d)还包含：去除在绝缘层的上层形成的第2金属层。由此，能够以使栓塞不从通孔突出的方式使绝缘层的上表面平坦化。
本发明的第1方式的半导体装置的制造方法可以还具有将铜(Cu)线的一端接合在第3焊盘上的工序(f)。由此，能够将半导体芯片的焊盘与半导体封装件或者印刷基板等的端子或者电极电连接。
本发明的第2方式的半导体装置具有：第1焊盘，其由第1金属层构成；绝缘层，其配置于第1焊盘上，具有开口部；第2焊盘，其配置于绝缘层的开口部，具有比绝缘层的膜厚小的膜厚，由第2金属层构成；以及第3焊盘，其配置于第2焊盘上，由第3金属层构成。
根据本发明的第2方式，由于通过包含第1～第3焊盘的多个金属板构成多层构造的焊盘，因此，能够使焊盘的机械强度比以往提高而抑制裂纹的产生。
这里，在半导体装置还具有在俯视观察时覆盖第3焊盘的周边部的保护膜的情况下，期望在第3焊盘的未被保护膜覆盖的区域的下层，第2焊盘具有均匀的膜厚。由此，在第2焊盘的中央部比周边部薄的情况下产生的向中央部的应力集中被缓和，能够抑制焊盘中的裂纹的产生。
而且，可以是，第2焊盘具有由沿着第1焊盘配置的底部、和沿着绝缘层的开口部的4个侧面配置的4个侧壁构成的箱形的形状。由于第2焊盘的底部的膜厚比绝缘层的膜厚小，因此，能够使第1焊盘与第3焊盘之间的第2焊盘的电阻值下降，或者使第2焊盘的制造成本下降。
此外，可以是，绝缘层还具有通孔，该通孔具有比开口部的开口直径小的开口直径，半导体装置还具有栓塞，该栓塞配置于绝缘层的通孔，与第1焊盘和第3焊盘电连接。由此，能够强化第1焊盘与第3焊盘之间的电连接。
以上，可以是，第1焊盘具有1.5μm以下的膜厚。在使用多层构造的焊盘的情况下，即使为了半导体装置的高集成化而使各层的焊盘的膜厚变薄，也能够使焊盘的机械强度提高而抑制裂纹的产生。
而且，可以是，第2焊盘具有比第1焊盘以及第3焊盘各自的杨氏模量大的杨氏模量。例如，可以是，第1焊盘以及第3焊盘分别包含铝(Al)，第2焊盘包含钨(W)。由此，施加于第3焊盘的一部分区域的力在沿着第2焊盘的主面分散之后，经由第1焊盘施加于层间绝缘膜，因此，能够抑制层间绝缘膜中的裂纹的产生。
此外，可以是，第1焊盘配置于包含FSG(掺氟的硅酸盐玻璃)或者Low-k材料的层间绝缘膜上。通过使用这样的层间绝缘膜，能够降低焊盘的寄生电容，但层间绝缘膜的机械强度下降。但是，在使用多层构造的焊盘的情况下，即使层间绝缘膜的机械强度变低，也能够提高焊盘的机械强度而抑制裂纹的产生。
附图说明
图1是本发明一个实施方式的半导体装置的第1工序的剖视图。
图2是本发明一个实施方式的半导体装置的第2工序的剖视图。
图3是本发明一个实施方式的半导体装置的第3工序的剖视图。
图4是本发明一个实施方式的半导体装置的第3工序的剖视图。
图5是本发明一个实施方式的半导体装置的第4工序的剖视图。
图6是本发明一个实施方式的半导体装置的第5工序的剖视图。
图7是本发明一个实施方式的半导体装置的第5工序的剖视图。
图8是本发明一个实施方式的半导体装置的第6工序的剖视图。
图9是本发明一个实施方式的半导体装置的第7工序的剖视图。
图10是本发明一个实施方式的半导体装置的第8工序的剖视图。
图11是本发明一个实施方式的半导体装置的第8工序的剖视图。
图12是本发明一个实施方式的半导体装置的第9工序的剖视图。
图13是本发明一个实施方式的半导体装置的第9工序的剖视图。
图14是本发明一个实施方式的半导体装置的第10工序的剖视图。
图15是本发明一个实施方式的半导体装置的第11的工序的剖视图。
图16是本发明一个实施方式的半导体装置的剖视图。
图17是本发明一个实施方式的半导体装置的俯视图。
标号说明
10：半导体衬底；11：栅电极；12、13：杂质区域；14：接触区域；15、16：侧壁绝缘膜；20：层间绝缘膜；21、22：栓塞；30：金属层；31、32：金属布线；40：层间绝缘膜；41、42：栓塞；50：金属层；51：金属布线；52：第1焊盘；60：层间绝缘膜；60a：通孔；60b：开口部；70：金属膜；71：栓塞；72：第2焊盘；72a：底部；72b～72e：侧壁；80：金属层；81：第3焊盘；90：钝化膜；100：线。
具体实施方式
以下，参照附图对本发明的实施方式进行详细说明。另外，对同一结构要素赋予同一参照标号，省略重复的说明。
<半导体装置的制造方法>
图1～图15是本发明一个实施方式的半导体装置的制造工序的剖视图。以下，作为一例，对使用P型的半导体衬底制造包含N沟道MOS晶体管的半导体装置的情况进行说明。
在第1工序中，如图1所示，在半导体衬底10上隔着栅绝缘膜形成栅电极11，通过光刻法来构图。例如，半导体衬底10由包含硼(B)离子等P型的杂质的硅(Si)等构成。栅绝缘膜由二氧化硅(SiO2)等构成，栅电极11由掺杂有杂质并具有导电性的多晶硅等构成。
此外，使用通过光刻法形成的掩模，向栅电极11的两侧的半导体衬底10的区域注入锑(Sb)或者磷(P)离子等N型的杂质。由此，形成了作为N沟道MOS晶体管的源极以及漏极的N型的杂质区域12以及13。
而且，使用通过光刻法形成的掩模向半导体衬底10的规定的区域注入硼(B)离子等P型的杂质。由此，形成了半导体衬底10的接触区域即P型的杂质区域14。此外，可以如图1所示，在栅绝缘膜以及栅电极11的侧面形成侧壁绝缘膜15以及16。
在第2工序中，如图2所示，在设置有栅电极11等的半导体衬底10上形成层间绝缘膜20。层间绝缘膜20以及以下说明的层间绝缘膜40和60例如可以由二氧化硅(SiO2)或者BPSG(Boron Phosphorus Silicon Glass：硼磷硅玻璃)等构成。而且，通过光刻法在层间绝缘膜20上设置光致抗蚀剂，以光致抗蚀剂为掩模对层间绝缘膜20进行蚀刻，由此，在层间绝缘膜20中设置通孔以及接触孔。
向层间绝缘膜20的通孔以及接触孔填充钨(W)等金属，形成栓塞21以及22。另外，在形成栓塞时，可以在钨(W)等金属的周围配置钛(Ti)或者氮化钛(Ti)等阻挡金属。此后，通过CMP(Chemical Mechanical Polishing：化学机械研磨)等对层间绝缘膜20的上表面进行研磨，由此，去除形成于层间绝缘膜20的上表面的多余的金属膜。
层间绝缘膜20的通孔到达栅电极11，形成于通孔的栓塞21与栅电极11电连接。层间绝缘膜20的接触孔到达半导体衬底10的接触区域14，形成于接触孔的栓塞22与接触区域14电连接。
在第3工序中，如图3所示，在层间绝缘膜20上形成金属层30。金属层30例如包含铝(Al)。而且，通过光刻法在金属层30上设置光致抗蚀剂，以光致抗蚀剂为掩模对金属层30进行蚀刻，由此，如图4所示，在层间绝缘膜20上形成金属布线31以及32。金属布线31经由栓塞21与栅电极11电连接，金属布线32经由栓塞22与半导体衬底10的接触区域14电连接。
在第4工序中，如图5所示，在设置有金属布线31以及32的层间绝缘膜20上形成层间绝缘膜40。而且，通过光刻法在层间绝缘膜40上设置光致抗蚀剂，以光致抗蚀剂为掩模对层间绝缘膜40进行蚀刻，由此，在层间绝缘膜40设置通孔。
向层间绝缘膜40的通孔填充钨(W)等金属，形成栓塞41以及42。此后，通过CMP等对层间绝缘膜40的上表面进行研磨，由此，去除形成于层间绝缘膜40的上层的多余的金属膜。层间绝缘膜40的通孔到达金属布线31以及32，形成于通孔的栓塞41以及42分别与金属布线31以及32电连接。
在第5工序中，如图6所示，在层间绝缘膜40上形成金属层50。金属层50例如包含铝(Al)，相当于构成多层构造的焊盘的第1金属层。而且，通过光刻法在金属层50上设置光致抗蚀剂，以光致抗蚀剂为掩模对金属层50进行蚀刻，由此，如图7所示，在层间绝缘膜40上形成金属布线51。与此同时，在层间绝缘膜40上形成由第1金属层构成的第1焊盘52。金属布线51经由栓塞41与金属布线31电连接，第1焊盘52经由栓塞42与金属布线32电连接。
在第6工序中，如图8所示，在设置有金属布线51以及第1焊盘52的层间绝缘膜40上形成层间绝缘膜60作为绝缘层。而且，在第7工序中，通过光刻法在层间绝缘膜60上设置光致抗蚀剂，以光致抗蚀剂为掩模对层间绝缘膜60进行蚀刻，由此，如图9所示，在层间绝缘膜60上设置通孔60a。与此同时，通过去除第1焊盘52的至少一部分区域上的层间绝缘膜60，在层间绝缘膜60设置开口部60b。通孔60a具有比开口部60b的开口直径小的开口直径。
在第8工序中，如图10所示，在第1焊盘52以及层间绝缘膜60上形成金属膜70。金属膜70例如包含钨(W)，相当于构成多层构造的焊盘的第2金属层。由此，向层间绝缘膜60的通孔60a填充包含钨(W)的金属，形成栓塞71。与此同时，在层间绝缘膜60的开口部60b处，由第2金属层构成的第2焊盘72形成于第1焊盘52上。
第2焊盘72形成为除了作为层间绝缘膜60的侧壁的部分之外具有比相邻的层间绝缘膜60的膜厚(栓塞71的厚度)小的膜厚。由此，由于无需对第2焊盘72的中央部进行研磨而使其变薄，因此，防止研磨工序中的凹陷(dishing，中央部的过度研磨)的产生，通过使向中央部的应力集中缓和，能够抑制焊盘中的裂纹的产生。
一般情况下，当通过CMP对焊盘那样的大的板进行研磨时，产生凹陷。当由于凹陷而使焊盘的中央部凹入时，在引线接合工序中，应力集中于焊盘的中央部。因此，如果无需对焊盘的中央部进行研磨，则不产生凹陷，因此，能够使焊盘的机械强度比以往提高而抑制裂纹的产生。
另一方面，在层间绝缘膜60的通孔60a中，可以以使金属膜70具有比相邻的层间绝缘膜60的膜厚大的膜厚的方式形成金属膜70。由此，能够在向通孔60a内填充足够的量的金属而形成栓塞71的同时，在开口部60b形成第2焊盘72。
此后，如图11所示，通过CMP等对层间绝缘膜60的上表面进行研磨，由此，去除了形成于层间绝缘膜60的上层的多余的金属膜。由此，栓塞71不从通孔60a突出，能够使层间绝缘膜60的上表面平坦化。栓塞71以及第2焊盘72与第1焊盘52电连接。
在第9工序中，如图12所示，在层间绝缘膜60以及第2焊盘72上形成金属层80。金属层80例如包含铝(Al)，相当于构成多层构造的焊盘的第3金属层。而且，通过光刻法在金属层80上设置光致抗蚀剂，以光致抗蚀剂为掩模对金属层80进行蚀刻，由此，如图13所示，在层间绝缘膜60以及第2焊盘72上形成由第3金属层构成的第3焊盘81。第3焊盘81经由栓塞71以及第2焊盘72与第1焊盘52电连接。
在第10工序中，如图14所示，通过光刻法在层间绝缘膜60以及第3焊盘81上形成俯视时覆盖第3焊盘81的周边部的钝化膜(保护膜)90。另外，在本申请中，“俯视”是指从与半导体衬底10的主面(图中的上表面)垂直的方向对各部分进行透视。钝化膜90例如由氮化硅(Si3N4)、二氧化硅(SiO2)或者氧化镁(MgO)等的绝缘膜构成。
而且，在第11工序中，如图15所示，可以将线100的一端与第3焊盘81接合。由此，能够将半导体芯片的焊盘与半导体封装件或者印刷基板等的端子或者电极电连接。在本申请中，也将在第3焊盘81的主面(图中的上表面)中未被钝化膜90覆盖的区域称为“接合区域”。例如，在通过放电使线100的前端的金属熔融而成为球状之后，通过热、超声波或者压力来将线100的前端与第3焊盘81的接合区域连接。
在引线接合工序中，使用铜(Cu)或者金(Au)等的线。特别地，铜线与金线或铝焊盘相比，具有高硬度，在引线接合时，有时焊盘的强度不足而无法耐受机械的应力，焊盘或层间绝缘膜产生裂纹。
根据本实施方式，由于通过包含第1焊盘52、第2焊盘72以及第3焊盘81的多个金属板构成多层构造的焊盘，因此，能够使焊盘的机械强度比以往提高而抑制裂纹的产生。此外，由于以使第2焊盘72具有比层间绝缘膜60的膜厚小的膜厚的方式形成第2焊盘72，因此，无需对第2焊盘72进行研磨而使其变薄。而且，通过与形成金属布线或者栓塞同时地形成第1焊盘52以及第2焊盘72，无需对通常的半导体装置的制造方法追加新的工序，就能够制造本实施方式的半导体装置。
<半导体装置>
图16是本发明一个实施方式的半导体装置的剖视图，图17是本发明一个实施方式的半导体装置的俯视图。如图16以及图17所示，本发明一个实施方式的半导体装置具有半导体衬底10、层间绝缘膜20、金属布线31和32、层间绝缘膜40、金属布线51和第1焊盘52、层间绝缘膜60、第2焊盘72、第3焊盘81以及钝化膜90。
如图16所示，在P型的半导体衬底10上例如配置有具有栅电极11的N沟道MOS晶体管以及接触区域14。在半导体衬底10上配置有层间绝缘膜20，在层间绝缘膜20上配置有金属布线31和32以及层间绝缘膜40。金属布线31经由配置于层间绝缘膜20的通孔的栓塞与栅电极11电连接。金属布线32经由配置于层间绝缘膜20的接触孔的栓塞与半导体衬底10的接触区域14电连接。
在层间绝缘膜40上配置有：金属布线51；由第1金属层构成的第1焊盘52；以及层间绝缘膜60。金属布线51经由配置于层间绝缘膜40的通孔的栓塞与金属布线31电连接。在该例中，金属布线51与N沟道MOS晶体管的栅电极11电连接，用于向栅电极11供给信号。第1焊盘52经由配置于层间绝缘膜40的通孔的栓塞与金属布线32电连接。
在第1焊盘52上配置有具有通孔60a(图9)以及开口部60b(图9)的绝缘层即层间绝缘膜60。通孔60a具有比开口部60b的开口直径小的开口直径。在层间绝缘膜60的开口部60b配置有由第2金属层构成的第2焊盘72。此外，在层间绝缘膜60以及第2焊盘72上配置有由第3金属层构成的第3焊盘81。而且，可以将线100(图15)的一端与第3焊盘81接合。
如图16以及图17所示，第1焊盘52、第2焊盘72以及第3焊盘81层叠，构成了多层构造的焊盘。在该例中，多层构造的焊盘与半导体衬底10的接触区域14电连接，用于向半导体衬底10供给电位。根据本实施方式，由于通过包含第1焊盘52、第2焊盘72以及第3焊盘81的多个金属板构成多层构造的焊盘，因此，能够使焊盘的机械强度比以往提高而抑制裂纹的产生。
此外，可以是，半导体装置还具有配置于层间绝缘膜60的通孔60a的栓塞71。栓塞71与第1焊盘52以及第3焊盘81电连接。由此，能够强化第1焊盘52与第3焊盘81之间的电连接。
在俯视时，钝化膜90覆盖第3焊盘81的周边部。这里，期望在第3焊盘81的未被钝化膜90覆盖的区域(接合区域)的下层，第2焊盘72具有均匀的(大致恒定的)膜厚。由此，在第2焊盘72的中央部比周边部薄的情况下产生的向中央部的应力集中被缓和，能够抑制焊盘中的裂纹的产生。
第2焊盘72除了作为层间绝缘膜60的侧壁的部分之外，具有比相邻的层间绝缘膜60的膜厚(栓塞71的厚度)小的膜厚。例如，第2焊盘72具有由沿着第1焊盘52配置的底部72a、以及沿着层间绝缘膜60的开口部60b(图9)的4个侧面配置的4个侧壁72b～72e构成的箱形的形状。由于第2焊盘72的底部72a的膜厚比层间绝缘膜60的膜厚小，因此，能够使第1焊盘52与第3焊盘81之间的第2焊盘72的电阻值下降，或者使第2焊盘72的制造成本下降。
以上，可以是，第1焊盘具有1.5μm以下的膜厚。在使用多层构造的焊盘的情况下，即使为了半导体装置的高集成化而使各层的焊盘的膜厚变薄，也能够使焊盘的机械强度提高而抑制裂纹的产生。此外，可以是，配置于层间绝缘膜60的栓塞71具有1.5μm以下的厚度，第2焊盘72具有1.5μm以下的膜厚，或者，第3焊盘81具有1.5μm以下的膜厚。
而且，可以是，第2焊盘72具有比第1焊盘52以及第3焊盘81各自的杨氏模量大的杨氏模量。例如，第1焊盘52以及第3焊盘81分别包含铝(Al)，由铝(Al)或者铝的合金(Al-Cu等)构成。此外，第2焊盘72包含钨(W)，由钨(W)或者作为钨与硅的化合物的硅化钨(WSi)等构成。
这里，铝(Al)的杨氏模量是大约70GPa。此外，钨(W)的杨氏模量是大约410GPa，硅化钨(WSi)的杨氏模量是大约403GPa。另外，二氧化硅(SiO2)的杨氏模量是大约70GPa。
通过由具有上述那样的杨氏模量的第1焊盘52、第2焊盘72以及第3焊盘81构成多层构造的焊盘，施加于第3焊盘81的一部分区域的力在沿着第2焊盘72的主面分散后，经由第1焊盘52施加于层间绝缘膜40，因此，能够抑制层间绝缘膜40中的裂纹的产生。
此外，第1焊盘52可以配置于包含FSG(为了降低相对介电常数而掺氟的硅酸盐玻璃)或者Low-k材料的层间绝缘膜40上。Low-k材料是指相对介电常数比二氧化硅(SiO2)低的层间绝缘膜材料，例如，具有3.0以下的相对介电常数(k)。
具体而言，作为层间绝缘膜40，能够使用PE-CVD(Plasma Enhanced-ChemicalVapor Deposition：等离子体增强化学气相沉积)的添加了碳的硅氧化膜(SiOC膜)、向二氧化硅(SiO2)导入空位来降低了相对介电常数的多孔二氧化硅膜。
通过使用这样的层间绝缘膜40，能够降低焊盘的寄生电容，但层间绝缘膜40的机械强度下降。但是，在使用多层构造的焊盘的情况下，即使层间绝缘膜40的机械强度变低，也能够提高焊盘的机械强度而抑制裂纹的产生。

Claims (12)

1.一种半导体装置的制造方法，其中，该半导体装置的制造方法具有如下工序：
工序(a)，形成由第1金属层构成的第1焊盘；
工序(b)，在所述第1焊盘上形成绝缘层；
工序(c)，通过去除所述第1焊盘的至少一部分区域上的所述绝缘层，在所述绝缘层设置开口部；
工序(d)，以使第2焊盘具有比所述绝缘层的膜厚小的膜厚的方式，在所述绝缘层的所述开口部形成由第2金属层构成的第2焊盘；以及
工序(e)，在所述第2焊盘上形成由第3金属层构成的第3焊盘。
2.根据权利要求1所述的制造方法，其中，
工序(c)包含：在所述绝缘层设置具有比所述开口部的开口直径小的开口直径的通孔，
工序(d)包含：以使所述第2金属层具有比所述绝缘层的膜厚大的膜厚的方式在所述绝缘层的所述通孔形成所述第2金属层。
3.根据权利要求2所述的制造方法，其中，
工序(d)还包含：去除在所述绝缘层的上层形成的所述第2金属层。
4.根据权利要求1～3中的任意一项所述的制造方法，其中，
该制造方法还具有将铜线的一端接合在所述第3焊盘上的工序(f)。
5.一种半导体装置，其中，该半导体装置具有：
第1焊盘，其由第1金属层构成；
绝缘层，其配置于所述第1焊盘上，具有开口部；
第2焊盘，其配置于所述绝缘层的所述开口部，具有比所述绝缘层的膜厚小的膜厚，由第2金属层构成；以及
第3焊盘，其配置于所述第2焊盘上，由第3金属层构成。
6.根据权利要求5所述的半导体装置，其中，
该半导体装置还具有保护膜，在俯视时，所述保护膜覆盖所述第3焊盘的周边部，
在所述第3焊盘的未被所述保护膜覆盖的区域的下层，所述第2焊盘具有均匀的膜厚。
7.根据权利要求5或6所述的半导体装置，其中，
所述第2焊盘具有由沿着所述第1焊盘配置的底部、和沿着所述绝缘层的所述开口部的4个侧面配置的4个侧壁构成的箱形的形状。
8.根据权利要求5～7中的任意一项所述的半导体装置，其中，
所述绝缘层还具有通孔，该通孔具有比所述开口部的开口直径小的开口直径，
该半导体装置还具有栓塞，所述栓塞配置于所述绝缘层的所述通孔，与所述第1焊盘和所述第3焊盘电连接。
9.根据权利要求5～8中的任意一项所述的半导体装置，其中，
所述第1焊盘具有1.5μm以下的膜厚。
10.根据权利要求5～9中的任意一项所述的半导体装置，其中，
所述第2焊盘具有比所述第1焊盘以及所述第3焊盘各自的杨氏模量大的杨氏模量。
11.根据权利要求5～10中的任意一项所述的半导体装置，其中，
所述第1焊盘以及所述第3焊盘分别包含铝，所述第2焊盘包含钨。
12.根据权利要求5～11中的任意一项所述的半导体装置，其中，
所述第1焊盘配置于包含掺氟的硅酸盐玻璃或者Low-k材料的层间绝缘膜上。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112420647A (zh) * 2019-08-23 2021-02-26 铠侠股份有限公司 半导体装置及其制造方法
CN113474871A (zh) * 2019-03-06 2021-10-01 三菱电机株式会社 半导体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020155719A1 (en) * 2001-04-24 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20060091536A1 (en) * 2004-11-02 2006-05-04 Tai-Chun Huang Bond pad structure with stress-buffering layer capping interconnection metal layer
CN101383303A (zh) * 2007-07-23 2009-03-11 株式会社瑞萨科技 半导体装置及其制造方法
US20140042633A1 (en) * 2012-08-10 2014-02-13 Samsung Electronics Co., Ltd. Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01130545A (ja) * 1987-11-17 1989-05-23 Mitsubishi Electric Corp 樹脂封止型半導体装置
JPH0794639A (ja) 1993-06-14 1995-04-07 Toshiba Corp 半導体装置及び製造方法
JP3176806B2 (ja) * 1994-09-09 2001-06-18 松下電子工業株式会社 半導体保護装置
JP3457123B2 (ja) * 1995-12-07 2003-10-14 株式会社リコー 半導体装置
JP2974022B1 (ja) * 1998-10-01 1999-11-08 ヤマハ株式会社 半導体装置のボンディングパッド構造
JP2001326242A (ja) * 2000-05-16 2001-11-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6647198B2 (en) * 2000-07-14 2003-11-11 Semco Machine Corporation Apparatus for housing fiber optic modules
JP2003068740A (ja) * 2001-08-30 2003-03-07 Hitachi Ltd 半導体集積回路装置およびその製造方法
KR100437460B1 (ko) * 2001-12-03 2004-06-23 삼성전자주식회사 본딩패드들을 갖는 반도체소자 및 그 제조방법
JP4242336B2 (ja) * 2004-02-05 2009-03-25 パナソニック株式会社 半導体装置
JP2005243907A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
JP2008244134A (ja) * 2007-03-27 2008-10-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5205066B2 (ja) * 2008-01-18 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2010080772A (ja) * 2008-09-26 2010-04-08 Rohm Co Ltd 半導体装置
JP2012146720A (ja) * 2011-01-07 2012-08-02 Renesas Electronics Corp 半導体装置およびその製造方法
JP5677115B2 (ja) * 2011-02-07 2015-02-25 セイコーインスツル株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020155719A1 (en) * 2001-04-24 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20060091536A1 (en) * 2004-11-02 2006-05-04 Tai-Chun Huang Bond pad structure with stress-buffering layer capping interconnection metal layer
CN1770437A (zh) * 2004-11-02 2006-05-10 台湾积体电路制造股份有限公司 接合垫结构
CN101383303A (zh) * 2007-07-23 2009-03-11 株式会社瑞萨科技 半导体装置及其制造方法
US20140042633A1 (en) * 2012-08-10 2014-02-13 Samsung Electronics Co., Ltd. Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113474871A (zh) * 2019-03-06 2021-10-01 三菱电机株式会社 半导体装置
CN113474871B (zh) * 2019-03-06 2023-10-20 三菱电机株式会社 半导体装置
CN112420647A (zh) * 2019-08-23 2021-02-26 铠侠股份有限公司 半导体装置及其制造方法
CN112420647B (zh) * 2019-08-23 2024-04-09 铠侠股份有限公司 半导体装置及其制造方法

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