JP2005243907A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2005243907A JP2005243907A JP2004051486A JP2004051486A JP2005243907A JP 2005243907 A JP2005243907 A JP 2005243907A JP 2004051486 A JP2004051486 A JP 2004051486A JP 2004051486 A JP2004051486 A JP 2004051486A JP 2005243907 A JP2005243907 A JP 2005243907A
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Abstract
【解決手段】半導体チップ上に、ボンディングパッド1が複数個設けられる。それぞれのボンディングパッド1においては、最上層の配線層を用いて形成された第1メタル11の下に、ライン状の第2メタル12が複数個設けられる。ボンディングパッド1は、第2メタル12の長手方向に並べて配設される。つまり、第2メタル12の長手方向L1と、ボンディングパッド1の配列方向L2とが同じ方向になるように、ボンディングパッド1を並べて配設する。
【選択図】図7
Description
図1〜図3は、本発明の実施の形態1に係る半導体装置のボンディングパッドの構造を示す図であり、図1はボンディングパッドの上面図、図2および図3はそれぞれ図1のA−A線およびB−B線に沿った当該ボンディングパッドの断面図である。
W≦D≦2×W ・・・(1)
の関係を満たす場合に、上記の効果が得られた。ここで、図4は図2に示す領域Cの拡大断面図である。ビアホールは上方向からのエッチングにより形成されるため、その上部が底部よりも広く形成される傾向にある。そのため第2メタル12は、図4の如くそれぞれが逆台形型に形成される。ビアホールの底部では比較的設計寸法に近い寸法で形成可能であるので、本明細書においては第2メタル12の幅Wおよび間隔Dを、図4に示すように第2メタル12の底部における寸法として定義している。
W0≦D0≦2×W0 ・・・(2)
の関係を満たす場合において、上記の効果が得られた。
図11および図12は、実施の形態2に係る半導体装置のボンディングパッドの断面図である。なお、その上面図は図1と同様であるので省略するが、図11および図12は、それぞれ図1のA−A線およびB−B線に沿った当該ボンディングパッドの断面に相当している。そして図13は、図11に示す領域Cの拡大図である。これらの図において、図2および図3に示したものと同様の機能を有する要素には同一符号を付してある。当該半導体装置は、第2メタル12の下に第3メタル13が形成されないことを除いて、実施の形態1の半導体装置と同様の構造であるので、ここでは各要素の説明は省略する。
上記のように、実施の形態2によれば、実施の形態1よりもクラックの発生を抑制することが可能である。しかし、その形成工程には次のような問題点がある。図14はその問題点を説明するための図であり、第2メタル12を形成するためのビアホールの形成工程を示している。同図の左側はボンディングパッド1が形成されるパッド形成領域を示しており、右側は第1下層配線層の本来の配線113が形成される通常配線領域を示している。
ボンディングパッドの下方にクラックが生じ、それが配線にまで到達すると、当該配線のメタルマイグレーション耐性が劣化してしまう。また、ボンディングパッドの下方に配線を通すことによって、ボンディングパッドと当該配線との間の層間絶縁膜にクラックが発生しやすくなり、強度が低下する傾向がある。従って、クラックの発生を防止するという視点からは、ボンディングパッドの下方に不用意に配線を通さないことが望ましい。しかし、半導体装置の高集積化のためには、ボンディングパッドの下の領域も有効利用する必要があり、ボンディングパッドの下方に配線を通すことが余儀なくされている。そこで本実施の形態では、ボンディングパッドの下方に、配線を通した場合でも、強度の劣化を抑制することが可能な半導体装置構造を提案する。
実施の形態4の実験および応力シミュレーションによって、ボンディングパッドの下方に配線を通す場合でも、当該配線上面に複数個のメタルを設けることで、クラックの発生が抑制されることが分かった。実施の形態5ではその結果に着目し、今度はボンディングパッドの下方に通す配線自体を複数個に分割することで、半導体装置の更なる強度向上を図る。
Claims (22)
- 最上層配線層を用いて形成された第1メタルと、
前記第1メタルの下に配置され当該第1メタルと接続する複数のライン状の第2メタルとを有するボンディングパッドを複数個備える半導体装置であって、
前記複数のボンディングパッドは、
前記ライン状の第2メタルの長手方向に並べて配設されている
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の第2メタルの底部における幅Wおよび間隔Dが、
W≦D≦2×Wの関係を満たす
ことを特徴とする半導体装置。 - 請求項1または請求項2記載の半導体装置であって、
前記複数の第2メタルは、
前記第1メタルの下の絶縁膜に埋め込まれており、当該絶縁膜内でその上部が互いに接続している
ことを特徴とする半導体装置。 - 請求項1から請求項3のいずれかに記載の半導体装置であって、
前記最上層配線層の1層下の第1下層配線層をさらに有し、
前記ボンディングパッドは、
前記第2メタルの下に配置され当該第2メタルと接続し、前記第1下層配線層を用いて形成された第3メタルをさらに備える
ことを特徴とする半導体装置。 - 請求項1から請求項3のいずれかに記載の半導体装置であって、
前記最上層配線層の1層下の第1下層配線層をさらに有し、
前記ボンディングパッドは、
前記第2メタルの下に配置され、前記第1下層配線層表面のバリアメタルを用いて形成されたエッチングストッパをさらに備える
ことを特徴とする半導体装置。 - 請求項1から請求項5のいずれかに記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層と、
前記ボンディングパッドの下方の領域における前記第2下層配線層による配線上に配置され、当該配線に接続する複数の所定形状の第4メタルとをさらに備える
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記ボンディングパッドの下方の領域において、前記第2下層配線層による前記配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - 請求項1から請求項5のいずれかに記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層をさらに備え、
前記ボンディングパッドの下方の領域において、前記第2下層配線層による配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - 最上層配線層を用いて形成された第1メタルと、
前記第1メタルの下に配置され当該第1メタルと接続する複数のライン状の第2メタルとを有するボンディングパッドを備える半導体装置であって、
前記複数の第2メタルは、
前記第1メタルの下の絶縁膜に埋め込まれており、当該絶縁膜内でその上部が互いに接続している
ことを特徴とする半導体装置。 - 請求項9記載の半導体装置であって、
前記複数の第2メタルの底部における幅Wおよび間隔Dが、
W≦D≦2×Wの関係を満たす
ことを特徴とする半導体装置。 - 請求項9または請求項10記載の半導体装置であって、
前記最上層配線層の1層下の第1下層配線層をさらに有し、
前記ボンディングパッドは、
前記第2メタルの下に配置され当該第2メタルと接続し、前記第1下層配線層を用いて形成された第3メタルをさらに備える
ことを特徴とする半導体装置。 - 請求項9または請求項10記載の半導体装置であって、
前記最上層配線層の1層下の第1下層配線層をさらに有し、
前記ボンディングパッドは、
前記第2メタルの下に配置され、前記第1下層配線層表面のバリアメタルを用いて形成されたエッチングストッパをさらに備える
ことを特徴とする半導体装置。 - 請求項9から請求項12のいずれかに記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層と、
前記ボンディングパッドの下方の領域における前記第2下層配線層による配線上に配置され、当該配線に接続する複数の所定形状の第4メタルとをさらに備える
ことを特徴とする半導体装置。 - 請求項13記載の半導体装置であって、
前記ボンディングパッドの下方の領域における前記第2下層配線層による前記配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - 請求項9から請求項12のいずれかに記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層をさらに備え、
前記ボンディングパッドの下方の領域において、前記第2下層配線層による配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - 最上層配線層を用いて形成された第1メタルと、
前記第1メタルの下に配置され当該第1メタルと接続する複数のライン状の第2メタルとを有するボンディングパッドを備える半導体装置であって、
当該半導体装置は、前記最上層配線層の1層下の第1下層配線層を有し、
前記ボンディングパッドは、
前記第2メタルの下に配置され、前記第1下層配線層表面のバリアメタルを用いて形成されたエッチングストッパを備える
ことを特徴とする半導体装置。 - 請求項16記載の半導体装置であって、
前記複数の第2メタルの底部における幅Wおよび間隔Dが、
W≦D≦2×Wの関係を満たす
ことを特徴とする半導体装置。 - 請求項16または請求項17記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層と、
前記ボンディングパッドの下方の領域における前記第2下層配線層による配線上に配置され、当該配線に接続する複数の所定形状の第4メタルとをさらに備える
ことを特徴とする半導体装置。 - 請求項18記載の半導体装置であって、
前記ボンディングパッドの下方の領域において、前記第2下層配線層による前記配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - 請求項16または請求項17記載の半導体装置であって、
前記ボンディングパッドよりも下層の第2下層配線層をさらに備え、
前記ボンディングパッドの下方の領域において、前記第2下層配線層による配線が、複数のライン状に分割されている
ことを特徴とする半導体装置。 - ボンディングパッドと、
前記ボンディングパッドの下方を通る配線とを備える半導体装置であって、
前記ボンディングパッドの下方の領域における前記配線上に、複数の所定形状の第4メタルを備える
ことを特徴とする半導体装置。 - 請求項21記載の半導体装置であって、
前記ボンディングパッドの下方の領域において、前記配線が複数のライン状に分割されている
ことを特徴とする半導体装置。
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US7956473B2 (en) | 2007-07-23 | 2011-06-07 | Renesas Electronics Corporation | Semiconductor device |
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JP2017120912A (ja) * | 2015-12-29 | 2017-07-06 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | Bsi接合能力改善のためのパッド領域下のサポート構造 |
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JPWO2017145256A1 (ja) * | 2016-02-23 | 2018-10-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10777507B2 (en) | 2016-02-23 | 2020-09-15 | Renesas Electronics Corporation | Semiconductor device including a pad and a wiring line arranged for bringing a probe into contact with the pad and method of manufacturing the same |
US10818601B1 (en) | 2016-02-23 | 2020-10-27 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US8178981B2 (en) | 2012-05-15 |
CN1947231A (zh) | 2007-04-11 |
TWI397135B (zh) | 2013-05-21 |
CN1947231B (zh) | 2010-06-23 |
US20070182001A1 (en) | 2007-08-09 |
CN101819956B (zh) | 2012-07-04 |
TW200534415A (en) | 2005-10-16 |
CN101459172B (zh) | 2013-06-12 |
CN101459172A (zh) | 2009-06-17 |
KR20060126572A (ko) | 2006-12-07 |
KR101127893B1 (ko) | 2012-03-21 |
US20100155960A1 (en) | 2010-06-24 |
JPWO2005083767A1 (ja) | 2007-11-29 |
CN101819956A (zh) | 2010-09-01 |
WO2005083767A1 (ja) | 2005-09-09 |
US7701063B2 (en) | 2010-04-20 |
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