JP4242336B2 - Semiconductor device - Google Patents

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JP4242336B2
JP4242336B2 JP2004356108A JP2004356108A JP4242336B2 JP 4242336 B2 JP4242336 B2 JP 4242336B2 JP 2004356108 A JP2004356108 A JP 2004356108A JP 2004356108 A JP2004356108 A JP 2004356108A JP 4242336 B2 JP4242336 B2 JP 4242336B2
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pad
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metal layer
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JP2005252230A (ja
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忠昭 三村
賢治 植田
篤人 水谷
毅 濱谷
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パナソニック株式会社
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Description

本発明は、半導体装置の外部接続用電極に関するものであり、特にパッド部の構造と配置に関するものである。   The present invention relates to an external connection electrode of a semiconductor device, and more particularly to the structure and arrangement of a pad portion.

図11は従来の半導体装置の外部接続用電極であるパッドとその周辺部の構成を示し、図11(a)、(b)はそれぞれ平面図、断面図である。
図11において、22は電極パッド、31は電極パッド22を除いた半導体基板上に形成された第1の保護膜(例えば、PドープされたP−SiN膜)、32は第1の保護膜31上にさらに形成された第2の保護膜(例えば、ポリイミド膜)である。電極パッド22は、最上層に形成された第1のパッドメタル67と、一つ下の配線層に形成された第2層のパッドメタル65と、第1のパッドメタル67と第2のパッドメタル65をそれらの間の層間絶縁膜71に形成されたビア66を介して電気的に接続する積層ビア構造をとっている。ビア66はW(タングステン)等の金属で形成される。
FIG. 11 shows a configuration of a pad, which is an external connection electrode of a conventional semiconductor device, and its peripheral portion, and FIGS. 11A and 11B are a plan view and a sectional view, respectively.
In FIG. 11, 22 is an electrode pad, 31 is a first protective film (for example, P-doped P-SiN film) formed on the semiconductor substrate excluding the electrode pad 22, and 32 is the first protective film 31. It is the 2nd protective film (for example, polyimide film) further formed on it. The electrode pad 22 includes a first pad metal 67 formed in the uppermost layer, a second layer pad metal 65 formed in the next lower wiring layer, a first pad metal 67 and a second pad metal. A laminated via structure in which 65 is electrically connected through a via 66 formed in the interlayer insulating film 71 between them is adopted. The via 66 is formed of a metal such as W (tungsten).

電極パッド22の直下以外では、半導体基板(図示せず)上に形成された回路素子と接続された配線10、その上層に形成された電源層メタル91、さらにその上層に形成されたダミーの配線パターン14と、各層の間の層間絶縁膜71,72,73が形成されている。ダミーの配線パターン14の代わりに、電源層メタル91を繰り返して形成する場合もある。   Except directly under the electrode pad 22, the wiring 10 connected to the circuit element formed on the semiconductor substrate (not shown), the power supply layer metal 91 formed on the upper layer, and the dummy wiring formed on the upper layer Interlayer insulating films 71, 72, 73 between the pattern 14 and each layer are formed. In some cases, the power supply layer metal 91 is repeatedly formed instead of the dummy wiring pattern 14.

電極パッド22の直下には、層間絶縁膜72,73があり、第1のパッドメタル67と第2のパッドメタル65は、層間絶縁膜71,72,73に形成されたビアを介して、配線10と接続されている。   Immediately below the electrode pad 22 are interlayer insulating films 72 and 73, and the first pad metal 67 and the second pad metal 65 are interconnected via vias formed in the interlayer insulating films 71, 72 and 73. 10 is connected.

チップサイズの縮小を目的として、外部接続用のパッドを入出力回路セルの素子形成領域上に配置した構造も提案されている。例えば、ロジック回路やドライバ回路の上に層間絶縁膜を設け、その上に入力パッドあるいは出力パッドを形成した半導体集積回路が提案されている(例えば、特許文献1参照)。
特開平06−244235号公報
For the purpose of reducing the chip size, a structure in which pads for external connection are arranged on the element formation region of the input / output circuit cell has been proposed. For example, a semiconductor integrated circuit in which an interlayer insulating film is provided on a logic circuit or a driver circuit and an input pad or an output pad is formed thereon has been proposed (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 06-244235

しかしながら、素子上に上記したような構造の電極パッドが形成された場合、パッドへのワイヤボンディング時の衝撃荷重の影響によって、パッド直下の配線や層間絶縁膜にダメージが生じる恐れがある。あるいは、パッド直下に形成された拡散素子、例えば、トランジスタの動作特性の変化(劣化)という影響を与える可能性がある。   However, when the electrode pad having the structure as described above is formed on the element, there is a possibility that damage to the wiring and the interlayer insulating film immediately below the pad may occur due to the impact load at the time of wire bonding to the pad. Alternatively, there is a possibility of an influence of change (deterioration) in operating characteristics of a diffusion element formed immediately below the pad, for example, a transistor.

特に、金ボールボンドによるワイヤボンディングでは、半導体チップを230−240℃に加熱して所定の荷重を加えながら超音波を印加することにより、アルミパッドの表面の酸化膜を破ってアルミニウムの真性面と金の界面で金−アルミニウム合金を形成させるため、印加する超音波エネルギーによってパッド下の層間絶縁膜とメタルとの界面に生じる応力により、層間絶縁膜(SiO2等で形成されている)にクラックが発生する。 In particular, in wire bonding by gold ball bonding, the semiconductor chip is heated to 230-240 ° C. and an ultrasonic wave is applied while applying a predetermined load, thereby breaking the oxide film on the surface of the aluminum pad, and the intrinsic surface of aluminum. Since the gold-aluminum alloy is formed at the gold interface, the stress generated at the interface between the interlayer insulating film under the pad and the metal by the applied ultrasonic energy causes cracks in the interlayer insulating film (formed of SiO 2 or the like). Will occur.

図12は、電極パッド上にボールボンドを行なったときに層間絶縁膜に生じる応力の分布図である。ここでは、4層配線構造の電極パッド上に金属バンプを金ボールボンディング工法で形成したときの応力分布をCAE解析(有限要素法)により計算した結果を示している。   FIG. 12 is a distribution diagram of stress generated in the interlayer insulating film when ball bonding is performed on the electrode pad. Here, the result of calculating the stress distribution by the CAE analysis (finite element method) when the metal bump is formed on the electrode pad of the four-layer wiring structure by the gold ball bonding method is shown.

電極パッドは、最上層のパッドメタル61(以下、第1のメタル61という)の下に、第1の層間絶縁膜71、第2層のパッドメタル62(以下、第2のメタル62という)、第2の層間絶縁膜72、第3のメタル91、第3の層間絶縁膜73、最下層メタル10が形成されている。第1のメタル61上に金属バンプ43が形成される時に、超音波が図中の矢印に示すように半導体基板に沿う水平方向に印加される。このことにより、下層のメタル62,91のエッジ部に応力が集中する(図中に白っぽく表示されている)。   The electrode pad includes a first interlayer insulating film 71, a second layer pad metal 62 (hereinafter referred to as a second metal 62) below the uppermost pad metal 61 (hereinafter referred to as a first metal 61), A second interlayer insulating film 72, a third metal 91, a third interlayer insulating film 73, and a lowermost layer metal 10 are formed. When the metal bumps 43 are formed on the first metal 61, ultrasonic waves are applied in the horizontal direction along the semiconductor substrate as indicated by arrows in the figure. As a result, stress concentrates on the edge portions of the lower metals 62 and 91 (shown as whitish in the figure).

この応力が層間絶縁膜71,72,73の降伏応力を超えると、脆性破壊を生じ、クラックが発生する。その際には、印加される超音波エネルギーの大きさに応じて内部応力も大きくなることがCAE解析により判明している。また、ボンディングされる電極パッドの直下に形成されているトランジスタの特性(Vt、Gm、ホットキャリア寿命等)が劣化することが判明している。   When this stress exceeds the yield stress of the interlayer insulating films 71, 72, 73, brittle fracture occurs and cracks occur. At that time, it has been found by CAE analysis that the internal stress increases in accordance with the magnitude of the applied ultrasonic energy. It has also been found that the characteristics (Vt, Gm, hot carrier lifetime, etc.) of the transistor formed immediately below the electrode pad to be bonded deteriorate.

一方、プローブ検査(P検)の一般的方法であるカンチレバー方式のP検では、タングステンなどのプローブ針で電極パッドを押圧するため、ウエハのP検時もパッドメタルの直下に大きな集中荷重がかかり、層間絶縁膜にクラックが発生する。また電極パッドにプローブ針の針跡(圧跡)が残る。組み立て時のワイヤボンドは通常、この圧跡付の電極パッド上へ行うのであるが、圧跡部はパッド表面のアルミニウムがプローブ針によって削られているため、金ボールとの合金が形成されない領域となる。近年では、ワイヤボンドのボンディングピッチの縮小が要求され、パッドサイズ、ボール径が小さくなってきているので、相対的に圧跡の面積が増大してきており、所定の面積の合金形成、ボンディングができなくなるという問題が生じている。   On the other hand, in the cantilever-type P test, which is a general method of probe test (P test), the electrode pad is pressed with a probe needle such as tungsten, so a large concentrated load is applied directly under the pad metal even during the P test of the wafer. Cracks are generated in the interlayer insulating film. In addition, a probe mark (pressure mark) of the probe needle remains on the electrode pad. Wire bonding at the time of assembly is usually performed on the electrode pad with the impression, but the impression part is a region where an alloy with the gold ball is not formed because the aluminum on the pad surface is scraped by the probe needle. . In recent years, wire bond bonding pitches have been required to be reduced, and the pad size and ball diameter have become smaller, so the area of the impression has been relatively increased, making it possible to form and bond an alloy with a predetermined area. There is a problem of disappearing.

本発明は上記問題を解決するもので、ボンディングやプローブの際に電極パッドの表面や下層の配線および層間絶縁膜に与えるダメージを低減することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to reduce damage given to the surface of an electrode pad, a lower layer wiring, and an interlayer insulating film during bonding or probing.

上記問題を解決するために、本発明の半導体装置は、外部接続用電極であるパッド部が、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとからなり、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように、少なくとも一端部が互いに1.5μm以上2μm以下の範囲でずれて配置されたことを特徴とする。 In order to solve the above problem, in a semiconductor device of the present invention, a pad portion which is an external connection electrode includes a first pad metal layer formed as an uppermost layer and an interlayer below the first pad metal layer. A second pad metal layer formed with an insulating film interposed therebetween, and a via that penetrates the interlayer insulating film and electrically connects the first pad metal layer and the second pad metal layer. At least one end of each pad metal layer and the other end of the second pad metal layer are shifted from each other within a range of 1.5 μm to 2 μm so that the end of the second pad metal layer does not coincide with the thickness direction of each layer. It is characterized by that.

また本発明の半導体装置は、外部接続用電極であるパッド部が、ボンディング用の第1のパッド領域とプローブ検査用の第2のパッド領域とからなり、前記第1のパッド領域は、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとから構成され、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように、少なくとも一端部が互いに1.5μm以上2μm以下の範囲でずれて配置され、前記第2のパッド領域は、前記第1のパッドメタル層のみで構成されたことを特徴とする。 In the semiconductor device of the present invention, the pad portion that is an electrode for external connection includes a first pad region for bonding and a second pad region for probe inspection, and the first pad region is the uppermost layer. A first pad metal layer formed on the first pad metal layer, a second pad metal layer formed below the first pad metal layer with an interlayer insulating film interposed therebetween, and a first pad metal layer penetrating the interlayer insulating film. A pad metal layer and a via that electrically connects the second pad metal layer are formed, and an end portion of the first pad metal layer and an end portion of the second pad metal layer extend along the thickness direction of each layer. At least one end portion thereof is deviated from the range of 1.5 μm or more and 2 μm or less , and the second pad region is composed of only the first pad metal layer. .

2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも外側にずれていてよい。また第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも内側にずれていてよい。 The end portion of the second pad metal layer may be shifted outward from the end portion of the first pad metal layer. Further, the end portion of the second pad metal layer may be shifted inward from the end portion of the first pad metal layer.

第2のパッド領域の第1のパッドメタル層の下に層間絶縁膜を挟んで、第2のパッドメタル層と同一層をなすように複数個のダミーメタルが配設されるのが好ましい。
パッド部の下の層に回路素子または配線が配設されていてよい。
It is preferable that a plurality of dummy metals are disposed so as to form the same layer as the second pad metal layer with an interlayer insulating film interposed between the first pad metal layer in the second pad region.
A circuit element or wiring may be disposed in a layer below the pad portion.

第1のパッド領域と第2のパッド領域の少なくとも一方の下の層に回路素子または配線が配設されていてよい。   A circuit element or wiring may be disposed in a layer below at least one of the first pad region and the second pad region.

本発明の半導体装置によれば、ボンディング時やプロービング時にパッドメタル層のエッジに発生する応力を小さくし、パッドメタル層の下の層間絶縁膜にかかる応力を緩和することができるので、パッドメタル層の下の層間絶縁膜のダメージを低減できる。   According to the semiconductor device of the present invention, the stress generated at the edge of the pad metal layer during bonding or probing can be reduced, and the stress applied to the interlayer insulating film under the pad metal layer can be reduced. Damage to the underlying interlayer insulating film can be reduced.

また、ボンディング用の第1のパッド領域から区分してプローブ検査用の第2のパッド領域を設けることにより、第1のパッド領域において、プロービングに起因する層間絶縁膜のダメージと圧跡とを回避することができる。   Further, by providing a second pad area for probe inspection separately from the first pad area for bonding, damage and pressure marks on the interlayer insulating film due to probing can be avoided in the first pad area. can do.

パッド部を回路素子または配線の領域上に配置した場合も、ボンディング荷重によって配線部や拡散部にダメージを発生させることなく、パッド部に対する接続を容易に行うことができる。したがって、パッド部を回路素子または配線の領域を避けて配置する場合に比べて、少なくともパッド部の総面積分だけチップサイズを縮小することができ、チップコストも低減可能となる。   Even when the pad portion is disposed on the circuit element or the wiring region, connection to the pad portion can be easily performed without causing damage to the wiring portion or the diffusion portion due to the bonding load. Therefore, the chip size can be reduced by at least the total area of the pad portion and the chip cost can be reduced as compared with the case where the pad portion is arranged avoiding the circuit element or wiring region.

以下、本発明の実施の形態について、図面を参照しながら説明する。
本発明でいう半導体装置は、ウエハ状態の半導体集積回路装置とその個別の半導体装置の双方を含むが、ここでは半導体集積回路装置について説明する。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The semiconductor device referred to in the present invention includes both a semiconductor integrated circuit device in a wafer state and individual semiconductor devices. Here, the semiconductor integrated circuit device will be described.

図1は本発明の第1の実施形態の半導体装置の要部構成を示し、図1(a)、(b)は同半導体装置の外部接続用電極であるパッドとその周辺部の平面図、断面図である。ここではパッドは、入出力回路の素子領域または配線上に形成されており、4層配線構造である場合を示している。   FIG. 1 shows a configuration of a main part of a semiconductor device according to a first embodiment of the present invention, and FIGS. 1A and 1B are plan views of a pad which is an external connection electrode of the semiconductor device and its peripheral part, It is sectional drawing. Here, the pad is formed on the element region or wiring of the input / output circuit, and shows a case of a four-layer wiring structure.

図1において、11はプロービングによるウエハ検査用のプローブパッド、21はワイヤボンド等の組み立てに用いるボンディングパッド、31はプローブパッド11およびボンディングパッド21の上面を除いた半導体基板上に形成されたP−SiN膜などの第1の保護膜、32は第1の保護膜31上に形成されたポリイミド膜などの第2の保護膜である。   In FIG. 1, 11 is a probe pad for wafer inspection by probing, 21 is a bonding pad used for assembly such as wire bonding, and 31 is a P− formed on a semiconductor substrate excluding the upper surfaces of the probe pad 11 and bonding pad 21. A first protective film 32 such as an SiN film, and a second protective film 32 such as a polyimide film formed on the first protective film 31.

ボンディングパッド21は、最上層のパッドメタル61(以下第1のメタル61という)と、そのひとつ下の配線層に形成された第2層のパッドメタル62(以下第2のメタル62という)と、第1のメタル61と第2のメタル62との間の層間絶縁膜71を貫通してこれらメタル61,62間を接続するビア63とからなる積層ビア構造を有している。積層ビア構造は、ワイヤボンドなどのボンディング工程で生じる衝撃エネルギーを吸収し、パッドの直下の配線部や拡散素子にかかる応力を緩和し、ダメージの発生を抑えるのに効果がある。   The bonding pad 21 includes a top layer pad metal 61 (hereinafter referred to as a first metal 61), a second layer pad metal 62 (hereinafter referred to as a second metal 62) formed in a wiring layer immediately below the bonding metal, and It has a laminated via structure including a via 63 that passes through the interlayer insulating film 71 between the first metal 61 and the second metal 62 and connects between the metals 61 and 62. The laminated via structure is effective in absorbing impact energy generated in a bonding process such as wire bonding, relaxing stress applied to the wiring portion and the diffusion element directly under the pad, and suppressing the occurrence of damage.

ボンディングパッド21の第2のメタル62の下には、例えば電源供給のための電源層である第3のメタル91、さらに下層には、入出力回路内への信号供給のための最下層メタル10が形成されており、第1および第2のメタル61,62と、最下層メタル10とは、引出し部メタル81のスタック構造により電気的に接続されている。第2のメタル62と第3のメタル91との間、および第3のメタル91と最下層メタル10との間にはそれぞれ層間絶縁膜72,73が形成されている。   Below the second metal 62 of the bonding pad 21, for example, a third metal 91 which is a power supply layer for supplying power, and further below the lowermost metal 10 for supplying signals to the input / output circuit. The first and second metals 61 and 62 and the lowermost layer metal 10 are electrically connected by a stack structure of the lead portion metal 81. Interlayer insulating films 72 and 73 are formed between the second metal 62 and the third metal 91 and between the third metal 91 and the lowermost metal 10, respectively.

ボンディングパッド21とプローブパッド11は、第1のメタル61に一体に形成されていて、第1のメタル61上の第1の保護膜31に分離して形成された2個のコンタクト窓からそれぞれ露出している。ただし実際には、プローブパッド11とボンディングパッド21を単に領域として使い分けてもよく、必ずしも第1の保護膜31によって分離する必要はない。   The bonding pad 21 and the probe pad 11 are formed integrally with the first metal 61 and are exposed from two contact windows formed separately on the first protective film 31 on the first metal 61. is doing. However, in practice, the probe pad 11 and the bonding pad 21 may be used properly as regions, and need not be separated by the first protective film 31.

プローブパッド11は、ボンディングパッド21のような2層のメタル61,62による積層ビア構造ではなく、第1のメタル61だけで構成されており、その下には層間絶縁膜71,72を介して第3のメタル91がある。第3のメタル91の下には、ボンディングパッド21と同様に、層間絶縁膜73と最下層メタル10がある。   The probe pad 11 is composed of only the first metal 61 instead of the laminated via structure of the two layers of metal 61 and 62 as in the bonding pad 21, and the interlayer insulating films 71 and 72 are interposed thereunder. There is a third metal 91. Under the third metal 91, similarly to the bonding pad 21, there is an interlayer insulating film 73 and a lowermost layer metal 10.

第2のメタル62はボンディングパッド21よりも縦横に大きく、ボンディングパッド21,プローブパッド11のそれぞれの下層にある2つの第3のメタル91は、第2のメタル62のエッジ部よりも中央寄りで隣接している。   The second metal 62 is larger than the bonding pad 21 in the vertical and horizontal directions, and the two third metals 91 in the lower layers of the bonding pad 21 and the probe pad 11 are closer to the center than the edge portion of the second metal 62. Adjacent.

図2は、プローブパッド11およびボンディングパッド21の各層の平面図であり、図2(a)は、第1のメタル61の層を示し、図2(b)、(c)は、第2のメタル62の層を2例を挙げて示している。   FIG. 2 is a plan view of each layer of the probe pad 11 and the bonding pad 21. FIG. 2A shows the layer of the first metal 61, and FIGS. 2B and 2C show the second layer. Two layers of the metal 62 are shown.

図2(a)には、第1のメタル61に、第1の保護膜31により分離されるプローブパッド11の領域とボンディングパッド21の領域を示している。引出し部メタル81はパッドメタル61と同一幅である。   FIG. 2A shows a region of the probe pad 11 and a region of the bonding pad 21 separated by the first protective film 31 on the first metal 61. The lead metal 81 has the same width as the pad metal 61.

図2(b)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも大きくしている。
図2(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
In FIG. 2B, the width of the second metal 62 is made larger than the width of the first metal 61 as can be understood from the width of the lead portion metal 81.
In FIG. 2C, the width of the second metal 62 is made smaller than the width of the first metal 61 as understood from the width of the lead portion metal 81.

図2(b)、(c)のいずれも構造も、第1のメタル61のエッジ61aと第2のメタル62のエッジ62aを、各層の厚み方向に沿って一致しないように、すなわち、平面視したときに垂直方向に一致しないように、また僅かに重なることがないように、互いにずれた配置としたものである。ここでは、第1のメタル61に比べて第2のメタル62の一対の端部が飛び出すかあるいは窪んでいるが、これに限らず、互いの端部が層間絶縁膜の上下で一致しないようにずれていれば、一方が飛び出して他方が窪んでいてもよい。なお第2のメタル62のもう一対のエッジ62aも、図1からも明らかなように、引出し部メタル81に接するか、第1のメタル61のエッジ61aからずれている。51はプローブパッド11の下の領域の層間絶縁膜を示しており、上述した層間絶縁膜71の一部である。この領域にはメタルを形成していない。   2 (b) and 2 (c), the edge 61a of the first metal 61 and the edge 62a of the second metal 62 are not aligned along the thickness direction of each layer, that is, in plan view. In this case, the positions are shifted from each other so that they do not coincide with each other in the vertical direction and do not overlap slightly. Here, the pair of end portions of the second metal 62 protrudes or is recessed as compared with the first metal 61, but this is not limiting, and the end portions of the second metal 62 do not coincide with each other above and below the interlayer insulating film. As long as it is shifted, one side may jump out and the other side may be depressed. Note that the other pair of edges 62 a of the second metal 62 is also in contact with the lead portion metal 81 or shifted from the edge 61 a of the first metal 61, as is apparent from FIG. 1. Reference numeral 51 denotes an interlayer insulating film in a region below the probe pad 11, which is a part of the above-described interlayer insulating film 71. No metal is formed in this region.

図3は、プロービング、ボールボンドを行なう際のパッド周辺部の状態を示し、図3(a)、(b)はそれぞれ平面図、断面図である。プローブ針42のすべりにより、プローブパッド11上に、プローブ痕41が生じている。ワイヤボンドで行われるように、ボンディングパッド21上に金属バンプ43が形成されている。   FIG. 3 shows the state of the pad periphery when probing and ball bonding are performed, and FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively. A probe mark 41 is generated on the probe pad 11 due to the sliding of the probe needle 42. Metal bumps 43 are formed on the bonding pads 21 as performed by wire bonding.

このようにプロービング、ボールボンドする際の荷重がパッドにかかっても、上述したように第1のメタル61のエッジ61aと第2のメタル62のエッジ62aとが互いにずれているため、それぞれのエッジ部61a,62aで生じる応力集中を緩和することができ、層間絶縁膜71,72のクラック等の物理的ダメージの発生を抑制することができる。プローブパッド11の下の領域でも、メタルを形成しないことで層間絶縁膜71,72の総膜厚を厚くできるため、そのクラックの発生を抑制することができる。これらの結果、第1のメタル61と第3のメタル91との間の電気的ショート/リークを防ぐことが可能である。このことは、第2のメタル62よりも下層にある第3のメタル91、最下層メタル10、層間絶縁膜72,73についても言える。   As described above, since the edge 61a of the first metal 61 and the edge 62a of the second metal 62 are displaced from each other as described above, even when the load during probing and ball bonding is applied to the pad, the respective edges are different. Stress concentration generated in the portions 61a and 62a can be alleviated, and the occurrence of physical damage such as cracks in the interlayer insulating films 71 and 72 can be suppressed. Even in the region below the probe pad 11, since the total film thickness of the interlayer insulating films 71 and 72 can be increased by not forming metal, the occurrence of cracks can be suppressed. As a result, an electrical short / leak between the first metal 61 and the third metal 91 can be prevented. This also applies to the third metal 91, the lowermost layer metal 10, and the interlayer insulating films 72 and 73 that are lower than the second metal 62.

ワイヤボンディング時のワイヤのイニシャルボール径を45μmとし、ワイヤボンディング時の超音波パワーを一定とした場合、第1のメタル61と第2のメタル62の端部が一致している従来構造では、クラック発生率が3.2%であったのに対し、図2(b)、(c)に示すように第1のメタル61と第2のメタル62の両端部をずらした本発明の構造ではクラック発生率は低下し、1.5〜2μmずらした時にはクラック発生率は0%となった。これ以上大きくしても効果は変わらず、大きくしすぎるとパッド間の距離が大きくなり、パッド配置密度が低下する。   In the conventional structure in which the end portions of the first metal 61 and the second metal 62 match when the initial ball diameter of the wire during wire bonding is 45 μm and the ultrasonic power during wire bonding is constant, While the occurrence rate was 3.2%, the structure of the present invention in which both ends of the first metal 61 and the second metal 62 are shifted as shown in FIGS. The generation rate decreased, and the crack generation rate became 0% when shifted by 1.5 to 2 μm. Increasing it further does not change the effect. If it is too large, the distance between the pads increases, and the pad arrangement density decreases.

この第1の実施形態では、プローブパッド11とボンディングパッド21の双方を備えた外部接続用電極について説明したが、少なくともボンディングパッド21を備えた外部接続用電極に上記構造を適用すれば、荷重が印加された時の層間絶縁膜のクラックの発生を抑制できる。   In the first embodiment, the external connection electrode including both the probe pad 11 and the bonding pad 21 has been described. However, if the above structure is applied to at least the external connection electrode including the bonding pad 21, a load is applied. Generation of cracks in the interlayer insulating film when applied can be suppressed.

図4は本発明の第2の実施形態の半導体装置の要部構成を示し、図4(a)、(b)はそれぞれ同半導体装置の外部接続用電極であるパッドとその周辺部の平面図、断面図である。   FIG. 4 shows a configuration of a main part of a semiconductor device according to a second embodiment of the present invention. FIGS. 4A and 4B are plan views of a pad which is an external connection electrode of the semiconductor device and its peripheral part, respectively. FIG.

この第2の実施形態の半導体装置が第1の実施形態の半導体装置と異なるのは、プローブパッド11の下に、ボンディングパッド21の第2のメタル62と同一層をなすように、数μm角の微小なバッファメタル64を格子状に、つまり縦横に複数列に配列していることである。これらの微小なバッファメタル64が存在することにより、プローブ時の荷重によってプローブパッド11の下の層間絶縁膜71内に生じる応力集中を緩和することができ、層間絶縁膜71,72でのクラックの発生を防ぐことが可能となる。したがって、第1のメタル61と第3のメタル91との間の電気的ショート/リークをより確実に防ぐことができる。   The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that it is several μm square so as to form the same layer as the second metal 62 of the bonding pad 21 under the probe pad 11. The small buffer metals 64 are arranged in a lattice pattern, that is, in a plurality of rows vertically and horizontally. The presence of these minute buffer metals 64 can alleviate stress concentration generated in the interlayer insulating film 71 under the probe pad 11 due to the load during the probe, and cracks in the interlayer insulating films 71 and 72 can be reduced. Occurrence can be prevented. Therefore, electrical short / leakage between the first metal 61 and the third metal 91 can be prevented more reliably.

図5は、プローブパッド11およびボンディングパッド21の各層の平面図であり、図5(a)は、第1のメタル61の層を示し、図5(b)、(c)は、第2のメタル62およびメタル64の層を、2例を挙げて示している。   FIG. 5 is a plan view of each layer of the probe pad 11 and the bonding pad 21. FIG. 5A shows the layer of the first metal 61, and FIGS. 5B and 5C show the second layer. Two layers of metal 62 and metal 64 are shown.

さきに説明した図2と同様に、図5(a)においては、第1のメタル61に、第1の保護膜31により分離されるプローブパッド11の領域とボンディングパッド21の領域を示している。引出し部メタル81はパッドメタル61と同一幅である。   Similar to FIG. 2 described above, FIG. 5A shows the region of the probe pad 11 and the region of the bonding pad 21 separated by the first protective film 31 in the first metal 61. . The lead metal 81 has the same width as the pad metal 61.

図5(b)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅、メタル64の配列幅を、第1のメタル61の幅よりも大きくしている。
図5(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
In FIG. 5B, the width of the second metal 62 and the arrangement width of the metal 64 are made larger than the width of the first metal 61 as can be understood from the width of the lead metal 81.
In FIG. 5C, the width of the second metal 62 is made smaller than the width of the first metal 61 as understood from the width of the lead portion metal 81.

図5(b)(c)のいずれの場合も、メタルエッジ61a,62aの重なりを無くしており、ボンディング時の応力の緩和が可能になっている。
図6は本発明の第3の実施形態の半導体装置の要部構成を示し、図6(a)、(b)はそれぞれ同半導体装置の外部接続用電極であるパッドとその周辺部の平面図、断面図である。
5B and 5C, the metal edges 61a and 62a are not overlapped, and the stress during bonding can be relaxed.
FIG. 6 shows a configuration of a main part of a semiconductor device according to a third embodiment of the present invention, and FIGS. 6A and 6B are plan views of a pad which is an external connection electrode of the semiconductor device and its peripheral part, respectively. FIG.

この第3の実施形態の半導体装置が第1の実施形態の半導体装置と異なるのは、第1の実施形態におけるボンディングパッド21の外側、すなわち、チップ外周のスクライブ領域側に外部パッドを配置していることである。ここでは、これら2つのパッドを内部パッド68、外部パッド69と称する。   The semiconductor device of the third embodiment is different from the semiconductor device of the first embodiment in that an external pad is arranged outside the bonding pad 21 in the first embodiment, that is, on the scribe area side of the outer periphery of the chip. It is that you are. Here, these two pads are referred to as an internal pad 68 and an external pad 69.

内部パッド68、外部パッド69とも、ボンディングパッド21と同様に、第1のメタル61と第2のメタル62,65、およびこれらのメタル間を接続するビア63,66による積層ビアパッド構造としている。92は、例えば電源供給のための第2の電源層として形成されたメタルである。電源層であれば、3層目の第3のメタル91と合わせて形成することで、電源配線内の電位のさらなる安定化を図ることができる。   Similar to the bonding pad 21, the internal pad 68 and the external pad 69 have a stacked via pad structure including the first metal 61 and the second metal 62 and 65 and vias 63 and 66 connecting these metals. 92 is a metal formed as a second power supply layer for supplying power, for example. If the power supply layer is formed together with the third metal 91 in the third layer, the potential in the power supply wiring can be further stabilized.

図7は、内部パッド68および外部パッド69の各層の平面図であり、図7(a)は、第1のメタル61の層を示し、図7(b)、(c)は、第2のメタル62,メタル65の層を、2例を挙げて示している。   FIG. 7 is a plan view of each layer of the internal pad 68 and the external pad 69. FIG. 7A shows the layer of the first metal 61, and FIGS. 7B and 7C show the second layer. Two layers of the metal 62 and the metal 65 are shown.

さきに説明した図2と同様に、図7(a)においては、第1のメタル61に、第1の保護膜31により分離される内部パッド68の領域と外部パッド69の領域を示している。引出し部メタル81はパッドメタル61と同一幅である。   Similar to FIG. 2 described above, FIG. 7A shows the region of the internal pad 68 and the region of the external pad 69 separated by the first protective film 31 in the first metal 61. . The lead metal 81 has the same width as the pad metal 61.

図7(b)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を、第1のメタル61の幅よりも大きくしている。
図7(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
In FIG. 7B, the width of the second metal 62 is made larger than the width of the first metal 61 as can be understood from the width of the lead portion metal 81.
In FIG. 7C, the width of the second metal 62 is made smaller than the width of the first metal 61 as understood from the width of the lead portion metal 81.

図7(b)(c)のいずれの場合も、メタルエッジ61a,62aの重なりを無くしており、ボンディング時の応力の緩和が可能になっている。
図8は、図6に示した第3の実施形態の半導体装置について、プロービング、ボールボンドを行なった際のパッド周辺部の状態を示し、図8(a)、(b)はそれぞれ平面図、断面図である。外部パッド69に対してプローブ針42でプロービングを行なっており、プローブ針42のすべりにより、外部パッド69上に、プローブ痕41が生じている。金属バンプ43は内部パッド68上に形成している。
In both cases of FIGS. 7B and 7C, the metal edges 61a and 62a are not overlapped, and the stress during bonding can be relaxed.
FIG. 8 shows the state of the pad peripheral portion when probing and ball bonding are performed for the semiconductor device of the third embodiment shown in FIG. 6, and FIGS. 8A and 8B are plan views, respectively. It is sectional drawing. Probing is performed on the external pad 69 with the probe needle 42, and the probe mark 41 is generated on the external pad 69 due to the sliding of the probe needle 42. The metal bump 43 is formed on the internal pad 68.

なお、内部パッド68と外部パッド69とは必ずしも同一種の金属で単一の膜として形成しなくてもよく、別個金属からなる別個の膜であってもよい。
図9は、入出力回路の領域上にパッド部が複数配置された様子を示す平面図である。複数のパッド部のそれぞれにおいて、内側の内部パッド68上に金属バンプ43を設けており、外側の外部パッド69上にプローブ痕41が生じている。
The internal pad 68 and the external pad 69 do not necessarily have to be formed as a single film of the same type of metal, and may be separate films made of separate metals.
FIG. 9 is a plan view showing a state in which a plurality of pad portions are arranged on the input / output circuit region. In each of the plurality of pad portions, the metal bump 43 is provided on the inner pad 68 inside, and the probe mark 41 is generated on the outer pad 69 outside.

図10も、入出力回路の領域上にパッド部が複数配置された様子を示す平面図である。
金属バンプ43を交互に内側の内部パッド68上と外側の外部パッド69上とに設けており、残りの内部パッド68と外部パッド69上とにプローブ痕41が生じている。
FIG. 10 is also a plan view showing a state in which a plurality of pad portions are arranged on the input / output circuit region.
Metal bumps 43 are alternately provided on the inner pads 68 and the outer pads 69 on the inner side, and probe marks 41 are generated on the remaining inner pads 68 and the outer pads 69.

このようにプローブのためのパッドとボンディングのためのパッド(あるいはパッド領域)をそれぞれジグザグ状に配置することで、見かけ上のパッドピッチを拡大することができる。またセル内に複数のパッドを設けることでバンプ接続時のピッチを拡大することができる。   Thus, by arranging the pads for probes and pads (or pad regions) for bonding in a zigzag manner, the apparent pad pitch can be expanded. Moreover, the pitch at the time of bump connection can be expanded by providing a some pad in a cell.

このため、たとえば個別の半導体装置を金属バンプ43を用いてキャリア基板上にフリップチップ実装してCSP(Chip Size Package)や、BGA(Ball Grid Array)などの表面実装型パッケージとする場合に、キャリア基板の電極ピッチを拡大させることができ、基板設計上のルールが緩和され、基板コストの低減も図ることができるなど、非常に大きなメリットがある。   Therefore, for example, when an individual semiconductor device is flip-chip mounted on a carrier substrate using metal bumps 43 to form a surface mount package such as a CSP (Chip Size Package) or a BGA (Ball Grid Array), the carrier The substrate electrode pitch can be increased, the rules for designing the substrate can be relaxed, and the substrate cost can be reduced.

金属バンプ43としては、例えば、金ボールをベースとした2段突起状のスタッドバンプや、電解めっき法あるいは無電解めっき法による金、ニッケル、銅などの金属バンプを形成することができる。いずれの場合も、上述したように入出力回路の領域上に形成した複数のパッド(あるいはパッド領域)を交互に用いることにより、実質的な接続ピッチを拡大できるため、接続歩留まりの向上、生産性の向上が可能となる。   As the metal bumps 43, for example, stud bumps having a two-stage protrusion based on gold balls, or metal bumps such as gold, nickel, copper, etc. by electrolytic plating or electroless plating can be formed. In any case, the substantial connection pitch can be expanded by alternately using a plurality of pads (or pad regions) formed on the input / output circuit region as described above, thereby improving the connection yield and productivity. Can be improved.

本発明の半導体装置は、外部接続用電極の下に回路素子や配線があっても荷重の影響を及ぼしにくいので、外部接続用電極でプローブ検査や外部接続のためのボンディングが行われる半導体装置として有用である。   Since the semiconductor device of the present invention is less susceptible to the load even if there is a circuit element or wiring under the external connection electrode, as a semiconductor device in which probe inspection or bonding for external connection is performed with the external connection electrode Useful.

本発明の第1の実施形態の半導体装置のパッドとその周辺部の構成図1 is a configuration diagram of a pad and its peripheral portion of a semiconductor device according to a first embodiment of the present invention. 図1のパッドの各層の平面図Plan view of each layer of the pad of FIG. 図1のパッドのプロービングおよびボールボンド時の状態を示す構成図FIG. 1 is a block diagram showing a state of probing and ball bonding of the pad of FIG. 本発明の第2の実施形態の半導体装置のパッドとその周辺部の構成図The block diagram of the pad of the semiconductor device of the 2nd Embodiment of this invention, and its peripheral part 図4のパッドの各層の平面図4 is a plan view of each layer of the pad of FIG. 本発明の第3の実施形態の半導体装置のパッドとその周辺部の構成図The block diagram of the pad of the semiconductor device of the 3rd Embodiment of this invention, and its periphery part 図6のパッドの各層の平面図Plan view of each layer of pad of FIG. 図6のパッドのプロービングおよびボールボンド時の状態を示す構成図The block diagram which shows the state at the time of probing and ball bonding of the pad of FIG. 図6のパッドが複数配置された様子を示す平面図The top view which shows a mode that the pad of FIG. 6 is arranged in multiple numbers 図6のパッドが複数配置された様子を示す別の平面図Another top view which shows a mode that two or more pads of Drawing 6 are arranged 従来の半導体装置のパッドとその周辺部の構成図Configuration diagram of pads and peripheral parts of conventional semiconductor devices 図11の半導体装置の層間絶縁膜に生じる応力の分布図11 is a distribution diagram of stress generated in the interlayer insulating film of the semiconductor device of FIG.

符号の説明Explanation of symbols

10 最下層メタル
11 プローブパッド(第2のパッド領域)
21 ボンディングパッド(第1のパッド領域)
42 プローブ針
43 金属バンプ
61 最上層のパッドメタル(第1のパッドメタル層)
61a エッジ
62 第2層のパッドメタル(第2のパッドメタル層)
62a エッジ
63 ビア
64 バッファメタル(ダミーメタル)
71 層間絶縁膜
72 層間絶縁膜
73 層間絶縁膜
81 引出し部メタル
91 第3のメタル
10 Lowermost layer metal 11 Probe pad (second pad area)
21 Bonding pad (first pad area)
42 Probe needle 43 Metal bump 61 Uppermost layer pad metal (first pad metal layer)
61a Edge 62 Second layer pad metal (second pad metal layer)
62a Edge 63 Via 64 Buffer metal (dummy metal)
71 Interlayer insulating film 72 Interlayer insulating film 73 Interlayer insulating film 81 Lead metal 91 Third metal

Claims (7)

  1. 外部接続用電極であるパッド部が、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとからなり、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように、少なくとも一端部が互いに1.5μm以上2μm以下の範囲でずれて配置された半導体装置。 A pad portion which is an electrode for external connection, a first pad metal layer formed in the uppermost layer; a second pad metal layer formed by sandwiching an interlayer insulating film under the first pad metal layer; And a via that electrically connects the first pad metal layer and the second pad metal layer through the interlayer insulating film, and an end of the first pad metal layer and the second pad metal layer A semiconductor device in which at least one end portion is shifted from each other within a range of 1.5 μm or more and 2 μm or less so that the end portion of the substrate does not coincide with the thickness direction of each layer.
  2. 外部接続用電極であるパッド部が、ボンディング用の第1のパッド領域とプローブ検査用の第2のパッド領域とからなり、前記第1のパッド領域は、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとから構成され、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように、少なくとも一端部が互いに1.5μm以上2μm以下の範囲でずれて配置され、前記第2のパッド領域は、前記第1のパッドメタル層のみで構成された半導体装置。 The pad portion, which is an external connection electrode, includes a first pad region for bonding and a second pad region for probe inspection, and the first pad region is a first pad formed in the uppermost layer. A metal layer; a second pad metal layer formed by sandwiching an interlayer insulating film under the first pad metal layer; and the first pad metal layer and the second pad penetrating the interlayer insulating film At least one end so that the end of the first pad metal layer and the end of the second pad metal layer do not coincide with each other in the thickness direction of each layer. The semiconductor device is configured such that the portions are shifted from each other in a range of 1.5 μm or more and 2 μm or less , and the second pad region is configured by only the first pad metal layer.
  3. 第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも外側にずれている請求項1または請求項2のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein an end portion of the second pad metal layer is shifted outward from an end portion of the first pad metal layer.
  4. 第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも内側にずれている請求項1または請求項2のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein an end portion of the second pad metal layer is displaced inward from an end portion of the first pad metal layer.
  5. 第2のパッド領域の第1のパッドメタル層の下に層間絶縁膜を挟んで、第2のパッドメタル層と同一層をなすように複数個のダミーメタルが配設された請求項2記載の半導体装置。   3. The plurality of dummy metals are disposed so as to form the same layer as the second pad metal layer with an interlayer insulating film sandwiched between the first pad metal layer in the second pad region. Semiconductor device.
  6. パッド部の下の層に回路素子または配線が配設されている請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein a circuit element or a wiring is disposed in a layer below the pad portion.
  7. 第1のパッド領域と第2のパッド領域の少なくとも一方の下の層に回路素子または配線が配設されている請求項2記載の半導体装置。   3. The semiconductor device according to claim 2, wherein a circuit element or a wiring is disposed in a layer below at least one of the first pad region and the second pad region.
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2854731B1 (fr) * 2003-05-05 2005-08-12 St Microelectronics Sa Circuit integre et procede de test associe
US7157734B2 (en) * 2005-05-27 2007-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bond pad structures and methods of manufacturing thereof
JP4449824B2 (ja) * 2005-06-01 2010-04-14 カシオ計算機株式会社 半導体装置およびその実装構造
JP4717523B2 (ja) * 2005-06-13 2011-07-06 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2007042817A (ja) * 2005-08-02 2007-02-15 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置およびその製造方法
TWI339419B (en) * 2005-12-05 2011-03-21 Megica Corp Semiconductor chip
JP2008098225A (ja) * 2006-10-06 2008-04-24 Nec Electronics Corp 半導体装置
JP4403424B2 (ja) 2006-11-30 2010-01-27 ソニー株式会社 固体撮像装置
JP5111878B2 (ja) * 2007-01-31 2013-01-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5010948B2 (ja) * 2007-03-06 2012-08-29 オリンパス株式会社 半導体装置
US20080303177A1 (en) * 2007-06-06 2008-12-11 United Microelectronics Corp. Bonding pad structure
JP5027605B2 (ja) 2007-09-25 2012-09-19 パナソニック株式会社 半導体装置
DE102007046556A1 (de) * 2007-09-28 2009-04-02 Infineon Technologies Austria Ag Halbleiterbauelement mit Kupfermetallisierungen
US8089156B2 (en) * 2007-10-24 2012-01-03 Panasonic Corporation Electrode structure for semiconductor chip with crack suppressing dummy metal patterns
US7786584B2 (en) * 2007-11-26 2010-08-31 Infineon Technologies Ag Through substrate via semiconductor components
KR101043748B1 (ko) 2007-12-18 2011-06-27 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
JP5342154B2 (ja) * 2008-02-25 2013-11-13 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
FR2930840B1 (fr) * 2008-04-30 2010-08-13 St Microelectronics Crolles 2 Procede de reprise de contact sur un circuit eclaire par la face arriere
JP4343256B1 (ja) 2008-07-10 2009-10-14 Necエレクトロニクス株式会社 半導体装置の製造方法
US20100013109A1 (en) * 2008-07-21 2010-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fine pitch bond pad structure
US8581423B2 (en) * 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
JP5557100B2 (ja) * 2010-07-23 2014-07-23 株式会社ジェイテクト 電動モータ駆動用の半導体素子
CN102136458A (zh) * 2011-02-24 2011-07-27 中颖电子股份有限公司 针对boac构架的改进结构
JP2011119765A (ja) * 2011-03-07 2011-06-16 Panasonic Corp 半導体装置およびその製造方法
CN102314009A (zh) * 2011-09-09 2012-01-11 深圳市华星光电技术有限公司 液晶显示模组及液晶显示面板
US8532156B2 (en) 2011-09-13 2013-09-10 Seagate Technology Llc Semiconductor laser with test pads
US8923357B2 (en) 2011-09-13 2014-12-30 Seagate Technology Llc Semiconductor laser with cathode metal layer disposed in trench region
US8928142B2 (en) 2013-02-22 2015-01-06 Fairchild Semiconductor Corporation Apparatus related to capacitance reduction of a signal port
US9780051B2 (en) * 2013-12-18 2017-10-03 Nxp Usa, Inc. Methods for forming semiconductor devices with stepped bond pads
JP2016012650A (ja) * 2014-06-27 2016-01-21 ルネサスエレクトロニクス株式会社 半導体装置
KR20160056379A (ko) * 2014-11-10 2016-05-20 삼성전자주식회사 트리플 패드 구조를 이용하는 칩 및 그것의 패키징 방법

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59222952A (en) 1983-06-01 1984-12-14 Toshiba Corp Semiconductor device
US5248903A (en) 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
JP2749241B2 (ja) 1993-02-16 1998-05-13 ローム株式会社 半導体集積回路
US6300688B1 (en) * 1994-12-07 2001-10-09 Quicklogic Corporation Bond pad having vias usable with antifuse process technology
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
US5891805A (en) * 1996-12-13 1999-04-06 Intel Corporation Method of forming contacts
US6552438B2 (en) * 1998-06-24 2003-04-22 Samsung Electronics Co. Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2000198566A (ja) 1999-01-06 2000-07-18 Canon Inc シ―ト吸着搬送装置及び記録装置
TW442873B (en) * 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
US6306749B1 (en) * 1999-06-08 2001-10-23 Winbond Electronics Corp Bond pad with pad edge strengthening structure
US6291331B1 (en) * 1999-10-04 2001-09-18 Taiwan Semiconductor Manufacturing Company Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue
JP2001267323A (ja) 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2001284394A (ja) 2000-03-31 2001-10-12 Matsushita Electric Ind Co Ltd 半導体素子
JP2002016069A (ja) 2000-06-29 2002-01-18 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002016065A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体装置
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
US6586839B2 (en) 2000-08-31 2003-07-01 Texas Instruments Incorporated Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers
KR100368115B1 (ko) * 2001-01-26 2003-01-15 삼성전자 주식회사 반도체 소자의 본딩 패드 구조 및 그 제조방법
JP3561747B2 (ja) * 2001-03-30 2004-09-02 ユーディナデバイス株式会社 高周波半導体装置の多層配線構造
US6455943B1 (en) * 2001-04-24 2002-09-24 United Microelectronics Corp. Bonding pad structure of semiconductor device having improved bondability
FR2824954A1 (fr) * 2001-05-18 2002-11-22 St Microelectronics Sa Plot de connexion d'un circuit integre
JP3538170B2 (ja) * 2001-09-11 2004-06-14 松下電器産業株式会社 半導体装置及びその製造方法
JP2003142485A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US20030218259A1 (en) * 2002-05-21 2003-11-27 Chesire Daniel Patrick Bond pad support structure for a semiconductor device
JP3910493B2 (ja) * 2002-06-14 2007-04-25 新光電気工業株式会社 半導体装置及びその製造方法
US7023090B2 (en) * 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells
US7049701B2 (en) * 2003-10-15 2006-05-23 Kabushiki Kaisha Toshiba Semiconductor device using insulating film of low dielectric constant as interlayer insulating film

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US7391114B2 (en) 2008-06-24
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CN1652329A (zh) 2005-08-10
JP2005252230A (ja) 2005-09-15
US20050173801A1 (en) 2005-08-11

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