CN112420647B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN112420647B
CN112420647B CN202010847335.2A CN202010847335A CN112420647B CN 112420647 B CN112420647 B CN 112420647B CN 202010847335 A CN202010847335 A CN 202010847335A CN 112420647 B CN112420647 B CN 112420647B
Authority
CN
China
Prior art keywords
pad
metal
layer
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010847335.2A
Other languages
English (en)
Other versions
CN112420647A (zh
Inventor
中西一浩
山北茂洋
野岛和弘
门多健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of CN112420647A publication Critical patent/CN112420647A/zh
Application granted granted Critical
Publication of CN112420647B publication Critical patent/CN112420647B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05097—Random arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05546—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

实施方式提供能够提高由焊盘等引起的成品率的半导体装置及其制造方法。根据一个实施方式，半导体装置具备：基板；下部焊盘，设置于所述基板的上方；以及上部焊盘，设置于所述下部焊盘上。所述下部焊盘包括第一焊盘和设置于所述第一焊盘上的多个第一连接部，所述上部焊盘设置于所述多个第一连接部上，或者，所述上部焊盘包括第二焊盘和设置于所述第二焊盘下的多个第二连接部，所述下部焊盘设置于所述多个第二连接部下。

Description

半导体装置及其制造方法
【相关申请】
本申请享受以日本专利申请2019-153110号(申请日：2019年8月23日)作为基础申请的优先权。本申请通过参考该基础申请而包括基础的全部内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
在贴合多个晶片的金属焊盘来制造半导体装置的情况下，期望抑制由金属焊盘等引起的成品率的降低。
发明内容
实施方式提供能够提高由焊盘等引起的成品率的半导体装置及其制造方法。
根据一个实施方式，半导体装置具备：基板；下部焊盘，设置于所述基板的上方；以及上部焊盘，设置于所述下部焊盘上。所述下部焊盘包括第一焊盘和设置于所述第一焊盘上的多个第一连接部，所述上部焊盘设置于所述多个第一连接部上，或者，所述上部焊盘包括第二焊盘和设置于所述第二焊盘下的多个第二连接部，所述下部焊盘设置于所述多个第二连接部下。
附图说明
图1是表示第一实施方式的半导体装置的构造的剖视图。
图2是表示第一实施方式的柱状部的构造的剖视图。
图3是表示第一实施方式的半导体装置的制造方法的剖视图。
图4的(a)～(c)是表示第一实施方式的金属焊盘等的构造的剖视图及立体图。
图5的(a)～(c)是表示第一实施方式的金属焊盘等的构造的剖视图。
图6的(a)～(c)是表示第一实施方式的比较例的金属焊盘等的构造的剖视图及立体图。
图7的(a)～(c)是用于说明第一实施方式的比较例的金属焊盘等的问题的剖视图。
图8的(a)～(c)是用于说明第一实施方式的金属焊盘等的优点的剖视图。
图9的(a)～图11的(c)是表示第一实施方式的半导体装置的制造方法的剖视图及立体图。
图12的(a)、(b)是表示第一实施方式的第一变形例的半导体装置的制造方法的剖视图。
图13的(a)、(b)是表示第一实施方式的第二及第三变形例的金属焊盘等的构造的剖视图。
图14的(a)～图16的(b)是表示第一实施方式的第四变形例的半导体装置的制造方法的剖视图及立体图。
图17的(a)～(c)是表示第二实施方式的金属焊盘等的构造的剖视图及立体图。
图18的(a)、(b)是用于对第二实施方式及其比较例的金属焊盘等的构造进行比较的剖视图。
图19的(a)～(c)是表示第二实施方式的金属焊盘等的构造的剖视图。
图20的(a)～图21的(c)是表示第二实施方式的半导体装置的制造方法的剖视图及立体图。
图22的(a)、(b)是表示第二实施方式的第一及第二变形例的金属焊盘等的构造的剖视图。
附图标记说明
1：阵列芯片，2：电路芯片，
11：存储单元阵列，12：绝缘膜，13：层间绝缘膜，14：层间绝缘膜，
14a：绝缘膜，14b：绝缘膜，14c：绝缘膜，14d：绝缘膜，
14e：绝缘膜，14f：绝缘膜，14g：绝缘膜，14h：绝缘膜，
14i：绝缘膜，14j：绝缘膜，15：基板，16：基板，
21：台阶构造部，22：接触插塞，
23：字布线层，24：通孔插塞，
31：晶体管，32：栅极电极，33：接触插塞，
34：布线层，35：布线层，36：布线层，36a：通孔插塞，
36b：布线，37：通孔插塞，38：金属焊盘，
38a：第一下部焊盘，38b：下部连接部，38c：第二下部焊盘，
41：金属焊盘，41a：第一上部焊盘，41b：上部连接部，
41c：第二上部焊盘，42：通孔插塞，43：布线层，44：布线层，
45：通孔插塞，46：金属焊盘，47：钝化膜，
51：绝缘层，52：阻挡绝缘膜，53：电荷存储层，
54：隧道绝缘膜，55：沟道半导体层，56：芯绝缘膜。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1至图22中，对相同的结构标注相同的附图标记，并省略重复的说明。
(第一实施方式)
图1是表示第一实施方式的半导体装置的构造的剖视图。图1的半导体装置是将阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备包括多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12及存储单元阵列11下的层间绝缘膜13。绝缘膜12例如是硅氧化膜或硅氮化膜。层间绝缘膜13例如是硅氧化膜、或包括硅氧化膜和其他绝缘膜的层叠膜。
电路芯片2设置于阵列芯片1下。附图标记S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备层间绝缘膜14和层间绝缘膜14下的基板15。层间绝缘膜14例如是硅氧化膜或包括硅氧化膜和其他绝缘膜的层叠膜。基板15例如是硅基板等半导体基板。
图1示出了与基板15的表面平行且相互垂直的X方向及Y方向、及与基板15的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向进行处理，将-Z方向作为下方向进行处理。-Z方向与重力方向可以一致也可以不一致。
阵列芯片1具备多条字线WL和源极线SL作为存储单元阵列11内的电极层。图1示出了存储单元阵列11的阶梯构造部21。各字线WL经由接触插塞22与字布线层23电连接。贯穿多个字线WL的各柱状部CL经由通孔插塞24而与位线BL电连接，且与源极线SL电连接。源极线SL包括作为半导体层的第一层SL1和作为金属层的第二层SL2。
电路芯片2具备多个晶体管31。各晶体管31具备隔着栅极绝缘膜设置于基板15上的栅极电极32和设置于基板15内的未图示的源极扩散层以及漏极扩散层。另外，电路芯片2具备：多个接触插塞33，设置于这些晶体管31的源极扩散层或漏极扩散层上；布线层34，设置于这些接触插塞33上，包括多个布线；以及布线层35，设置于布线层34上，包括多个布线。
电路芯片2还具备：布线层36，设置于布线层35上，包括多个布线；多个通孔插塞37，设置于布线层36上；以及多个金属焊盘38，设置于这些通孔插塞37上。金属焊盘38例如是Cu(铜)层或Al(铝)层。金属焊盘38是下部焊盘的例子。关于金属焊盘38的详细情况，在后面叙述。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，与金属焊盘38电连接。
阵列芯片1具备设置于金属焊盘38上的多个金属焊盘41和设置于金属焊盘41上的多个通孔插塞42。另外，阵列芯片1具备：布线层43，设置于这些通孔插塞42上，包括多个布线；以及布线层44，设置于布线层43上，包括多个布线。金属焊盘41例如为Cu层或Al层。金属焊盘41是上部焊盘的例子。关于金属焊盘41的详细情况，在后面叙述。
阵列芯片1还具备设置于布线层44上的多个通孔插塞45、设置于这些通孔插塞45上或绝缘膜12上的金属焊盘46、以及设置于金属焊盘46上或绝缘膜12上的钝化膜47。金属焊盘46例如是Cu层或Al层，作为图1的半导体装置的外部连接焊盘(焊接盘)发挥功能。钝化膜47例如是硅氧化膜等绝缘膜，具有使金属焊盘46的上表面露出的开口部P。金属焊盘46能够经由该开口部P通过接合线、焊球、金属凸块等与安装基板或其他装置连接。
图2是表示第一实施方式的柱状部CL的构造的剖视图。
如图2所示，存储单元阵列11具备在层间绝缘膜13(图1)上交替层叠的多个字线WL和多个绝缘层51。字线WL例如是W(钨)层。绝缘层51例如是硅氧化膜。
柱状部CL依次包括阻挡绝缘膜52、电荷蓄积层53、隧道绝缘膜54、沟道半导体层55、以及芯绝缘膜56。电荷蓄积层53例如是硅氮化膜，隔着阻挡绝缘膜52形成于字线WL及绝缘层51的侧面。电荷蓄积层53也可以是多晶硅层等半导体层。沟道半导体层55例如是多晶硅层，隔着隧道绝缘膜54形成于电荷蓄积层53的侧面。阻挡绝缘膜52、隧道绝缘膜54以及芯绝缘膜56例如是硅氧化膜或者金属绝缘膜。
图3是表示第一实施方式的半导体装置的制造方法的剖视图。图3表示包括多个阵列芯片1的阵列晶片W1和包括多个电路芯片2的电路晶片W2。阵列晶片W1也被称为存储器晶片，电路晶片W2也被称为CMOS晶片。
请注意：图3的存储器晶片W1的朝向与图1的存储器芯片1的朝向相反。在本实施方式中，通过将阵列晶片W1与电路晶片W2贴合来制造半导体装置。图3示出了为了贴合而使朝向反转之前的存储器晶片W1，图1示出了为了贴合而使朝向反转而进行贴合及切割后的存储器芯片1。
在图3中，附图标记S1表示存储器晶片W1的上表面，附图标记S2表示电路晶片W2的上表面。请注意：存储器晶片W1具备设置于绝缘膜12下的基板16。基板16例如是硅基板等半导体基板。基板15是第一基板的例子，基板16是第二基板的例子。
在本实施方式中，首先，如图3所示，在存储器晶片W1的基板16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、阶梯结构部21、金属焊盘41等，在电路晶片W2的基板15上形成层间绝缘膜14、晶体管31、金属焊盘38等。例如，在基板16上依次形成通孔插塞45、布线层44、布线层43、通孔插塞42以及金属焊盘41。另外，在基板15上依次形成接触插塞33、布线层34、布线层35、布线层36、通孔插塞37以及金属焊盘38。接着，利用机械压力将阵列晶片W1与电路晶片W2贴合。由此，层间绝缘膜13和层间绝缘膜14被粘接。接着，在400℃下对阵列晶片W1和电路晶片W2进行退火。由此，金属焊盘41与金属焊盘38接合。
之后，通过CMP(Chemical Mechanical Polishing，化学机械抛光)将基板15薄膜化，通过CMP去除基板16后，将阵列晶片W1及电路晶片W2切断成多个芯片。这样，制造出图1的半导体装置。图1示出了包括金属焊盘38的电路芯片1和包括配置于金属焊盘38上的金属焊盘41的阵列芯片1。另外，金属焊盘46和钝化膜47例如在基板15的薄膜化及基板16的除去之后，形成于绝缘膜12上。
另外，在本实施方式中，使阵列晶片W1与电路晶片W2贴合，但也可以代替地使阵列晶片W1彼此贴合。参照图1至图3所述的内容、参照图4至图22后述的内容，也能够应用于阵列晶片W1彼此的贴合。
另外，图1示出了层间绝缘膜13与层间绝缘膜14的边界面、金属焊盘41与金属焊盘38的边界面，但通常在上述退火后这些边界面不被观察到。然而，这些边界面的位置例如能够通过检测金属焊盘41的侧面和/或金属焊盘38的侧面的倾斜、金属焊盘41的侧面与金属焊盘38的位置偏移来估计。
图4是表示第一实施方式的金属焊盘38、41等的构造的剖视图及立体图。
图4的(a)是表示相互电连接的1组金属焊盘38、41的剖视图。图4的(b)是表示图4的(a)的金属焊盘41的立体图。图4的(c)是表示图4的(a)的金属焊盘38的立体图。金属焊盘38是下部焊盘的例子，金属焊盘41是上部焊盘的例子。
以下，参照图4的(a)对金属焊盘38、41等的构造进行说明。在该说明中，也适当参照图4的(b)及图4的(c)。
金属焊盘38包括设置于通孔插塞37上的第一下部焊盘38a、设置于第一下部焊盘38a上的多个下部连接部38b、以及设置于这些下部连接部38b上的第二下部焊盘38c。金属焊盘41设置于第二下部焊盘38c上。第一下部焊盘38a、下部连接部38b以及第二下部焊盘38c分别是第一焊盘、第一连接部以及第三焊盘的例子。
金属焊盘41包括设置于第二下部焊盘38c上的第一上部焊盘41a、设置于第一上部焊盘41a上的多个上部连接部41b、以及设置于这些上部连接部41b上的第二上部焊盘41c。通孔插塞42设置于第二上部焊盘41c上。第一上部焊盘41a、上部连接部41b以及第二上部焊盘41c分别是第四焊盘、第二连接部以及第二焊盘的例子。
在本实施方式中，通孔插塞37和第一下部焊盘38a同时形成，下部连接部38b和第二下部焊盘38c同时形成。通孔插塞37和第一下部焊盘38a依次包括阻挡金属层A1和布线材料层B1，下部连接部38b和第二下部焊盘38c依次包括阻挡金属层A2和布线材料层B2。因此，第一下部焊盘38a不隔着阻挡金属层而设置于通孔插塞37上，下部连接部38b隔着阻挡金属层A2设置于第一下部焊盘38a上，第二下部焊盘38c不隔着阻挡金属层而设置于下部连接部38b上。阻挡金属层A1、A2例如是含Ti(钛)层或含Ta(钽)层。配线材料层B1、B2例如是Cu层。
在本实施方式中，通孔插塞42和第二上部焊盘41c同时形成，上部连接部41b和第一上部焊盘41a同时形成。通孔插塞42和第二上部焊盘41c依次包括阻挡金属层A4和布线材料层B4，上部连接部41b和第一上部焊盘41a依次包括阻挡金属层A3和布线材料层B3。因此，第二上部焊盘41c不隔着阻挡金属层而设置于通孔插塞42下，上部连接部41b隔着阻挡金属层A3而设置于第二上部焊盘41c下，第一下部焊盘41a不隔着阻挡金属层而设置于下部连接部41b下。阻挡金属层A3、A4例如是含Ti层或含Ta层。配线材料层B3、B4例如是Cu层。
如上所述，本实施方式的金属焊盘38包括通过多个下部连接部38b而电连接的第一下部焊盘38a和第二下部焊盘38c。这些下部连接部38b通过层间绝缘膜14而相互分离。图4的(c)示出了配置成四角格子状的5×4个下部连接部38b，但下部连接部38b的个数和配置并不限定于此。
同样地，本实施方式的金属焊盘41包括通过多个上部连接部41b而电连接的第一上部焊盘41a和第二上部焊盘41c。这些上部连接部41b通过层间绝缘膜13而相互分离。图4的(b)表示配置成四角格子状的5×4个上部连接部41b，但上部连接部41b的个数和配置并不限定于此。
在本实施方式的1组金属焊盘38、41中，上部连接部41b的个数与下部连接部38b的个数相同，但也可以与下部连接部38b的个数不同。在本实施方式的1组金属焊盘38、41中，上部连接部41b的配置与下部连接部38b的配置相同，但也可以与下部连接部38b的配置不同。
图5是表示第一实施方式的金属焊盘38等的构造的剖视图。
图5的(a)、图5的(b)、图5的(c)分别表示图4的(c)的截面C2中的下部连接部38b的形状的第一例、第二例、第三例。图5的(a)的下部连接部38b配置为二维阵列状。图5的(b)的下部连接部38b配置成一维阵列状，在X方向上相互邻接，在Y方向上延伸。图5的(c)的下部连接部38b包括较小的下部连接部38b和较大的下部连接部38b。本实施方式的金属焊盘38可以包括任意形状的下部连接部38b。
另外，图4的(b)的截面C1中的上部连接部41b的形状能够设定为与这些例子相同的形状。
图6是表示第一实施方式的比较例的金属焊盘38、41等的构造的剖视图及立体图。
图6的(a)是表示相互电连接的1组金属焊盘38、41的剖视图。图6的(b)是表示图6的(a)的金属焊盘41的立体图。图6的(c)是表示图6的(a)的金属焊盘38的立体图。
本比较例的金属焊盘38，由单一的焊盘形成。另外，本比较例的金属焊盘41也由单一的焊盘形成。在本比较例中，通孔插塞37和金属焊盘38依次包括阻挡金属层A5和布线材料层B5，通孔插塞42和金属焊盘41依次包括阻挡金属层A6和布线材料层B6。阻挡金属层A5、A6例如为含Ti层或含Ta层。配线材料层B5、B6例如为Cu层。
图7是用于说明第一实施方式的比较例的金属焊盘38、41等的问题的剖视图。
图7的(a)示出了参照图3说明的进行退火期间的金属焊盘38、41。若对金属焊盘38、41进行退火，则金属焊盘38、41热膨胀，在金属焊盘38、41的贴合面S有可能产生空隙(附图标记α1)。
图7的(b)示出了进行退火后被冷却的期间的金属焊盘38、41。若将金属焊盘38、41在退火后冷却，则金属焊盘38、41热收缩，拉伸应力作用于金属焊盘38、41、通孔插塞37、42。附图标记α2表示形状从附图标记α1所示的状态变化后的空隙。
图7的(c)示出了冷却结束后的金属焊盘38、41。附图标记α3表示形状从附图标记α2所示的状态变化的空隙。在上述拉伸应力较大的情况下，因拉伸应力而有可能在金属焊盘38、41中、通孔插塞37、42中产生进一步的空隙。附图标记α4表示通孔插塞37中产生的空隙。一般地，由于通孔插塞37较细，因此若在通孔插塞37产生空隙，则有可能在通孔插塞37产生接触不良，或通孔插塞37过度地成为高电阻。这在通孔插塞42中产生空隙的情况下也是同样的。
图8是用于说明第一实施方式的金属焊盘38、41等的优点的剖视图。
图8的(a)示出了参照图3说明的进行退火期间的金属焊盘38、41。若对金属焊盘38、41进行退火，则金属焊盘38、41热膨胀，在金属焊盘38、41的贴合面S有可能产生空隙(附图标记β1)。
图8的(b)表示进行退火后被冷却的期间的金属焊盘38、41。若将金属焊盘38、41在退火后冷却，则金属焊盘38、41热收缩，拉伸应力作用于金属焊盘38、41、通孔插塞37、42。附图标记β2表示形状从附图标记β1所示的状态变化后的空隙。
图8的(c)示出了冷却结束后的金属焊盘38、41。附图标记β3示出了形状从附图标记β2所示的状态变化后的空隙。在上述拉伸应力大的情况下，因拉伸应力而有可能在金属焊盘38、41中、通孔插塞37、42中产生进一步的空隙。附图标记β4表示在下部连接部38b产生的空隙。本实施方式的金属焊盘38包括多个下部连接部38b，因此即使在某个下部连接部38b产生空隙，只要在其他的下部连接部38b中不产生空隙，就能够抑制在金属焊盘38整体产生接触不良、金属焊盘38整体过度地成为高电阻。这在金属焊盘41的上部连接部41b产生了空隙的情况下也是同样的。
另外，在下部连接部38b产生了空隙的情况下，下部连接部38b的下表面的阻挡金属层A2作为吸收位置发挥功能。即，附图标记β4所示的空隙即使被施加电流也不会移动。由此，能够抑制该空隙移动到通孔插塞37而对通孔插塞37带来接触不良、高电阻。这在金属焊盘41的上部连接部41b产生了空隙的情况下也是同样的。
这样，根据本实施方式，能够减少由空隙引起的金属焊盘38、41及其通孔插塞37、42的不良，能够提高半导体装置的成品率。
图9至图11是表示第一实施方式的半导体装置的制造方法的剖视图及立体图。在此，对在电路晶片W2用的基板15的上方形成金属焊盘38等的工艺进行说明。该说明也能够应用于在阵列晶片W1用的基板16的上方形成金属焊盘41等的工艺。
首先，在基板15的(参照图1、图3)的上方形成布线层36的(图9的(a))。图9的(a)示出了在构成层间绝缘膜14的绝缘膜14a中形成的布线层36。绝缘膜14a例如是SiO2膜(硅氧化膜)。配线层36依次包括在基板15的上方依次形成的阻挡金属层A7和配线材料层B7。阻挡金属层A7例如是含Ti层或含Ta层。配线材料层B7例如是Cu层。
接着，在布线层36及绝缘膜14a上形成构成层间绝缘膜14的绝缘膜14b(图9的(b))。绝缘膜14b例如是SiO2膜。接着，在该绝缘膜14b上形成通孔插塞37用的开口部H1和第一下部焊盘38a用的开口部H2(图9的(c))。接着，在开口部H1、H2内依次形成阻挡金属层A1和布线材料层B1(图10的(a))。其结果，在开口部H1内的布线层36上形成通孔插塞37，在开口部H2内的通孔插塞37上形成第一下部焊盘38a。
接着，在第一下部焊盘38a以及绝缘膜14b上形成构成层间绝缘膜14的绝缘膜14c(图10的(b))。绝缘膜14c例如是SiO2膜。接着，在该绝缘膜14c上形成下部连接部38b用的多个开口部H3和第二下部焊盘38c用的开口部H4(图10的(c)、图11的(a))。接着，在开口部H3、H4内依次形成阻挡金属层A2和布线材料层B2(图11的(b))。其结果，在开口部H3内的第一下部焊盘38a上形成下部连接部38b，在开口部H4内的下部连接部38b上形成第二下部焊盘38c。图11的(c)是与图11的(b)对应的立体图。
这样，在电路晶片W2用的基板15的上方形成布线层36、通孔插塞37以及金属焊盘38。同样地，在阵列晶片W1用的基板16的上方形成布线层43、通孔插塞42以及金属焊盘41。金属焊盘41的第二上部焊盘41c、上部连接部41b及第一上部焊盘41a分别能够与金属焊盘38的第一下部焊盘38a、下部连接部38b及第二下部焊盘38c同样地形成。另外，阻挡金属层A4、布线材料层B4、阻挡金属层A3以及布线材料层B3分别能够与阻挡金属层A1、布线材料层B1、阻挡金属层A2以及布线材料层B2同样地形成。之后，通过执行图3的方法，制造出图1的半导体装置。
图12是表示第一实施方式的第一变形例的半导体装置的制造方法的剖视图。
图12的(a)是表示图11的(a)与图11的(b)之间的工序的剖视图。在形成开口部H3、H4之后，也可以通过各向同性蚀刻对开口部H3、H4进行加工。其结果，开口部H3、H4的侧面被加工成锥形形状(图12的(a))。另外，也可以代替追加图12的(a)的工序，而实施图11的(a)的工序，以使开口部H3、H4的侧面成为锥形形状。
接着，在开口部H3、H4内依次形成阻挡金属层A2和布线材料层B2(图12的(b))。其结果，在开口部H3内的第一下部焊盘38a上形成下部连接部38b，在开口部H4内的下部连接部38b上形成第二下部焊盘38c。之后，通过执行图3的方法，制造出图1的半导体装置。
图13是表示第一实施方式的第二以及第三变形例的金属焊盘38、41等的构造的剖视图。
图13的(a)表示第二变形例的金属焊盘38、41。本变形例的金属焊盘38具有与第一实施方式的金属焊盘38(图4的(a))相同的构造。另一方面，本变形例的金属焊盘41具有与第一实施方式的比较例的金属焊盘41(图6的(a))相同的构造。由此，能够减少由空隙引起的金属焊盘38及其通孔插塞37的不良，能够提高半导体装置的成品率。
另一方面，图13的(b)表示第三变形例的金属焊盘38、41。本变形例的金属焊盘38具有与第一实施方式的比较例的金属焊盘38(图6的(a))相同的构造。另一方面，本变形例的金属焊盘41具有与第一实施方式的金属焊盘41(图4的(a))相同的构造。由此，能够减少由空隙引起的金属焊盘41及其通孔插塞42的不良，能够提高半导体装置的成品率。
另外，图13的(a)的金属焊盘41、图13的(b)的金属焊盘38，能够通过将图9的(a)至图11的(c)的工序中的图10的(b)至图11的(c)的工序省略而形成。但是，在该情况下，使绝缘膜14b的膜厚进一步变厚，使开口部H2的深度更深。
图14至图16是表示第一实施方式的第四变形例的半导体装置的制造方法的剖视图及立体图。在此，对在电路晶片W2用的基板15的上方形成金属焊盘38等的工艺进行说明。该说明也能够应用于在阵列晶片W1用的基板16的上方形成金属焊盘41等的工艺。
首先，在基板15的(参照图1、图3)的上方形成构成布线层36的通孔插塞36a(图14的(a))。图14的(a)表示在构成层间绝缘膜14的绝缘膜14d内形成的通孔插塞36a。绝缘膜14d例如是SiO2膜。
接着，在通孔插塞36a及绝缘膜14d上形成构成层间绝缘膜14的绝缘膜14e(图14的(b))。绝缘膜14e例如是SiO2膜。接着，在该绝缘膜14e中形成构成布线层36的布线36b以及第一下部焊盘P1用的开口部H5(图14的(c))。接下来，在开口部H5内形成布线36b以及第一下部焊盘P1(图15的(a))。其结果，在开口部H5内的通孔插塞36a上形成布线36b，进而，在开口部H5内形成与布线36b电连接的第一下部焊盘P1。
接着，在布线36b、第一下部焊盘P1以及绝缘膜14e上形成构成层间绝缘膜14的绝缘膜14f(图15的(b))。绝缘膜14f例如是SiO2膜。接着，在该绝缘膜14f上形成多个通孔插塞37用的多个开口部H6和金属焊盘38用的开口部H7(图15的(c))。接着，在开口部H6、H7内依次形成阻挡金属层和布线材料层B8的(图16的(a))。其结果，在开口部H6内的第一下部焊盘P1上形成通孔插塞37，在开口部H7内的通孔插塞37上形成金属焊盘38。在本变形例中，通孔插塞37作为下部连接部P2发挥功能，金属焊盘38作为第二下部焊盘P3发挥功能。图16的(b)是与图16的(a)对应的立体图。
这样，在电路晶片W2用的基板15的上方形成布线层36、通孔插塞37以及金属焊盘38。同样地，在阵列晶片W1用的基板16的上方形成布线层43、通孔插塞42以及金属焊盘41。之后，通过执行图3的方法，制造出图1的半导体装置。
本变形例的第一下部焊盘P1(布线层36)、下部连接部P2(通孔插塞37)以及第二下部焊盘P2(金属焊盘38)具有与第一实施方式(图4的(a))的第一下部焊盘38a、下部连接部38b以及第二下部焊盘38c相同的构造。即，在本变形例中，通过布线层36、通孔插塞37以及金属焊盘38来实现与第一实施方式的金属焊盘38相同的构造。由此，例如能够减少电路晶片W2的布线层(包括焊盘层)的数量。
同样地，在本变形例中，也可以通过布线层43、通孔插塞42以及金属焊盘41来实现与第一实施方式的金属焊盘41相同的构造。由此，例如能够减少阵列晶片W1的布线层(包括焊盘层)的数量。在该情况下，第一上部焊盘由金属焊盘41实现，多个上部连接部由多个通孔插塞42实现，第二上部焊盘由布线层43实现。第二上部焊盘与布线层43内的布线电连接，该布线与布线层43内的通孔插塞电连接。
如上所述，本实施方式的金属焊盘38包括第一下部焊盘38a、多个下部连接部38b和第二下部焊盘38c，本实施方式的金属焊盘41包括第一上部焊盘41a、多个上部连接部41b和第二上部焊盘41c。因此，根据本实施方式，能够提高由金属焊盘38、41等引起的半导体装置的成品率。
另外，在本实施方式中，第一下部焊盘38a由阻挡金属A1和布线材料层B1形成，下部连接部38b和第二下部焊盘38c由阻挡金属A2和布线材料层B2形成，但也可以代替地，第一下部焊盘38a的一部分由阻挡金属A1和布线材料层B1形成，第一下部焊盘38a的剩余部分、下部连接部38b和第二下部焊盘38c由阻挡金属A2和布线材料层B2形成。在该情况下，阻挡金属A2介于第一下部焊盘38a的一部分与剩余部分之间。
(第二实施方式)
图17是表示第二实施方式的金属焊盘38、41等的构造的剖视图及立体图。
图17的(a)是表示相互电连接的1组金属焊盘38、41的剖视图。图17的(b)是表示图17的(a)的金属焊盘41的立体图。图17的(c)是表示图17的(a)的金属焊盘38的立体图。
以下，参照图17的(a)对金属焊盘38、41等的构造进行说明。在该说明中，也适当参照图17的(b)及图17的(c)。
本实施方式的金属焊盘38包括设置于通孔插塞37上的第一下部焊盘38a和设置于第一下部焊盘38a上的多个下部连接部38b，但不包括第一实施方式那样的第二下部焊盘38c。本实施方式的金属焊盘41设置于这些下部连接部38b上。
本实施方式的金属焊盘41包括设置于这些下部连接部38b上的多个上部连接部41b和设置于这些上部连接部41b上的第二上部焊盘41c，但不包括第一实施方式那样的第一上部焊盘41a。通孔插塞42设置于第二上部焊盘41c上。通孔插塞42上的布线层43依次包括阻挡金属层A9和布线材料层B9。阻挡金属层A9例如是含Ti层或含Ta层。配线材料层B9例如是Cu层。
如上所述，本实施方式的金属焊盘38包括与多个下部连接部38b电连接的第一下部焊盘38a。这些下部连接部38b通过层间绝缘膜14而相互分离。图17的(c)示出了配置成四角格子状的5×4个下部连接部38b，但下部连接部38b的个数和配置并不限定于此。
同样地，本实施方式的金属焊盘41包括与多个上部连接部41b电连接的第二上部焊盘41c。这些上部连接部41b通过层间绝缘膜13而相互分离。图17的(b)示出了配置成四角格子状的5×4个上部连接部41b，但上部连接部41b的个数和配置并不限定于此。
在本实施方式的1组金属焊盘38、41中，上部连接部41b的个数与下部连接部38b的个数相同，但也可以与下部连接部38b的个数不同。在本实施方式的1组金属焊盘38、41中，进一步地、上部连接部41b的配置与下部连接部38b的配置相同，但也可以与下部连接部38b的配置不同。例如，可以将下部连接部38b的个数设为20个，将下部连接部41b的个数设为10个，在2个下部连接部38b上配置1个下部连接部41b。
根据本实施方式，与第一实施方式同样地，能够减少由空隙引起的金属焊盘38、41及其通孔插塞37、42的不良，能够提高半导体装置的成品率。进而，根据本实施方式，如后所述，能够减少因凹陷而引起的金属焊盘38、41的不良。
图18是用于对第二实施方式及其比较例的金属焊盘38等的构造进行比较的剖视图。
图18的(a)示出了第二实施方式的比较例的金属焊盘38的截面。本比较例的金属焊盘38具有比较大的尺寸。因此，当通过CMP使金属焊盘38的表面平坦化时，如图18的(a)所示，有可能在金属焊盘38的表面形成大的凹陷(凹部)。这对于金属焊盘41也是同样的。在该情况下，若将金属焊盘38与金属焊盘41贴合，则有可能产生金属焊盘38、41的接合不良。
图18的(b)表示第二实施方式的金属焊盘38的截面。当通过CMP将本实施方式的金属焊盘38的表面平坦化时，凹陷形成于尺寸小的各下部连接部38b，而不是尺寸大的第一下部焊盘38a。因此，如图18的(b)所示，凹陷的尺寸变小。这对于金属焊盘41也是同样的。因此，根据本实施方式，在使金属焊盘38与金属焊盘41贴合时，不易产生金属焊盘38、41的接合不良。
图19是表示第二实施方式的金属焊盘38等的构造的剖视图。
图19的(a)、图19的(b)、图19的(c)分别表示下部连接部38b的XY截面形状的第一例、第二例、第三例。图19的(a)的下部连接部38b配置成一维阵列状，在X方向上相互邻接，在Y方向上延伸。图19的(b)的下部连接部38b配置成二维阵列状，具体而言，配置成四角格子状。图19的(c)的下部连接部38b配置成二维阵列状，具体而言，配置为三角格子状。图19的(b)的各下部连接部38b具有四边形的平面形状，图19的(c)的各下部连接部38b具有圆形的平面形状。本实施方式的金属焊盘38可以包括任意形状的下部连接部38b。
另外，本实施方式的上部连接部41b的形状能够设定为与这些例子相同的形状。
本实施方式的金属焊盘38例如能够通过将图9的(a)至图11的(c)的工序中形成开口部H4的工序省略而形成。这对于本实施方式的金属焊盘41也是同样的。另一方面，这些金属焊盘38、41也可以通过以下的方法形成。
图20及图21是表示第二实施方式的半导体装置的制造方法的剖视图及立体图。在此，对在电路晶片W2用的基板15的上方形成金属焊盘38等的工艺进行说明。该说明也能够应用于在阵列晶片W1用的基板16的上方形成金属焊盘41等的工艺。
首先，在基板15(参照图1、图3)的上方形成布线层36(图20的(a))。图20的(a)表示在构成层间绝缘膜14的绝缘膜14g内形成的布线层36。绝缘膜14g例如是SiO2膜。
接下来，在布线层36及绝缘膜14g上依次形成绝缘膜14h、14i、14j(图20的(b))。绝缘膜14h例如是SiO2膜。绝缘膜14i例如是SiN膜(硅氮化膜)。绝缘膜14j例如是SiO2膜。
接着，形成贯通绝缘膜14h、14i、14j的开口部H8(图20的(b))。接下来，形成贯通绝缘膜14j的多个开口部H9(图20的(c))。接着，去除开口部H8与开口部H9之间的绝缘膜14i，形成连接开口部H8和开口部H9的开口部H10(图21的(a))。
此外，绝缘膜14h与绝缘膜14j之间的膜也可以代替作为绝缘膜14i而作为包括绝缘膜(例如SiO2膜)和半导体膜(例如非晶硅膜)的膜。在该情况下，也可以是，绝缘膜14h与绝缘膜14j之间的膜中，在图21的(b)的工序中被去除的部分作为半导体膜，在图21的(b)的工序中未被去除的部分作为绝缘膜。
接着，在开口部H8、H9、H10内依次形成阻挡金属层和布线材料层(图21的(c))。其结果，在绝缘膜14h内形成通孔插塞37，在绝缘膜14i内形成第一下部焊盘38a，在绝缘膜14j内形成下部连接部38b。图21的(c)是与图21的(b)对应的立体图。
这样，在电路晶片W2用的基板15的上方形成布线层36、通孔插塞37以及金属焊盘38。同样地，在阵列晶片W1用的基板16的上方形成布线层43、通孔插塞42以及金属焊盘41。金属焊盘41的第二上部焊盘41c及上部连接部41b分别能够与金属焊盘38的第一下部焊盘38a及下部连接部38b同样地形成。之后，通过执行图3的方法，制造出图1的半导体装置。
图22是表示第二实施方式的第一及第二变形例的金属焊盘38、41等的构造的剖视图。
图22的(a)示出了第一变形例的金属焊盘38、41。本变形例的金属焊盘38具有与第二实施方式的金属焊盘38(图17的(a))相同的构造。另一方面，本变形例的金属焊盘41具有与第一实施方式的比较例的金属焊盘41(图6的(a))相同的构造。由此，能够减少由空隙引起的金属焊盘38及其通孔插塞37的不良，能够提高半导体装置的成品率。
另一方面，图22的(b)表示第二变形例的金属焊盘38、41。本变形例的金属焊盘38具有与第一实施方式的比较例的金属焊盘38(图6的(a))相同的构造。另一方面，本变形例的金属焊盘41具有与第二实施方式的金属焊盘41(图17的(a))相同的构造。由此，能够减少由空隙引起的金属焊盘41及其通孔插塞42的不良，能够提高半导体装置的成品率。
另外，图22的(a)的金属焊盘41、图22的(b)的金属焊盘38能够通过将图9的(a)至图11的(c)的工序中的图10的(b)至图11的(c)的工序省略而形成。但是，在该情况下，使绝缘膜14b的膜厚更厚，使开口部H2的深度更深。
如上所述，本实施方式的金属焊盘38包括第一下部焊盘38a和多个下部连接部38b，本实施方式的金属焊盘41包括多个上部连接部41b和第二上部焊盘41c。因此，根据本实施方式，能够提高由金属焊盘38、41等引起的半导体装置的成品率。
另外，在本实施方式中，第一下部焊盘38a由阻挡金属A1和布线材料层B1形成，下部连接部38b由阻挡金属A2和布线材料层B2形成，但也可以代替地，第一下部焊盘38a的一部分由阻挡金属A1和布线材料层B1形成，第一下部焊盘38a的剩余部分和下部连接部38b由阻挡金属A2和布线材料层B2形成。在前者的情况下，实现了多组阻挡金属A2以及布线材料层B2构成多个下部连接部38b的构造。在后者的情况下，实现了具有梳形形状的1组阻挡金属A2和布线材料层B2构成多个下部连接部38b和第一下部焊盘38a的剩余部分的构造。
以上，对几个实施方式进行了说明，但这些实施方式仅作为例子进行提示，并不意图限定发明的范围。本说明书中说明的新的装置以及方法能够以其他各种方式来实施。另外，对于本说明书中说明的装置以及方法的方式，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。所附的权利要求书及其等同的范围意图包括发明的范围及主旨中所包括的这样的方式及变形例。

Claims (10)

1.一种半导体装置，具备：
第一芯片，具有第一布线层；
第二芯片，与所述第一芯片接合，具有第二布线层；以及
金属焊盘，设置于所述第一芯片及所述第二芯片的接合面上，将所述第一布线层的第一布线电连接于所述第二布线层的第二布线，
所述金属焊盘包括设置于所述第一芯片的第一部分，
所述第一部分包括第一焊盘和设置于所述第一焊盘的上方且直接设置于所述第一焊盘上的多个第一连接部，
所述多个第一连接部分别包括第一金属体和覆盖所述第一金属体的外周部的第一阻挡金属层，
所述多个第一连接部的所述第一金属体分别隔着所述第一阻挡金属层而与所述第一焊盘连接。
2.根据权利要求1所述的半导体装置，其中，
所述金属焊盘包括设置于所述第一芯片的所述第一部分上的第二部分，
所述第二部分包括第二焊盘和多个第二连接部，所述第二连接部设置于所述第二焊盘的下方且直接设置于所述第二焊盘上，
所述多个第二连接部分别包括第二金属体和覆盖所述第二金属体的外周部分的第二阻挡金属层，
所述多个第二连接部的所述第二金属体分别隔着所述第二阻挡金属层而与所述第二焊盘接触。
3.根据权利要求2所述的半导体装置，其中，
所述第二连接部的个数与所述第一连接部的个数相同。
4.根据权利要求2所述的半导体装置，其中，
所述金属焊盘还包括设置于所述多个第一连接部上且所述多个第二连接部下的第三焊盘。
5.根据权利要求4所述的半导体装置，其中，
所述金属焊盘还包括设置于所述第三焊盘上且所述多个第二连接部下的第四焊盘。
6.根据权利要求4所述的半导体装置，其中，
所述第三焊盘不隔着所述第一阻挡金属层而设置于所述第一连接部上。
7.根据权利要求5所述的半导体装置，其中，
所述第四焊盘不隔着所述第二阻挡金属层而设置于所述第三焊盘上。
8.根据权利要求2所述的半导体装置，其中，
所述第一焊盘设置于所述第一布线层内，
或者，
所述第二焊盘设置于所述第二布线层内。
9.一种半导体装置的制造方法，包括如下步骤：
在包括第一布线层的第一芯片的上方形成第一金属焊盘；
在包括第二布线层的第二芯片的上方形成第二金属焊盘；
通过将形成于所述第一芯片上的所述第一金属焊盘与形成于所述第二芯片上的所述第二金属焊盘贴合，在所述第一金属焊盘上配置所述第二金属焊盘，
所述第一金属焊盘包括设置于所述第一芯片的第一部分，
所述第一部分包括第一焊盘和设置于所述第一焊盘的上方且直接设置于所述第一焊盘上的多个第一连接部，
所述多个第一连接部分别包括第一金属体和覆盖所述第一金属体的外周部分的第一阻挡金属层，所述多个第一连接部隔着所述第一阻挡金属层而与所述第一焊盘连接。
10.根据权利要求9所述的半导体装置的制造方法，其中，
所述第一金属焊盘通过在所述多个第一连接部上进一步形成第三焊盘而形成，所述第二金属焊盘通过将所述第一金属焊盘与所述第二金属焊盘贴合而配置于所述第三焊盘上，
所述第二金属焊盘包括设置于所述第二芯片的第二部分，
所述第二部分包括第四焊盘和多个第二连接部，所述多个第二连接部形成于所述第四焊盘的下方且直接形成于所述第四焊盘上，
所述多个第二连接部分别包括第二金属体和覆盖所述第二金属体的外周部分的第二阻挡金属层，所述多个第二连接部隔着所述第二阻挡金属层而与所述第四焊盘连接。
CN202010847335.2A 2019-08-23 2020-08-21 半导体装置及其制造方法 Active CN112420647B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-153110 2019-08-23
JP2019153110A JP2021034560A (ja) 2019-08-23 2019-08-23 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN112420647A CN112420647A (zh) 2021-02-26
CN112420647B true CN112420647B (zh) 2024-04-09

Family

ID=74646039

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010847335.2A Active CN112420647B (zh) 2019-08-23 2020-08-21 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US11594514B2 (zh)
JP (1) JP2021034560A (zh)
CN (1) CN112420647B (zh)
TW (1) TWI757836B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7120642B2 (ja) * 2019-08-30 2022-08-17 株式会社ニューギン 遊技機
JP2021150574A (ja) * 2020-03-23 2021-09-27 キオクシア株式会社 半導体装置
JP2022131445A (ja) * 2021-02-26 2022-09-07 キオクシア株式会社 半導体装置及びその製造方法
JP2022142498A (ja) * 2021-03-16 2022-09-30 キオクシア株式会社 半導体記憶装置および半導体記憶装置の製造方法
US20230082971A1 (en) * 2021-09-10 2023-03-16 Kioxia Corporation Semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668047A (zh) * 2009-11-18 2012-09-12 松下电器产业株式会社 半导体装置
CN102971851A (zh) * 2010-07-09 2013-03-13 佳能株式会社 固态图像拾取设备
CN104465759A (zh) * 2013-09-12 2015-03-25 株式会社东芝 半导体装置
CN107527821A (zh) * 2016-06-16 2017-12-29 精工爱普生株式会社 半导体装置及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070207592A1 (en) * 2006-03-03 2007-09-06 Lu James J Wafer bonding of damascene-patterned metal/adhesive redistribution layers
JP5376916B2 (ja) 2008-11-26 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5378130B2 (ja) * 2009-09-25 2013-12-25 株式会社東芝 半導体発光装置
KR102235927B1 (ko) 2011-05-24 2021-04-05 소니 주식회사 반도체 장치
KR101764468B1 (ko) * 2014-07-17 2017-08-02 주식회사 동부하이텍 쇼트키 다이오드 및 그 제조 방법
CN108242444B (zh) * 2016-12-23 2020-11-27 上海新昇半导体科技有限公司 真空管场效应晶体管阵列及其制造方法
JP2018148071A (ja) 2017-03-07 2018-09-20 東芝メモリ株式会社 記憶装置
CN108336074B (zh) * 2018-01-17 2019-03-29 武汉新芯集成电路制造有限公司 一种多层芯片及其集成方法
US10727205B2 (en) * 2018-08-15 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits
CN110476209B (zh) * 2019-06-28 2020-11-17 长江存储科技有限责任公司 三维存储器件中的存储器内计算

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668047A (zh) * 2009-11-18 2012-09-12 松下电器产业株式会社 半导体装置
CN102971851A (zh) * 2010-07-09 2013-03-13 佳能株式会社 固态图像拾取设备
CN104465759A (zh) * 2013-09-12 2015-03-25 株式会社东芝 半导体装置
CN107527821A (zh) * 2016-06-16 2017-12-29 精工爱普生株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
US20210057376A1 (en) 2021-02-25
JP2021034560A (ja) 2021-03-01
CN112420647A (zh) 2021-02-26
US11594514B2 (en) 2023-02-28
TWI757836B (zh) 2022-03-11
TW202114107A (zh) 2021-04-01

Similar Documents

Publication Publication Date Title
CN112420647B (zh) 半导体装置及其制造方法
TWI782794B (zh) 半導體裝置
TWI711164B (zh) 半導體裝置及其製造方法
TWI776616B (zh) 半導體裝置及其製造方法
TWI782400B (zh) 半導體裝置及其製造方法
TW202010107A (zh) 半導體裝置及其製造方法
CN113380781A (zh) 半导体装置及其制造方法
US11600585B2 (en) Semiconductor device with metal plugs and method for manufacturing the same
JP2021044399A (ja) 半導体装置およびその製造方法
CN115483222A (zh) 半导体装置及其制造方法
JP2020150226A (ja) 半導体装置およびその製造方法
CN111725190A (zh) 半导体存储装置及其制造方法
CN112510011B (zh) 半导体装置及其制造方法
JP2023040988A (ja) 半導体装置およびその製造方法
JP2024044997A (ja) 半導体装置およびその製造方法
TW202312366A (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant