CN111725190A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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Publication number
CN111725190A
CN111725190A CN201910728217.7A CN201910728217A CN111725190A CN 111725190 A CN111725190 A CN 111725190A CN 201910728217 A CN201910728217 A CN 201910728217A CN 111725190 A CN111725190 A CN 111725190A
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chip
pad
memory device
semiconductor
bonding pad
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铃木和贵
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种能够削减作为非存储区域的无效区域的半导体存储装置及其制造方法。一实施方式的半导体存储装置具有第1芯片与第2芯片，所述第1芯片具有：多个电极层，在第1方向上积层；半导体膜，在多个电极层内在第1方向上延伸；及存储膜，配置在多个电极层与半导体膜之间；所述第2芯片将半导体衬底朝上接合在第1芯片上，且具有：MOS晶体管，设置在半导体衬底的下表面；布线，设置在MOS晶体管的下方，且电连接至MOS晶体管；接合垫，设置在MOS晶体管的下方，且在其上表面进行接合；及通孔，以接合垫的上表面为底贯通半导体衬底，且在上方开口。

Description

半导体存储装置及其制造方法
[相关申请]
本申请享有以日本专利申请2019-50331号(申请日：2019年3月18日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体存储装置及其制造方法。
背景技术
作为半导体存储装置之一的三维半导体存储器中，已知形成有存储单元阵列的阵列芯片与包含驱动存储单元阵列的电路的电路芯片贴合而成的构造。
在具有所述构造的三维半导体存储器中，通常将接合垫设置在阵列芯片。因此，必须在阵列芯片中，确保与存储单元阵列的形成区域分开的接合垫的形成区域。在阵列芯片中，接合垫的形成区域是作为非存储区域的无效区域。
发明内容
本发明的实施方式提供一种能够削减无效区域的半导体存储装置及其制造方法。
一实施方式的半导体存储装置具有第1芯片与第2芯片，所述第1芯片具有：多个电极层，在第1方向上积层；半导体膜，在多个电极层内在第1方向上延伸；及存储膜，配置在多个电极层与半导体膜之间；所述第2芯片将半导体衬底朝上接合在第1芯片上，且具有：MOS晶体管，设置在半导体衬底的下表面；布线，设置在MOS晶体管的下方，且电连接至MOS晶体管；接合垫，设置在MOS晶体管的下方，且在其上表面进行接合；及通孔，以接合垫的上表面为底贯通半导体衬底，且在上方开口。
附图说明
图1(a)是第1实施方式的半导体存储装置的阵列芯片的概略俯视图，(b)是第1实施方式的半导体存储装置的电路芯片的概略俯视图。
图2是切取图1(a)、(b)的阵列芯片及电路芯片的一部分，并将其主要部分的构造放大表示所得的剖视图。
图3是将积层体的一部分及存储柱的一部分放大所得的剖视图。
图4是表示第2芯片的成膜步骤的剖视图。
图5是表示衬底的刻蚀步骤的剖视图。
图6是表示通孔的形成步骤的剖视图。
图7是表示保护膜的成膜步骤的剖视图。
图8是表示变化例的电路芯片的概略构造的剖视图。
图9(a)是第2实施方式的半导体存储装置的阵列芯片的概略俯视图，(b)是第2实施方式的半导体存储装置的电路芯片的概略俯视图。
图10是第3实施方式的半导体存储装置的电路芯片的概略剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。
(第1实施方式)
图1(a)是第1实施方式的半导体存储装置的阵列芯片的概略俯视图。图1(b)是第1实施方式的半导体存储装置的电路芯片的概略俯视图。图2是切取图1(a)、(b)的阵列芯片及电路芯片的一部分，并将其主要部分的构造放大表示所得的剖视图。
本实施方式的半导体存储装置是将图1(a)、(b)所示的阵列芯片1(第1芯片)与电路芯片2(第2芯片)贴合，以整体构成三维型构造的半导体存储芯片。接着，使用图2的放大剖视图对存储芯片1及电路芯片2的主要部分的构成进行说明。首先，阵列芯片1如图2所示，具有衬底10、积层体11、存储柱12、接触插塞13a～13d、布线层14a～14c、及垫15(第1垫)。
衬底10例如为硅衬底。在衬底10上，在与衬底10平行的X方向及Y方向上设置多个电极层与多个绝缘层交替积层而成的积层体11。积层体11中，在衬底10上的X方向及X方向以阵列状排列有在与衬底10正交的Z方向(第1方向)上贯通积层体11的多个存储柱12。在本实施方式中，将包含积层体11的主要部分、设置在积层体11中的多个存储柱12、及设置在它们上方的接触插塞13a～13d、及布线层14a～14c的区域称为单元阵列区域R1。
此外，在图2中，将布线层14a～14c简化后一体示出，但实际上各布线层14a～14c分别包含被层间绝缘膜16绝缘分离的多条布线(例如位线)。同样地，也将垫15简化后一体示出，但实际上包含被层间绝缘膜16绝缘分离的多个垫。
另外，将包含单元阵列区域R1的周围的单元阵列区域R1以外的区域称为周边区域R2。在图1(a)中示出了2个单元阵列区域R1，但单元阵列区域R1实际上阵列状地排列在X方向、及Y方向。
此处，使用图3的将包含存储膜的存储柱的一部分放大所得的剖视图，对存储柱12的构成进行说明。图3图示了积层体11的一部分、及在积层体11内在Z方向延伸的存储柱12中包含的2个存储元件。与电极层111对向的存储膜(电荷阻挡膜121，电荷储存层122，穿隧绝缘膜123)及半导体膜124的部分对应于1个存储单元。
存储柱12成为在Z方向上包含串联连接的多个存储元件及连接至这些多个存储元件的两端的选择晶体管(未图示)的构造。各电极层111是作为与这些存储元件分别电连接的字线或用来选择这些存储元件的选择晶体管的栅极电极发挥功能。
如图3所示，存储柱12具有电荷阻挡膜121、电荷储存层122、穿隧绝缘膜123、半导体膜124、及芯膜125。
电荷阻挡膜121、穿隧绝缘膜123及芯膜125例如为氧化硅膜。电荷储存层122例如为氮化硅膜(SiN)。半导体膜124例如为多晶硅膜等膜，且作为沟道发挥功能。多个存储柱12中的各半导体膜124的上端经由图2所示的接触插塞13a连接至布线层14a。
布线层14a中设置着单独连接至半导体膜124的多条位线。各位线经由接触插塞13b连接至布线层14b。布线层14b经由接触插塞13c连接至布线层14c。布线层14c经由接触插塞13d连接至垫15的面15a。在本实施方式中，接触插塞13a～13d及布线层14a～14c的材料为铝。垫15的材料为铜。
在积层体11中，多个电极层111与多个绝缘层112在与衬底10正交的Z方向(第1方向)上交替地积层。此外，图2及图3中虽未示出，但积层体11的端部为了将各电极层111电连接至电路芯片2而形成为阶梯状。该阶梯状形成的端部包含在周边区域R2中。
各电极层111例如为钨(w)等金属层。各绝缘层112积层在电极层111之上下，将各电极层111绝缘分离。各绝缘层112例如为氧化硅层(SiO2)。
接着，返回图2，对电路芯片2的构成进行说明。电路芯片2具有衬底20、保护膜21、MOS晶体管22、接触插塞23a～23f、布线层24a～24c、垫25(第2垫)、接合垫26、虚设垫27、及层间绝缘膜28。
此外，在图2中，将布线层24a～24c简化后一体示出，但实际上包含被层间绝缘膜28绝缘分离的多条布线。同样地，垫25也是简化后一体示出，但实际上包含被层间绝缘膜28绝缘分离的多个垫。
衬底20例如为硅衬底。衬底20的单面由保护膜21覆盖。保护膜21例如为聚酰亚胺膜。在衬底20的相反侧的单面设置着用来驱动阵列芯片1的MOS(Metal-Oxide-Semiconductor，金属氧化物半导体)晶体管22。
MOS晶体管22例如是具有栅极电极22a、及扩散层22b的MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)。扩散层22b是源极区域或漏极区域。栅极电极22a经由接触插塞23a连接至设置在布线层24a的布线。扩散层22b经由接触插塞23b连接至设置在布线层24a且与所述布线绝缘的另一布线。
布线层24a经由接触插塞23c连接至布线层24b。布线层24b经由接触插塞23d连接至布线层24c。在与布线层24c相同的层设置着接合垫26。布线层24c经由接触插塞23e连接至垫25的面25a。垫25以与面25a为相反侧的面25b接合在设置在阵列芯片1的垫15的与面15a为相反侧的面15b。接合垫26经由接触插塞23f连接至虚设垫27。虚设垫27接合在阵列芯片1的垫15。
在本实施方式中，接触插塞23a～23f、布线层24a～24c、及接合垫26的材料为铝。垫25及虚设垫27的材料为铜。
接合垫26通过形成在层间绝缘膜28的通孔29露出。接合线30接合在接合垫26。电路芯片2经由接合线30连接至安装衬底或其他芯片。在本实施方式中，如图1(b)所示，多个接合垫26与作为存储柱12的形成区域的单元阵列区域R1对向地形成。
以下，对如上所述那样构成的半导体存储装置的制造步骤进行说明。此处，参照图4～图7对电路芯片2的主要制造步骤进行说明。
首先，如图4所示，在晶圆衬底20上形成MOS晶体管22、接触插塞23a～23f、布线层24a～24c、垫25、接合垫26、虚设垫27、及层间绝缘膜28。
接着，如图5所示，将衬底20的一部分去除。具体来说，对与接合垫26对向的部分进行刻蚀。
接着，如图6所示，形成通孔29。通孔29从通过将衬底20的一部分去除而露出的层间绝缘膜28的表面到达接合垫26。
接着，如图7所示，将保护膜21成膜。至此，电路芯片2完成。之后，使电路芯片2上下翻转(旋转180度)后贴合在阵列芯片1。由此，将垫25及虚设垫27接合在阵列芯片1的垫15。
根据以上说明的本实施方式，以往，将形成在阵列芯片1的接合垫26形成在电路芯片2。因此，阵列芯片1中不需要接合垫26的形成区域，所以能够将不直接有助于存储功能的无效区域削减。由此，能够使阵列芯片1的面积缩小。
进而，根据本实施方式，电路芯片2在接合垫26之下具有虚设垫27。因此，能够利用虚设垫27缓和将接合线30接合时接合垫26中产生的冲击。
(变化例1)
图8是表示变化例的电路芯片的概略构造的剖视图。对与所述第1实施方式的电路芯片2相同的构成要素标注相同符号，并省略详细说明。
在第1实施方式的电路芯片2中，接合垫26与布线层24c配置在同一层。也就是说，接合垫26配置在垫25的正下方的层。
另一方面，在本变化例的电路芯片2a中，如图8所示，接合垫26与中间的布线层24b配置在同一层。因此，与布线层24c为同一层的布线层24d设置在接合垫26与虚设垫27之间。布线层24d经由接触插塞23f连接至虚设垫27，并且经由接触插塞23g连接至接合垫26。
即便以上说明的本变化例中，也与第1实施方式同样地将接合垫26形成在电路芯片2a，因此能够削减阵列芯片1的无效区域。进而，根据本变化例，能够利用布线层24d及虚设垫27缓和将接合线30接合时接合垫26中产生的冲击。
此外，在所述第1实施方式及本变化例中，电路芯片2包含三层布线层，但布线层数并无特别限制。另外，接合垫26的位置也不限于最上层、中间层、及最下层，只要与多个布线层的其中任一层为同一层即可。
(第2实施方式)
图9(a)是第2实施方式的半导体存储装置的阵列芯片的概略俯视图。图9(b)是第2实施方式的半导体存储装置的电路芯片的概略俯视图。对与所述第1实施方式的电路芯片2相同的构成要素标注相同符号，并省略详细的说明。另外，在本实施方式中，仅接合垫26的配置与第1实施方式不同，因此省略剖视图。
在本实施方式中，如图9(b)所示，在电路芯片2b中，多个接合垫26与阵列芯片1的周边区域R2对向地配置。具体来说，各接合垫26配置在X方向上相互对向的单元阵列区域R1之间或设置在阵列芯片1的积层体11的阶梯状的端部、即连结(hookup)区域。
因此，根据本实施方式，例如当在电路芯片2b中，因空间情况而难以将接合垫26与单元阵列区域R1对向地配置时，能够确保接合垫26的形成部位。即便在此情况下，也因接合垫26形成在电路芯片2而能够削减阵列芯片1的无效区域，使之缩小。
(第3实施方式)
图10是第3实施方式的半导体存储装置的电路芯片的概略剖视图。对与所述第1实施方式的电路芯片2相同的构成要素标注相同符号，并省略详细的说明。
在图10所示的电路芯片2c中，接合垫26与最靠近衬底20的布线层24a配置在同一层。因此，布线层24d及布线层24e设置在接合垫26与虚设垫27之间。
布线层24d与布线层24c配置在同一层，且经由接触插塞23f连接至虚设垫27，并且经由接触插塞23g连接至布线层24e。另一方面，布线层24e与布线层24b配置在同一层，且经由接触插塞23h连接至接合垫26。
在本实施方式中，接合垫26的材料为钨。另一方面，接合线30的材料为铝。因此，在接合步骤中可能无法将两者接合。
因此，在本实施方式中，以覆盖接合垫26及衬底20的方式形成铝层31。由此，能够经由铝层31将接合线30与接合垫26接合。
即便在以上说明的本实施方式中，也因接合垫26形成在电路芯片2而能够削减阵列芯片1的无效区域，使其缩小。进而，在本实施方式中，即便接合垫26的材料与接合线30的材料不同，也能够将两者接合。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出，并无意图限定发明范围。这些实施方式能够以其它各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书中记载的发明及其均等的范围内。
[符号说明]
1 阵列芯片(第1芯片)
2 电路芯片(第2芯片)
10 衬底
11 积层体
15 第1垫
22 MOS晶体管
24a～24c 布线层
25 第2垫
26 接合垫
27 虚设垫
29 通孔
31 铝层
111 电极层
122 电荷储存层
124 半导体膜
R1 单元阵列区域
R2 周边区域

Claims (8)

1.一种半导体存储装置，包括第1芯片与第2芯片，所述第1芯片具有：
多个电极层，在第1方向上积层；
半导体膜，在所述多个电极层内在所述第1方向上延伸；及
存储膜，配置在所述多个电极层与所述半导体膜之间；
所述第2芯片将半导体衬底朝上接合在所述第1芯片上，且具有：
MOS晶体管，设置在所述半导体衬底的下表面；
布线，设置在所述MOS晶体管的下方，且电连接至所述MOS晶体管；
接合垫，设置在所述MOS晶体管的下方，且在其上表面进行接合；及
通孔，以所述接合垫的上表面为底贯通所述半导体衬底，且在上方开口。
2.根据权利要求1所述的半导体存储装置，其具有：
第1垫，设置在所述第1芯片与所述第2芯片的贴合面，且将所述半导体膜的上端电连接至所述布线；及
第2垫，设置在所述第1芯片与所述第2芯片的贴合面，且在所述第1方向上至少一部分与所述接合垫重叠。
3.根据权利要求1所述的半导体存储装置，其中所述接合垫与至少包含所述多个存储柱的单元阵列区域对向地设置。
4.根据权利要求1所述的半导体存储装置，其中所述接合垫与包括至少包含所述多个存储柱的单元阵列区域的周围的周边区域对向地设置。
5.根据权利要求2所述的半导体存储装置，其中所述第2芯片更具有设置在所述接合垫与所述第1垫之间的虚设垫。
6.根据权利要求1至5中任一项所述的半导体存储装置，其中所述接合垫与所述布线设置在同一层。
7.根据权利要求1至5中任一项所述的半导体存储装置，其中所述接合垫包含钨，且接合在所述接合垫的接合线包含铝，
在所述接合垫与所述接合线之间设置着铝层。
8.一种半导体存储装置的制造方法，将半导体衬底朝上地将第2芯片接合在第1芯片上，所述第1芯片具有：多个电极层，在第1方向上积层；半导体膜，在所述多个电极层内在所述第1方向上延伸；及存储膜，配置在所述多个电极层与所述半导体膜之间；
在所述第2芯片形成：MOS晶体管，设置在所述半导体衬底的下表面；布线，设置在所述MOS晶体管的下方，且电连接至所述MOS晶体管；接合垫，设置在所述MOS晶体管的下方，且在其上表面进行接合；及通孔，以所述接合垫的上表面为底贯通所述半导体衬底，且在上方开口。
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