TWI776181B - 半導體裝置及半導體裝置的製造方法 - Google Patents

半導體裝置及半導體裝置的製造方法 Download PDF

Info

Publication number
TWI776181B
TWI776181B TW109122869A TW109122869A TWI776181B TW I776181 B TWI776181 B TW I776181B TW 109122869 A TW109122869 A TW 109122869A TW 109122869 A TW109122869 A TW 109122869A TW I776181 B TWI776181 B TW I776181B
Authority
TW
Taiwan
Prior art keywords
substrate
regions
semiconductor device
plug
insulating film
Prior art date
Application number
TW109122869A
Other languages
English (en)
Other versions
TW202111868A (zh
Inventor
佐貫朋也
中塚圭祐
吉水康人
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202111868A publication Critical patent/TW202111868A/zh
Application granted granted Critical
Publication of TWI776181B publication Critical patent/TWI776181B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)

Abstract

實施形態提供可以減小基板與接觸栓塞之間之接觸電阻的半導體裝置及半導體裝置的製造方法。 依據一個實施形態，半導體裝置係具備：包含2個元件區域的基板，且前述元件區域朝向平行於前述基板之表面的第1方向延伸，且在與前述第1方向交叉的第2方向互相鄰接的基板。前述裝置進一步具備：設置於前述基板之上方的佈線層。前述裝置進一步具備：設置於前述基板與前述佈線層之間的絕緣膜。前述裝置進一步具備：在前述絕緣膜內，朝向前述第2方向以及與前述第1及第2方向交叉的第3方向延伸，且設置於前述元件區域之每一區域之上，用於電連接前述元件區域與前述佈線層的栓塞。

Description

半導體裝置及半導體裝置的製造方法
[關連申請] 本申請主張日本專利申請2019-165574號(申請日：2019年9月11日)之基礎申請案的優先權。本申請參照該基礎申請案而包含基礎申請案之全部內容。 本發明的實施形態關於半導體裝置及半導體裝置的製造方法。
形成接觸於基板的接觸栓塞之情況下，存在基板與接觸栓塞之接觸電阻變高的問題。
實施形態提供可以減小基板與接觸栓塞之間之接觸電阻的半導體裝置及半導體裝置的製造方法。 根據一個實施形態，半導體裝置係具備：基板，該基板包含2個元件區域，前述元件區域係朝平行於前述基板之表面的第1方向延伸，且在與前述第1方向交叉的第2方向互相鄰接。前述裝置進一步具備：設置於前述基板之上方的佈線層。前述裝置進一步具備：設置於前述基板與前述佈線層之間的絕緣膜。前述裝置進一步具備：栓塞，該栓塞係在前述絕緣膜內朝向前述第2方向以及與前述第1及第2方向交叉的第3方向延伸，且設置於前述元件區域之每一區域之上，用於電連接前述元件區域與前述佈線層。
以下，參照圖面說明本發明的實施形態。圖1~圖10中，針對同一構成標記同一符號，並省略重複之說明。 (第1實施形態) 圖1係表示第1實施形態之半導體裝置的結構的剖面圖。圖1的半導體裝置係將陣列晶片1與電路晶片2黏貼而成的三維記憶體。 陣列晶片1具備：包含多個記憶單元的記憶單元陣列11；記憶單元陣列11上的絕緣膜12；及記憶單元陣列11下之層間絕緣膜13。絕緣膜12例如為氧化矽膜或氮化矽膜。層間絕緣膜13例如為氧化矽膜或包含氧化矽膜與其他絕緣膜的堆疊膜。 電路晶片2設置於陣列晶片1之下。符號S表示陣列晶片1與電路晶片2之黏合面。電路晶片2具備：層間絕緣膜14、及層間絕緣膜14下之基板15。層間絕緣膜14例如為氧化矽膜或包含氧化矽膜與其他絕緣膜的堆疊膜。基板15例如為矽基板等之半導體基板。 圖1中示出，平行於基板15之表面且互相垂直的X方向和Y方向，及垂直於基板15之表面的Z方向。本說明書中，將+Z方向設為上方向，將-Z方向設為下方向。-Z方向可以與重力方向一致或不一致。Y方向為第1方向之例，X方向為與第1方向交叉的第2方向之例，Z方向為與第1及第2方向交叉的第3方向之例。 陣列晶片1具備作為記憶單元陣列11內之電極層的多條字元線WL和源極線SL。圖1中示出記憶單元陣列11之階層結構部21。各字元線WL經由接觸栓塞22電連接於字元佈線層23。貫穿多條字元線WL的各柱狀部CL係經由穿孔栓塞24電連接於位元線BL，且電連接於源極線SL。源極線SL包含，半導體層之第1層SL1和金屬層之第2層SL2。 電路晶片2具備多個電晶體31。各電晶體31具備：隔著閘極絕緣膜設置於基板15上的閘極電極32、及設置於基板15內的未圖示之源極擴散層及汲極擴散層。此外，電路晶片2具備：設置於這些電晶體31之源極擴散層或汲極擴散層上的多個接觸栓塞33、設置於這些接觸栓塞33上且包含多條佈線的佈線層34、及設置於佈線層34上且包含多條佈線的佈線層35。 電路晶片2還具備：設置於佈線層35上且包含多條佈線的佈線層36、設置於佈線層36上的多個穿孔栓塞37、及設置於這些穿孔栓塞37上的多個金屬焊墊38。金屬焊墊38例如為Cu(銅)層或Al(鋁)層。金屬焊墊38為第1焊墊之例。電路晶片2作為對陣列晶片1之動作進行控制的控制電路(邏輯電路)而發揮功能。該控制電路係由電晶體31等構成，且電連接於金屬焊墊38。 陣列晶片1具備：設置於金屬焊墊38上的多個金屬焊墊41、設置於金屬焊墊41上的多個穿孔栓塞42、及設置於這些穿孔栓塞42上且包含多條佈線的佈線層43。金屬焊墊41例如為Cu層或Al層。金屬焊墊41為第2焊墊之例。 陣列晶片1還具備：設置於佈線層43上的多個穿孔栓塞44、設置於這些穿孔栓塞44上或絕緣膜12上的金屬焊墊45、及設置於金屬焊墊45上或絕緣膜12上的鈍化膜46。金屬焊墊45例如為Cu層或Al層，作為圖1的半導體裝置的外部連接焊墊(接合焊墊)而發揮功能。金屬焊墊45為第3焊墊之例。鈍化膜46例如為氧化矽膜等之絕緣膜，具有使金屬焊墊45之上面露出的開口部P。金屬焊墊45經由該開口部P藉由接合導線、焊球、金屬凸塊等可以連接於安裝基板或其他裝置。 圖2係表示第1實施形態之柱狀部CL之結構的剖面圖。 如圖2所示，記憶單元陣列11具備：交替堆疊在層間絕緣膜13(圖1)上的多條字元線WL和多個絕緣層51。字元線WL例如為W(鎢)層。絕緣層51例如為氧化矽膜。 柱狀部CL依序包含塊狀絕緣膜52、電荷蓄積層53、隧道絕緣膜54、通道半導體層55及芯絕緣膜56。電荷蓄積層53例如為氮化矽膜，隔著塊狀絕緣膜52形成於字元線WL及絕緣層51之側面。電荷蓄積層53可以是多晶矽層等之半導體層。通道半導體層55例如為多晶矽層，隔著隧道絕緣膜54形成於電荷蓄積層53之側面。塊狀絕緣膜52、隧道絕緣膜54及芯絕緣膜56例如為氧化矽膜或金屬絕緣膜。 圖3係表示第1實施形態之半導體裝置的製造方法的剖面圖。圖3中示出包含多個陣列晶片1的陣列晶圓W1及包含多個電路晶片2的電路晶圓W2。陣列晶圓W1亦稱為記憶體晶圓，電路晶圓W2亦稱為CMOS晶圓。 需要留意圖3之記憶體晶圓W1之方向和圖1的記憶體晶片1之方向相反。本實施形態中，藉由黏合陣列晶圓W1與電路晶圓W2來製造半導體裝置。圖3中示出為了黏合而反轉方向前之記憶體晶圓W1，圖1中示出為了黏合而反轉方向進行了黏合及切割後之記憶體晶片1。 圖3中符號S1表示記憶體晶圓W1之上表面，符號S2表示電路晶圓W2之上表面。需要留意記憶體晶圓W1具備設置於絕緣膜12下的基板16。基板16例如為矽基板等之半導體基板。 本實施形態中，首先，如圖3所示，在記憶體晶圓W1之基板16上形成記憶單元陣列11、絕緣膜12、層間絕緣膜13、階層結構部21、和金屬焊墊41等，在電路晶圓W2之基板15上形成層間絕緣膜14、電晶體31、及金屬焊墊38等。接著，藉由機械式壓力黏合陣列晶圓W1與電路晶圓W2。藉此而使層間絕緣膜13與層間絕緣膜14黏合。接著，在400℃下對陣列晶圓W1及電路晶圓W2進行退火。藉此而使金屬焊墊41與金屬焊墊38接合。 之後，藉由CMP(Chemical Mechanical Polishing)使基板15薄膜化，藉由CMP除去基板16之後，將陣列晶圓W1及電路晶圓W2切斷為多個晶片。藉此，製造圖1的半導體裝置。又，金屬焊墊45與鈍化膜46例如在基板15之薄膜化及基板16之除去之後形成於絕緣膜12上。 又，本實施形態中係將陣列晶圓W1與電路晶圓W2黏合，但是作為其之取代，亦可以將陣列晶圓W1彼此黏合。參照圖1~圖3的前述內容或參照圖4~圖10之後述內容亦適用於陣列晶圓W1彼此之黏合。 又，圖1中雖示出層間絕緣膜13與層間絕緣膜14之境界面或金屬焊墊41與金屬焊墊38之境界面，通常在上述退火後觀察不到這些境界面。但是，這些境界面之位置，例如可以藉由檢測金屬焊墊41之側面或金屬焊墊38之側面之傾斜或金屬焊墊41之側面與金屬焊墊38間之位置偏移來推定。 圖4係表示第1實施形態之電路晶片2之結構的剖面圖。 如上所述，本實施形態之電路晶片2具備：基板15，及形成於基板15上的層間絕緣膜14，還具備多個元件分離區域61、多個元件區域62、及多個接觸栓塞63。 這些元件分離區域61及元件區域62係朝向Y方向延伸，交替佈置於X方向。本實施形態之基板15具備朝向Y方向延伸的多個元件分離溝，在基板15之元件分離溝內形成有元件分離區域61。元件區域62為挾持於元件分離溝間的凸部，從基板15向層間絕緣膜14向Z方向突出，且延伸於Y方向，在X方向隔著元件分離區域61互相隣接。圖4所示多個元件分離溝係在圖4所示剖面以外之部位互相連接，構成設置於基板15的1個凹部。 設置於基板15內的各元件分離區域61例如由氧化矽膜等之絕緣膜形成。元件分離區域61亦稱為STI(Shallow Trench Isolation)區域。另一方面，挾持於元件分離區域61間的各元件區域62，成為基板15之一部分，例如成為矽層等之半導體層。本實施形態之基板15包含擴散層，元件區域62成為該擴散層之一部分。符號W係表示各元件區域62之X方向之寬度，更詳細為，表示各元件區域62之上表面(上端)之X方向之寬度。該寬度W為第1寬度之例。本實施形態中係由包含元件區域62的基板15，及形成於基板15內的元件分離區域61構成1個基板，於該基板上佈置有接觸栓塞63等。 接觸栓塞63係圖1所示接觸栓塞33之一種，在層間絕緣膜14內形成於元件區域62上，朝向Z方向延伸。接觸栓塞63，係與元件區域62之上表面相接，電連接於元件區域62。各接觸栓塞63包含依序形成於元件區域62之上表面或層間絕緣膜14之側面的阻障金屬層63a和栓塞材層63b。阻障金屬層63a例如為含有Ti(鈦)或Ta(鉭)的金屬層。栓塞材層63b例如為含有W(鎢)、Al(鋁)或Cu(銅)的金屬層。 接觸栓塞63例如具有長方形之平面形狀，亦稱為桿接觸。符號W1係表示各接觸栓塞63之X方向之寬度，更具體為，表示各接觸栓塞63之下表面(下端)之X方向之寬度。該寬度W1為第2寬度之例。本實施形態中，接觸栓塞63之寬度W1設為大於元件區域62之寬度W(W1＞W)。 各元件區域62具有與元件分離區域61相接的+X方向之側面，及與另一元件分離區域61相接的-X方向之側面。本實施形態之各接觸栓塞63係位於1個元件區域62上、設置於該元件區域62之+X方向之側面的元件分離區域61上、及設置於該元件區域62之-X方向之側面的元件分離區域61上。亦即，本實施形態之各接觸栓塞63係跨越1個元件區域62和挾持該元件區域62的2個元件分離區域61而佈置。藉由這樣的各接觸栓塞63之佈置，可以實現將寬度W1設為大於寬度W。 如上所述，金屬焊墊45(圖1)作為接合焊墊而發揮功能。金屬焊墊45經由任一之金屬焊墊41、金屬焊墊38、接觸栓塞63及元件區域62電連接於基板15。藉此，從金屬焊墊45對基板15可以供給例如電源電壓或接地電壓。 圖5係表示第1實施形態之比較例之電路晶片2之結構的剖面圖。 本比較例之電路晶片2，係取代前述接觸栓塞63而具備多個接觸栓塞64。各接觸栓塞64具備和前述阻障金屬層63a同樣之阻障金屬層64a，及和前述栓塞材層63b同樣之栓塞材層64b。接觸栓塞64例如具有長方形之平面形狀。符號W2係表示各接觸栓塞64之X方向之寬度，更具體為，表示各接觸栓塞64之下表面(下端)之X方向之寬度。本變形例中，接觸栓塞64之寬度W2設為小於元件區域62之寬度W(W2＜W)。 在此，對第1實施形態之接觸栓塞63與其之比較例之接觸栓塞64進行比較。 本比較例之接觸栓塞64直接形成於基板15上。因此，本比較例中，和將接觸栓塞64形成於矽化物層上等之情況比較，存在基板15與接觸栓塞64之接觸電阻變高之問題。 另一方面，本實施形態之接觸栓塞63亦直接形成於基板15上。但是，本實施形態之接觸栓塞63具有大的寬度W1，具體而言，接觸栓塞63之寬度W1設為大於元件區域62之寬度W。藉此，可以確保較大的接觸栓塞63與元件區域62之接觸面積。依據本實施形態，可以確保較大的接觸栓塞63與元件區域62之接觸面積，因此，可以減小基板15與接觸栓塞63之接觸電阻。 本實施形態中，各接觸栓塞63之寬度W1大於元件區域62之寬度W，因此，各接觸栓塞63可以跨越1個元件區域62與挾持該元件區域62的2個元件分離區域61而佈置。結果，圖4所示各元件區域62之剖面中，各元件區域62之上表面整體與接觸栓塞63之下表面接觸。藉此，能夠盡可能地確保較大的接觸栓塞63與元件區域62之接觸面積，可以大幅減小基板15與接觸栓塞64之接觸電阻。 圖6係表示第1實施形態之電路晶圓W2之製造方法的剖面圖。 首先，於基板15內形成多個元件分離溝H1，在這些元件分離溝H1內填埋氧化矽膜等之絕緣膜(圖6(a))。結果，於元件分離溝H1內形成元件分離區域61，於元件分離溝H1間形成元件區域62。 接著，在基板15之整面形成層間絕緣膜14(圖6(b))。又，在圖6(b)之工程中，形成圖1所示層間絕緣膜14之一部分而非全部。 接著，在層間絕緣膜14內形成多個接觸孔H2，在這些接觸孔H2內形成接觸栓塞63(圖6(c))。此時，各接觸孔H2形成為到達對應的元件區域62。結果，於元件區域62上形成接觸栓塞63。各接觸栓塞63係跨越對應的元件區域62和挾持該元件區域62的2個元件分離區域61而形成。 之後，藉由參照圖3說明的方法，將陣列晶圓W1與電路晶圓W2黏合。由此而製造圖1的半導體裝置。本實施形態之電路晶片2係以具有圖4所示結構的方式予以製造。 如上所述，本實施形態之接觸栓塞63之寬度W1設為大於元件區域62之寬度W。因此，依據本實施形態，可以減小基板15與接觸栓塞63之接觸電阻。 又，本實施形態之電路晶片2，除圖4所示接觸栓塞63以外，亦可以具備圖5所示接觸栓塞64。接觸栓塞63之例為設置於電晶體31之源極擴散層或汲極擴散層上的源極電極或汲極電極。在第4實施形態中詳細說明這樣的例。 (第2實施形態) 圖7係表示第2實施形態之電路晶片2之結構的剖面圖。 本實施形態之電路晶片2，係取代前述接觸栓塞63而具備接觸栓塞65。接觸栓塞65係具備和前述阻障金屬層63a同樣之阻障金屬層65a，及和前述栓塞材層63b同樣之栓塞材層65b。接觸栓塞65例如具有長方形之平面形狀。符號W3係表示接觸栓塞65之X方向之寬度，更具體為，表示接觸栓塞65之下表面(下端)之X方向之寬度。本實施形態中，接觸栓塞65之寬度W3設為大於元件區域62之寬度W(W3＞W)。本實施形態之接觸栓塞65朝向Z方向和X方向延伸。 本實施形態之接觸栓塞65係形成於多個(在此為3個)元件區域62上。具體而言，接觸栓塞65係跨越3個元件區域62和4個元件分離區域61而形成。換言之，本實施形態之接觸栓塞65具有將第1實施形態之3個接觸栓塞63連接在一起的形狀。這樣的接觸栓塞65例如在圖6(c)之工程中藉由形成將3個接觸孔H2連接在一起的大的接觸孔而可以形成。 本實施形態中，可以確保較大的接觸栓塞65與多個元件區域62之接觸面積。因此，依據本實施形態，藉由確保較大的接觸栓塞65與元件區域62之接觸面積，可以減小基板15與接觸栓塞65之接觸電阻。這樣的接觸栓塞65可以作為將元件區域62彼此進行連接的局部佈線而發揮功能。 (第3實施形態) 圖8係表示第3實施形態之電路晶片2之結構的剖面圖。 本實施形態之電路晶片2中係取代前述接觸栓塞63而具備接觸栓塞66。接觸栓塞66係具備和前述阻障金屬層63a同樣之阻障金屬層66a，及和前述栓塞材層63b同樣之栓塞材層66b。接觸栓塞66例如具有長方形之平面形狀。符號W4係表示接觸栓塞66之X方向之寬度，更具體為，表示接觸栓塞66之下表面(下端)之X方向之寬度。本實施形態中，接觸栓塞66之寬度W4設為大於元件區域62之寬度W(W4＞W)。本實施形態之接觸栓塞66係朝向Z方向和X方向延伸。 本實施形態之接觸栓塞66和第2實施形態之接觸栓塞65同樣地形成於多個(在此為3個)元件區域62上。但是，本實施形態中，接觸栓塞66之下之元件分離區域61被除去。因此，本實施形態之接觸栓塞66不僅接觸元件區域62之上表面，亦接觸元件區域62之側面，而且亦與位於比元件區域62之上表面低的位置之基板15之上表面(亦即元件分離溝之底面)接觸。這樣的接觸栓塞66，例如在圖6(c)之工程中藉由形成將3個接觸孔H2連接在一起的大的接觸孔，而且使該接觸孔到達元件分離溝之底面的方式來形成而可以形成。 本實施形態中，元件分離溝之底面成為阱擴散層。依據本實施形態，藉由使接觸栓塞66接觸元件分離溝之底面，可以使接觸栓塞66作為阱接觸而發揮功能。 本實施形態中，能夠進一步確保較大的接觸栓塞66與多個元件區域62之接觸面積。因此，依據本實施形態，可以確保較大的接觸栓塞66與元件區域62之接觸面積，可以減小基板15與接觸栓塞66之接觸電阻。這樣的接觸栓塞66可以作為將元件區域62彼此進行連接的局部佈線而發揮功能。 (第4實施形態) 圖9係表示第4實施形態之電路晶片2之結構的平面圖。本實施形態之電路晶片2係具備第2實施形態之接觸栓塞65和第1實施形態之比較例之接觸栓塞64。 圖9(a)係表示在電路晶片2之基板15上作為電晶體31而形成有4個N型電晶體N1、4個N型電晶體N2、4個N型電晶體N3、及4個N型電晶體N4的區域。圖9(b)係表示在電路晶片2之基板15上作為電晶體31而形成有4個P型電晶體P1、4個P型電晶體P2、4個N型電晶體P3、及4個P型電晶體P4的區域。圖9(a)之區域與圖9(b)之區域係形成於1個電路晶片2之同一基板15上。 圖9(a)示出藉由元件分離區域61互相分離的2個元件區域62，及在這些元件區域62上經由閘極絕緣膜形成的多個閘極電極32。這些閘極電極32包含X方向之長度較短的多個閘極電極32a，及X方向之長度較長的多個閘極電極32b。閘極電極32a，係構成電晶體N2、N4，形成於2個元件區域62之中之任何一個上。閘極電極32b，係構成電晶體N1、N3，跨越2個元件區域62而形成。 圖9(a)進一步示出形成於2個元件區域62之中之任何一個之上的多個接觸栓塞64，及跨越2個元件區域62形成的多個接觸栓塞65。接觸栓塞64佈置於電晶體N2、N1之間或電晶體N1、N3之間或電晶體N3、N4之間。接觸栓塞65佈置於與電晶體N2鄰接的位置或與電晶體N4鄰接的位置。圖9(a)之接觸栓塞65，係作為設置於電晶體N2、N4之源極擴散層上的源極電極使用，使用於對電晶體N2、N4供給接地電壓(VSS電壓)。圖9(a)中，4個電晶體N2之接地電位可以相同，因此這些電晶體N4用之接觸栓塞統合為接觸栓塞65。關於電晶體N4亦同樣。藉此，可以節省半導體裝置的Y方向之空間。 圖9(b)示出藉由元件分離區域61互相分離的4個元件區域62，及在這些元件區域62上隔著閘極絕緣膜被形成的多個閘極電極32。這些閘極電極32包含X方向之長度較短的多個閘極電極32a及X方向之長度較長的多個閘極電極32b。閘極電極32a構成電晶體P2、P4，形成於2個元件區域62之中之任何一個之上。閘極電極32b構成電晶體P1、P3，跨越2個元件區域62而形成。 圖9(b)進一步示出形成於2個元件區域62之中之任何一個之上的多個接觸栓塞64，及跨越2個元件區域62而形成的多個接觸栓塞65。接觸栓塞64佈置於與電晶體P2鄰接的位置或與電晶體P4鄰接的位置。接觸栓塞65佈置於電晶體P1、P3之間。圖9(b)之接觸栓塞65為設置於電晶體P1、P3之源極擴散層上的源極電極，使用於對電晶體P1、P3供給電源電壓(VDD電壓)。圖9(a)中，電晶體P1、P3之電源電位可以相同，因此這些電晶體P1、P3用之接觸栓塞統合為接觸栓塞65。藉此，可以節省半導體裝置的Y方向之空間。 圖10係表示圖9之區域R1及區域R2之電路構成的電路圖。 區域R1包含1個N型電晶體N1、1個N型電晶體N2、1個N型電晶體N3、及1個N型電晶體N4。區域R2包含1個P型電晶體P1、1個P型電晶體P2、1個P型電晶體P3、及1個P型電晶體P4。 電晶體P1、P3之源極連接於電源佈線(VDD佈線)。電晶體P1、P3之汲極分別連接於電晶體P2、P4之源極。電晶體P2之汲極連接於電晶體N1、N2之汲極或電晶體N4、P4之閘極。電晶體P4之汲極連接於電晶體N3、N4之汲極或電晶體N2、P2之閘極。電晶體N1、N3之源極互相連接。電晶體N2、N4之源極連接於接地佈線(VSS佈線)。區域R1及區域R2構成這樣的電路。 本實施形態之電路晶片2具備多個與區域R1為相同電路構成的之區域，並且具備多個與區域R2為相同電路構成的區域。作為示例之一，圖9(a)及圖9(b)作為和區域R1相同之電路構成的區域而示出包含4個區域R1，作為和區域R2相同之電路構成的區域而示出包含4個區域R2。 依據本實施形態，利用第2實施形態之接觸栓塞65來形成電晶體N2、N4、P1、P3之源極電極，可以減小供給電源電壓或接地電壓的接觸栓塞與基板15之間之接觸電阻。電源電壓或接地電壓受到接觸電阻之大幅影響，因此依據本實施形態，可以有效地提升電路晶片2之電壓供給之効率。 又，本實施形態之電晶體N2、N4、P1、P3之源極電極亦可以由第1實施形態之接觸栓塞63來形成，亦可以由第3實施形態之接觸栓塞66形成。後者之情況下，容易確保較大的基板15與接觸栓塞66之接觸面積，因此能夠減小接觸電阻，並且可以減小區域R1及區域R2之面積。藉此，可以提升半導體裝置的集積度。 又，第1實施形態之接觸栓塞63或第2實施形態之接觸栓塞65或第3實施形態之接觸栓塞66都可以作為電晶體31之汲極電極。藉此，可以減小汲極電極中的接觸電阻。 以上，說明幾個實施形態，但是這些實施形態僅為例示，並非用來限定發明的範圍。本說明書中說明的新穎的裝置及方法，可以利用其他各種形態實施。又，在不脫離發明的要旨之範圍內，可以針對本說明書中說明的裝置及方法之形態進行各種省略、替換、變更。所附的申請專利範圍及與其均等之範圍旨在涵蓋包含於發明的範圍或主旨的形態或變形例。
1:陣列晶片 2:電路晶片 11:記憶單元陣列 12:絕緣膜 13:層間絕緣膜 14:層間絕緣膜 15:基板 16:基板 21:階層結構部 22:接觸栓塞 23:字元佈線層 24:穿孔栓塞 31:電晶體 32,32a,32b:閘極電極 33:接觸栓塞 34:佈線層 35:佈線層 36:佈線層 37:穿孔栓塞 38:金屬焊墊 41:金屬焊墊 42:穿孔栓塞 43:佈線層 44:穿孔栓塞 45:金屬焊墊 46:鈍化膜 51:絕緣層 52:塊狀絕緣膜 53:電荷蓄積層 54:隧道絕緣膜 55:通道半導體層 56:芯絕緣膜 61:元件分離區域 62:元件區域 63,64,65,66:接觸栓塞 63a,64a,65a,66a:阻障金屬層 63b,64b,65b,66b:栓塞材層
[圖1]表示第1實施形態之半導體裝置的結構的剖面圖。 [圖2]表示第1實施形態之柱狀部之結構的剖面圖。 [圖3]表示第1實施形態之半導體裝置的製造方法的剖面圖。 [圖4]表示第1實施形態之電路晶片之結構的剖面圖。 [圖5]表示第1實施形態之比較例之電路晶片之結構的剖面圖。 [圖6(a)~(c)]表示第1實施形態之電路晶圓之製造方法的剖面圖。 [圖7]表示第2實施形態之電路晶片之結構的剖面圖。 [圖8]表示第3實施形態之電路晶片之結構的剖面圖。 [圖9(a)、(b)]表示第4實施形態之電路晶片之結構的平面圖。 [圖10]表示圖9之區域R1及區域R2之電路構成的電路圖。
14:層間絕緣膜
15:基板
61:元件分離區域
62:元件區域
65:接觸栓塞
65a:阻障金屬層
65b:栓塞材層
W3:接觸栓塞65之X方向之寬度
W:元件區域62之X方向之寬度

Claims (11)

  1. 一種半導體裝置，係具備：基板，該基板包含2個元件區域，前述元件區域係朝向平行於前述基板之表面的第1方向延伸，且在與前述第1方向交叉的第2方向互相鄰接；佈線層，設置於前述基板之上方；絕緣膜，設置於前述基板與前述佈線層之間；及栓塞，該栓塞係在前述絕緣膜內朝向前述第2方向以及與前述第1及第2方向交叉的第3方向延伸，且設置於前述元件區域之上表面及側面，用於電連接前述元件區域與前述佈線層。
  2. 如請求項1之半導體裝置，其中前述基板包含設置於前述元件區域間的元件分離區域，前述元件區域隔著前述元件分離區域在前述第2方向上彼此相鄰。
  3. 如請求項2之半導體裝置，其中前述栓塞，係設置於前述元件區域之每一區域及前述元件分離區域上。
  4. 如請求項2之半導體裝置，其中前述基板包含：包含前述2個元件區域的3個以上的元件區域；及包含前述元件分離區域的2個以上的元件分離區域；前述栓塞，係設置於前述3個以上的元件區域之每一區域之上，用於將前述3個以上的元件區域與前述佈線層 進行電連接。
  5. 如請求項1之半導體裝置，其中前述栓塞係接觸位於比前述元件區域之前述上表面低的位置之前述基板之上表面。
  6. 如請求項5之半導體裝置，其中前述基板包含：包含前述2個元件區域的3個以上之元件區域，前述栓塞，係設置於前述3個以上的元件區域之每一區域之上，用於電連接前述3個以上的元件區域與前述佈線層。
  7. 如請求項1至6之任一項之半導體裝置，其中前述元件區域之每一區域，係在前述第2方向具有第1寬度，前述栓塞，係在前述第2方向具有大於前述第1寬度的第2寬度。
  8. 如請求項1至6之任一項之半導體裝置，其中前述元件區域包含設置於前述基板內的擴散層。
  9. 如請求項1至6之任一項之半導體裝置，其中前述栓塞為設置於電晶體之源極擴散層或汲極擴散層上的源極電極或汲極電極。
  10. 如請求項1至6之任一項之半導體裝置， 其中進一步具備：第1焊墊，係設置於前述基板之上方，且經由前述栓塞電連接於前述元件區域；第2焊墊，設置於前述第1焊墊上；及接合焊墊，設置於前述第2焊墊之上方，且電連接於前述第2焊墊。
  11. 一種半導體裝置的製造方法，包含：在基板內形成朝向平行於前述基板之表面的第1方向延伸，且在與前述第1方向交叉的第2方向互相鄰接的2個元件區域，在前述基板上形成絕緣膜，在前述絕緣膜上形成佈線層，在前述絕緣膜內形成，朝向前述第2方向以及與前述第1及第2方向交叉的第3方向延伸，且設置於前述元件區域之每一區域之上表面及側面，用於電連接前述元件區域與前述佈線層的栓塞。
TW109122869A 2019-09-11 2020-07-07 半導體裝置及半導體裝置的製造方法 TWI776181B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-165574 2019-09-11
JP2019165574A JP2021044399A (ja) 2019-09-11 2019-09-11 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW202111868A TW202111868A (zh) 2021-03-16
TWI776181B true TWI776181B (zh) 2022-09-01

Family

ID=74850210

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109122869A TWI776181B (zh) 2019-09-11 2020-07-07 半導體裝置及半導體裝置的製造方法

Country Status (4)

Country Link
US (1) US11450611B2 (zh)
JP (1) JP2021044399A (zh)
CN (1) CN112490284B (zh)
TW (1) TWI776181B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230082971A1 (en) * 2021-09-10 2023-03-16 Kioxia Corporation Semiconductor device and method for manufacturing the same
CN117558714B (zh) * 2024-01-09 2024-03-22 盛合晶微半导体(江阴)有限公司 混合键合封装结构、偏移量测试方法、贴片机

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180366583A1 (en) * 2015-10-26 2018-12-20 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US20180374858A1 (en) * 2016-01-29 2018-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures
TW201916195A (zh) * 2017-10-10 2019-04-16 美商格芯（美國）集成電路科技有限公司 形成導電接觸結構至半導體裝置之方法及所產生的結構
US20190221557A1 (en) * 2018-01-17 2019-07-18 Sandisk Technologies Llc Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
TW201935685A (zh) * 2018-02-20 2019-09-01 美商格芯（美國）集成電路科技有限公司 進行用於ｆｉｎｆｅｔ半導體裝置之鰭片切口蝕刻程序的方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198122B1 (en) * 1997-02-21 2001-03-06 Kabushiki Kaisha Toshiba Semiconductor memory and method of fabricating the same
US6717222B2 (en) * 2001-10-07 2004-04-06 Guobiao Zhang Three-dimensional memory
JP2003273210A (ja) * 2002-03-12 2003-09-26 Fujitsu Ltd 半導体装置及びその製造方法
US8513087B2 (en) * 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
JP2004153015A (ja) * 2002-10-30 2004-05-27 Fujitsu Ltd 半導体装置及びその製造方法
WO2007023569A1 (ja) * 2005-08-26 2007-03-01 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法
JP2008010758A (ja) * 2006-06-30 2008-01-17 Fujitsu Ltd 半導体装置及びその製造方法
JP4322897B2 (ja) * 2006-07-07 2009-09-02 エルピーダメモリ株式会社 半導体装置の製造方法
US8022493B2 (en) * 2007-09-27 2011-09-20 Dongbu Hitek Co., Ltd. Image sensor and manufacturing method thereof
JP5329068B2 (ja) * 2007-10-22 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置
KR101353346B1 (ko) * 2008-01-21 2014-02-17 삼성전자주식회사 주변 회로 영역의 불순물 영역들에 대한 열적 부담을완화시키는 반도체 소자의 제조 방법
JP5376916B2 (ja) 2008-11-26 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US11018133B2 (en) * 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US8748305B2 (en) * 2009-11-17 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for semiconductor devices
JP5521726B2 (ja) * 2010-04-16 2014-06-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
CN102237295B (zh) * 2010-04-28 2014-04-09 中国科学院微电子研究所 半导体结构制造方法
KR101741069B1 (ko) * 2010-06-11 2017-05-30 삼성전자 주식회사 비휘발성 메모리 장치
CN102456723A (zh) * 2010-10-26 2012-05-16 联华电子股份有限公司 半导体结构及其制造方法
JP5837783B2 (ja) * 2011-09-08 2015-12-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US20130320451A1 (en) * 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US9263322B2 (en) * 2013-09-18 2016-02-16 Globalfoundries Singapore Pte. Ltd. Reliable contacts
KR20150106660A (ko) * 2014-03-12 2015-09-22 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR101913453B1 (ko) * 2014-05-30 2018-10-31 매그나칩 반도체 유한회사 Ｓｏｉ 구조에 중공을 포함하는 반도체 소자 및 그 제조 방법
KR102276642B1 (ko) * 2014-07-28 2021-07-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180366583A1 (en) * 2015-10-26 2018-12-20 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US20180374858A1 (en) * 2016-01-29 2018-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures
TW201916195A (zh) * 2017-10-10 2019-04-16 美商格芯（美國）集成電路科技有限公司 形成導電接觸結構至半導體裝置之方法及所產生的結構
US20190221557A1 (en) * 2018-01-17 2019-07-18 Sandisk Technologies Llc Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
TW201935685A (zh) * 2018-02-20 2019-09-01 美商格芯（美國）集成電路科技有限公司 進行用於ｆｉｎｆｅｔ半導體裝置之鰭片切口蝕刻程序的方法

Also Published As

Publication number Publication date
US20210074638A1 (en) 2021-03-11
US11450611B2 (en) 2022-09-20
CN112490284B (zh) 2024-01-12
TW202111868A (zh) 2021-03-16
JP2021044399A (ja) 2021-03-18
CN112490284A (zh) 2021-03-12

Similar Documents

Publication Publication Date Title
US11758732B2 (en) Hybrid bonding contact structure of three-dimensional memory device
TWI814591B (zh) 半導體裝置
TWI711164B (zh) 半導體裝置及其製造方法
TWI770401B (zh) 半導體裝置及其製造方法
TWI782400B (zh) 半導體裝置及其製造方法
CN112420647A (zh) 半导体装置及其制造方法
TWI776181B (zh) 半導體裝置及半導體裝置的製造方法
JP2020155485A (ja) 半導体装置およびその製造方法
TWI701802B (zh) 半導體裝置及其製造方法
TWI854341B (zh) 半導體裝置
TWI812044B (zh) 半導體裝置及其製造方法
TWI851373B (zh) 半導體裝置
JP2023034974A (ja) 半導体装置および基板

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent